udb 0.1.16 → 0.1.17

data/.data/spec/std/isa/csr/mideleg.yaml

@@ -101,8 +101,16 @@ fields:
       *Supervisor Software Interrupt delegation*
 
       When 1, Supervisor Software interrupts are delegated to HS/S-mode.
-    type: RW
+    type(): |
+      return SSI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: 0
+    sw_write(csr_value): |
+      if (csr_value.SSI == 0) {
+        if (implemented?(ExtensionName::H)) {
+          CSR[hideleg].SSI = 0;
+        }
+      }
+      return csr_value.SSI;
   VSSI:
     location: 2
     description: |
@@ -116,13 +124,22 @@ fields:
     definedBy:
       extension:
         name: H
+    sw_write(csr_value): |
+      if (csr_value.VSSI == 0) {
+        CSR[hie].VSSIE = 0;
+        CSR[hip].VSSIP = 0;
+        CSR[hideleg].VSSI = 0;
+      }
+      return csr_value.VSSI;
   MSI:
     location: 3
     description: |
       *Machine Software interrupt delegation*
 
-      Since M-mode interrupts cannot be delegated, this field is read-only zero.
-    type: RO
+      When 1, Machine Software interrupts are delegated to HS/S-mode.
+      This is unusual but permitted. See https://github.com/riscv/riscv-isa-manual/issues/3162.
+    type(): |
+      return MSI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: 0
   STI:
     location: 5
@@ -130,7 +147,8 @@ fields:
       *Supervisor Timer interrupt delegation*
 
       When 1, Supervisor Timer interrupts are delegated to HS/S-mode.
-    type: RW
+    type(): |
+      return STI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: 0
   VSTI:
     location: 6
@@ -145,13 +163,22 @@ fields:
     definedBy:
       extension:
         name: H
+    sw_write(csr_value): |
+      if (csr_value.VSTI == 0) {
+        CSR[hie].VSTIE = 0;
+        CSR[hip].VSTIP = 0;
+        CSR[hideleg].VSTI = 0;
+      }
+      return csr_value.VSTI;
   MTI:
     location: 7
     description: |
       *Machine Timer interrupt delegation*
 
-      Since M-mode interrupts cannot be delegated, this field is read-only zero.
-    type: RO
+      When 1, Machine Timer interrupts are delegated to HS/S-mode.
+      This is unusual but permitted. See https://github.com/riscv/riscv-isa-manual/issues/3162.
+    type(): |
+      return MTI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: 0
   SEI:
     location: 9
@@ -159,7 +186,8 @@ fields:
       *Supervisor External interrupt delegation*
 
       When 1, Supervisor External interrupts are delegated to HS/S-mode.
-    type: RW
+    type(): |
+      return SEI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: 0
   VSEI:
     location: 10
@@ -172,13 +200,22 @@ fields:
     definedBy:
       extension:
         name: H
+    sw_write(csr_value): |
+      if (csr_value.VSEI == 0) {
+        CSR[hie].VSEIE = 0;
+        CSR[hip].VSEIP = 0;
+        CSR[hideleg].VSEI = 0;
+      }
+      return csr_value.VSEI;
   MEI:
     location: 11
     description: |
       *Machine External interrupt delegation*
 
-      Since M-mode interrupts cannot be delegated, this field is read-only zero.
-    type: RO
+      When 1, Machine External interrupts are delegated to HS/S-mode.
+      This is unusual but permitted. See https://github.com/riscv/riscv-isa-manual/issues/3162.
+    type(): |
+      return MEI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: 0
   SGEI:
     location: 12
@@ -191,6 +228,12 @@ fields:
     definedBy:
       extension:
         name: H
+    sw_write(csr_value): |
+      if (csr_value.SGEI == 0) {
+        CSR[hie].SGEIE = 0;
+        CSR[hip].SGEIP = 0;
+      }
+      return csr_value.SGEI;
   LCOFI:
     location: 13
     description: |
@@ -202,3 +245,8 @@ fields:
     definedBy:
       extension:
         name: Sscofpmf
+    sw_write(csr_value): |
+      if (csr_value.LCOFI == 0) {
+        CSR[hideleg].LCOFI = 0;
+      }
+      return csr_value.LCOFI;

data/.data/spec/std/isa/csr/mie.yaml

@@ -20,7 +20,8 @@ fields:
     location: 1
     description: |
       Enables Supervisor Software Interrupts.
-    type: RW
+    type(): |
+      return SSI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     definedBy:
       extension:
         name: S
@@ -29,7 +30,8 @@ fields:
     location: 2
     description: |
       Enables Virtual Supervisor Software Interrupts.
-    type: RW
+    type(): |
+      return VSSI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     definedBy:
       extension:
         name: H
@@ -37,13 +39,15 @@ fields:
   MSIE:
     location: 3
     description: Enables Machine Software Interrupts.
-    type: RW
+    type(): |
+      return MSI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: 0
   STIE:
     location: 5
     description: |
       Enables Supervisor Timer Interrupts.
-    type: RW
+    type(): |
+      return STI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     definedBy:
       extension:
         name: S
@@ -52,7 +56,8 @@ fields:
     location: 6
     description: |
       Enables Virtual Supervisor Timer Interrupts.
-    type: RW
+    type(): |
+      return VSTI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     definedBy:
       extension:
         name: H
@@ -60,13 +65,15 @@ fields:
   MTIE:
     location: 7
     description: Enables Machine Timer Interrupts.
-    type: RW
+    type(): |
+      return MTI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: 0
   SEIE:
     location: 9
     description: |
       Enables Supervisor External Interrupts.
-    type: RW
+    type(): |
+      return SEI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     definedBy:
       extension:
         name: S
@@ -75,7 +82,8 @@ fields:
     location: 10
     description: |
       Enables Virtual Supervisor External Interrupts.
-    type: RW
+    type(): |
+      return VSEI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     definedBy:
       extension:
         name: H
@@ -83,7 +91,8 @@ fields:
   MEIE:
     location: 11
     description: Enables Machine External Interrupts.
-    type: RW
+    type(): |
+      return MEI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: 0
   SGEIE:
     location: 12

data/.data/spec/std/isa/csr/mip.yaml

@@ -185,7 +185,8 @@ fields:
       <%- if ext?(:Smaia) -%>
       * `mvip.SSIP`
       <%- end -%>
-    type: RW
+    type(): |
+      return SSI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: 0
     definedBy:
       extension:
@@ -214,7 +215,8 @@ fields:
       * `hip.VSSIP`
       * `hvip.VSSIP`
       * `vsip.SSIP` when `hideleg.VSSI` is set
-    type: RW
+    type(): |
+      return VSSI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: 0
     definedBy:
       extension:
@@ -225,13 +227,16 @@ fields:
     description: |
       *Machine Software Interrupt Pending*
 
-      Unused field.
+      Interrupt-pending bit for machine-level software interrupts.
+      MSIP is read-only in mip, and is written by accesses to memory-mapped control registers,
+      which are used to provide machine-level interprocessor interrupts.
 
       <%- if ext?(:Smaia) -%>
       With AIA/IMSIC, IPIs are delivered as external interrupts. As a result, this bit is
       unused and hardwired to 0.
       <%- end -%>
-    type: RO
+    type(): |
+      return MSI_INTR_IMPL ? CsrFieldType::ROH : CsrFieldType::RO;
     reset_value: 0
   STIP:
     location: 5
@@ -261,7 +266,8 @@ fields:
       * `mvip.STIP` when when `menvcfg.STCE` is clear
       <%- end -%>
 
-    type: RW
+    type(): |
+      return STI_INTR_IMPL ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value: 0
     definedBy:
       extension:
@@ -298,7 +304,8 @@ fields:
       * `hip.VSTIP`
       * `vsip.STIP` when `hideleg.VSTI` is set
       * `hvip.VSTIP` <% if ext?(:Sstc) %>when `menvcfg.STCE` is clear<% end %> (though `hvip.VSTIP` is writable)
-    type: RO-H
+    type(): |
+      return VSTI_INTR_IMPL ? CsrFieldType::ROH : CsrFieldType::RO;
     reset_value: 0
     definedBy:
       extension:
@@ -312,7 +319,8 @@ fields:
       Reports the current pending state of an M-mode timer interrupt.
 
       Bit is controlled by the timer device (using `mtimecmp`), and is not writable.
-    type: RO-H
+    type(): |
+      return MTI_INTR_IMPL ? CsrFieldType::ROH : CsrFieldType::RO;
     reset_value: 0
   SEIP:
     location: 9
@@ -334,7 +342,8 @@ fields:
       _Alias_:
 
       * `sip.SEIP` when `mideleg.SEI` is set (though `sip.SEIP` is read-only)
-    type: RW-H
+    type(): |
+      return SEI_INTR_IMPL ? CsrFieldType::RWH : CsrFieldType::RO;
     definedBy:
       extension:
         name: S
@@ -363,7 +372,8 @@ fields:
 
       * `hip.VSEIP`
       * `vsip.SEIP` when `hideleg.VSEI` is set
-    type: RO-H
+    type(): |
+      return VSEI_INTR_IMPL ? CsrFieldType::ROH : CsrFieldType::RO;
     reset_value: 0
     definedBy:
       extension:
@@ -378,7 +388,8 @@ fields:
 
       MEIP is controlled by the external interrupt controller <% if ext?(:Smaia) %>(AIA) <% end %>.
       It is not writable by software.
-    type: RO-H
+    type(): |
+      return MEI_INTR_IMPL ? CsrFieldType::ROH : CsrFieldType::RO;
     reset_value: 0
   SGEIP:
     location: 12

data/.data/spec/std/isa/csr/misa.yaml

@@ -27,9 +27,6 @@ fields:
     location: 0
     description: |
       Indicates support for the `A` (atomic) extension.
-
-      [when,"MUTABLE_MISA_A == true"]
-      Writing 0 to this field will cause all atomic instructions to raise an `IllegalInstruction` exception.
     type(): |
       return (implemented?(ExtensionName::A) && MUTABLE_MISA_A) ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value(): |
@@ -41,9 +38,6 @@ fields:
     location: 1
     description: |
       Indicates support for the `B` (bitmanip) extension.
-
-      [when,"MUTABLE_MISA_B == true"]
-      Writing 0 to this field will cause all bitmanip instructions to raise an `IllegalInstruction` exception.
     type(): |
       return (implemented?(ExtensionName::B) && MUTABLE_MISA_B) ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value(): |
@@ -157,7 +151,9 @@ fields:
       Indicates support for the `M` (integer multiply/divide) extension.
 
       [when,"MUTABLE_MISA_M == true"]
-      Writing 0 to this field will cause all attempts to execute an integer multiply or divide instruction to raise an `IllegalInstruction` exception.
+      Writing 0 to this field will cause all attempts to execute an integer divide or
+      remainder instruction to raise an `IllegalInstruction` exception. The multiply
+      instructions are provided by `Zmmul` and are unaffected.
     type(): |
       return (implemented?(ExtensionName::M) && MUTABLE_MISA_M) ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value(): |
@@ -229,9 +225,17 @@ fields:
     definedBy:
       extension:
         name: Zvl32b
+  X:
+    location: 23
+    description: |
+      The `X` bit will be set if there are any non-standard extensions.
+    type: RO
+    reset_value(): |
+      return NON_STANDARD_EXTENSION_IMPLEMENTED ? 1 : 0;
 sw_read(): |
   return (
     (CSR[misa].MXL `<< (xlen() - 2)) |
+    (CSR[misa].X `<< 23) |
     (CSR[misa].V `<< 21) |
     (CSR[misa].U `<< 20) |
     (CSR[misa].S `<< 18) |

data/.data/spec/std/isa/csr/mstatus.yaml

@@ -40,9 +40,9 @@ fields:
       # this is read-only if FS and VS are both read-only
       # otherwise, it is read-only with hardware update
 
-      if (implemented?(ExtensionName::F) && (HW_MSTATUS_FS_DIRTY_UPDATE != "never")) {
+      if (implemented?(ExtensionName::F)) {
         return CsrFieldType::ROH;
-      } else if (implemented?(ExtensionName::V) && (HW_MSTATUS_VS_DIRTY_UPDATE != "never")) {
+      } else if (implemented?(ExtensionName::V)) {
         return CsrFieldType::ROH;
       } else {
         return CsrFieldType::RO;

data/.data/spec/std/isa/csr/schema.adoc

@@ -53,7 +53,7 @@ Privilege Mode::
 |===
 | *key*         | priv_mode
 | *value type*  | one of ["M", "S", "U", or "VS"]
-| *description* | The least-privilege mode that can access this CSR
+| *description* | The least-privilege mode that can access this CSR. For an indirect CSR, this also identifies the target indirect CSR address space.
 |===
 
 Length::
@@ -72,12 +72,12 @@ Indirect::
 | *key*         | indirect
 | *value type*  | Boolean
 | *default*     | false
-| *description* | Whether or not the CSR is accessible through the indirect CSRs of the `Smcdrind`/`Sscdrind` extensions.
+| *description* | Whether or not the CSR is accessible through the indirect CSRs of the `Smcsrind`/`Sscsrind` extensions.
 |===
 
 Address::
 
-[IMPORTANT] `address` is a required key *unless* the CSR is only accessible through the indirect registers of the `Smcsrind`/`Sscrind` extensions, in which case `indirect_address` is required. Both `address` and `indirect_address` may be specified when a CSR is accessible directly and indirectly.
+[IMPORTANT] `address` is a required key *unless* the CSR is only accessible through the indirect registers of the `Smcsrind`/`Sscsrind` extensions, in which case `indirect_address` is required. Both `address` and `indirect_address` may be specified when a CSR is accessible directly and indirectly.
 
 |===
 | *key*         | address
@@ -88,7 +88,13 @@ Address::
 |===
 | *key*         | indirect_address
 | *value type*  | Integer
-| *description* | Indirect sddress of the CSR, as given to the indirect CSRs of the `Smcsrind`/`Sscdrind` extensions
+| *description* | Indirect address of the CSR, as given to the indirect CSRs of the `Smcsrind`/`Sscsrind` extensions
+|===
+
+|===
+| *key*         | indirect_slot
+| *value type*  | Integer between 1-6
+| *description* | Indirect window slot of the CSR, corresponding to its appearance in *ireg<slot>
 |===
 
 Virtual Address::

data/.data/spec/std/isa/csr/senvcfg.yaml

@@ -88,17 +88,12 @@ fields:
     description: |
       *Cache Block Invalidate instruction Enable*
 
-      This field has restricted values based on the value of `menvcfg.CBIE`.
-      When an invalid value is written, it is ignored and the field remains unchanged.
+      The legal values of this field do not depend on `menvcfg.CBIE`.
+      When the reserved value `10` is written, it is ignored and the field remains unchanged.
 
-      [separator="!",%autowidth,cols=",.>"]
-      !===
-      ! [.rotate]#`menvcfg.CBIE`# ! Valid values of `senvcfg.CBIE`
-
-      ! 00 ! 00
-      ! 01 ! 00, 01
-      ! 11 ! 00, 01, 11
-      !===
+      Execution of `cbo.inval` in U-mode is enabled only if it is also enabled in S-mode
+      by `menvcfg.CBIE`. If `menvcfg.CBIE` is `01`, an enabled `cbo.inval` performs a
+      flush operation in U-mode even if `senvcfg.CBIE` is `11`.
 
       Controls execution of the cache block invalidate instruction, `cbo.inval`,
       in U-mode
@@ -120,9 +115,8 @@ fields:
     sw_write(csr_value): |
       if (csr_value.CBIE == 0 || csr_value.CBIE == 1 || csr_value.CBIE == 3) {
         return csr_value.CBIE;
-      } else {
-        return UNDEFINED_LEGAL_DETERMINISTIC;
       }
+      return CSR[senvcfg].CBIE;
     reset_value: UNDEFINED_LEGAL
   UKTE:
     location: 8

data/.data/spec/std/isa/csr/sstateen0.yaml

@@ -9,7 +9,7 @@ name: sstateen0
 long_name: Supervisor State Enable 0 Register
 address: 0x10C
 priv_mode: S
-length: MXLEN
+length: 64
 writable: true
 description: |
   Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,

data/.data/spec/std/isa/csr/sstateen1.yaml

@@ -9,7 +9,7 @@ name: sstateen1
 long_name: Supervisor State Enable 1 Register
 address: 0x10D
 priv_mode: S
-length: MXLEN
+length: 64
 writable: true
 description: |
   Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
@@ -61,8 +61,7 @@ definedBy:
 
 fields:
   DATA:
-    location_rv64: 63-0
-    location_rv32: 31-0
+    location: 31-0
     description: Data value
     type: RW
     sw_write(csr_value): |

data/.data/spec/std/isa/csr/sstateen2.yaml

@@ -9,7 +9,7 @@ name: sstateen2
 long_name: Supervisor State Enable 2 Register
 address: 0x10E
 priv_mode: S
-length: MXLEN
+length: 64
 writable: true
 description: |
   Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
@@ -61,8 +61,7 @@ definedBy:
 
 fields:
   DATA:
-    location_rv64: 63-0
-    location_rv32: 31-0
+    location: 31-0
     description: Data value
     type: RW
     sw_write(csr_value): |

data/.data/spec/std/isa/csr/sstateen3.yaml

@@ -9,7 +9,7 @@ name: sstateen3
 long_name: Supervisor State Enable 3 Register
 address: 0x10F
 priv_mode: S
-length: MXLEN
+length: 64
 writable: true
 description: |
   Each bit of a `stateen` CSR controls less-privileged access to an extension’s state,
@@ -61,8 +61,7 @@ definedBy:
 
 fields:
   DATA:
-    location_rv64: 63-0
-    location_rv32: 31-0
+    location: 31-0
     description: Data value
     type: RW
     sw_write(csr_value): |

data/.data/spec/std/isa/csr/tcontrol.yaml

@@ -0,0 +1,37 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: "csr_schema.json#"
+kind: csr
+name: tcontrol
+long_name: Trigger Control
+address: 0x7A5
+priv_mode: M
+length: XLEN
+writable: true
+description: |
+  This optional register is only accessible in M-mode and Debug Mode and provides
+  various control bits related to triggers.
+definedBy:
+  extension:
+    name: Sdtrig
+fields:
+  MPTE:
+    location: 7
+    description: |
+      M-mode previous trigger enable field.
+      MPTE and MTE provide one solution to a problem regarding triggers with action=0
+      firing in M-mode trap handlers.
+      When any trap into M-mode is taken, MPTE is set to the value of MTE.
+    type: RW-H
+    reset_value: 0
+  MTE:
+    location: 3
+    description: |
+      M-mode trigger enable field.
+      0 (disabled):: Triggers with action=0 do not match/fire while the hart is in M-mode.
+      1 (enabled):: Triggers do match/fire while the hart is in M-mode.
+      When any trap into M-mode is taken, MTE is set to 0. When `mret` is executed, MTE is
+      set to the value of MPTE.
+    type: RW-H
+    reset_value: 0

data/.data/spec/std/isa/csr/tinfo.yaml

@@ -0,0 +1,44 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: "csr_schema.json#"
+kind: csr
+name: tinfo
+long_name: Trigger Info
+address: 0x7A4
+priv_mode: M
+length: XLEN
+writable: true
+description: |
+  This register provides access to the trigger selected by `tselect`.
+  The reset values listed here apply to every underlying trigger.
+
+  This register is optional if no triggers are implemented, or if `type` is not writable
+  and `version` would be 0. In this case the debugger can read the only supported type
+  from `tdata1`.
+
+  Writing this read/write CSR has no effect.
+definedBy:
+  extension:
+    name: Sdtrig
+fields:
+  VERSION:
+    location: 31-24
+    description: |
+      Contains the version of the Sdtrig extension implemented.
+
+      0 (0):: Supports triggers as described in this spec at commit 5a5c078, made on
+      February 2, 2023.
+
+      1 (1):: Supports triggers as described in the ratified version 1.0 of this document.
+    type: RO
+    reset_value: UNDEFINED_LEGAL
+  TYPES:
+    location: 15-0
+    description: |
+      One bit for each possible `type` enumerated in `tdata1`. Bit N corresponds to type N.
+      If the bit is set, then that type is supported by the currently selected trigger.
+
+      If the currently selected trigger doesn't exist, this field contains 1.
+    type: RO
+    reset_value: UNDEFINED_LEGAL

data/.data/spec/std/isa/ext/Smctr.yaml

@@ -51,7 +51,7 @@ requirements:
   extension:
     allOf:
       - name: S
-        version: ~> 1.13 # The latest ratified version of S when Sscntr was ratified
+        version: ~> 1.13 # The latest ratified version of S when Ssctr was ratified
       - name: Smcsrind
         version: ~> 1.0
       - name: Ssctr

data/.data/spec/std/isa/ext/Ssctr.yaml

@@ -18,6 +18,6 @@ requirements:
   extension:
     allOf:
       - name: S
-        version: ~> 1.13 # The latest ratified version of S when Sscntr was ratified
+        version: ~> 1.13 # The latest ratified version of S when Ssctr was ratified
       - name: Sscsrind
         version: ~> 1.0

data/.data/spec/std/isa/ext/Ssstrict.yaml

@@ -43,9 +43,9 @@ versions:
 requirements:
   allOf:
     - param:
-        name: TRAP_ON_UNIMPLEMENTED_INSTRUCTION
+        name: TRAP_ON_RESERVED_INSTRUCTION
         equal: true
-        reason: Ssstrict requires unimplemented opcodes to trap
+        reason: Ssstrict requires unimplemented opcodes in the standard or reserved encoding spaces to trap
     - param:
         name: TRAP_ON_UNIMPLEMENTED_CSR
         equal: true

data/.data/spec/std/isa/ext/Sv32.yaml

@@ -6,8 +6,8 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Sv32
-long_name: 32-bit virtual address translation (3 level)
-description: 32-bit virtual address translation (3 level)
+long_name: 32-bit virtual address translation (2 level)
+description: 32-bit virtual address translation (2 level)
 type: privileged
 versions:
   - version: "1.0"

data/.data/spec/std/isa/ext/Svpbmt.yaml

@@ -8,8 +8,8 @@ kind: extension
 name: Svpbmt
 long_name: Page-based memory types
 description: |
-  This extension mandates that the `satp` mode Bare must
-  be supported.
+  This extension specifies page-based memory types, adding the PBMT field
+  to page-table entries to control memory type, cacheability, and ordering attributes.
 type: privileged
 versions:
   - version: "1.0.0"

data/.data/spec/std/isa/ext/Zaamo.yaml

@@ -6,7 +6,7 @@
 $schema: "ext_schema.json#"
 kind: extension
 name: Zaamo
-long_name: Load-acquire/Store-release atomic instructions
+long_name: Atomic Memory Operations
 type: unprivileged
 versions:
   - version: "1.0.0"

data/.data/spec/std/isa/ext/Zbc.yaml

@@ -17,6 +17,10 @@ versions:
   - version: "1.0.0"
     state: ratified
     ratification_date: 2021-06
+    requirements:
+      extension:
+        name: Zbkc
+        version: "~> 1.0.0"
     repositories:
       - url: https://github.com/riscv/riscv-bitmanip
         branch: main