udb 0.1.16 → 0.1.17

data/.data/spec/std/isa/inst/Zalrsc/lr.w.aq.yaml

@@ -76,12 +76,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
 
   if (!is_naturally_aligned(32, virtual_address)) {
@@ -103,8 +97,4 @@ operation(): |
   }
 
   XReg load_value = load_reserved(32, virtual_address, aq, rl, $encoding);
-  if (xlen() == 64) {
-    X[xd] = load_value;
-  } else {
-    X[xd] = sext(load_value[31:0], 32);
-  }
+  X[xd] = sext(load_value[31:0], 32);

data/.data/spec/std/isa/inst/Zalrsc/lr.w.aqrl.yaml

@@ -76,12 +76,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
 
   if (!is_naturally_aligned(32, virtual_address)) {
@@ -103,8 +97,4 @@ operation(): |
   }
 
   XReg load_value = load_reserved(32, virtual_address, aq, rl, $encoding);
-  if (xlen() == 64) {
-    X[xd] = load_value;
-  } else {
-    X[xd] = sext(load_value[31:0], 32);
-  }
+  X[xd] = sext(load_value[31:0], 32);

data/.data/spec/std/isa/inst/Zalrsc/lr.w.rl.yaml

@@ -76,12 +76,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
 
   if (!is_naturally_aligned(32, virtual_address)) {
@@ -103,8 +97,4 @@ operation(): |
   }
 
   XReg load_value = load_reserved(32, virtual_address, aq, rl, $encoding);
-  if (xlen() == 64) {
-    X[xd] = load_value;
-  } else {
-    X[xd] = sext(load_value[31:0], 32);
-  }
+  X[xd] = sext(load_value[31:0], 32);

data/.data/spec/std/isa/inst/Zalrsc/lr.w.yaml

@@ -76,12 +76,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
 
   if (!is_naturally_aligned(32, virtual_address)) {
@@ -103,8 +97,4 @@ operation(): |
   }
 
   XReg load_value = load_reserved(32, virtual_address, aq, rl, $encoding);
-  if (xlen() == 64) {
-    X[xd] = load_value;
-  } else {
-    X[xd] = sext(load_value[31:0], 32);
-  }
+  X[xd] = sext(load_value[31:0], 32);

data/.data/spec/std/isa/inst/Zalrsc/sc.SIZE.AQRL.layout

@@ -175,17 +175,11 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
 
   if (!is_naturally_aligned(<%= current_size[:align_bits] %>, virtual_address)) {
-    # can raise either LoadAddressMisaligned *or* LoadAccessFault
+    # can raise either StoreAmoAddressMisaligned *or* StoreAmoAccessFault
     #
     # from the spec:
     #   If the address is not naturally aligned, an address-misaligned exception or
@@ -194,11 +188,11 @@ operation(): |
     #   for the misalignment, if the misaligned access should not be emulated.
 
     if (LRSC_MISALIGNED_BEHAVIOR == "always raise misaligned exception") {
-      raise(ExceptionCode::LoadAddressMisaligned, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAddressMisaligned, effective_ldst_mode(), virtual_address);
     } else if (LRSC_MISALIGNED_BEHAVIOR == "always raise access fault") {
-      raise(ExceptionCode::LoadAccessFault, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAccessFault, effective_ldst_mode(), virtual_address);
     } else {
-      unpredictable("Implementations may raise either a LoadAddressMisaligned or a LoadAccessFault when an LR/SC address is misaligned");
+      unpredictable("Implementations may raise either a StoreAmoAddressMisaligned or a StoreAmoAccessFault when an SC address is misaligned");
     }
   }
 

data/.data/spec/std/isa/inst/Zalrsc/sc.d.aq.yaml

@@ -132,17 +132,11 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
 
   if (!is_naturally_aligned(64, virtual_address)) {
-    # can raise either LoadAddressMisaligned *or* LoadAccessFault
+    # can raise either StoreAmoAddressMisaligned *or* StoreAmoAccessFault
     #
     # from the spec:
     #   If the address is not naturally aligned, an address-misaligned exception or
@@ -151,11 +145,11 @@ operation(): |
     #   for the misalignment, if the misaligned access should not be emulated.
 
     if (LRSC_MISALIGNED_BEHAVIOR == "always raise misaligned exception") {
-      raise(ExceptionCode::LoadAddressMisaligned, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAddressMisaligned, effective_ldst_mode(), virtual_address);
     } else if (LRSC_MISALIGNED_BEHAVIOR == "always raise access fault") {
-      raise(ExceptionCode::LoadAccessFault, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAccessFault, effective_ldst_mode(), virtual_address);
     } else {
-      unpredictable("Implementations may raise either a LoadAddressMisaligned or a LoadAccessFault when an LR/SC address is misaligned");
+      unpredictable("Implementations may raise either a StoreAmoAddressMisaligned or a StoreAmoAccessFault when an SC address is misaligned");
     }
   }
 

data/.data/spec/std/isa/inst/Zalrsc/sc.d.aqrl.yaml

@@ -132,17 +132,11 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
 
   if (!is_naturally_aligned(64, virtual_address)) {
-    # can raise either LoadAddressMisaligned *or* LoadAccessFault
+    # can raise either StoreAmoAddressMisaligned *or* StoreAmoAccessFault
     #
     # from the spec:
     #   If the address is not naturally aligned, an address-misaligned exception or
@@ -151,11 +145,11 @@ operation(): |
     #   for the misalignment, if the misaligned access should not be emulated.
 
     if (LRSC_MISALIGNED_BEHAVIOR == "always raise misaligned exception") {
-      raise(ExceptionCode::LoadAddressMisaligned, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAddressMisaligned, effective_ldst_mode(), virtual_address);
     } else if (LRSC_MISALIGNED_BEHAVIOR == "always raise access fault") {
-      raise(ExceptionCode::LoadAccessFault, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAccessFault, effective_ldst_mode(), virtual_address);
     } else {
-      unpredictable("Implementations may raise either a LoadAddressMisaligned or a LoadAccessFault when an LR/SC address is misaligned");
+      unpredictable("Implementations may raise either a StoreAmoAddressMisaligned or a StoreAmoAccessFault when an SC address is misaligned");
     }
   }
 

data/.data/spec/std/isa/inst/Zalrsc/sc.d.rl.yaml

@@ -132,17 +132,11 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
 
   if (!is_naturally_aligned(64, virtual_address)) {
-    # can raise either LoadAddressMisaligned *or* LoadAccessFault
+    # can raise either StoreAmoAddressMisaligned *or* StoreAmoAccessFault
     #
     # from the spec:
     #   If the address is not naturally aligned, an address-misaligned exception or
@@ -151,11 +145,11 @@ operation(): |
     #   for the misalignment, if the misaligned access should not be emulated.
 
     if (LRSC_MISALIGNED_BEHAVIOR == "always raise misaligned exception") {
-      raise(ExceptionCode::LoadAddressMisaligned, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAddressMisaligned, effective_ldst_mode(), virtual_address);
     } else if (LRSC_MISALIGNED_BEHAVIOR == "always raise access fault") {
-      raise(ExceptionCode::LoadAccessFault, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAccessFault, effective_ldst_mode(), virtual_address);
     } else {
-      unpredictable("Implementations may raise either a LoadAddressMisaligned or a LoadAccessFault when an LR/SC address is misaligned");
+      unpredictable("Implementations may raise either a StoreAmoAddressMisaligned or a StoreAmoAccessFault when an SC address is misaligned");
     }
   }
 

data/.data/spec/std/isa/inst/Zalrsc/sc.d.yaml

@@ -132,17 +132,11 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
 
   if (!is_naturally_aligned(64, virtual_address)) {
-    # can raise either LoadAddressMisaligned *or* LoadAccessFault
+    # can raise either StoreAmoAddressMisaligned *or* StoreAmoAccessFault
     #
     # from the spec:
     #   If the address is not naturally aligned, an address-misaligned exception or
@@ -151,11 +145,11 @@ operation(): |
     #   for the misalignment, if the misaligned access should not be emulated.
 
     if (LRSC_MISALIGNED_BEHAVIOR == "always raise misaligned exception") {
-      raise(ExceptionCode::LoadAddressMisaligned, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAddressMisaligned, effective_ldst_mode(), virtual_address);
     } else if (LRSC_MISALIGNED_BEHAVIOR == "always raise access fault") {
-      raise(ExceptionCode::LoadAccessFault, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAccessFault, effective_ldst_mode(), virtual_address);
     } else {
-      unpredictable("Implementations may raise either a LoadAddressMisaligned or a LoadAccessFault when an LR/SC address is misaligned");
+      unpredictable("Implementations may raise either a StoreAmoAddressMisaligned or a StoreAmoAccessFault when an SC address is misaligned");
     }
   }
 

data/.data/spec/std/isa/inst/Zalrsc/sc.w.aq.yaml

@@ -134,17 +134,11 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
 
   if (!is_naturally_aligned(32, virtual_address)) {
-    # can raise either LoadAddressMisaligned *or* LoadAccessFault
+    # can raise either StoreAmoAddressMisaligned *or* StoreAmoAccessFault
     #
     # from the spec:
     #   If the address is not naturally aligned, an address-misaligned exception or
@@ -153,11 +147,11 @@ operation(): |
     #   for the misalignment, if the misaligned access should not be emulated.
 
     if (LRSC_MISALIGNED_BEHAVIOR == "always raise misaligned exception") {
-      raise(ExceptionCode::LoadAddressMisaligned, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAddressMisaligned, effective_ldst_mode(), virtual_address);
     } else if (LRSC_MISALIGNED_BEHAVIOR == "always raise access fault") {
-      raise(ExceptionCode::LoadAccessFault, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAccessFault, effective_ldst_mode(), virtual_address);
     } else {
-      unpredictable("Implementations may raise either a LoadAddressMisaligned or a LoadAccessFault when an LR/SC address is misaligned");
+      unpredictable("Implementations may raise either a StoreAmoAddressMisaligned or a StoreAmoAccessFault when an SC address is misaligned");
     }
   }
 

data/.data/spec/std/isa/inst/Zalrsc/sc.w.aqrl.yaml

@@ -134,17 +134,11 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
 
   if (!is_naturally_aligned(32, virtual_address)) {
-    # can raise either LoadAddressMisaligned *or* LoadAccessFault
+    # can raise either StoreAmoAddressMisaligned *or* StoreAmoAccessFault
     #
     # from the spec:
     #   If the address is not naturally aligned, an address-misaligned exception or
@@ -153,11 +147,11 @@ operation(): |
     #   for the misalignment, if the misaligned access should not be emulated.
 
     if (LRSC_MISALIGNED_BEHAVIOR == "always raise misaligned exception") {
-      raise(ExceptionCode::LoadAddressMisaligned, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAddressMisaligned, effective_ldst_mode(), virtual_address);
     } else if (LRSC_MISALIGNED_BEHAVIOR == "always raise access fault") {
-      raise(ExceptionCode::LoadAccessFault, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAccessFault, effective_ldst_mode(), virtual_address);
     } else {
-      unpredictable("Implementations may raise either a LoadAddressMisaligned or a LoadAccessFault when an LR/SC address is misaligned");
+      unpredictable("Implementations may raise either a StoreAmoAddressMisaligned or a StoreAmoAccessFault when an SC address is misaligned");
     }
   }
 

data/.data/spec/std/isa/inst/Zalrsc/sc.w.rl.yaml

@@ -134,17 +134,11 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
 
   if (!is_naturally_aligned(32, virtual_address)) {
-    # can raise either LoadAddressMisaligned *or* LoadAccessFault
+    # can raise either StoreAmoAddressMisaligned *or* StoreAmoAccessFault
     #
     # from the spec:
     #   If the address is not naturally aligned, an address-misaligned exception or
@@ -153,11 +147,11 @@ operation(): |
     #   for the misalignment, if the misaligned access should not be emulated.
 
     if (LRSC_MISALIGNED_BEHAVIOR == "always raise misaligned exception") {
-      raise(ExceptionCode::LoadAddressMisaligned, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAddressMisaligned, effective_ldst_mode(), virtual_address);
     } else if (LRSC_MISALIGNED_BEHAVIOR == "always raise access fault") {
-      raise(ExceptionCode::LoadAccessFault, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAccessFault, effective_ldst_mode(), virtual_address);
     } else {
-      unpredictable("Implementations may raise either a LoadAddressMisaligned or a LoadAccessFault when an LR/SC address is misaligned");
+      unpredictable("Implementations may raise either a StoreAmoAddressMisaligned or a StoreAmoAccessFault when an SC address is misaligned");
     }
   }
 

data/.data/spec/std/isa/inst/Zalrsc/sc.w.yaml

@@ -134,17 +134,11 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) {
-    # even though this is a memory operation, the exception occurs before that would be known,
-    # so mode() is the correct reporting mode rathat than effective_ldst_mode()
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg virtual_address = X[xs1];
   XReg value = X[xs2];
 
   if (!is_naturally_aligned(32, virtual_address)) {
-    # can raise either LoadAddressMisaligned *or* LoadAccessFault
+    # can raise either StoreAmoAddressMisaligned *or* StoreAmoAccessFault
     #
     # from the spec:
     #   If the address is not naturally aligned, an address-misaligned exception or
@@ -153,11 +147,11 @@ operation(): |
     #   for the misalignment, if the misaligned access should not be emulated.
 
     if (LRSC_MISALIGNED_BEHAVIOR == "always raise misaligned exception") {
-      raise(ExceptionCode::LoadAddressMisaligned, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAddressMisaligned, effective_ldst_mode(), virtual_address);
     } else if (LRSC_MISALIGNED_BEHAVIOR == "always raise access fault") {
-      raise(ExceptionCode::LoadAccessFault, effective_ldst_mode(), virtual_address);
+      raise(ExceptionCode::StoreAmoAccessFault, effective_ldst_mode(), virtual_address);
     } else {
-      unpredictable("Implementations may raise either a LoadAddressMisaligned or a LoadAccessFault when an LR/SC address is misaligned");
+      unpredictable("Implementations may raise either a StoreAmoAddressMisaligned or a StoreAmoAccessFault when an SC address is misaligned");
     }
   }
 

data/.data/spec/std/isa/inst/Zba/add.uw.yaml

@@ -34,8 +34,4 @@ pseudoinstructions:
   - when: xs2 == 0
     to: zext.w xd, xs1
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   X[xd] = X[xs2] + X[xs1][31:0];

data/.data/spec/std/isa/inst/Zba/sh1add.uw.yaml

@@ -32,8 +32,4 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   X[xd] = X[xs2] + (X[xs1][31:0] << 1);

data/.data/spec/std/isa/inst/Zba/sh1add.yaml

@@ -28,8 +28,4 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   X[xd] = X[xs2] + (X[xs1] << 1);

data/.data/spec/std/isa/inst/Zba/sh2add.uw.yaml

@@ -32,8 +32,4 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   X[xd] = X[xs2] + (X[xs1][31:0] << 2);

data/.data/spec/std/isa/inst/Zba/sh2add.yaml

@@ -28,8 +28,4 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   X[xd] = X[xs2] + (X[xs1] << 2);

data/.data/spec/std/isa/inst/Zba/sh3add.uw.yaml

@@ -32,8 +32,4 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   X[xd] = X[xs2] + (X[xs1][31:0] << 3);

data/.data/spec/std/isa/inst/Zba/sh3add.yaml

@@ -28,8 +28,4 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   X[xd] = X[xs2] + (X[xs1] << 3);

data/.data/spec/std/isa/inst/Zba/slli.uw.yaml

@@ -34,8 +34,4 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   X[xd] = X[xs1][31:0] << shamt;

data/.data/spec/std/isa/inst/Zbb/clz.yaml

@@ -29,8 +29,4 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   X[xd] = (xlen() - 1) - $signed(highest_set_bit(X[xs1]));

data/.data/spec/std/isa/inst/Zbb/clzw.yaml

@@ -30,8 +30,4 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   X[xd] = 31 - $signed(highest_set_bit(X[xs1][31:0]));

data/.data/spec/std/isa/inst/Zbb/cpop.yaml

@@ -38,10 +38,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg bitcount = 0;
   XReg xs1_val = X[xs1];
 

data/.data/spec/std/isa/inst/Zbb/cpopw.yaml

@@ -40,10 +40,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg bitcount = 0;
   XReg xs1_val = X[xs1];
 

data/.data/spec/std/isa/inst/Zbb/ctz.yaml

@@ -30,10 +30,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   if (xlen() == 32) {
     X[xd] = lowest_set_bit(X[xs1][31:0]);
   } else {

data/.data/spec/std/isa/inst/Zbb/ctzw.yaml

@@ -32,10 +32,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   # lowest_set_bit() reports xlen() (64 here) for a zero input, but ctzw must report 32
   if (X[xs1][31:0] == 0) {
     X[xd] = 32;

data/.data/spec/std/isa/inst/Zbb/max.yaml

@@ -36,8 +36,4 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   X[xd] = ($signed(X[xs1]) > $signed(X[xs2])) ? X[xs1] : X[xs2];

data/.data/spec/std/isa/inst/Zbb/maxu.yaml

@@ -28,8 +28,4 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   X[xd] = (X[xs1] > X[xs2]) ? X[xs1] : X[xs2];

data/.data/spec/std/isa/inst/Zbb/min.yaml

@@ -28,8 +28,4 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   X[xd] = ($signed(X[xs1]) < $signed(X[xs2])) ? X[xs1] : X[xs2];

data/.data/spec/std/isa/inst/Zbb/minu.yaml

@@ -28,8 +28,4 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   X[xd] = (X[xs1] < X[xs2]) ? X[xs1] : X[xs2];

data/.data/spec/std/isa/inst/Zbb/orc.b.yaml

@@ -28,10 +28,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg input = X[xs1];
   XReg output = 0;
 

data/.data/spec/std/isa/inst/Zbb/sext.b.yaml

@@ -27,10 +27,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   if (xlen() == 32) {
     X[xd] = {{24{X[xs1][7]}}, X[xs1][7:0]};
   } else if (xlen() == 64) {

data/.data/spec/std/isa/inst/Zbb/sext.h.yaml

@@ -27,10 +27,6 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   if (xlen() == 32) {
     X[xd] = {{16{X[xs1][15]}}, X[xs1][15:0]};
   } else if (xlen() == 64) {

data/.data/spec/std/isa/inst/Zbb/zext.h.yaml

@@ -45,8 +45,4 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   X[xd] = X[xs1][15:0];

data/.data/spec/std/isa/inst/Zbc/clmulr.yaml

@@ -28,10 +28,6 @@ encoding:
     - name: xd
       location: 11-7
 operation(): |
-  if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
-    raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
-  }
-
   XReg xs1_val = X[xs1];
   XReg xs2_val = X[xs2];
   XReg output = 0;