udb 0.1.16 → 0.1.17

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (604) hide show
  1. checksums.yaml +4 -4
  2. data/.data/cfgs/example_rv64_with_overlay.yaml +20 -0
  3. data/.data/cfgs/mc100-32-full-example.yaml +6 -0
  4. data/.data/cfgs/qc_iu.yaml +14 -0
  5. data/.data/cfgs/rv32-riscv-tests.yaml +9 -0
  6. data/.data/cfgs/rv32-vector.yaml +10 -1
  7. data/.data/cfgs/rv64-riscv-tests.yaml +9 -0
  8. data/.data/cfgs/rv64-vector.yaml +11 -2
  9. data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.mva01s.yaml +2 -2
  10. data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.mvsa01.yaml +2 -2
  11. data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.pop.yaml +2 -2
  12. data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.popret.yaml +2 -2
  13. data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.popretz.yaml +2 -2
  14. data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.push.yaml +2 -2
  15. data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.pushfp.yaml +2 -2
  16. data/.data/spec/schemas/README.adoc +4 -1
  17. data/.data/spec/schemas/csr_schema.json +2 -2
  18. data/.data/spec/std/isa/csr/H/hgeie.yaml +38 -0
  19. data/.data/spec/std/isa/csr/H/hgeip.yaml +33 -0
  20. data/.data/spec/std/isa/csr/H/hideleg.yaml +120 -0
  21. data/.data/spec/std/isa/csr/H/hie.yaml +74 -0
  22. data/.data/spec/std/isa/csr/H/hip.yaml +88 -0
  23. data/.data/spec/std/isa/csr/H/hvip.yaml +46 -0
  24. data/.data/spec/std/isa/csr/H/vsie.yaml +86 -0
  25. data/.data/spec/std/isa/csr/H/vsip.yaml +98 -0
  26. data/.data/spec/std/isa/csr/H/vsscratch.yaml +29 -0
  27. data/.data/spec/std/isa/csr/I/pmpaddr0.yaml +7 -7
  28. data/.data/spec/std/isa/csr/I/pmpaddr1.yaml +7 -7
  29. data/.data/spec/std/isa/csr/I/pmpaddr10.yaml +7 -7
  30. data/.data/spec/std/isa/csr/I/pmpaddr11.yaml +7 -7
  31. data/.data/spec/std/isa/csr/I/pmpaddr12.yaml +7 -7
  32. data/.data/spec/std/isa/csr/I/pmpaddr13.yaml +7 -7
  33. data/.data/spec/std/isa/csr/I/pmpaddr14.yaml +7 -7
  34. data/.data/spec/std/isa/csr/I/pmpaddr15.yaml +7 -7
  35. data/.data/spec/std/isa/csr/I/pmpaddr16.yaml +7 -7
  36. data/.data/spec/std/isa/csr/I/pmpaddr17.yaml +7 -7
  37. data/.data/spec/std/isa/csr/I/pmpaddr18.yaml +7 -7
  38. data/.data/spec/std/isa/csr/I/pmpaddr19.yaml +7 -7
  39. data/.data/spec/std/isa/csr/I/pmpaddr2.yaml +7 -7
  40. data/.data/spec/std/isa/csr/I/pmpaddr20.yaml +7 -7
  41. data/.data/spec/std/isa/csr/I/pmpaddr21.yaml +7 -7
  42. data/.data/spec/std/isa/csr/I/pmpaddr22.yaml +7 -7
  43. data/.data/spec/std/isa/csr/I/pmpaddr23.yaml +7 -7
  44. data/.data/spec/std/isa/csr/I/pmpaddr24.yaml +7 -7
  45. data/.data/spec/std/isa/csr/I/pmpaddr25.yaml +7 -7
  46. data/.data/spec/std/isa/csr/I/pmpaddr26.yaml +7 -7
  47. data/.data/spec/std/isa/csr/I/pmpaddr27.yaml +7 -7
  48. data/.data/spec/std/isa/csr/I/pmpaddr28.yaml +7 -7
  49. data/.data/spec/std/isa/csr/I/pmpaddr29.yaml +7 -7
  50. data/.data/spec/std/isa/csr/I/pmpaddr3.yaml +7 -7
  51. data/.data/spec/std/isa/csr/I/pmpaddr30.yaml +7 -7
  52. data/.data/spec/std/isa/csr/I/pmpaddr31.yaml +7 -7
  53. data/.data/spec/std/isa/csr/I/pmpaddr32.yaml +7 -7
  54. data/.data/spec/std/isa/csr/I/pmpaddr33.yaml +7 -7
  55. data/.data/spec/std/isa/csr/I/pmpaddr34.yaml +7 -7
  56. data/.data/spec/std/isa/csr/I/pmpaddr35.yaml +7 -7
  57. data/.data/spec/std/isa/csr/I/pmpaddr36.yaml +7 -7
  58. data/.data/spec/std/isa/csr/I/pmpaddr37.yaml +7 -7
  59. data/.data/spec/std/isa/csr/I/pmpaddr38.yaml +7 -7
  60. data/.data/spec/std/isa/csr/I/pmpaddr39.yaml +7 -7
  61. data/.data/spec/std/isa/csr/I/pmpaddr4.yaml +7 -7
  62. data/.data/spec/std/isa/csr/I/pmpaddr40.yaml +7 -7
  63. data/.data/spec/std/isa/csr/I/pmpaddr41.yaml +7 -7
  64. data/.data/spec/std/isa/csr/I/pmpaddr42.yaml +7 -7
  65. data/.data/spec/std/isa/csr/I/pmpaddr43.yaml +7 -7
  66. data/.data/spec/std/isa/csr/I/pmpaddr44.yaml +7 -7
  67. data/.data/spec/std/isa/csr/I/pmpaddr45.yaml +7 -7
  68. data/.data/spec/std/isa/csr/I/pmpaddr46.yaml +7 -7
  69. data/.data/spec/std/isa/csr/I/pmpaddr47.yaml +7 -7
  70. data/.data/spec/std/isa/csr/I/pmpaddr48.yaml +7 -7
  71. data/.data/spec/std/isa/csr/I/pmpaddr49.yaml +7 -7
  72. data/.data/spec/std/isa/csr/I/pmpaddr5.yaml +7 -7
  73. data/.data/spec/std/isa/csr/I/pmpaddr50.yaml +7 -7
  74. data/.data/spec/std/isa/csr/I/pmpaddr51.yaml +7 -7
  75. data/.data/spec/std/isa/csr/I/pmpaddr52.yaml +7 -7
  76. data/.data/spec/std/isa/csr/I/pmpaddr53.yaml +7 -7
  77. data/.data/spec/std/isa/csr/I/pmpaddr54.yaml +7 -7
  78. data/.data/spec/std/isa/csr/I/pmpaddr55.yaml +7 -7
  79. data/.data/spec/std/isa/csr/I/pmpaddr56.yaml +7 -7
  80. data/.data/spec/std/isa/csr/I/pmpaddr57.yaml +7 -7
  81. data/.data/spec/std/isa/csr/I/pmpaddr58.yaml +7 -7
  82. data/.data/spec/std/isa/csr/I/pmpaddr59.yaml +7 -7
  83. data/.data/spec/std/isa/csr/I/pmpaddr6.yaml +7 -7
  84. data/.data/spec/std/isa/csr/I/pmpaddr60.yaml +7 -7
  85. data/.data/spec/std/isa/csr/I/pmpaddr61.yaml +7 -7
  86. data/.data/spec/std/isa/csr/I/pmpaddr62.yaml +7 -7
  87. data/.data/spec/std/isa/csr/I/pmpaddr63.yaml +7 -7
  88. data/.data/spec/std/isa/csr/I/pmpaddr7.yaml +7 -7
  89. data/.data/spec/std/isa/csr/I/pmpaddr8.yaml +7 -7
  90. data/.data/spec/std/isa/csr/I/pmpaddr9.yaml +7 -7
  91. data/.data/spec/std/isa/csr/I/pmpaddrN.layout +7 -7
  92. data/.data/spec/std/isa/csr/Smcsrind/mireg.yaml +2 -2
  93. data/.data/spec/std/isa/csr/Smcsrind/mireg2.yaml +2 -2
  94. data/.data/spec/std/isa/csr/Smcsrind/mireg3.yaml +2 -2
  95. data/.data/spec/std/isa/csr/Smcsrind/mireg4.yaml +2 -2
  96. data/.data/spec/std/isa/csr/Smcsrind/mireg5.yaml +2 -2
  97. data/.data/spec/std/isa/csr/Smcsrind/mireg6.yaml +2 -2
  98. data/.data/spec/std/isa/csr/Smcsrind/sireg.yaml +2 -2
  99. data/.data/spec/std/isa/csr/Smcsrind/sireg2.yaml +2 -2
  100. data/.data/spec/std/isa/csr/Smcsrind/sireg3.yaml +2 -2
  101. data/.data/spec/std/isa/csr/Smcsrind/sireg4.yaml +2 -2
  102. data/.data/spec/std/isa/csr/Smcsrind/sireg5.yaml +2 -2
  103. data/.data/spec/std/isa/csr/Smcsrind/sireg6.yaml +2 -2
  104. data/.data/spec/std/isa/csr/Smcsrind/vsireg.yaml +2 -2
  105. data/.data/spec/std/isa/csr/Smcsrind/vsireg2.yaml +2 -2
  106. data/.data/spec/std/isa/csr/Smcsrind/vsireg3.yaml +2 -2
  107. data/.data/spec/std/isa/csr/Smcsrind/vsireg4.yaml +2 -2
  108. data/.data/spec/std/isa/csr/Smcsrind/vsireg5.yaml +2 -2
  109. data/.data/spec/std/isa/csr/Smcsrind/vsireg6.yaml +2 -2
  110. data/.data/spec/std/isa/csr/Smctr/sctrctl.yaml +1 -1
  111. data/.data/spec/std/isa/csr/Smctr/sctrdepth.yaml +43 -0
  112. data/.data/spec/std/isa/csr/Smctr/sctrstatus.yaml +37 -0
  113. data/.data/spec/std/isa/csr/Smctr/vsctrctl.yaml +3 -1
  114. data/.data/spec/std/isa/csr/Sstc/stimecmp.yaml +42 -0
  115. data/.data/spec/std/isa/csr/Sstc/stimecmph.yaml +43 -0
  116. data/.data/spec/std/isa/csr/Sstc/vstimecmp.yaml +45 -0
  117. data/.data/spec/std/isa/csr/Sstc/vstimecmph.yaml +46 -0
  118. data/.data/spec/std/isa/csr/V/vcsr.yaml +1 -1
  119. data/.data/spec/std/isa/csr/V/vl.yaml +1 -1
  120. data/.data/spec/std/isa/csr/V/vlenb.yaml +1 -1
  121. data/.data/spec/std/isa/csr/V/vstart.yaml +1 -1
  122. data/.data/spec/std/isa/csr/V/vtype.yaml +20 -1
  123. data/.data/spec/std/isa/csr/V/vxrm.yaml +1 -1
  124. data/.data/spec/std/isa/csr/V/vxsat.yaml +1 -1
  125. data/.data/spec/std/isa/csr/Zicntr/mcountinhibit.layout +1 -15
  126. data/.data/spec/std/isa/csr/Zicntr/mcountinhibit.yaml +29 -267
  127. data/.data/spec/std/isa/csr/mideleg.yaml +57 -9
  128. data/.data/spec/std/isa/csr/mie.yaml +18 -9
  129. data/.data/spec/std/isa/csr/mip.yaml +21 -10
  130. data/.data/spec/std/isa/csr/misa.yaml +11 -7
  131. data/.data/spec/std/isa/csr/mstatus.yaml +2 -2
  132. data/.data/spec/std/isa/csr/schema.adoc +10 -4
  133. data/.data/spec/std/isa/csr/senvcfg.yaml +6 -12
  134. data/.data/spec/std/isa/csr/sstateen0.yaml +1 -1
  135. data/.data/spec/std/isa/csr/sstateen1.yaml +2 -3
  136. data/.data/spec/std/isa/csr/sstateen2.yaml +2 -3
  137. data/.data/spec/std/isa/csr/sstateen3.yaml +2 -3
  138. data/.data/spec/std/isa/csr/tcontrol.yaml +37 -0
  139. data/.data/spec/std/isa/csr/tinfo.yaml +44 -0
  140. data/.data/spec/std/isa/ext/Smctr.yaml +1 -1
  141. data/.data/spec/std/isa/ext/Ssctr.yaml +1 -1
  142. data/.data/spec/std/isa/ext/Ssstrict.yaml +2 -2
  143. data/.data/spec/std/isa/ext/Sv32.yaml +2 -2
  144. data/.data/spec/std/isa/ext/Svpbmt.yaml +2 -2
  145. data/.data/spec/std/isa/ext/Zaamo.yaml +1 -1
  146. data/.data/spec/std/isa/ext/Zbc.yaml +4 -0
  147. data/.data/spec/std/isa/ext/Zvfbfa.yaml +24 -0
  148. data/.data/spec/std/isa/ext/Zvfofp4min.yaml +21 -0
  149. data/.data/spec/std/isa/ext/Zvfofp8min.yaml +20 -0
  150. data/.data/spec/std/isa/inst/B/andn.yaml +0 -4
  151. data/.data/spec/std/isa/inst/B/orn.yaml +0 -4
  152. data/.data/spec/std/isa/inst/B/rev8.yaml +0 -4
  153. data/.data/spec/std/isa/inst/B/rol.yaml +0 -4
  154. data/.data/spec/std/isa/inst/B/rolw.yaml +0 -4
  155. data/.data/spec/std/isa/inst/B/ror.yaml +0 -4
  156. data/.data/spec/std/isa/inst/B/rori.yaml +0 -4
  157. data/.data/spec/std/isa/inst/B/roriw.yaml +0 -4
  158. data/.data/spec/std/isa/inst/B/rorw.yaml +0 -4
  159. data/.data/spec/std/isa/inst/B/xnor.yaml +0 -4
  160. data/.data/spec/std/isa/inst/C/c.addi.yaml +2 -2
  161. data/.data/spec/std/isa/inst/C/c.addi16sp.yaml +2 -2
  162. data/.data/spec/std/isa/inst/C/c.addi4spn.yaml +2 -2
  163. data/.data/spec/std/isa/inst/C/c.addiw.yaml +2 -2
  164. data/.data/spec/std/isa/inst/C/c.beqz.yaml +2 -2
  165. data/.data/spec/std/isa/inst/C/c.bnez.yaml +2 -2
  166. data/.data/spec/std/isa/inst/C/c.ebreak.yaml +2 -2
  167. data/.data/spec/std/isa/inst/C/c.j.yaml +2 -2
  168. data/.data/spec/std/isa/inst/C/c.jal.yaml +2 -2
  169. data/.data/spec/std/isa/inst/C/c.jalr.yaml +2 -2
  170. data/.data/spec/std/isa/inst/C/c.jr.yaml +2 -2
  171. data/.data/spec/std/isa/inst/C/c.ld.yaml +2 -2
  172. data/.data/spec/std/isa/inst/C/c.ldsp.yaml +2 -2
  173. data/.data/spec/std/isa/inst/C/c.li.yaml +2 -2
  174. data/.data/spec/std/isa/inst/C/c.lui.yaml +2 -2
  175. data/.data/spec/std/isa/inst/C/c.lw.yaml +2 -2
  176. data/.data/spec/std/isa/inst/C/c.lwsp.yaml +2 -2
  177. data/.data/spec/std/isa/inst/C/c.mv.yaml +2 -2
  178. data/.data/spec/std/isa/inst/C/c.nop.yaml +2 -2
  179. data/.data/spec/std/isa/inst/C/c.sd.yaml +2 -2
  180. data/.data/spec/std/isa/inst/C/c.sdsp.yaml +5 -5
  181. data/.data/spec/std/isa/inst/C/c.sw.yaml +2 -2
  182. data/.data/spec/std/isa/inst/C/c.swsp.yaml +2 -2
  183. data/.data/spec/std/isa/inst/I/ld.yaml +9 -4
  184. data/.data/spec/std/isa/inst/I/sd.yaml +9 -4
  185. data/.data/spec/std/isa/inst/I/wfi.yaml +1 -1
  186. data/.data/spec/std/isa/inst/M/div.yaml +2 -2
  187. data/.data/spec/std/isa/inst/M/divu.yaml +2 -2
  188. data/.data/spec/std/isa/inst/M/divuw.yaml +2 -2
  189. data/.data/spec/std/isa/inst/M/divw.yaml +2 -2
  190. data/.data/spec/std/isa/inst/M/mul.yaml +0 -4
  191. data/.data/spec/std/isa/inst/M/mulh.yaml +0 -4
  192. data/.data/spec/std/isa/inst/M/mulhsu.yaml +0 -4
  193. data/.data/spec/std/isa/inst/M/mulhu.yaml +0 -4
  194. data/.data/spec/std/isa/inst/M/mulw.yaml +0 -4
  195. data/.data/spec/std/isa/inst/M/rem.yaml +2 -2
  196. data/.data/spec/std/isa/inst/M/remu.yaml +2 -2
  197. data/.data/spec/std/isa/inst/M/remuw.yaml +2 -2
  198. data/.data/spec/std/isa/inst/M/remw.yaml +2 -2
  199. data/.data/spec/std/isa/inst/V/vfadd.vf.yaml +3 -1
  200. data/.data/spec/std/isa/inst/V/vfadd.vv.yaml +3 -1
  201. data/.data/spec/std/isa/inst/V/vfclass.v.yaml +3 -1
  202. data/.data/spec/std/isa/inst/V/vfmacc.vf.yaml +3 -1
  203. data/.data/spec/std/isa/inst/V/vfmacc.vv.yaml +3 -1
  204. data/.data/spec/std/isa/inst/V/vfmadd.vf.yaml +3 -1
  205. data/.data/spec/std/isa/inst/V/vfmadd.vv.yaml +3 -1
  206. data/.data/spec/std/isa/inst/V/vfmax.vf.yaml +3 -1
  207. data/.data/spec/std/isa/inst/V/vfmax.vv.yaml +3 -1
  208. data/.data/spec/std/isa/inst/V/vfmerge.vfm.yaml +3 -1
  209. data/.data/spec/std/isa/inst/V/vfmin.vf.yaml +3 -1
  210. data/.data/spec/std/isa/inst/V/vfmin.vv.yaml +3 -1
  211. data/.data/spec/std/isa/inst/V/vfmsac.vf.yaml +3 -1
  212. data/.data/spec/std/isa/inst/V/vfmsac.vv.yaml +3 -1
  213. data/.data/spec/std/isa/inst/V/vfmsub.vf.yaml +3 -1
  214. data/.data/spec/std/isa/inst/V/vfmsub.vv.yaml +3 -1
  215. data/.data/spec/std/isa/inst/V/vfmul.vf.yaml +3 -1
  216. data/.data/spec/std/isa/inst/V/vfmul.vv.yaml +3 -1
  217. data/.data/spec/std/isa/inst/V/vfmv.f.s.yaml +3 -1
  218. data/.data/spec/std/isa/inst/V/vfmv.s.f.yaml +3 -1
  219. data/.data/spec/std/isa/inst/V/vfmv.v.f.yaml +3 -1
  220. data/.data/spec/std/isa/inst/V/vfncvt.f.f.w.yaml +3 -1
  221. data/.data/spec/std/isa/inst/V/vfncvt.rod.f.f.w.yaml +3 -1
  222. data/.data/spec/std/isa/inst/V/vfncvt.rtz.x.f.w.yaml +3 -1
  223. data/.data/spec/std/isa/inst/V/vfncvt.rtz.xu.f.w.yaml +3 -1
  224. data/.data/spec/std/isa/inst/V/vfncvt.x.f.w.yaml +3 -1
  225. data/.data/spec/std/isa/inst/V/vfncvt.xu.f.w.yaml +3 -1
  226. data/.data/spec/std/isa/inst/V/vfnmacc.vf.yaml +3 -1
  227. data/.data/spec/std/isa/inst/V/vfnmacc.vv.yaml +3 -1
  228. data/.data/spec/std/isa/inst/V/vfnmadd.vf.yaml +3 -1
  229. data/.data/spec/std/isa/inst/V/vfnmadd.vv.yaml +3 -1
  230. data/.data/spec/std/isa/inst/V/vfnmsac.vf.yaml +3 -1
  231. data/.data/spec/std/isa/inst/V/vfnmsac.vv.yaml +3 -1
  232. data/.data/spec/std/isa/inst/V/vfnmsub.vf.yaml +3 -1
  233. data/.data/spec/std/isa/inst/V/vfnmsub.vv.yaml +3 -1
  234. data/.data/spec/std/isa/inst/V/vfrec7.v.yaml +3 -1
  235. data/.data/spec/std/isa/inst/V/vfrsqrt7.v.yaml +3 -1
  236. data/.data/spec/std/isa/inst/V/vfrsub.vf.yaml +3 -1
  237. data/.data/spec/std/isa/inst/V/vfsgnj.vf.yaml +3 -1
  238. data/.data/spec/std/isa/inst/V/vfsgnj.vv.yaml +3 -1
  239. data/.data/spec/std/isa/inst/V/vfsgnjn.vf.yaml +3 -1
  240. data/.data/spec/std/isa/inst/V/vfsgnjn.vv.yaml +3 -1
  241. data/.data/spec/std/isa/inst/V/vfsgnjx.vf.yaml +3 -1
  242. data/.data/spec/std/isa/inst/V/vfsgnjx.vv.yaml +3 -1
  243. data/.data/spec/std/isa/inst/V/vfslide1down.vf.yaml +3 -1
  244. data/.data/spec/std/isa/inst/V/vfslide1up.vf.yaml +3 -1
  245. data/.data/spec/std/isa/inst/V/vfsub.vf.yaml +3 -1
  246. data/.data/spec/std/isa/inst/V/vfsub.vv.yaml +3 -1
  247. data/.data/spec/std/isa/inst/V/vfwadd.vf.yaml +3 -1
  248. data/.data/spec/std/isa/inst/V/vfwadd.vv.yaml +3 -1
  249. data/.data/spec/std/isa/inst/V/vfwadd.wf.yaml +3 -1
  250. data/.data/spec/std/isa/inst/V/vfwadd.wv.yaml +3 -1
  251. data/.data/spec/std/isa/inst/V/vfwcvt.f.f.v.yaml +3 -1
  252. data/.data/spec/std/isa/inst/V/vfwcvt.f.x.v.yaml +3 -1
  253. data/.data/spec/std/isa/inst/V/vfwcvt.f.xu.v.yaml +3 -1
  254. data/.data/spec/std/isa/inst/V/vfwmacc.vf.yaml +3 -1
  255. data/.data/spec/std/isa/inst/V/vfwmacc.vv.yaml +3 -1
  256. data/.data/spec/std/isa/inst/V/vfwmsac.vf.yaml +3 -1
  257. data/.data/spec/std/isa/inst/V/vfwmsac.vv.yaml +3 -1
  258. data/.data/spec/std/isa/inst/V/vfwmul.vf.yaml +3 -1
  259. data/.data/spec/std/isa/inst/V/vfwmul.vv.yaml +3 -1
  260. data/.data/spec/std/isa/inst/V/vfwnmacc.vf.yaml +3 -1
  261. data/.data/spec/std/isa/inst/V/vfwnmacc.vv.yaml +3 -1
  262. data/.data/spec/std/isa/inst/V/vfwnmsac.vf.yaml +3 -1
  263. data/.data/spec/std/isa/inst/V/vfwnmsac.vv.yaml +3 -1
  264. data/.data/spec/std/isa/inst/V/vfwsub.vf.yaml +3 -1
  265. data/.data/spec/std/isa/inst/V/vfwsub.vv.yaml +3 -1
  266. data/.data/spec/std/isa/inst/V/vfwsub.wf.yaml +3 -1
  267. data/.data/spec/std/isa/inst/V/vfwsub.wv.yaml +3 -1
  268. data/.data/spec/std/isa/inst/V/vmfeq.vf.yaml +3 -1
  269. data/.data/spec/std/isa/inst/V/vmfeq.vv.yaml +3 -1
  270. data/.data/spec/std/isa/inst/V/vmfge.vf.yaml +3 -1
  271. data/.data/spec/std/isa/inst/V/vmfgt.vf.yaml +3 -1
  272. data/.data/spec/std/isa/inst/V/vmfle.vf.yaml +3 -1
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  523. data/.data/spec/std/isa/param/HPM_COUNTER11_WIDTH.yaml +29 -0
  524. data/.data/spec/std/isa/param/HPM_COUNTER12_WIDTH.yaml +29 -0
  525. data/.data/spec/std/isa/param/HPM_COUNTER13_WIDTH.yaml +29 -0
  526. data/.data/spec/std/isa/param/HPM_COUNTER14_WIDTH.yaml +29 -0
  527. data/.data/spec/std/isa/param/HPM_COUNTER15_WIDTH.yaml +29 -0
  528. data/.data/spec/std/isa/param/HPM_COUNTER16_WIDTH.yaml +29 -0
  529. data/.data/spec/std/isa/param/HPM_COUNTER17_WIDTH.yaml +29 -0
  530. data/.data/spec/std/isa/param/HPM_COUNTER18_WIDTH.yaml +29 -0
  531. data/.data/spec/std/isa/param/HPM_COUNTER19_WIDTH.yaml +29 -0
  532. data/.data/spec/std/isa/param/HPM_COUNTER20_WIDTH.yaml +29 -0
  533. data/.data/spec/std/isa/param/HPM_COUNTER21_WIDTH.yaml +29 -0
  534. data/.data/spec/std/isa/param/HPM_COUNTER22_WIDTH.yaml +29 -0
  535. data/.data/spec/std/isa/param/HPM_COUNTER23_WIDTH.yaml +29 -0
  536. data/.data/spec/std/isa/param/HPM_COUNTER24_WIDTH.yaml +29 -0
  537. data/.data/spec/std/isa/param/HPM_COUNTER25_WIDTH.yaml +29 -0
  538. data/.data/spec/std/isa/param/HPM_COUNTER26_WIDTH.yaml +29 -0
  539. data/.data/spec/std/isa/param/HPM_COUNTER27_WIDTH.yaml +29 -0
  540. data/.data/spec/std/isa/param/HPM_COUNTER28_WIDTH.yaml +29 -0
  541. data/.data/spec/std/isa/param/HPM_COUNTER29_WIDTH.yaml +29 -0
  542. data/.data/spec/std/isa/param/HPM_COUNTER30_WIDTH.yaml +29 -0
  543. data/.data/spec/std/isa/param/HPM_COUNTER31_WIDTH.yaml +29 -0
  544. data/.data/spec/std/isa/param/HPM_COUNTER3_WIDTH.yaml +29 -0
  545. data/.data/spec/std/isa/param/HPM_COUNTER4_WIDTH.yaml +29 -0
  546. data/.data/spec/std/isa/param/HPM_COUNTER5_WIDTH.yaml +29 -0
  547. data/.data/spec/std/isa/param/HPM_COUNTER6_WIDTH.yaml +29 -0
  548. data/.data/spec/std/isa/param/HPM_COUNTER7_WIDTH.yaml +29 -0
  549. data/.data/spec/std/isa/param/HPM_COUNTER8_WIDTH.yaml +29 -0
  550. data/.data/spec/std/isa/param/HPM_COUNTER9_WIDTH.yaml +29 -0
  551. data/.data/spec/std/isa/param/HPM_COUNTERN_WIDTH.layout +27 -0
  552. data/.data/spec/std/isa/param/HW_MSTATUS_FS_DIRTY_UPDATE.yaml +2 -4
  553. data/.data/spec/std/isa/param/HW_MSTATUS_VS_DIRTY_UPDATE.yaml +2 -4
  554. data/.data/spec/std/isa/param/LRSC_FAIL_ON_NON_EXACT_LRSC.yaml +1 -1
  555. data/.data/spec/std/isa/param/LRSC_FAIL_ON_VA_SYNONYM.yaml +1 -1
  556. data/.data/spec/std/isa/param/LRSC_MISALIGNED_BEHAVIOR.yaml +4 -4
  557. data/.data/spec/std/isa/param/LRSC_RESERVATION_STRATEGY.yaml +1 -1
  558. data/.data/spec/std/isa/param/MCOUNTENABLE_EN.yaml +2 -5
  559. data/.data/spec/std/isa/param/MEI_INTR_IMPL.yaml +28 -0
  560. data/.data/spec/std/isa/param/MSI_INTR_IMPL.yaml +28 -0
  561. data/.data/spec/std/isa/param/MSTATUS_FS_LEGAL_VALUES.yaml +8 -15
  562. data/.data/spec/std/isa/param/MSTATUS_VS_LEGAL_VALUES.yaml +7 -15
  563. data/.data/spec/std/isa/param/MTI_INTR_IMPL.yaml +28 -0
  564. data/.data/spec/std/isa/param/MTVAL_WIDTH.yaml +17 -5
  565. data/.data/spec/std/isa/param/MUTABLE_MISA_A.yaml +1 -1
  566. data/.data/spec/std/isa/param/MUTABLE_MISA_B.yaml +1 -1
  567. data/.data/spec/std/isa/param/MUTABLE_MISA_C.yaml +1 -1
  568. data/.data/spec/std/isa/param/MUTABLE_MISA_D.yaml +1 -1
  569. data/.data/spec/std/isa/param/MUTABLE_MISA_F.yaml +1 -1
  570. data/.data/spec/std/isa/param/MUTABLE_MISA_M.yaml +1 -1
  571. data/.data/spec/std/isa/param/MUTABLE_MISA_Q.yaml +1 -1
  572. data/.data/spec/std/isa/param/MUTABLE_MISA_U.yaml +1 -1
  573. data/.data/spec/std/isa/param/MUTABLE_MISA_V.yaml +1 -1
  574. data/.data/spec/std/isa/param/{PMLEN.yaml → NON_STANDARD_EXTENSION_IMPLEMENTED.yaml} +6 -9
  575. data/.data/spec/std/isa/param/NUM_EXTERNAL_GUEST_INTERRUPTS.yaml +1 -1
  576. data/.data/spec/std/isa/param/NUM_PMP_ENTRIES.yaml +1 -1
  577. data/.data/spec/std/isa/param/REPORT_CAUSE_IN_MTVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml +1 -1
  578. data/.data/spec/std/isa/param/REPORT_CAUSE_IN_STVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml +1 -1
  579. data/.data/spec/std/isa/param/REPORT_CAUSE_IN_VSTVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml +1 -1
  580. data/.data/spec/std/isa/param/SCOUNTENABLE_EN.yaml +2 -6
  581. data/.data/spec/std/isa/param/SCTRDEPTH_DEPTH_LEGAL_VALUES.yaml +27 -0
  582. data/.data/spec/std/isa/param/SEI_INTR_IMPL.yaml +28 -0
  583. data/.data/spec/std/isa/param/SSI_INTR_IMPL.yaml +28 -0
  584. data/.data/spec/std/isa/param/STI_INTR_IMPL.yaml +33 -0
  585. data/.data/spec/std/isa/param/STVAL_WIDTH.yaml +81 -0
  586. data/.data/spec/std/isa/param/SUPPORTED_PMLEN_SMMPM.yaml +40 -0
  587. data/.data/spec/std/isa/param/SUPPORTED_PMLEN_SMNPM.yaml +42 -0
  588. data/.data/spec/std/isa/param/SUPPORTED_PMLEN_SSNPM.yaml +42 -0
  589. data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_S.yaml +1 -1
  590. data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_U.yaml +1 -1
  591. data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_VS.yaml +1 -1
  592. data/.data/spec/std/isa/param/TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY.yaml +1 -1
  593. data/.data/spec/std/isa/param/VSEI_INTR_IMPL.yaml +28 -0
  594. data/.data/spec/std/isa/param/VSSI_INTR_IMPL.yaml +28 -0
  595. data/.data/spec/std/isa/param/VSTI_INTR_IMPL.yaml +33 -0
  596. data/.data/spec/std/isa/param/WFI_FINITE.yaml +20 -0
  597. data/.data/spec/std/isa/param/WFI_U_MODE.yaml +20 -0
  598. data/lib/udb/Z3_VERSION +1 -1
  599. data/lib/udb/log.rb +16 -0
  600. data/lib/udb/obj/csr.rb +38 -45
  601. data/lib/udb/obj/database_obj.rb +1 -1
  602. data/lib/udb/obj/exception_code.rb +3 -3
  603. data/lib/udb/version.rb +1 -1
  604. metadata +79 -10
@@ -48,16 +48,16 @@ fields:
48
48
  return csr_value.ADDR;
49
49
  }
50
50
  sw_read(): |
51
- # when the mode is NAPOT and PMP_GRANULARITY >= 16,
51
+ # when the mode is NAPOT and PMP_GRANULARITY >= 4,
52
52
  # bits (PMP_GRANULARITY-4):0 must read as ones
53
53
  if (MXLEN == 32) {
54
- if ((PMP_GRANULARITY >= 16) &&
54
+ if ((PMP_GRANULARITY >= 4) &&
55
55
  (CSR[pmpcfg2].pmp8cfg[4] == 1)) {
56
56
  return CSR[pmpaddr8].ADDR | {PMP_GRANULARITY-3{1'b1}};
57
57
 
58
- # when the mode is OFF or TOR and PMP_GRANULARITY >= 8,
58
+ # when the mode is OFF or TOR and PMP_GRANULARITY >= 3,
59
59
  # bits (PMP_GRANULARITY-3):0 must read as zeros
60
- } else if ((PMP_GRANULARITY >= 8) &&
60
+ } else if ((PMP_GRANULARITY >= 3) &&
61
61
  (CSR[pmpcfg2].pmp8cfg[4] == 0)) {
62
62
  Bits<PHYS_ADDR_WIDTH-2> mask = {PMP_GRANULARITY-2{1'b1}};
63
63
  return CSR[pmpaddr8].ADDR & ~mask;
@@ -67,13 +67,13 @@ sw_read(): |
67
67
  return CSR[pmpaddr8].ADDR;
68
68
  }
69
69
  } else {
70
- if ((PMP_GRANULARITY >= 16) &&
70
+ if ((PMP_GRANULARITY >= 4) &&
71
71
  (CSR[pmpcfg2].pmp8cfg[4] == 1)) {
72
72
  return CSR[pmpaddr8].ADDR | {PMP_GRANULARITY-3{1'b1}};
73
73
 
74
- # when the mode is OFF or TOR and PMP_GRANULARITY >= 8,
74
+ # when the mode is OFF or TOR and PMP_GRANULARITY >= 3,
75
75
  # bits (PMP_GRANULARITY-3):0 must read as zeros
76
- } else if ((PMP_GRANULARITY >= 8) &&
76
+ } else if ((PMP_GRANULARITY >= 3) &&
77
77
  (CSR[pmpcfg2].pmp8cfg[4] == 0)) {
78
78
  Bits<PHYS_ADDR_WIDTH-2> mask = {PMP_GRANULARITY-2{1'b1}};
79
79
  return CSR[pmpaddr8].ADDR & ~mask;
@@ -48,16 +48,16 @@ fields:
48
48
  return csr_value.ADDR;
49
49
  }
50
50
  sw_read(): |
51
- # when the mode is NAPOT and PMP_GRANULARITY >= 16,
51
+ # when the mode is NAPOT and PMP_GRANULARITY >= 4,
52
52
  # bits (PMP_GRANULARITY-4):0 must read as ones
53
53
  if (MXLEN == 32) {
54
- if ((PMP_GRANULARITY >= 16) &&
54
+ if ((PMP_GRANULARITY >= 4) &&
55
55
  (CSR[pmpcfg2].pmp9cfg[4] == 1)) {
56
56
  return CSR[pmpaddr9].ADDR | {PMP_GRANULARITY-3{1'b1}};
57
57
 
58
- # when the mode is OFF or TOR and PMP_GRANULARITY >= 8,
58
+ # when the mode is OFF or TOR and PMP_GRANULARITY >= 3,
59
59
  # bits (PMP_GRANULARITY-3):0 must read as zeros
60
- } else if ((PMP_GRANULARITY >= 8) &&
60
+ } else if ((PMP_GRANULARITY >= 3) &&
61
61
  (CSR[pmpcfg2].pmp9cfg[4] == 0)) {
62
62
  Bits<PHYS_ADDR_WIDTH-2> mask = {PMP_GRANULARITY-2{1'b1}};
63
63
  return CSR[pmpaddr9].ADDR & ~mask;
@@ -67,13 +67,13 @@ sw_read(): |
67
67
  return CSR[pmpaddr9].ADDR;
68
68
  }
69
69
  } else {
70
- if ((PMP_GRANULARITY >= 16) &&
70
+ if ((PMP_GRANULARITY >= 4) &&
71
71
  (CSR[pmpcfg2].pmp9cfg[4] == 1)) {
72
72
  return CSR[pmpaddr9].ADDR | {PMP_GRANULARITY-3{1'b1}};
73
73
 
74
- # when the mode is OFF or TOR and PMP_GRANULARITY >= 8,
74
+ # when the mode is OFF or TOR and PMP_GRANULARITY >= 3,
75
75
  # bits (PMP_GRANULARITY-3):0 must read as zeros
76
- } else if ((PMP_GRANULARITY >= 8) &&
76
+ } else if ((PMP_GRANULARITY >= 3) &&
77
77
  (CSR[pmpcfg2].pmp9cfg[4] == 0)) {
78
78
  Bits<PHYS_ADDR_WIDTH-2> mask = {PMP_GRANULARITY-2{1'b1}};
79
79
  return CSR[pmpaddr9].ADDR & ~mask;
@@ -50,16 +50,16 @@ fields:
50
50
  return csr_value.ADDR;
51
51
  }
52
52
  sw_read(): |
53
- # when the mode is NAPOT and PMP_GRANULARITY >= 16,
53
+ # when the mode is NAPOT and PMP_GRANULARITY >= 4,
54
54
  # bits (PMP_GRANULARITY-4):0 must read as ones
55
55
  if (MXLEN == 32) {
56
- if ((PMP_GRANULARITY >= 16) &&
56
+ if ((PMP_GRANULARITY >= 4) &&
57
57
  (CSR[pmpcfg<%= pmpcfg_num_32 %>].pmp<%= pmpaddr_num %>cfg[4] == 1)) {
58
58
  return CSR[pmpaddr<%= pmpaddr_num %>].ADDR | {PMP_GRANULARITY-3{1'b1}};
59
59
 
60
- # when the mode is OFF or TOR and PMP_GRANULARITY >= 8,
60
+ # when the mode is OFF or TOR and PMP_GRANULARITY >= 3,
61
61
  # bits (PMP_GRANULARITY-3):0 must read as zeros
62
- } else if ((PMP_GRANULARITY >= 8) &&
62
+ } else if ((PMP_GRANULARITY >= 3) &&
63
63
  (CSR[pmpcfg<%= pmpcfg_num_32 %>].pmp<%= pmpaddr_num %>cfg[4] == 0)) {
64
64
  Bits<PHYS_ADDR_WIDTH-2> mask = {PMP_GRANULARITY-2{1'b1}};
65
65
  return CSR[pmpaddr<%= pmpaddr_num %>].ADDR & ~mask;
@@ -69,13 +69,13 @@ sw_read(): |
69
69
  return CSR[pmpaddr<%= pmpaddr_num %>].ADDR;
70
70
  }
71
71
  } else {
72
- if ((PMP_GRANULARITY >= 16) &&
72
+ if ((PMP_GRANULARITY >= 4) &&
73
73
  (CSR[pmpcfg<%= pmpcfg_num_64 %>].pmp<%= pmpaddr_num %>cfg[4] == 1)) {
74
74
  return CSR[pmpaddr<%= pmpaddr_num %>].ADDR | {PMP_GRANULARITY-3{1'b1}};
75
75
 
76
- # when the mode is OFF or TOR and PMP_GRANULARITY >= 8,
76
+ # when the mode is OFF or TOR and PMP_GRANULARITY >= 3,
77
77
  # bits (PMP_GRANULARITY-3):0 must read as zeros
78
- } else if ((PMP_GRANULARITY >= 8) &&
78
+ } else if ((PMP_GRANULARITY >= 3) &&
79
79
  (CSR[pmpcfg<%= pmpcfg_num_64 %>].pmp<%= pmpaddr_num %>cfg[4] == 0)) {
80
80
  Bits<PHYS_ADDR_WIDTH-2> mask = {PMP_GRANULARITY-2{1'b1}};
81
81
  return CSR[pmpaddr<%= pmpaddr_num %>].ADDR & ~mask;
@@ -46,7 +46,7 @@ fields:
46
46
  Register state of the CSR selected by the current `miselect` value
47
47
  reset_value: UNDEFINED_LEGAL
48
48
  sw_write(csr_value): |
49
- Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 1);
49
+ Csr handle = indirect_csr_lookup(PrivilegeMode::M, CSR[miselect].VALUE, 1);
50
50
  if (!handle.valid) {
51
51
  unimplemented_csr($encoding);
52
52
  }
@@ -56,7 +56,7 @@ fields:
56
56
  csr_sw_write(handle, csr_value.VALUE);
57
57
  return csr_hw_read(handle);
58
58
  sw_read(): |
59
- Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 1);
59
+ Csr handle = indirect_csr_lookup(PrivilegeMode::M, CSR[miselect].VALUE, 1);
60
60
  if (!handle.valid) {
61
61
  unimplemented_csr($encoding);
62
62
  }
@@ -46,7 +46,7 @@ fields:
46
46
  Register state of the CSR selected by the current `miselect` value
47
47
  reset_value: UNDEFINED_LEGAL
48
48
  sw_write(csr_value): |
49
- Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 2);
49
+ Csr handle = indirect_csr_lookup(PrivilegeMode::M, CSR[miselect].VALUE, 2);
50
50
  if (!handle.valid) {
51
51
  unimplemented_csr($encoding);
52
52
  }
@@ -56,7 +56,7 @@ fields:
56
56
  csr_sw_write(handle, csr_value.VALUE);
57
57
  return csr_hw_read(handle);
58
58
  sw_read(): |
59
- Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 2);
59
+ Csr handle = indirect_csr_lookup(PrivilegeMode::M, CSR[miselect].VALUE, 2);
60
60
  if (!handle.valid) {
61
61
  unimplemented_csr($encoding);
62
62
  }
@@ -46,7 +46,7 @@ fields:
46
46
  Register state of the CSR selected by the current `miselect` value
47
47
  reset_value: UNDEFINED_LEGAL
48
48
  sw_write(csr_value): |
49
- Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 3);
49
+ Csr handle = indirect_csr_lookup(PrivilegeMode::M, CSR[miselect].VALUE, 3);
50
50
  if (!handle.valid) {
51
51
  unimplemented_csr($encoding);
52
52
  }
@@ -56,7 +56,7 @@ fields:
56
56
  csr_sw_write(handle, csr_value.VALUE);
57
57
  return csr_hw_read(handle);
58
58
  sw_read(): |
59
- Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 3);
59
+ Csr handle = indirect_csr_lookup(PrivilegeMode::M, CSR[miselect].VALUE, 3);
60
60
  if (!handle.valid) {
61
61
  unimplemented_csr($encoding);
62
62
  }
@@ -46,7 +46,7 @@ fields:
46
46
  Register state of the CSR selected by the current `miselect` value
47
47
  reset_value: UNDEFINED_LEGAL
48
48
  sw_write(csr_value): |
49
- Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 4);
49
+ Csr handle = indirect_csr_lookup(PrivilegeMode::M, CSR[miselect].VALUE, 4);
50
50
  if (!handle.valid) {
51
51
  unimplemented_csr($encoding);
52
52
  }
@@ -56,7 +56,7 @@ fields:
56
56
  csr_sw_write(handle, csr_value.VALUE);
57
57
  return csr_hw_read(handle);
58
58
  sw_read(): |
59
- Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 4);
59
+ Csr handle = indirect_csr_lookup(PrivilegeMode::M, CSR[miselect].VALUE, 4);
60
60
  if (!handle.valid) {
61
61
  unimplemented_csr($encoding);
62
62
  }
@@ -46,7 +46,7 @@ fields:
46
46
  Register state of the CSR selected by the current `miselect` value
47
47
  reset_value: UNDEFINED_LEGAL
48
48
  sw_write(csr_value): |
49
- Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 5);
49
+ Csr handle = indirect_csr_lookup(PrivilegeMode::M, CSR[miselect].VALUE, 5);
50
50
  if (!handle.valid) {
51
51
  unimplemented_csr($encoding);
52
52
  }
@@ -56,7 +56,7 @@ fields:
56
56
  csr_sw_write(handle, csr_value.VALUE);
57
57
  return csr_hw_read(handle);
58
58
  sw_read(): |
59
- Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 5);
59
+ Csr handle = indirect_csr_lookup(PrivilegeMode::M, CSR[miselect].VALUE, 5);
60
60
  if (!handle.valid) {
61
61
  unimplemented_csr($encoding);
62
62
  }
@@ -46,7 +46,7 @@ fields:
46
46
  Register state of the CSR selected by the current `miselect` value
47
47
  reset_value: UNDEFINED_LEGAL
48
48
  sw_write(csr_value): |
49
- Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 6);
49
+ Csr handle = indirect_csr_lookup(PrivilegeMode::M, CSR[miselect].VALUE, 6);
50
50
  if (!handle.valid) {
51
51
  unimplemented_csr($encoding);
52
52
  }
@@ -56,7 +56,7 @@ fields:
56
56
  csr_sw_write(handle, csr_value.VALUE);
57
57
  return csr_hw_read(handle);
58
58
  sw_read(): |
59
- Csr handle = indirect_csr_lookup(CSR[miselect].VALUE, 6);
59
+ Csr handle = indirect_csr_lookup(PrivilegeMode::M, CSR[miselect].VALUE, 6);
60
60
  if (!handle.valid) {
61
61
  unimplemented_csr($encoding);
62
62
  }
@@ -46,7 +46,7 @@ fields:
46
46
  The data read from or written to the register selected by the current `siselect` value.
47
47
  reset_value: UNDEFINED_LEGAL
48
48
  sw_write(csr_value): |
49
- Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 1);
49
+ Csr handle = indirect_csr_lookup(PrivilegeMode::S, CSR[siselect].VALUE, 1);
50
50
  if (!handle.valid) {
51
51
  unimplemented_csr($encoding);
52
52
  }
@@ -56,7 +56,7 @@ fields:
56
56
  csr_sw_write(handle, csr_value.VALUE);
57
57
  return csr_hw_read(handle);
58
58
  sw_read(): |
59
- Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 1);
59
+ Csr handle = indirect_csr_lookup(PrivilegeMode::S, CSR[siselect].VALUE, 1);
60
60
  if (!handle.valid) {
61
61
  unimplemented_csr($encoding);
62
62
  }
@@ -46,7 +46,7 @@ fields:
46
46
  The data read from or written to the register selected by the current `siselect` value.
47
47
  reset_value: UNDEFINED_LEGAL
48
48
  sw_write(csr_value): |
49
- Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 2);
49
+ Csr handle = indirect_csr_lookup(PrivilegeMode::S, CSR[siselect].VALUE, 2);
50
50
  if (!handle.valid) {
51
51
  unimplemented_csr($encoding);
52
52
  }
@@ -56,7 +56,7 @@ fields:
56
56
  csr_sw_write(handle, csr_value.VALUE);
57
57
  return csr_hw_read(handle);
58
58
  sw_read(): |
59
- Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 2);
59
+ Csr handle = indirect_csr_lookup(PrivilegeMode::S, CSR[siselect].VALUE, 2);
60
60
  if (!handle.valid) {
61
61
  unimplemented_csr($encoding);
62
62
  }
@@ -46,7 +46,7 @@ fields:
46
46
  The data read from or written to the register selected by the current `siselect` value.
47
47
  reset_value: UNDEFINED_LEGAL
48
48
  sw_write(csr_value): |
49
- Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 3);
49
+ Csr handle = indirect_csr_lookup(PrivilegeMode::S, CSR[siselect].VALUE, 3);
50
50
  if (!handle.valid) {
51
51
  unimplemented_csr($encoding);
52
52
  }
@@ -56,7 +56,7 @@ fields:
56
56
  csr_sw_write(handle, csr_value.VALUE);
57
57
  return csr_hw_read(handle);
58
58
  sw_read(): |
59
- Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 3);
59
+ Csr handle = indirect_csr_lookup(PrivilegeMode::S, CSR[siselect].VALUE, 3);
60
60
  if (!handle.valid) {
61
61
  unimplemented_csr($encoding);
62
62
  }
@@ -46,7 +46,7 @@ fields:
46
46
  The data read from or written to the register selected by the current `siselect` value.
47
47
  reset_value: UNDEFINED_LEGAL
48
48
  sw_write(csr_value): |
49
- Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 4);
49
+ Csr handle = indirect_csr_lookup(PrivilegeMode::S, CSR[siselect].VALUE, 4);
50
50
  if (!handle.valid) {
51
51
  unimplemented_csr($encoding);
52
52
  }
@@ -56,7 +56,7 @@ fields:
56
56
  csr_sw_write(handle, csr_value.VALUE);
57
57
  return csr_hw_read(handle);
58
58
  sw_read(): |
59
- Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 4);
59
+ Csr handle = indirect_csr_lookup(PrivilegeMode::S, CSR[siselect].VALUE, 4);
60
60
  if (!handle.valid) {
61
61
  unimplemented_csr($encoding);
62
62
  }
@@ -46,7 +46,7 @@ fields:
46
46
  The data read from or written to the register selected by the current `siselect` value.
47
47
  reset_value: UNDEFINED_LEGAL
48
48
  sw_write(csr_value): |
49
- Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 5);
49
+ Csr handle = indirect_csr_lookup(PrivilegeMode::S, CSR[siselect].VALUE, 5);
50
50
  if (!handle.valid) {
51
51
  unimplemented_csr($encoding);
52
52
  }
@@ -56,7 +56,7 @@ fields:
56
56
  csr_sw_write(handle, csr_value.VALUE);
57
57
  return csr_hw_read(handle);
58
58
  sw_read(): |
59
- Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 5);
59
+ Csr handle = indirect_csr_lookup(PrivilegeMode::S, CSR[siselect].VALUE, 5);
60
60
  if (!handle.valid) {
61
61
  unimplemented_csr($encoding);
62
62
  }
@@ -46,7 +46,7 @@ fields:
46
46
  The data read from or written to the register selected by the current `siselect` value.
47
47
  reset_value: UNDEFINED_LEGAL
48
48
  sw_write(csr_value): |
49
- Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 6);
49
+ Csr handle = indirect_csr_lookup(PrivilegeMode::S, CSR[siselect].VALUE, 6);
50
50
  if (!handle.valid) {
51
51
  unimplemented_csr($encoding);
52
52
  }
@@ -56,7 +56,7 @@ fields:
56
56
  csr_sw_write(handle, csr_value.VALUE);
57
57
  return csr_hw_read(handle);
58
58
  sw_read(): |
59
- Csr handle = indirect_csr_lookup(CSR[siselect].VALUE, 6);
59
+ Csr handle = indirect_csr_lookup(PrivilegeMode::S, CSR[siselect].VALUE, 6);
60
60
  if (!handle.valid) {
61
61
  unimplemented_csr($encoding);
62
62
  }
@@ -46,7 +46,7 @@ fields:
46
46
  value of the `vsiselect` CSR.
47
47
  reset_value: UNDEFINED_LEGAL
48
48
  sw_write(csr_value): |
49
- Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 1);
49
+ Csr handle = indirect_csr_lookup(PrivilegeMode::VS, CSR[vsiselect].VALUE, 1);
50
50
  if (!handle.valid) {
51
51
  unimplemented_csr($encoding);
52
52
  }
@@ -56,7 +56,7 @@ fields:
56
56
  csr_sw_write(handle, csr_value.VALUE);
57
57
  return csr_hw_read(handle);
58
58
  sw_read(): |
59
- Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 1);
59
+ Csr handle = indirect_csr_lookup(PrivilegeMode::VS, CSR[vsiselect].VALUE, 1);
60
60
  if (!handle.valid) {
61
61
  unimplemented_csr($encoding);
62
62
  }
@@ -45,7 +45,7 @@ fields:
45
45
  Data read or written based on the currently selected `vsiselect` value.
46
46
  reset_value: UNDEFINED_LEGAL
47
47
  sw_write(csr_value): |
48
- Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 2);
48
+ Csr handle = indirect_csr_lookup(PrivilegeMode::VS, CSR[vsiselect].VALUE, 2);
49
49
  if (!handle.valid) {
50
50
  unimplemented_csr($encoding);
51
51
  }
@@ -55,7 +55,7 @@ fields:
55
55
  csr_sw_write(handle, csr_value.VALUE);
56
56
  return csr_hw_read(handle);
57
57
  sw_read(): |
58
- Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 2);
58
+ Csr handle = indirect_csr_lookup(PrivilegeMode::VS, CSR[vsiselect].VALUE, 2);
59
59
  if (!handle.valid) {
60
60
  unimplemented_csr($encoding);
61
61
  }
@@ -44,7 +44,7 @@ fields:
44
44
  description: The data read or written based on the currently selected `vsiselect` value.
45
45
  reset_value: UNDEFINED_LEGAL
46
46
  sw_write(csr_value): |
47
- Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 3);
47
+ Csr handle = indirect_csr_lookup(PrivilegeMode::VS, CSR[vsiselect].VALUE, 3);
48
48
  if (!handle.valid) {
49
49
  unimplemented_csr($encoding);
50
50
  }
@@ -54,7 +54,7 @@ fields:
54
54
  csr_sw_write(handle, csr_value.VALUE);
55
55
  return csr_hw_read(handle);
56
56
  sw_read(): |
57
- Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 3);
57
+ Csr handle = indirect_csr_lookup(PrivilegeMode::VS, CSR[vsiselect].VALUE, 3);
58
58
  if (!handle.valid) {
59
59
  unimplemented_csr($encoding);
60
60
  }
@@ -44,7 +44,7 @@ fields:
44
44
  description: The data read or written based on the currently selected `vsiselect` value.
45
45
  reset_value: UNDEFINED_LEGAL
46
46
  sw_write(csr_value): |
47
- Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 4);
47
+ Csr handle = indirect_csr_lookup(PrivilegeMode::VS, CSR[vsiselect].VALUE, 4);
48
48
  if (!handle.valid) {
49
49
  unimplemented_csr($encoding);
50
50
  }
@@ -54,7 +54,7 @@ fields:
54
54
  csr_sw_write(handle, csr_value.VALUE);
55
55
  return csr_hw_read(handle);
56
56
  sw_read(): |
57
- Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 4);
57
+ Csr handle = indirect_csr_lookup(PrivilegeMode::VS, CSR[vsiselect].VALUE, 4);
58
58
  if (!handle.valid) {
59
59
  unimplemented_csr($encoding);
60
60
  }
@@ -45,7 +45,7 @@ fields:
45
45
  The data read or written from the register selected by the value in `vsiselect`.
46
46
  reset_value: UNDEFINED_LEGAL
47
47
  sw_write(csr_value): |
48
- Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 5);
48
+ Csr handle = indirect_csr_lookup(PrivilegeMode::VS, CSR[vsiselect].VALUE, 5);
49
49
  if (!handle.valid) {
50
50
  unimplemented_csr($encoding);
51
51
  }
@@ -55,7 +55,7 @@ fields:
55
55
  csr_sw_write(handle, csr_value.VALUE);
56
56
  return csr_hw_read(handle);
57
57
  sw_read(): |
58
- Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 5);
58
+ Csr handle = indirect_csr_lookup(PrivilegeMode::VS, CSR[vsiselect].VALUE, 5);
59
59
  if (!handle.valid) {
60
60
  unimplemented_csr($encoding);
61
61
  }
@@ -45,7 +45,7 @@ fields:
45
45
  The data read or written from the register selected by the current value of `vsiselect`.
46
46
  reset_value: UNDEFINED_LEGAL
47
47
  sw_write(csr_value): |
48
- Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 6);
48
+ Csr handle = indirect_csr_lookup(PrivilegeMode::VS, CSR[vsiselect].VALUE, 6);
49
49
  if (!handle.valid) {
50
50
  unimplemented_csr($encoding);
51
51
  }
@@ -55,7 +55,7 @@ fields:
55
55
  csr_sw_write(handle, csr_value.VALUE);
56
56
  return csr_hw_read(handle);
57
57
  sw_read(): |
58
- Csr handle = indirect_csr_lookup(CSR[vsiselect].VALUE, 6);
58
+ Csr handle = indirect_csr_lookup(PrivilegeMode::VS, CSR[vsiselect].VALUE, 6);
59
59
  if (!handle.valid) {
60
60
  unimplemented_csr($encoding);
61
61
  }
@@ -13,7 +13,7 @@ priv_mode: S
13
13
  length: 64
14
14
  definedBy:
15
15
  extension:
16
- name: Smctr
16
+ name: Ssctr
17
17
  description: The `sctrctl` register enables and configures the Control Transfer Records capability in S mode.
18
18
  fields:
19
19
  U:
@@ -0,0 +1,43 @@
1
+ # Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
2
+ # SPDX-License-Identifier: BSD-3-Clause-Clear
3
+
4
+ # yaml-language-server: $schema=../../../../schemas/csr_schema.json
5
+
6
+ $schema: "csr_schema.json#"
7
+ kind: csr
8
+ name: sctrdepth
9
+ long_name: Supervisor Control Transfer Records Depth
10
+ address: 0x15F
11
+ writable: true
12
+ priv_mode: S
13
+ length: 32
14
+ description: |
15
+ The `sctrdepth` register is a 32-bit read/write register used to select the number
16
+ of records that can be held in the CTR buffer.
17
+ definedBy:
18
+ extension:
19
+ name: Smctr
20
+ fields:
21
+ DEPTH:
22
+ location: 2-0
23
+ description: |
24
+ Selects the depth of the CTR buffer.
25
+ type(): |
26
+ return ($array_size(SCTRDEPTH_DEPTH_LEGAL_VALUES) == 1) ? CsrFieldType::RO : CsrFieldType::RW;
27
+ reset_value(): |
28
+ if ($array_size(SCTRDEPTH_DEPTH_LEGAL_VALUES) == 1) {
29
+ if (SCTRDEPTH_DEPTH_LEGAL_VALUES[0] == 16) { return 0; }
30
+ else if (SCTRDEPTH_DEPTH_LEGAL_VALUES[0] == 32) { return 1; }
31
+ else if (SCTRDEPTH_DEPTH_LEGAL_VALUES[0] == 64) { return 2; }
32
+ else if (SCTRDEPTH_DEPTH_LEGAL_VALUES[0] == 128) { return 3; }
33
+ else if (SCTRDEPTH_DEPTH_LEGAL_VALUES[0] == 256) { return 4; }
34
+ else { return UNDEFINED_LEGAL; }
35
+ } else {
36
+ return UNDEFINED_LEGAL;
37
+ }
38
+ sw_write(csr_value): |
39
+ if ($array_includes?(SCTRDEPTH_DEPTH_LEGAL_VALUES, 32'd16 << csr_value.DEPTH)) {
40
+ return csr_value.DEPTH;
41
+ } else {
42
+ return UNDEFINED_LEGAL_DETERMINISTIC;
43
+ }
@@ -0,0 +1,37 @@
1
+ # Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
2
+ # SPDX-License-Identifier: BSD-3-Clause-Clear
3
+
4
+ # yaml-language-server: $schema=../../../../schemas/csr_schema.json
5
+
6
+ $schema: "csr_schema.json#"
7
+ kind: csr
8
+ name: sctrstatus
9
+ long_name: Supervisor Control Transfer Records Status
10
+ address: 0x14F
11
+ writable: true
12
+ priv_mode: S
13
+ length: 32
14
+ description: |
15
+ The `sctrstatus` register provides access to CTR status information and is
16
+ updated by hardware whenever CTR is active.
17
+ definedBy:
18
+ extension:
19
+ name: Smctr
20
+ fields:
21
+ WRPTR:
22
+ location: 7-0
23
+ description: |
24
+ Write Pointer. Indicates the physical CTR buffer entry to be written next.
25
+
26
+ Note: Bits above depth-1 are read-only zero depending on the configured CTR depth.
27
+ type: RW-H
28
+ reset_value: UNDEFINED_LEGAL
29
+ sw_write(csr_value): |
30
+ Bits<8> mask = (9'd16 << CSR[sctrdepth].DEPTH) - 1;
31
+ return csr_value.WRPTR & mask;
32
+ FROZEN:
33
+ location: 31
34
+ description: |
35
+ When set, inhibits transfer recording.
36
+ type: RW-H
37
+ reset_value: UNDEFINED_LEGAL
@@ -14,7 +14,9 @@ priv_mode: VS
14
14
  length: 64
15
15
  definedBy:
16
16
  extension:
17
- name: Smctr
17
+ allOf:
18
+ - name: Ssctr
19
+ - name: H
18
20
  description: |
19
21
  The `vsctrctl` register is a VS-mode's version of supervisor register `sctrctl` that
20
22
  configures the Control Transfer Records capability. When `V=1`, vsctrctl substitutes
@@ -0,0 +1,42 @@
1
+ # Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
2
+ # SPDX-License-Identifier: BSD-3-Clause-Clear
3
+
4
+ # yaml-language-server: $schema=../../../../schemas/csr_schema.json
5
+
6
+ $schema: "csr_schema.json#"
7
+ kind: csr
8
+ name: stimecmp
9
+ long_name: Supervisor timer compare
10
+ address: 0x14D
11
+ writable: true
12
+ priv_mode: S
13
+ length: 64
14
+ description: |
15
+ Supervisor timer compare register.
16
+
17
+ When `menvcfg.STCE` is set, `stimecmp` is operational and provides
18
+ supervisor mode with a CSR-based timer interrupt facility.
19
+ definedBy:
20
+ extension:
21
+ name: Sstc
22
+ fields:
23
+ TIME:
24
+ location: 63-0
25
+ description: |
26
+ Time compare value for supervisor timer interrupts.
27
+ type: RW
28
+ reset_value: UNDEFINED_LEGAL
29
+ sw_write(csr_value): |
30
+ if (mode() != PrivilegeMode::M) {
31
+ if (CSR[menvcfg].STCE == 1'b0 || CSR[mcounteren].TM == 1'b0) {
32
+ raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
33
+ }
34
+ }
35
+ return csr_value.TIME;
36
+ sw_read(): |
37
+ if (mode() != PrivilegeMode::M) {
38
+ if (CSR[menvcfg].STCE == 1'b0 || CSR[mcounteren].TM == 1'b0) {
39
+ raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
40
+ }
41
+ }
42
+ return CSR[stimecmp].TIME;
@@ -0,0 +1,43 @@
1
+ # Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
2
+ # SPDX-License-Identifier: BSD-3-Clause-Clear
3
+
4
+ # yaml-language-server: $schema=../../../../schemas/csr_schema.json
5
+
6
+ $schema: "csr_schema.json#"
7
+ kind: csr
8
+ name: stimecmph
9
+ long_name: Supervisor timer compare high
10
+ address: 0x15D
11
+ writable: true
12
+ priv_mode: S
13
+ length: 32
14
+ description: |
15
+ Upper 32 bits of the `stimecmp` CSR.
16
+ definedBy:
17
+ allOf:
18
+ - xlen: 32
19
+ - extension:
20
+ name: Sstc
21
+ fields:
22
+ TIME:
23
+ location: 31-0
24
+ alias: stimecmp.TIME[63:32]
25
+ description: |
26
+ Upper 32 bits of the supervisor timer compare value.
27
+ type: RW
28
+ reset_value: UNDEFINED_LEGAL
29
+ sw_write(csr_value): |
30
+ if (mode() != PrivilegeMode::M) {
31
+ if (CSR[menvcfg].STCE == 1'b0 || CSR[mcounteren].TM == 1'b0) {
32
+ raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
33
+ }
34
+ }
35
+ CSR[stimecmp].TIME = {csr_value.TIME, CSR[stimecmp].TIME[31:0]};
36
+ return csr_value.TIME;
37
+ sw_read(): |
38
+ if (mode() != PrivilegeMode::M) {
39
+ if (CSR[menvcfg].STCE == 1'b0 || CSR[mcounteren].TM == 1'b0) {
40
+ raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
41
+ }
42
+ }
43
+ return CSR[stimecmp].TIME[63:32];