udb 0.1.16 → 0.1.17
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/.data/cfgs/example_rv64_with_overlay.yaml +20 -0
- data/.data/cfgs/mc100-32-full-example.yaml +6 -0
- data/.data/cfgs/qc_iu.yaml +14 -0
- data/.data/cfgs/rv32-riscv-tests.yaml +9 -0
- data/.data/cfgs/rv32-vector.yaml +10 -1
- data/.data/cfgs/rv64-riscv-tests.yaml +9 -0
- data/.data/cfgs/rv64-vector.yaml +11 -2
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.mva01s.yaml +2 -2
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.mvsa01.yaml +2 -2
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.pop.yaml +2 -2
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.popret.yaml +2 -2
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.popretz.yaml +2 -2
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.push.yaml +2 -2
- data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.pushfp.yaml +2 -2
- data/.data/spec/schemas/README.adoc +4 -1
- data/.data/spec/schemas/csr_schema.json +2 -2
- data/.data/spec/std/isa/csr/H/hgeie.yaml +38 -0
- data/.data/spec/std/isa/csr/H/hgeip.yaml +33 -0
- data/.data/spec/std/isa/csr/H/hideleg.yaml +120 -0
- data/.data/spec/std/isa/csr/H/hie.yaml +74 -0
- data/.data/spec/std/isa/csr/H/hip.yaml +88 -0
- data/.data/spec/std/isa/csr/H/hvip.yaml +46 -0
- data/.data/spec/std/isa/csr/H/vsie.yaml +86 -0
- data/.data/spec/std/isa/csr/H/vsip.yaml +98 -0
- data/.data/spec/std/isa/csr/H/vsscratch.yaml +29 -0
- data/.data/spec/std/isa/csr/I/pmpaddr0.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr1.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr10.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr11.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr12.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr13.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr14.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr15.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr16.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr17.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr18.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr19.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr2.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr20.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr21.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr22.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr23.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr24.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr25.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr26.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr27.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr28.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr29.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr3.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr30.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr31.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr32.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr33.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr34.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr35.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr36.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr37.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr38.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr39.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr4.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr40.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr41.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr42.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr43.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr44.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr45.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr46.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr47.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr48.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr49.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr5.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr50.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr51.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr52.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr53.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr54.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr55.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr56.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr57.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr58.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr59.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr6.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr60.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr61.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr62.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr63.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr7.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr8.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddr9.yaml +7 -7
- data/.data/spec/std/isa/csr/I/pmpaddrN.layout +7 -7
- data/.data/spec/std/isa/csr/Smcsrind/mireg.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/mireg2.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/mireg3.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/mireg4.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/mireg5.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/mireg6.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/sireg.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/sireg2.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/sireg3.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/sireg4.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/sireg5.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/sireg6.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/vsireg.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/vsireg2.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/vsireg3.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/vsireg4.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/vsireg5.yaml +2 -2
- data/.data/spec/std/isa/csr/Smcsrind/vsireg6.yaml +2 -2
- data/.data/spec/std/isa/csr/Smctr/sctrctl.yaml +1 -1
- data/.data/spec/std/isa/csr/Smctr/sctrdepth.yaml +43 -0
- data/.data/spec/std/isa/csr/Smctr/sctrstatus.yaml +37 -0
- data/.data/spec/std/isa/csr/Smctr/vsctrctl.yaml +3 -1
- data/.data/spec/std/isa/csr/Sstc/stimecmp.yaml +42 -0
- data/.data/spec/std/isa/csr/Sstc/stimecmph.yaml +43 -0
- data/.data/spec/std/isa/csr/Sstc/vstimecmp.yaml +45 -0
- data/.data/spec/std/isa/csr/Sstc/vstimecmph.yaml +46 -0
- data/.data/spec/std/isa/csr/V/vcsr.yaml +1 -1
- data/.data/spec/std/isa/csr/V/vl.yaml +1 -1
- data/.data/spec/std/isa/csr/V/vlenb.yaml +1 -1
- data/.data/spec/std/isa/csr/V/vstart.yaml +1 -1
- data/.data/spec/std/isa/csr/V/vtype.yaml +20 -1
- data/.data/spec/std/isa/csr/V/vxrm.yaml +1 -1
- data/.data/spec/std/isa/csr/V/vxsat.yaml +1 -1
- data/.data/spec/std/isa/csr/Zicntr/mcountinhibit.layout +1 -15
- data/.data/spec/std/isa/csr/Zicntr/mcountinhibit.yaml +29 -267
- data/.data/spec/std/isa/csr/mideleg.yaml +57 -9
- data/.data/spec/std/isa/csr/mie.yaml +18 -9
- data/.data/spec/std/isa/csr/mip.yaml +21 -10
- data/.data/spec/std/isa/csr/misa.yaml +11 -7
- data/.data/spec/std/isa/csr/mstatus.yaml +2 -2
- data/.data/spec/std/isa/csr/schema.adoc +10 -4
- data/.data/spec/std/isa/csr/senvcfg.yaml +6 -12
- data/.data/spec/std/isa/csr/sstateen0.yaml +1 -1
- data/.data/spec/std/isa/csr/sstateen1.yaml +2 -3
- data/.data/spec/std/isa/csr/sstateen2.yaml +2 -3
- data/.data/spec/std/isa/csr/sstateen3.yaml +2 -3
- data/.data/spec/std/isa/csr/tcontrol.yaml +37 -0
- data/.data/spec/std/isa/csr/tinfo.yaml +44 -0
- data/.data/spec/std/isa/ext/Smctr.yaml +1 -1
- data/.data/spec/std/isa/ext/Ssctr.yaml +1 -1
- data/.data/spec/std/isa/ext/Ssstrict.yaml +2 -2
- data/.data/spec/std/isa/ext/Sv32.yaml +2 -2
- data/.data/spec/std/isa/ext/Svpbmt.yaml +2 -2
- data/.data/spec/std/isa/ext/Zaamo.yaml +1 -1
- data/.data/spec/std/isa/ext/Zbc.yaml +4 -0
- data/.data/spec/std/isa/ext/Zvfbfa.yaml +24 -0
- data/.data/spec/std/isa/ext/Zvfofp4min.yaml +21 -0
- data/.data/spec/std/isa/ext/Zvfofp8min.yaml +20 -0
- data/.data/spec/std/isa/inst/B/andn.yaml +0 -4
- data/.data/spec/std/isa/inst/B/orn.yaml +0 -4
- data/.data/spec/std/isa/inst/B/rev8.yaml +0 -4
- data/.data/spec/std/isa/inst/B/rol.yaml +0 -4
- data/.data/spec/std/isa/inst/B/rolw.yaml +0 -4
- data/.data/spec/std/isa/inst/B/ror.yaml +0 -4
- data/.data/spec/std/isa/inst/B/rori.yaml +0 -4
- data/.data/spec/std/isa/inst/B/roriw.yaml +0 -4
- data/.data/spec/std/isa/inst/B/rorw.yaml +0 -4
- data/.data/spec/std/isa/inst/B/xnor.yaml +0 -4
- data/.data/spec/std/isa/inst/C/c.addi.yaml +2 -2
- data/.data/spec/std/isa/inst/C/c.addi16sp.yaml +2 -2
- data/.data/spec/std/isa/inst/C/c.addi4spn.yaml +2 -2
- data/.data/spec/std/isa/inst/C/c.addiw.yaml +2 -2
- data/.data/spec/std/isa/inst/C/c.beqz.yaml +2 -2
- data/.data/spec/std/isa/inst/C/c.bnez.yaml +2 -2
- data/.data/spec/std/isa/inst/C/c.ebreak.yaml +2 -2
- data/.data/spec/std/isa/inst/C/c.j.yaml +2 -2
- data/.data/spec/std/isa/inst/C/c.jal.yaml +2 -2
- data/.data/spec/std/isa/inst/C/c.jalr.yaml +2 -2
- data/.data/spec/std/isa/inst/C/c.jr.yaml +2 -2
- data/.data/spec/std/isa/inst/C/c.ld.yaml +2 -2
- data/.data/spec/std/isa/inst/C/c.ldsp.yaml +2 -2
- data/.data/spec/std/isa/inst/C/c.li.yaml +2 -2
- data/.data/spec/std/isa/inst/C/c.lui.yaml +2 -2
- data/.data/spec/std/isa/inst/C/c.lw.yaml +2 -2
- data/.data/spec/std/isa/inst/C/c.lwsp.yaml +2 -2
- data/.data/spec/std/isa/inst/C/c.mv.yaml +2 -2
- data/.data/spec/std/isa/inst/C/c.nop.yaml +2 -2
- data/.data/spec/std/isa/inst/C/c.sd.yaml +2 -2
- data/.data/spec/std/isa/inst/C/c.sdsp.yaml +5 -5
- data/.data/spec/std/isa/inst/C/c.sw.yaml +2 -2
- data/.data/spec/std/isa/inst/C/c.swsp.yaml +2 -2
- data/.data/spec/std/isa/inst/I/ld.yaml +9 -4
- data/.data/spec/std/isa/inst/I/sd.yaml +9 -4
- data/.data/spec/std/isa/inst/I/wfi.yaml +1 -1
- data/.data/spec/std/isa/inst/M/div.yaml +2 -2
- data/.data/spec/std/isa/inst/M/divu.yaml +2 -2
- data/.data/spec/std/isa/inst/M/divuw.yaml +2 -2
- data/.data/spec/std/isa/inst/M/divw.yaml +2 -2
- data/.data/spec/std/isa/inst/M/mul.yaml +0 -4
- data/.data/spec/std/isa/inst/M/mulh.yaml +0 -4
- data/.data/spec/std/isa/inst/M/mulhsu.yaml +0 -4
- data/.data/spec/std/isa/inst/M/mulhu.yaml +0 -4
- data/.data/spec/std/isa/inst/M/mulw.yaml +0 -4
- data/.data/spec/std/isa/inst/M/rem.yaml +2 -2
- data/.data/spec/std/isa/inst/M/remu.yaml +2 -2
- data/.data/spec/std/isa/inst/M/remuw.yaml +2 -2
- data/.data/spec/std/isa/inst/M/remw.yaml +2 -2
- data/.data/spec/std/isa/inst/V/vfadd.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfadd.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfclass.v.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfmacc.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfmacc.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfmadd.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfmadd.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfmax.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfmax.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfmerge.vfm.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfmin.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfmin.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfmsac.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfmsac.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfmsub.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfmsub.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfmul.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfmul.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfmv.f.s.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfmv.s.f.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfmv.v.f.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfncvt.f.f.w.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfncvt.rod.f.f.w.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfncvt.rtz.x.f.w.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfncvt.rtz.xu.f.w.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfncvt.x.f.w.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfncvt.xu.f.w.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfnmacc.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfnmacc.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfnmadd.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfnmadd.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfnmsac.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfnmsac.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfnmsub.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfnmsub.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfrec7.v.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfrsqrt7.v.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfrsub.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfsgnj.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfsgnj.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfsgnjn.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfsgnjn.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfsgnjx.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfsgnjx.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfslide1down.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfslide1up.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfsub.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfsub.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfwadd.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfwadd.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfwadd.wf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfwadd.wv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfwcvt.f.f.v.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfwcvt.f.x.v.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfwcvt.f.xu.v.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfwmacc.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfwmacc.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfwmsac.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfwmsac.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfwmul.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfwmul.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfwnmacc.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfwnmacc.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfwnmsac.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfwnmsac.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfwsub.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfwsub.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfwsub.wf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vfwsub.wv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vmfeq.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vmfeq.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vmfge.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vmfgt.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vmfle.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vmfle.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vmflt.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vmflt.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vmfne.vf.yaml +3 -1
- data/.data/spec/std/isa/inst/V/vmfne.vv.yaml +3 -1
- data/.data/spec/std/isa/inst/Zaamo/amoadd.SIZE.AQRL.layout +1 -5
- data/.data/spec/std/isa/inst/Zaamo/amoadd.d.aq.yaml +0 -4
- data/.data/spec/std/isa/inst/Zaamo/amoadd.d.aqrl.yaml +0 -4
- data/.data/spec/std/isa/inst/Zaamo/amoadd.d.rl.yaml +0 -4
- data/.data/spec/std/isa/inst/Zaamo/amoadd.d.yaml +0 -4
- data/.data/spec/std/isa/inst/Zaamo/amoadd.w.aq.yaml +1 -5
- data/.data/spec/std/isa/inst/Zaamo/amoadd.w.aqrl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zaamo/amoadd.w.rl.yaml +1 -5
- data/.data/spec/std/isa/inst/Zaamo/amoadd.w.yaml +1 -5
- data/.data/spec/std/isa/inst/Zaamo/amoand.SIZE.AQRL.layout +1 -5
- data/.data/spec/std/isa/inst/Zaamo/amoand.d.aq.yaml +0 -4
- data/.data/spec/std/isa/inst/Zaamo/amoand.d.aqrl.yaml +0 -4
- data/.data/spec/std/isa/inst/Zaamo/amoand.d.rl.yaml +0 -4
- data/.data/spec/std/isa/inst/Zaamo/amoand.d.yaml +0 -4
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- data/.data/spec/std/isa/param/MCOUNTENABLE_EN.yaml +2 -5
- data/.data/spec/std/isa/param/MEI_INTR_IMPL.yaml +28 -0
- data/.data/spec/std/isa/param/MSI_INTR_IMPL.yaml +28 -0
- data/.data/spec/std/isa/param/MSTATUS_FS_LEGAL_VALUES.yaml +8 -15
- data/.data/spec/std/isa/param/MSTATUS_VS_LEGAL_VALUES.yaml +7 -15
- data/.data/spec/std/isa/param/MTI_INTR_IMPL.yaml +28 -0
- data/.data/spec/std/isa/param/MTVAL_WIDTH.yaml +17 -5
- data/.data/spec/std/isa/param/MUTABLE_MISA_A.yaml +1 -1
- data/.data/spec/std/isa/param/MUTABLE_MISA_B.yaml +1 -1
- data/.data/spec/std/isa/param/MUTABLE_MISA_C.yaml +1 -1
- data/.data/spec/std/isa/param/MUTABLE_MISA_D.yaml +1 -1
- data/.data/spec/std/isa/param/MUTABLE_MISA_F.yaml +1 -1
- data/.data/spec/std/isa/param/MUTABLE_MISA_M.yaml +1 -1
- data/.data/spec/std/isa/param/MUTABLE_MISA_Q.yaml +1 -1
- data/.data/spec/std/isa/param/MUTABLE_MISA_U.yaml +1 -1
- data/.data/spec/std/isa/param/MUTABLE_MISA_V.yaml +1 -1
- data/.data/spec/std/isa/param/{PMLEN.yaml → NON_STANDARD_EXTENSION_IMPLEMENTED.yaml} +6 -9
- data/.data/spec/std/isa/param/NUM_EXTERNAL_GUEST_INTERRUPTS.yaml +1 -1
- data/.data/spec/std/isa/param/NUM_PMP_ENTRIES.yaml +1 -1
- data/.data/spec/std/isa/param/REPORT_CAUSE_IN_MTVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml +1 -1
- data/.data/spec/std/isa/param/REPORT_CAUSE_IN_STVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml +1 -1
- data/.data/spec/std/isa/param/REPORT_CAUSE_IN_VSTVAL_ON_LANDING_PAD_SOFTWARE_CHECK.yaml +1 -1
- data/.data/spec/std/isa/param/SCOUNTENABLE_EN.yaml +2 -6
- data/.data/spec/std/isa/param/SCTRDEPTH_DEPTH_LEGAL_VALUES.yaml +27 -0
- data/.data/spec/std/isa/param/SEI_INTR_IMPL.yaml +28 -0
- data/.data/spec/std/isa/param/SSI_INTR_IMPL.yaml +28 -0
- data/.data/spec/std/isa/param/STI_INTR_IMPL.yaml +33 -0
- data/.data/spec/std/isa/param/STVAL_WIDTH.yaml +81 -0
- data/.data/spec/std/isa/param/SUPPORTED_PMLEN_SMMPM.yaml +40 -0
- data/.data/spec/std/isa/param/SUPPORTED_PMLEN_SMNPM.yaml +42 -0
- data/.data/spec/std/isa/param/SUPPORTED_PMLEN_SSNPM.yaml +42 -0
- data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_S.yaml +1 -1
- data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_U.yaml +1 -1
- data/.data/spec/std/isa/param/TRAP_ON_ECALL_FROM_VS.yaml +1 -1
- data/.data/spec/std/isa/param/TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY.yaml +1 -1
- data/.data/spec/std/isa/param/VSEI_INTR_IMPL.yaml +28 -0
- data/.data/spec/std/isa/param/VSSI_INTR_IMPL.yaml +28 -0
- data/.data/spec/std/isa/param/VSTI_INTR_IMPL.yaml +33 -0
- data/.data/spec/std/isa/param/WFI_FINITE.yaml +20 -0
- data/.data/spec/std/isa/param/WFI_U_MODE.yaml +20 -0
- data/lib/udb/Z3_VERSION +1 -1
- data/lib/udb/log.rb +16 -0
- data/lib/udb/obj/csr.rb +38 -45
- data/lib/udb/obj/database_obj.rb +1 -1
- data/lib/udb/obj/exception_code.rb +3 -3
- data/lib/udb/version.rb +1 -1
- metadata +79 -10
|
@@ -7,34 +7,26 @@ $schema: param_schema.json#
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kind: parameter
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name: MSTATUS_VS_LEGAL_VALUES
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description: The set of values that mstatus.VS will accept from a software write.
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long_name:
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long_name: mstatus.VS legal values
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schema:
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type: array
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items:
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type: integer
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enum:
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- 0
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- 1
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- 2
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-
- 3
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- 0 # Off
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- 1 # Initial
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- 2 # Clean
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- 3 # Dirty
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minItems: 1
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maxItems: 4
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uniqueItems: true
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requirements:
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idl(): |
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# [RULE] If the v registers are implemented, the VS field shall not be read-only zero.
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implemented?(ExtensionName::V)
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-> $array_size(MSTATUS_VS_LEGAL_VALUES) > 1;
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-
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# [RULE] If there is a hardware update to mstatus.VS, then the Dirty state must be supported
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implemented?(ExtensionName::V)
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-
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-> $array_includes?(MSTATUS_VS_LEGAL_VALUES, 0) &&
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$array_includes?(MSTATUS_VS_LEGAL_VALUES, 3);
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implemented?(ExtensionName::V)
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-> $array_includes?(MSTATUS_VS_LEGAL_VALUES, 3);
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reason: |
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If V is supported, both Off (0) and Dirty (3) must be supported
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-
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If there is a hardware update to mstatus.VS, then the Dirty state must be supported
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definedBy:
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extension:
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@@ -0,0 +1,28 @@
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1
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+
# Copyright (c) David_Harris@hmc.edu 13 July 2026
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# SPDX-License-Identifier: BSD-3-Clause-Clear
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# yaml-language-server: $schema=../../../schemas/param_schema.json
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$schema: param_schema.json#
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kind: parameter
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name: MTI_INTR_IMPL
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description: |
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Whether or not machine-level timer interrupts are implemented.
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Possible values:
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true::
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Machine-level timer interrupts are implemented.
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`mie.MTIE`, `mideleg.MTI`, and `mtimecmp` are writable.
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false::
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Machine-level timer interrupts are not implemented.
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`mie.MTIE` and `mideleg.MTI` are read-only zero. `mtimecmp` is optional and may be read-only zero.
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long_name: Machine-level timer interrupts are implemented
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schema:
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type: boolean
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definedBy:
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extension:
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allOf:
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- name: Zicsr
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- name: Sm
|
|
@@ -29,7 +29,7 @@ requirements:
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29
29
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30
30
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# in RV32, MTVAL must be able to hold a physical address if M-mode takes an exception
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# that reports an address
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32
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-
# Since
|
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32
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+
# Since physical address width can be larger than 32 with Sv32, need to downsize MTVAL in that case
|
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33
33
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(
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34
34
|
MXLEN == 32 &&
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35
35
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PHYS_ADDR_WIDTH > 32 &&
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|
@@ -42,11 +42,15 @@ requirements:
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REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED ||
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43
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REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT ||
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REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT ||
|
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45
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-
REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT
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45
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+
REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT ||
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+
REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT ||
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+
REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT ||
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+
REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT
|
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46
49
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)
|
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47
50
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) -> (MTVAL_WIDTH == 32);
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48
51
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-
# TODO: uncomment when we have support for parameter comparison
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# TODO: uncomment when we have support for parameter/function comparison
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+
# on the RHS of a constraint.
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# (
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51
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# (
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52
56
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# MXLEN == 64 ||
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|
@@ -64,10 +68,15 @@ requirements:
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64
68
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# REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED ||
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65
69
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# REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT ||
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70
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# REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT ||
|
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67
|
-
# REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT
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71
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+
# REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT ||
|
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72
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+
# REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT ||
|
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73
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+
# REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT ||
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74
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+
# REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT
|
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68
75
|
# )
|
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69
76
|
# ) -> (MTVAL_WIDTH >= PHYS_ADDR_WIDTH);
|
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70
77
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78
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+
# TODO: uncomment when we have support for parameter/function comparison
|
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79
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+
# on the RHS of a constraint.
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71
80
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# (
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72
81
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# implemented?(ExtensionName::S) &&
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73
82
|
# (
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@@ -79,7 +88,10 @@ requirements:
|
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79
88
|
# REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED ||
|
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80
89
|
# REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT ||
|
|
81
90
|
# REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT ||
|
|
82
|
-
# REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT
|
|
91
|
+
# REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT ||
|
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92
|
+
# REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT ||
|
|
93
|
+
# REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT ||
|
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94
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+
# REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT
|
|
83
95
|
# )
|
|
84
96
|
# ) -> (MTVAL_WIDTH >= max_va_size());
|
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85
97
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@@ -5,16 +5,13 @@
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5
5
|
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6
6
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$schema: param_schema.json#
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7
7
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kind: parameter
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8
|
-
name:
|
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8
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+
name: NON_STANDARD_EXTENSION_IMPLEMENTED
|
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9
9
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description: |
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10
|
-
|
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11
|
-
|
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12
|
-
long_name:
|
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10
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If any non-standard extensions are implemented, this parameter must be true.
|
|
11
|
+
This parameter is used as the reset value for `misa.X`.
|
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12
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+
long_name: Non-standard extensions implemented
|
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13
13
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schema:
|
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14
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type:
|
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14
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type: boolean
|
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15
15
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definedBy:
|
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16
16
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extension:
|
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17
|
-
|
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18
|
-
- name: Smmpm
|
|
19
|
-
- name: Smnpm
|
|
20
|
-
- name: Ssnpm
|
|
17
|
+
name: Sm
|
|
@@ -22,7 +22,7 @@ description: |
|
|
|
22
22
|
An implemented entry may still be read-only zero (but will never cause an exception).
|
|
23
23
|
The number of entries that are actually usable is given by
|
|
24
24
|
NUM_USABLE_PMP_ENTRIES.
|
|
25
|
-
long_name:
|
|
25
|
+
long_name: number of implemented PMP entries
|
|
26
26
|
schema:
|
|
27
27
|
type: integer
|
|
28
28
|
enum: [0, 16, 64]
|
|
@@ -7,7 +7,7 @@ $schema: param_schema.json#
|
|
|
7
7
|
kind: parameter
|
|
8
8
|
name: REPORT_CAUSE_IN_MTVAL_ON_LANDING_PAD_SOFTWARE_CHECK
|
|
9
9
|
description: |
|
|
10
|
-
When true, `mtval` is written with the
|
|
10
|
+
When true, `mtval` is written with the landing pad fault cause (code=2) when a SoftwareCheck exception is raised into M-mode due to a landing pad error.
|
|
11
11
|
|
|
12
12
|
When false, `mtval` is written with 0.
|
|
13
13
|
long_name: TODO
|
|
@@ -7,7 +7,7 @@ $schema: param_schema.json#
|
|
|
7
7
|
kind: parameter
|
|
8
8
|
name: REPORT_CAUSE_IN_STVAL_ON_LANDING_PAD_SOFTWARE_CHECK
|
|
9
9
|
description: |
|
|
10
|
-
When true, `stval` is written with the
|
|
10
|
+
When true, `stval` is written with the landing pad fault cause (code=2) when a SoftwareCheck exception is raised into S-mode due to a landing pad error.
|
|
11
11
|
|
|
12
12
|
When false, `stval` is written with 0.
|
|
13
13
|
long_name: TODO
|
|
@@ -7,7 +7,7 @@ $schema: param_schema.json#
|
|
|
7
7
|
kind: parameter
|
|
8
8
|
name: REPORT_CAUSE_IN_VSTVAL_ON_LANDING_PAD_SOFTWARE_CHECK
|
|
9
9
|
description: |
|
|
10
|
-
When true, `vstval` is written with the
|
|
10
|
+
When true, `vstval` is written with the landing pad fault cause (code=2) when a SoftwareCheck exception is raised into VS-mode due to a landing pad error.
|
|
11
11
|
|
|
12
12
|
When false, `vstval` is written with 0.
|
|
13
13
|
long_name: TODO
|
|
@@ -9,9 +9,8 @@ name: SCOUNTENABLE_EN
|
|
|
9
9
|
description: |
|
|
10
10
|
Indicates which counters can delegated via `scounteren`
|
|
11
11
|
|
|
12
|
-
|
|
13
|
-
|
|
14
|
-
SCOUNTENABLE_EN[3] to true.
|
|
12
|
+
`SCOUNTENABLE_EN[n]` controls whether `scounteren.HPM<n>` is writable. It does not
|
|
13
|
+
depend on whether `hpmcounter<n>`/`mhpmcounter<n>` is read-only zero.
|
|
15
14
|
|
|
16
15
|
SCOUNTENABLE_EN[0:2] must all be false if `Zicntr` is not implemented.
|
|
17
16
|
SCOUNTENABLE_EN[3:31] must all be false if `Zihpm` is not implemented.
|
|
@@ -29,14 +28,11 @@ requirements:
|
|
|
29
28
|
}
|
|
30
29
|
for (U32 i = 3; i < 32; i++) {
|
|
31
30
|
!implemented?(ExtensionName::Zihpm) -> !SCOUNTENABLE_EN[i];
|
|
32
|
-
(!HPM_COUNTER_EN[i]) -> !SCOUNTENABLE_EN[i];
|
|
33
31
|
}
|
|
34
32
|
reason: |
|
|
35
33
|
Counters 0-2 are defined by Zicntr
|
|
36
34
|
|
|
37
35
|
Counters 3..31 are defined by Zihpm
|
|
38
|
-
|
|
39
|
-
When mhpmcounter[i] does not exist, it cannot be enabled.
|
|
40
36
|
definedBy:
|
|
41
37
|
extension:
|
|
42
38
|
name: S
|
|
@@ -0,0 +1,27 @@
|
|
|
1
|
+
# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
|
2
|
+
# SPDX-License-Identifier: BSD-3-Clause-Clear
|
|
3
|
+
|
|
4
|
+
# yaml-language-server: $schema=../../../schemas/param_schema.json
|
|
5
|
+
|
|
6
|
+
$schema: param_schema.json#
|
|
7
|
+
kind: parameter
|
|
8
|
+
name: SCTRDEPTH_DEPTH_LEGAL_VALUES
|
|
9
|
+
description: |
|
|
10
|
+
The set of supported actual depths for the Control Transfer Records (CTR) buffer.
|
|
11
|
+
long_name: Supported CTR buffer depths
|
|
12
|
+
schema:
|
|
13
|
+
type: array
|
|
14
|
+
items:
|
|
15
|
+
type: integer
|
|
16
|
+
enum:
|
|
17
|
+
- 16
|
|
18
|
+
- 32
|
|
19
|
+
- 64
|
|
20
|
+
- 128
|
|
21
|
+
- 256
|
|
22
|
+
maxItems: 5
|
|
23
|
+
minItems: 1
|
|
24
|
+
uniqueItems: true
|
|
25
|
+
definedBy:
|
|
26
|
+
extension:
|
|
27
|
+
name: Smctr
|
|
@@ -0,0 +1,28 @@
|
|
|
1
|
+
# Copyright (c) David_Harris@hmc.edu 13 July 2026
|
|
2
|
+
# SPDX-License-Identifier: BSD-3-Clause-Clear
|
|
3
|
+
|
|
4
|
+
# yaml-language-server: $schema=../../../schemas/param_schema.json
|
|
5
|
+
|
|
6
|
+
$schema: param_schema.json#
|
|
7
|
+
kind: parameter
|
|
8
|
+
name: SEI_INTR_IMPL
|
|
9
|
+
description: |
|
|
10
|
+
Whether or not supervisor-level external interrupts are implemented.
|
|
11
|
+
|
|
12
|
+
Possible values:
|
|
13
|
+
|
|
14
|
+
true::
|
|
15
|
+
Supervisor-level external interrupts are implemented.
|
|
16
|
+
`mie.SEIE` and `mideleg.SEI` are writable.
|
|
17
|
+
|
|
18
|
+
false::
|
|
19
|
+
Supervisor-level external interrupts are not implemented.
|
|
20
|
+
`mie.SEIE`, `mip.SEIP`, and `mideleg.SEI` are read-only zero.
|
|
21
|
+
long_name: Supervisor-level external interrupts are implemented
|
|
22
|
+
schema:
|
|
23
|
+
type: boolean
|
|
24
|
+
definedBy:
|
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25
|
+
extension:
|
|
26
|
+
allOf:
|
|
27
|
+
- name: Zicsr
|
|
28
|
+
- name: S
|
|
@@ -0,0 +1,28 @@
|
|
|
1
|
+
# Copyright (c) David_Harris@hmc.edu 13 July 2026
|
|
2
|
+
# SPDX-License-Identifier: BSD-3-Clause-Clear
|
|
3
|
+
|
|
4
|
+
# yaml-language-server: $schema=../../../schemas/param_schema.json
|
|
5
|
+
|
|
6
|
+
$schema: param_schema.json#
|
|
7
|
+
kind: parameter
|
|
8
|
+
name: SSI_INTR_IMPL
|
|
9
|
+
description: |
|
|
10
|
+
Whether or not supervisor-level software interrupts are implemented.
|
|
11
|
+
|
|
12
|
+
Possible values:
|
|
13
|
+
|
|
14
|
+
true::
|
|
15
|
+
Supervisor-level software interrupts are implemented.
|
|
16
|
+
`mie.SSIE` and `mideleg.SSI` are writable.
|
|
17
|
+
|
|
18
|
+
false::
|
|
19
|
+
Supervisor-level software interrupts are not implemented.
|
|
20
|
+
`mie.SSIE`, `mip.SSIP`, and `mideleg.SSI` are read-only zero.
|
|
21
|
+
long_name: Supervisor-level software interrupts are implemented
|
|
22
|
+
schema:
|
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23
|
+
type: boolean
|
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24
|
+
definedBy:
|
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25
|
+
extension:
|
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26
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+
allOf:
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27
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+
- name: Zicsr
|
|
28
|
+
- name: S
|
|
@@ -0,0 +1,33 @@
|
|
|
1
|
+
# Copyright (c) David_Harris@hmc.edu 13 July 2026
|
|
2
|
+
# SPDX-License-Identifier: BSD-3-Clause-Clear
|
|
3
|
+
|
|
4
|
+
# yaml-language-server: $schema=../../../schemas/param_schema.json
|
|
5
|
+
|
|
6
|
+
$schema: param_schema.json#
|
|
7
|
+
kind: parameter
|
|
8
|
+
name: STI_INTR_IMPL
|
|
9
|
+
description: |
|
|
10
|
+
Whether or not supervisor-level timer interrupts are implemented.
|
|
11
|
+
If Sstc is implemented, then STI_INTR_IMPL must be true.
|
|
12
|
+
|
|
13
|
+
Possible values:
|
|
14
|
+
|
|
15
|
+
true::
|
|
16
|
+
Supervisor-level timer interrupts are implemented.
|
|
17
|
+
`mie.STIE` and `mideleg.STI` are writable.
|
|
18
|
+
|
|
19
|
+
false::
|
|
20
|
+
Supervisor-level timer interrupts are not implemented.
|
|
21
|
+
`mie.STIE`, `mip.STIP`, and `mideleg.STI` are read-only zero.
|
|
22
|
+
long_name: Supervisor-level timer interrupts are implemented
|
|
23
|
+
schema:
|
|
24
|
+
type: boolean
|
|
25
|
+
requirements:
|
|
26
|
+
idl(): |
|
|
27
|
+
implemented?(ExtensionName::Sstc) -> STI_INTR_IMPL;
|
|
28
|
+
reason: "When the Sstc extension is implemented, STIP reflects the timer interrupt signal resulting from `stimecmp`."
|
|
29
|
+
definedBy:
|
|
30
|
+
extension:
|
|
31
|
+
allOf:
|
|
32
|
+
- name: Zicsr
|
|
33
|
+
- name: S
|
|
@@ -18,3 +18,84 @@ schema:
|
|
|
18
18
|
definedBy:
|
|
19
19
|
extension:
|
|
20
20
|
name: S
|
|
21
|
+
requirements:
|
|
22
|
+
idl(): |
|
|
23
|
+
($array_size(SXLEN) == 1 && SXLEN[0] == 32) -> STVAL_WIDTH <= 32;
|
|
24
|
+
|
|
25
|
+
# in RV32, STVAL must be able to hold a physical address if S-mode takes an exception
|
|
26
|
+
# that reports an address
|
|
27
|
+
# Since physical address width can be larger than 32 with Sv32, need to downsize STVAL in that case
|
|
28
|
+
(
|
|
29
|
+
($array_size(SXLEN) == 1 && SXLEN[0] == 32) &&
|
|
30
|
+
PHYS_ADDR_WIDTH > 32 &&
|
|
31
|
+
(
|
|
32
|
+
implemented?(ExtensionName::Sdext) ||
|
|
33
|
+
implemented?(ExtensionName::Sstvala) ||
|
|
34
|
+
REPORT_VA_IN_STVAL_ON_BREAKPOINT ||
|
|
35
|
+
REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION ||
|
|
36
|
+
REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED ||
|
|
37
|
+
REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED ||
|
|
38
|
+
REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED ||
|
|
39
|
+
REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT ||
|
|
40
|
+
REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT ||
|
|
41
|
+
REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT ||
|
|
42
|
+
REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT ||
|
|
43
|
+
REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT ||
|
|
44
|
+
REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT
|
|
45
|
+
)
|
|
46
|
+
) -> (STVAL_WIDTH == 32);
|
|
47
|
+
|
|
48
|
+
# TODO: uncomment when we have support for parameter/function comparison
|
|
49
|
+
# on the RHS of a constraint.
|
|
50
|
+
# (
|
|
51
|
+
# (
|
|
52
|
+
# $array_includes?(SXLEN, 64) ||
|
|
53
|
+
# (
|
|
54
|
+
# ($array_size(SXLEN) == 1 && SXLEN[0] == 32) &&
|
|
55
|
+
# PHYS_ADDR_WIDTH <= 32
|
|
56
|
+
# )
|
|
57
|
+
# ) &&
|
|
58
|
+
# (
|
|
59
|
+
# implemented?(ExtensionName::Sdext) ||
|
|
60
|
+
# implemented?(ExtensionName::Sstvala) ||
|
|
61
|
+
# REPORT_VA_IN_STVAL_ON_BREAKPOINT ||
|
|
62
|
+
# REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION ||
|
|
63
|
+
# REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED ||
|
|
64
|
+
# REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED ||
|
|
65
|
+
# REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED ||
|
|
66
|
+
# REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT ||
|
|
67
|
+
# REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT ||
|
|
68
|
+
# REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT ||
|
|
69
|
+
# REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT ||
|
|
70
|
+
# REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT ||
|
|
71
|
+
# REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT
|
|
72
|
+
# )
|
|
73
|
+
# ) -> (STVAL_WIDTH >= PHYS_ADDR_WIDTH);
|
|
74
|
+
|
|
75
|
+
# TODO: uncomment when we have support for parameter/function comparison
|
|
76
|
+
# on the RHS of a constraint.
|
|
77
|
+
# (
|
|
78
|
+
# implemented?(ExtensionName::S) &&
|
|
79
|
+
# (
|
|
80
|
+
# implemented?(ExtensionName::Sdext) ||
|
|
81
|
+
# implemented?(ExtensionName::Sstvala) ||
|
|
82
|
+
# REPORT_VA_IN_STVAL_ON_BREAKPOINT ||
|
|
83
|
+
# REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION ||
|
|
84
|
+
# REPORT_VA_IN_STVAL_ON_LOAD_MISALIGNED ||
|
|
85
|
+
# REPORT_VA_IN_STVAL_ON_STORE_AMO_MISALIGNED ||
|
|
86
|
+
# REPORT_VA_IN_STVAL_ON_INSTRUCTION_MISALIGNED ||
|
|
87
|
+
# REPORT_VA_IN_STVAL_ON_LOAD_ACCESS_FAULT ||
|
|
88
|
+
# REPORT_VA_IN_STVAL_ON_STORE_AMO_ACCESS_FAULT ||
|
|
89
|
+
# REPORT_VA_IN_STVAL_ON_INSTRUCTION_ACCESS_FAULT ||
|
|
90
|
+
# REPORT_VA_IN_STVAL_ON_LOAD_PAGE_FAULT ||
|
|
91
|
+
# REPORT_VA_IN_STVAL_ON_STORE_AMO_PAGE_FAULT ||
|
|
92
|
+
# REPORT_VA_IN_STVAL_ON_INSTRUCTION_PAGE_FAULT
|
|
93
|
+
# )
|
|
94
|
+
# ) -> (STVAL_WIDTH >= max_va_size());
|
|
95
|
+
|
|
96
|
+
(
|
|
97
|
+
implemented?(ExtensionName::Sstvala) ||
|
|
98
|
+
REPORT_ENCODING_IN_STVAL_ON_ILLEGAL_INSTRUCTION
|
|
99
|
+
) -> (STVAL_WIDTH >= INSTR_ENC_SIZE);
|
|
100
|
+
reason: |
|
|
101
|
+
`stval` must be able to hold physical and/or virtual addresses
|
|
@@ -0,0 +1,40 @@
|
|
|
1
|
+
# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
|
2
|
+
# SPDX-License-Identifier: BSD-3-Clause-Clear
|
|
3
|
+
|
|
4
|
+
# yaml-language-server: $schema=../../../schemas/param_schema.json
|
|
5
|
+
|
|
6
|
+
$schema: param_schema.json#
|
|
7
|
+
kind: parameter
|
|
8
|
+
name: SUPPORTED_PMLEN_SMMPM
|
|
9
|
+
description: |
|
|
10
|
+
The `PMLEN` values supported by the `Smmpm` pointer masking facility
|
|
11
|
+
for M-mode, selected via the `PMM` field in `mseccfg`. `PMLEN` is the
|
|
12
|
+
number of high-order bits of an address that are masked.
|
|
13
|
+
|
|
14
|
+
Options:
|
|
15
|
+
|
|
16
|
+
0::
|
|
17
|
+
PMLEN=0 (pointer masking is disabled)
|
|
18
|
+
7::
|
|
19
|
+
PMLEN=XLEN-57 (i.e., PMLEN=7 on RV64)
|
|
20
|
+
16::
|
|
21
|
+
PMLEN=XLEN-48 (i.e., PMLEN=16 on RV64)
|
|
22
|
+
|
|
23
|
+
The current standard only supports these values (`zpm.adoc`, tag
|
|
24
|
+
`norm:pmlen_supported_values`). `PMM`=00 (pointer masking disabled,
|
|
25
|
+
PMLEN=0) is mandatory and always available, so it is mandatory
|
|
26
|
+
here.
|
|
27
|
+
long_name: Pointer mask length for M mode
|
|
28
|
+
schema:
|
|
29
|
+
type: array
|
|
30
|
+
items:
|
|
31
|
+
type: integer
|
|
32
|
+
enum: [0, 7, 16]
|
|
33
|
+
contains:
|
|
34
|
+
const: 0
|
|
35
|
+
minItems: 1
|
|
36
|
+
maxItems: 3
|
|
37
|
+
uniqueItems: true
|
|
38
|
+
definedBy:
|
|
39
|
+
extension:
|
|
40
|
+
name: Smmpm
|
|
@@ -0,0 +1,42 @@
|
|
|
1
|
+
# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
|
2
|
+
# SPDX-License-Identifier: BSD-3-Clause-Clear
|
|
3
|
+
|
|
4
|
+
# yaml-language-server: $schema=../../../schemas/param_schema.json
|
|
5
|
+
|
|
6
|
+
$schema: param_schema.json#
|
|
7
|
+
kind: parameter
|
|
8
|
+
name: SUPPORTED_PMLEN_SMNPM
|
|
9
|
+
description: |
|
|
10
|
+
The `PMLEN` values supported by the `Smnpm` pointer masking facility
|
|
11
|
+
for the next privilege mode below M-mode (S/HS if S-mode is
|
|
12
|
+
implemented, or U-mode otherwise), selected via the `PMM` field in
|
|
13
|
+
`menvcfg`. `PMLEN` is the number of high-order bits of an address
|
|
14
|
+
that are masked.
|
|
15
|
+
|
|
16
|
+
Options:
|
|
17
|
+
|
|
18
|
+
0::
|
|
19
|
+
PMLEN=0 (pointer masking is disabled)
|
|
20
|
+
7::
|
|
21
|
+
PMLEN=XLEN-57 (i.e., PMLEN=7 on RV64)
|
|
22
|
+
16::
|
|
23
|
+
PMLEN=XLEN-48 (i.e., PMLEN=16 on RV64)
|
|
24
|
+
|
|
25
|
+
The current standard only supports these values (`zpm.adoc`, tag
|
|
26
|
+
`norm:pmlen_supported_values`). `PMM`=00 (pointer masking disabled,
|
|
27
|
+
PMLEN=0) is mandatory and always available, so it is mandatory
|
|
28
|
+
here.
|
|
29
|
+
long_name: Pointer mask length for next mode below M mode
|
|
30
|
+
schema:
|
|
31
|
+
type: array
|
|
32
|
+
items:
|
|
33
|
+
type: integer
|
|
34
|
+
enum: [0, 7, 16]
|
|
35
|
+
contains:
|
|
36
|
+
const: 0
|
|
37
|
+
minItems: 1
|
|
38
|
+
maxItems: 3
|
|
39
|
+
uniqueItems: true
|
|
40
|
+
definedBy:
|
|
41
|
+
extension:
|
|
42
|
+
name: Smnpm
|
|
@@ -0,0 +1,42 @@
|
|
|
1
|
+
# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
|
2
|
+
# SPDX-License-Identifier: BSD-3-Clause-Clear
|
|
3
|
+
|
|
4
|
+
# yaml-language-server: $schema=../../../schemas/param_schema.json
|
|
5
|
+
|
|
6
|
+
$schema: param_schema.json#
|
|
7
|
+
kind: parameter
|
|
8
|
+
name: SUPPORTED_PMLEN_SSNPM
|
|
9
|
+
description: |
|
|
10
|
+
The `PMLEN` values supported by the `Ssnpm` pointer masking facility
|
|
11
|
+
for the next privilege mode below S-mode (U-mode, and VS-/VU-modes if
|
|
12
|
+
the H extension is present), selected via the `PMM` field in
|
|
13
|
+
`senvcfg`. `PMLEN` is the number of high-order bits of an address
|
|
14
|
+
that are masked.
|
|
15
|
+
|
|
16
|
+
Options:
|
|
17
|
+
|
|
18
|
+
0::
|
|
19
|
+
PMLEN=0 (pointer masking is disabled)
|
|
20
|
+
7::
|
|
21
|
+
PMLEN=XLEN-57 (i.e., PMLEN=7 on RV64)
|
|
22
|
+
16::
|
|
23
|
+
PMLEN=XLEN-48 (i.e., PMLEN=16 on RV64)
|
|
24
|
+
|
|
25
|
+
The current standard only supports these values (`zpm.adoc`, tag
|
|
26
|
+
`norm:pmlen_supported_values`). `PMM`=00 (pointer masking disabled,
|
|
27
|
+
PMLEN=0) is mandatory and always available, so it is mandatory
|
|
28
|
+
here.
|
|
29
|
+
long_name: Pointer mask length for next mode below S-mode
|
|
30
|
+
schema:
|
|
31
|
+
type: array
|
|
32
|
+
items:
|
|
33
|
+
type: integer
|
|
34
|
+
enum: [0, 7, 16]
|
|
35
|
+
contains:
|
|
36
|
+
const: 0
|
|
37
|
+
minItems: 1
|
|
38
|
+
maxItems: 3
|
|
39
|
+
uniqueItems: true
|
|
40
|
+
definedBy:
|
|
41
|
+
extension:
|
|
42
|
+
name: Ssnpm
|
|
@@ -11,7 +11,7 @@ description: |
|
|
|
11
11
|
|
|
12
12
|
The spec states that implementations may handle ECALLs transparently
|
|
13
13
|
without raising a trap, in which case the EEI must provide a builtin.
|
|
14
|
-
long_name:
|
|
14
|
+
long_name: "Trap on ECALL from S-mode"
|
|
15
15
|
schema:
|
|
16
16
|
type: boolean
|
|
17
17
|
default: true
|
|
@@ -11,7 +11,7 @@ description: |
|
|
|
11
11
|
|
|
12
12
|
The spec states that implementations may handle ECALLs transparently
|
|
13
13
|
without raising a trap, in which case the EEI must provide a builtin.
|
|
14
|
-
long_name:
|
|
14
|
+
long_name: "Trap on ECALL from U-mode"
|
|
15
15
|
schema:
|
|
16
16
|
type: boolean
|
|
17
17
|
default: true
|