udb 0.1.16 → 0.1.17

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
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-  data.tar.gz: 8e914af25855fd5335cee61d48b29b224886c39cb5b63b00530fc0fe0cc83747
+  metadata.gz: 23af2b77d0e140a2ed6d495199ca74bef1fea8e60c393d279d6d65d55102fb9d
+  data.tar.gz: 62fd794ee5ee064ce12267c1a40f20f734fac00d48dea014c48050fe19e7e485
 SHA512:
-  metadata.gz: 23f4835af0d1fd845ef8c48ddd7dfce7354aa6656ad993ed189234fbe2f43eb01700ec24972336bcc3ddb6e0c41ee609eac4a8f88f6021e388a09e69e2a59834
-  data.tar.gz: 2eb190eecd92203f877366434e3400b58d50007da7dfbdf5745bed97443a4c39d6120624cac2eebcba697ad77ae81bc1eaaca91c60b71dd02daee44768a4e26f
+  metadata.gz: 33a3cf04e12eac216db0553ac5e93eff7ea39578f787171a1edce00bdb40e55a15845a5744cecbb319f671169928faefb8b91f497506b685dfcacfb11918e0ec
+  data.tar.gz: 8deb16c837b1b07cf74bba2d97da79c553aaeb22c56044b47ce0aa969555dc0cecf681dc69eacde15007a6b63ab0aa3cccca303cd2660be36c03fdcef663bc62

data/.data/cfgs/example_rv64_with_overlay.yaml

@@ -613,3 +613,23 @@ params:
   MSTATEEN_IMSIC_TYPE: rw
   HSTATEEN_AIA_TYPE: rw
   HSTATEEN_IMSIC_TYPE: rw
+  MEI_INTR_IMPL: false
+  MSI_INTR_IMPL: false
+  MTI_INTR_IMPL: false
+  SEI_INTR_IMPL: false
+  SSI_INTR_IMPL: false
+  STI_INTR_IMPL: true
+  VSEI_INTR_IMPL: false
+  VSSI_INTR_IMPL: false
+  VSTI_INTR_IMPL: true
+  WFI_U_MODE: false
+  WFI_FINITE: true
+  NON_STANDARD_EXTENSION_IMPLEMENTED: false
+  HPM_COUNTER3_WIDTH: 64
+  HPM_COUNTER4_WIDTH: 64
+  HPM_COUNTER5_WIDTH: 64
+  HPM_COUNTER6_WIDTH: 64
+  HPM_COUNTER7_WIDTH: 64
+  HPM_COUNTER8_WIDTH: 64
+  HPM_COUNTER9_WIDTH: 64
+  HPM_COUNTER10_WIDTH: 64

data/.data/cfgs/mc100-32-full-example.yaml

@@ -162,3 +162,9 @@ params:
       false,
       false,
     ]
+  MEI_INTR_IMPL: false
+  MSI_INTR_IMPL: false
+  MTI_INTR_IMPL: false
+  WFI_U_MODE: false
+  WFI_FINITE: true
+  NON_STANDARD_EXTENSION_IMPLEMENTED: false

data/.data/cfgs/qc_iu.yaml

@@ -190,3 +190,17 @@ params:
   MTVEC_BASE_ALIGNMENT_DIRECT: 0x4
   MTVEC_BASE_ALIGNMENT_VECTORED: 0x4
   TIME_CSR_IMPLEMENTED: true
+  MEI_INTR_IMPL: false
+  MSI_INTR_IMPL: false
+  MTI_INTR_IMPL: false
+  WFI_U_MODE: false
+  WFI_FINITE: true
+  NON_STANDARD_EXTENSION_IMPLEMENTED: true
+  HPM_COUNTER3_WIDTH: 64
+  HPM_COUNTER4_WIDTH: 64
+  HPM_COUNTER5_WIDTH: 64
+  HPM_COUNTER6_WIDTH: 64
+  HPM_COUNTER7_WIDTH: 64
+  HPM_COUNTER8_WIDTH: 64
+  HPM_COUNTER9_WIDTH: 64
+  HPM_COUNTER10_WIDTH: 64

data/.data/cfgs/rv32-riscv-tests.yaml

@@ -248,3 +248,12 @@ params:
   # MSTATEEN_JVT_TYPE: rw
   HW_MSTATUS_FS_DIRTY_UPDATE: precise
   MUTABLE_MISA_F: false
+  MEI_INTR_IMPL: false
+  MSI_INTR_IMPL: false
+  MTI_INTR_IMPL: false
+  SEI_INTR_IMPL: false
+  SSI_INTR_IMPL: false
+  STI_INTR_IMPL: false
+  WFI_U_MODE: false
+  WFI_FINITE: true
+  NON_STANDARD_EXTENSION_IMPLEMENTED: false

data/.data/cfgs/rv32-vector.yaml

@@ -221,7 +221,7 @@ params:
   MSTATEEN_ENVCFG_TYPE: rw
   # Zvl32b parameters
   MUTABLE_MISA_V: false
-  HW_MSTATUS_VS_DIRTY_UPDATE: never
+  HW_MSTATUS_VS_DIRTY_UPDATE: imprecise
   RVV_VL_WHEN_AVL_LT_DOUBLE_VLMAX: "VLMAX"
   FOLLOW_VTYPE_RESET_RECOMMENDATION: true
   VLEN: 128
@@ -282,3 +282,12 @@ params:
       false,
       false,
     ]
+  MEI_INTR_IMPL: false
+  MSI_INTR_IMPL: false
+  MTI_INTR_IMPL: false
+  SEI_INTR_IMPL: false
+  SSI_INTR_IMPL: false
+  STI_INTR_IMPL: false
+  WFI_U_MODE: false
+  WFI_FINITE: true
+  NON_STANDARD_EXTENSION_IMPLEMENTED: false

data/.data/cfgs/rv64-riscv-tests.yaml

@@ -241,3 +241,12 @@ params:
       false,
       false,
     ]
+  MEI_INTR_IMPL: false
+  MSI_INTR_IMPL: false
+  MTI_INTR_IMPL: false
+  SEI_INTR_IMPL: false
+  SSI_INTR_IMPL: false
+  STI_INTR_IMPL: false
+  WFI_U_MODE: false
+  WFI_FINITE: true
+  NON_STANDARD_EXTENSION_IMPLEMENTED: false

data/.data/cfgs/rv64-vector.yaml

@@ -218,7 +218,7 @@ params:
   MSTATEEN_ENVCFG_TYPE: rw
   # Zvl32b parameters
   MUTABLE_MISA_V: false
-  HW_MSTATUS_VS_DIRTY_UPDATE: never
+  HW_MSTATUS_VS_DIRTY_UPDATE: imprecise
   RVV_VL_WHEN_AVL_LT_DOUBLE_VLMAX: "VLMAX"
   FOLLOW_VTYPE_RESET_RECOMMENDATION: true
   VLEN: 128
@@ -244,7 +244,7 @@ params:
   VFREDUSUM_INACTIVE_NODE_ELEMENT_BEHAVIOR: "additive_identity"
   VFREDUSUM_FINAL_NODE_ELEMENT_BEHAVIOR: "additive_identity"
   IMPRECISE_VECTOR_TRAP_SETTABLE: false
-  HW_MSTATUS_FS_DIRTY_UPDATE: never
+  HW_MSTATUS_FS_DIRTY_UPDATE: imprecise
   MUTABLE_MISA_F: false
   HPM_COUNTER_EN:
     [
@@ -281,3 +281,12 @@ params:
       false,
       false,
     ]
+  MEI_INTR_IMPL: false
+  MSI_INTR_IMPL: false
+  MTI_INTR_IMPL: false
+  SEI_INTR_IMPL: false
+  SSI_INTR_IMPL: false
+  STI_INTR_IMPL: false
+  WFI_U_MODE: false
+  WFI_FINITE: true
+  NON_STANDARD_EXTENSION_IMPLEMENTED: false

data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.mva01s.yaml

@@ -27,8 +27,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::Zcmp) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::Zcmp) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
   XReg xreg1 = (r1s[2:1]>0) ? {1,0,r1s[2:0]} : {0,1,r1s[2:0]};
   XReg xreg2 = (r2s[2:1]>0) ? {1,0,r2s[2:0]} : {0,1,r2s[2:0]};

data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.mvsa01.yaml

@@ -29,8 +29,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::Zcmp) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::Zcmp) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
   XReg xreg1 = (r1s[2:1]>0) ? {1,0,r1s[2:0]} : {0,1,r1s[2:0]};
   XReg xreg2 = (r2s[2:1]>0) ? {1,0,r2s[2:0]} : {0,1,r2s[2:0]};

data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.pop.yaml

@@ -36,8 +36,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::Xqccmp) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::Xqccmp) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg virtual_address_sp = get_and_validate_stack_pointer(X[2], $encoding);

data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.popret.yaml

@@ -36,8 +36,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::Xqccmp) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::Xqccmp) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg virtual_address_sp = get_and_validate_stack_pointer(X[2], $encoding);

data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.popretz.yaml

@@ -36,8 +36,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::Xqccmp) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::Xqccmp) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg virtual_address_sp = get_and_validate_stack_pointer(X[2], $encoding);

data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.push.yaml

@@ -37,8 +37,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::Xqccmp) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::Xqccmp) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg virtual_address_sp = get_and_validate_stack_pointer(X[2], $encoding);

data/.data/spec/custom/isa/qc_iu/inst/Xqccmp/qc.cm.pushfp.yaml

@@ -38,8 +38,8 @@ access:
   vs: always
   vu: always
 operation(): |
-  if (implemented?(ExtensionName::Xqccmp) && (CSR[misa].C == 1'b0)) {
-    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  if (implemented?(ExtensionName::Xqccmp) && MISA_CSR_IMPLEMENTED && (CSR[misa].C == 1'b0)) {
+    reserved_instruction($encoding);
   }
 
   XReg virtual_address_sp = get_and_validate_stack_pointer(X[2], $encoding);

data/.data/spec/schemas/README.adoc

@@ -36,8 +36,11 @@ published as GitHub releases under the tag `schemas/<schema_name>/<version>`.
 | 0.1 (current for all schemas except csr_schema.json)
 | https://riscv.github.io/riscv-unified-db/schemas/ext_schema.json/v0.1/ext_schema.json (example)
 
-| 0.2 (current for csr_schema.json)
+| 0.2 (current for csr_schema.json except indirect_address description fix)
 | https://riscv.github.io/riscv-unified-db/schemas/csr_schema.json/v0.2/csr_schema.json
+
+| 0.3 (current for csr_schema.json)
+| https://riscv.github.io/riscv-unified-db/schemas/csr_schema.json/v0.3/csr_schema.json
 |===
 
 == Schema Identification (`$id`)

data/.data/spec/schemas/csr_schema.json

@@ -1,6 +1,6 @@
 {
   "$schema": "http://json-schema.org/draft-07/schema#",
-  "$id": "v0.2",
+  "$id": "v0.3",
   "title": "CSR description",
   "description": "A CSR register specification",
   "$defs": {
@@ -225,7 +225,7 @@
     },
     "indirect_address": {
       "type": "integer",
-      "description": "Indirect address of the CSR, as given to the indirect CSRs of the `Smcsrind`/`Sscdrind` extensions"
+      "description": "Indirect address of the CSR, as given to the indirect CSRs of the `Smcsrind`/`Sscsrind` extensions"
     },
     "indirect_slot": {
       "type": "integer",

data/.data/spec/std/isa/csr/H/hgeie.yaml

@@ -0,0 +1,38 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hgeie
+long_name: Hypervisor Guest External Interrupt Enable Register
+writable: true
+description: |
+  The hgeie register is an HSXLEN-bit read/write register that contains enable bits for the guest external interrupts at this hart. Guest external interrupt number i corresponds with bit i in hgeie.
+
+  Guest external interrupts represent interrupts directed to individual virtual machines at VS-level. If a RISC-V platform supports placing a physical device under the direct control of a guest OS with minimal hypervisor intervention (known as pass-through or direct assignment between a virtual machine and the physical device), then, in such circumstance, interrupts from the device are intended for a specific virtual machine.
+
+  [Note]
+  Support for guest external interrupts requires an interrupt controller that can collect virtual-machine-directed interrupts separately from other interrupts.
+
+  The number of bits implemented in hgeie for guest external interrupts is UNSPECIFIED and may be zero. This number is known as GEILEN. The least-significant bits are implemented first, apart from bit 0. Hence, if GEILEN is nonzero, bits GEILEN:1 shall be writable in hgeie, and all other bit positions shall be read-only zeros.
+
+  Register hgeie selects the subset of guest external interrupts that cause a supervisor-level (HS-level) guest external interrupt. The enable bits in hgeie do not affect the VS-level external interrupt signal selected from hgeip by hstatus.VGEIN.
+address: 0x607
+priv_mode: S
+definedBy:
+  extension:
+    name: H
+length: SXLEN
+fields:
+  GEI_ENABLE:
+    long_name: Guest external interrupt enable bits
+    location_rv32: 31-1
+    location_rv64: 63-1
+    type(): |
+      return NUM_EXTERNAL_GUEST_INTERRUPTS > 0 ? CsrFieldType::RW : CsrFieldType::RO;
+    reset_value: UNDEFINED_LEGAL
+    description: Enable bits; see description of hgeie
+    sw_write(csr_value): |
+      return ((MXLEN'1 << NUM_EXTERNAL_GUEST_INTERRUPTS) - 1) & csr_value.GEI_ENABLE;

data/.data/spec/std/isa/csr/H/hgeip.yaml

@@ -0,0 +1,33 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hgeip
+long_name: Hypervisor Guest External Interrupt Pending Register
+writable: false
+description: |
+  The hgeip register is an HSXLEN-bit read-only register, formatted as that indicates pending guest external interrupts for this hart.
+
+  Guest external interrupts represent interrupts directed to individual virtual machines at VS-level.
+  If a RISC-V platform supports placing a physical device under the direct control of a guest OS with minimal hypervisor intervention (known as pass-through or direct assignment between a virtual machine and the physical device), then, in such circumstance, interrupts from the device are intended for a specific virtual machine.
+  Each bit of hgeip summarizes all pending interrupts directed to one virtual hart, as collected and reported by an interrupt controller. To distinguish specific pending interrupts from multiple devices, software must query the interrupt controller.
+
+  The number of bits implemented in hgeip and hgeie for guest external interrupts is UNSPECIFIED and may be zero.
+  This number is known as GEILEN. The least-significant bits are implemented first, apart from bit 0. Hence, if GEILEN is nonzero, bits GEILEN:1 shall be writable in hgeie, and all other bit positions shall be read-only zeros in both hgeip and hgeie
+address: 0xE12
+priv_mode: S
+definedBy:
+  extension:
+    name: H
+length: SXLEN
+fields:
+  GEI_PENDING:
+    long_name: Guest external interrupt pending bits
+    location_rv32: 31-1
+    location_rv64: 63-1
+    type: RO-H
+    reset_value: 0
+    description: Pending bits; see description of hgeip

data/.data/spec/std/isa/csr/H/hideleg.yaml

@@ -0,0 +1,120 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hideleg
+long_name: Hypervisor Interrupt Delegation Register
+description: |
+  Register hideleg is an HSXLEN-bit read/write register. By default, all traps at any privilege level are handled in M-mode, though M-mode usually uses the medeleg and mideleg CSRs to delegate some traps to HS-mode.
+  The hedeleg and hideleg CSRs allow these traps to be further delegated to a VS-mode guest; their layout is the same as medeleg and mideleg.
+  An interrupt that has been delegated to HS-mode (using mideleg) is further delegated to VS-mode if the corresponding hideleg bit is set.
+  Among bits 15:0 of hideleg, bits 10, 6, and 2 (corresponding to the standard VS-level interrupts) are writable, and bits 12, 9, 5, and 1 (corresponding to the standard S-level interrupts) are read-only zeros.
+address: 0x603
+writable: true
+priv_mode: S
+definedBy:
+  extension:
+    name: H
+length: SXLEN
+fields:
+  SSI:
+    location: 1
+    type: RO
+    reset_value: 0
+    long_name: Supervisor Software Interrupt
+    description: Supervisor Software Interrupt
+
+  VSSI:
+    location: 2
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    long_name: Virtual Supervisor Software Interrupt
+    description: Virtual Supervisor Software Interrupt
+    sw_write(csr_value): |
+      if (CSR[mideleg].VSSI == 0) {
+        return 0;
+      }
+      if (csr_value.VSSI == 0) {
+        CSR[vsip].SSIP = 0;
+        CSR[vsie].SSIE = 0;
+      }
+      return csr_value.VSSI;
+
+  STI:
+    location: 5
+    type: RO
+    reset_value: 0
+    long_name: Supervisor Timer Interrupt
+    description: Supervisor Timer Interrupt
+
+  VSTI:
+    location: 6
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    long_name: Virtual Supervisor Timer Interrupt
+    description: Virtual Supervisor Timer Interrupt
+    sw_write(csr_value): |
+      if (CSR[mideleg].VSTI == 0) {
+        return 0;
+      }
+      if (csr_value.VSTI == 0) {
+        CSR[vsip].STIP = 0;
+        CSR[vsie].STIE = 0;
+      }
+      return csr_value.VSTI;
+
+  SEI:
+    location: 9
+    type: RO
+    reset_value: 0
+    long_name: Supervisor External Interrupt
+    description: Supervisor External Interrupt
+
+  VSEI:
+    location: 10
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    long_name: Virtual Supervisor External Interrupt
+    description: Virtual Supervisor External Interrupt
+    sw_write(csr_value): |
+      if (CSR[mideleg].VSEI == 0) {
+        return 0;
+      }
+      if (csr_value.VSEI == 0) {
+        CSR[vsip].SEIP = 0;
+        CSR[vsie].SEIE = 0;
+      }
+      return csr_value.VSEI;
+
+  SGEI:
+    location: 12
+    type: RO
+    reset_value: 0
+    long_name: Supervisor Guest External Interrupt
+    description: Supervisor Guest External Interrupt
+
+  LCOFI:
+    location: 13
+    definedBy:
+      extension:
+        name: Sscofpmf
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    long_name: Local-Counter-Overfloat Interrupt
+    description: Local-Counter-Overfloat Interrupt
+    sw_write(csr_value): |
+      if (CSR[mideleg].LCOFI == 0) {
+        return 0;
+      }
+      if (csr_value.LCOFI == 0) {
+        CSR[vsip].LCOFIP = 0;
+        CSR[vsie].LCOFIE = 0;
+      }
+      return csr_value.LCOFI;
+
+sw_read(): |
+  XReg mask = CSR[mideleg].VSSI | CSR[mideleg].VSTI | CSR[mideleg].VSEI | CSR[mideleg].LCOFI;
+  return $bits(CSR[hideleg]) & mask;

data/.data/spec/std/isa/csr/H/hie.yaml

@@ -0,0 +1,74 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hie
+long_name: Hypervisor Interrupt Enable Register
+description: |
+  The `hie` register is a read/write register in HS-mode that enables interrupts.
+  It corresponds to the enable bits for VS-level and hypervisor-specific interrupts, and supplements
+  the HS-level `sie` register.
+address: 0x604
+writable: true
+priv_mode: S
+definedBy:
+  extension:
+    name: H
+length: SXLEN
+fields:
+  # TODO: For each writable bit in sie, the corresponding bit shall be read-only zero in both hip and hie.
+
+  SGEIE:
+    location: 12
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    description: |
+      Hypervisor guest external interrupt enable bit. When set, allows external interrupts to be delivered
+      to VS-mode based on the `hgeie` setting.
+    sw_write(csr_value): |
+      if (CSR[mideleg].SGEI == 0) {
+        return 0;
+      }
+      return csr_value.SGEIE;
+
+  VSEIE:
+    location: 10
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    description: |
+      VS-level external interrupt enable bit. When set, allows external interrupts directed to VS-level
+      to be processed based on the configuration in `hvip` and other platform-specific sources.
+    sw_write(csr_value): |
+      if (CSR[mideleg].VSEI == 0) {
+        return 0;
+      }
+      return csr_value.VSEIE;
+
+  VSTIE:
+    location: 6
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    description: |
+      VS-level timer interrupt enable bit. When set, allows VS-level timer interrupts to be processed
+      based on the `hvip` configuration and any platform-specific timer interrupts.
+    sw_write(csr_value): |
+      if (CSR[mideleg].VSTI == 0) {
+        return 0;
+      }
+      return csr_value.VSTIE;
+
+  VSSIE:
+    location: 2
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    description: |
+      VS-level software interrupt enable bit. When set, allows software interrupts directed to VS-level
+      to be processed, based on the configuration in `hvip`.
+    sw_write(csr_value): |
+      if (CSR[mideleg].VSSI == 0) {
+        return 0;
+      }
+      return csr_value.VSSIE;

data/.data/spec/std/isa/csr/H/hip.yaml

@@ -0,0 +1,88 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hip
+long_name: Hypervisor Interrupt Pending Register
+writable: true
+description: |
+  The `hip` register is an HSXLEN-bit read/write register that indicates pending interrupts at the hypervisor level.
+  It contains interrupt-pending bits for both VS-level and hypervisor-specific interrupts.
+address: 0x608
+priv_mode: S
+definedBy:
+  extension:
+    name: H
+sw_read(): |
+  XReg res = 0;
+
+  # SGEIP: 1 iff bitwise AND of hgeip and hgeie is nonzero
+  if (($bits(CSR[hgeie]) & $bits(CSR[hgeip])) != 0) {
+    res[12] = 1'b1;
+  }
+
+  # VSEIP: logical OR of hvip.VSEIP and platform-specific sources
+  if (CSR[hvip].VSEIP == 1'b1) {
+    res[10] = 1'b1;
+  }
+
+  # VSTIP: logical OR of hvip.VSTIP and vstimecmp comparison (if Sstc)
+  if (implemented?(ExtensionName::Sstc)) {
+    if ((CSR[hvip].VSTIP == 1'b1) || ((read_mtime() + CSR[htimedelta].DELTA) >= CSR[vstimecmp].TIME)) {
+      res[6] = 1'b1;
+    }
+  } else {
+    if (CSR[hvip].VSTIP == 1'b1) {
+      res[6] = 1'b1;
+    }
+  }
+
+  # VSSIP: alias of hvip.VSSIP
+  if (CSR[hvip].VSSIP == 1'b1) {
+    res[2] = 1'b1;
+  }
+
+  return res;
+length: SXLEN
+fields:
+  # TODO: For each writable bit in sie, the corresponding bit shall be read-only zero in both hip and hie.
+
+  SGEIP:
+    location: 12
+    type: RO-H
+    reset_value: 0
+    description: |
+      Pending interrupt bit for supervisor guest external interrupts (SGEI).
+      This bit is 1 if and only if the logical AND of `hgeip` and `hgeie` is nonzero.
+
+  VSEIP:
+    location: 10
+    type: RO-H
+    reset_value: 0
+    description: |
+      Pending interrupt bit for VS-level external interrupts (VSEI).
+      This bit is the logical OR of `vseip` from `hvip`, the interrupt from `hgeip` selected by `hstatus.VGEIN`,
+      and any other external interrupt signal directed to VS-level.
+
+  VSTIP:
+    location: 6
+    type: RO-H
+    reset_value: 0
+    description: |
+      Pending interrupt bit for VS-level timer interrupts (VSTI).
+      This bit is the logical OR of `vstip` from `hvip` and any other timer interrupt directed to VS-level.
+
+  VSSIP:
+    location: 2
+    type: RO-H
+    reset_value: 0
+    sw_write(csr_value): |
+      # VSSIP in hip is an alias of VSSIP in hvip
+      CSR[hvip].VSSIP = csr_value.VSSIP;
+      return csr_value.VSSIP;
+    description: |
+      Pending interrupt bit for VS-level software interrupts (VSSI).
+      This bit is an alias of the `vssip` bit in `hvip`.

data/.data/spec/std/isa/csr/H/hvip.yaml

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+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: hvip
+long_name: Hypervisor Virtual Interrupt Pending Register
+description: |
+  The `hvip` register is an HSXLEN-bit read/write register that a hypervisor can write to indicate virtual interrupts intended for VS-mode.
+  It contains interrupt-pending bits for virtual interrupts such as VS-level external interrupts, timer interrupts, and software interrupts.
+address: 0x645
+writable: true
+priv_mode: S
+definedBy:
+  extension:
+    name: H
+length: SXLEN
+fields:
+  VSEIP:
+    location: 10
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    description: |
+      Pending interrupt bit for VS-level external interrupts. This bit is writable and
+      is set to 1 to assert a VS-level external interrupt.
+      TODO: assert the interrupt
+
+  VSTIP:
+    location: 6
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    description: |
+      Pending interrupt bit for VS-level timer interrupts. This bit is writable and
+      is set to 1 to assert a VS-level timer interrupt.
+      TODO: assert the interrupt
+
+  VSSIP:
+    location: 2
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    description: |
+      Pending interrupt bit for VS-level software interrupts. This bit is writable and
+      is set to 1 to assert a VS-level software interrupt.
+      TODO: assert the interrupt