udb 0.1.16 → 0.1.17

data/.data/spec/std/isa/csr/Sstc/vstimecmp.yaml

@@ -0,0 +1,45 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: vstimecmp
+long_name: Virtual supervisor timer compare
+address: 0x24D
+writable: true
+virtual_address: 0x14D
+priv_mode: VS
+length: 64
+description: |
+  Virtual supervisor timer compare register.
+
+  When `menvcfg.STCE` and `henvcfg.STCE` are set, `vstimecmp` is operational
+  and provides VS-mode with a CSR-based timer interrupt facility.
+definedBy:
+  extension:
+    allOf:
+      - name: H
+      - name: Sstc
+fields:
+  TIME:
+    location: 63-0
+    description: |
+      Time compare value for virtual supervisor timer interrupts.
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    sw_write(csr_value): |
+      if (CSR[menvcfg].STCE == 1'b0 || CSR[mcounteren].TM == 1'b0) {
+        raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+      } else if (CSR[henvcfg].STCE == 1'b0 || CSR[hcounteren].TM == 1'b0) {
+        raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
+      }
+      return csr_value.TIME;
+sw_read(): |
+  if (CSR[menvcfg].STCE == 1'b0 || CSR[mcounteren].TM == 1'b0) {
+    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  } else if (CSR[henvcfg].STCE == 1'b0 || CSR[hcounteren].TM == 1'b0) {
+    raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
+  }
+  return CSR[vstimecmp].TIME;

data/.data/spec/std/isa/csr/Sstc/vstimecmph.yaml

@@ -0,0 +1,46 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: vstimecmph
+long_name: Virtual supervisor timer compare high
+address: 0x25D
+writable: true
+virtual_address: 0x15D
+priv_mode: VS
+length: 32
+description: |
+  Upper 32 bits of the `vstimecmp` CSR.
+definedBy:
+  allOf:
+    - xlen: 32
+    - extension:
+        allOf:
+          - name: H
+          - name: Sstc
+fields:
+  TIME:
+    location: 31-0
+    alias: vstimecmp.TIME[63:32]
+    description: |
+      Upper 32 bits of the virtual supervisor timer compare value.
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    sw_write(csr_value): |
+      if (CSR[menvcfg].STCE == 1'b0 || CSR[mcounteren].TM == 1'b0) {
+        raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+      } else if (CSR[henvcfg].STCE == 1'b0 || CSR[hcounteren].TM == 1'b0) {
+        raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
+      }
+      CSR[vstimecmp].TIME = {csr_value.TIME, CSR[vstimecmp].TIME[31:0]};
+      return csr_value.TIME;
+sw_read(): |
+  if (CSR[menvcfg].STCE == 1'b0 || CSR[mcounteren].TM == 1'b0) {
+    raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+  } else if (CSR[henvcfg].STCE == 1'b0 || CSR[hcounteren].TM == 1'b0) {
+    raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
+  }
+  return CSR[vstimecmp].TIME[63:32];

data/.data/spec/std/isa/csr/V/vcsr.yaml

@@ -10,7 +10,7 @@ long_name: Vector Control and Status Register
 address: 0x00F
 writable: true
 priv_mode: U
-length: MXLEN
+length: XLEN
 description: Contains aliases to vxrm and vxsat CSRs
 definedBy:
   extension:

data/.data/spec/std/isa/csr/V/vl.yaml

@@ -10,7 +10,7 @@ long_name: Vector Length
 address: 0xC20
 writable: false
 priv_mode: U
-length: MXLEN
+length: XLEN
 description: Holds an unsigned integer specifying number of elements to be updated with results from a vector instruction.
 definedBy:
   extension:

data/.data/spec/std/isa/csr/V/vlenb.yaml

@@ -10,7 +10,7 @@ long_name: Vector Byte Length
 address: 0xC22
 writable: false
 priv_mode: U
-length: MXLEN
+length: XLEN
 description: Holds the value VLEN/8, the vector register length in bytes.
 definedBy:
   extension:

data/.data/spec/std/isa/csr/V/vstart.yaml

@@ -10,7 +10,7 @@ long_name: Vector Start Index
 address: 0x008
 writable: true
 priv_mode: U
-length: MXLEN
+length: XLEN
 description: Specifies the index of the first element to be executed by a vector instruction.
 definedBy:
   extension:

data/.data/spec/std/isa/csr/V/vtype.yaml

@@ -10,7 +10,7 @@ long_name: Vector Type
 address: 0xC21
 writable: false
 priv_mode: U
-length: MXLEN
+length: XLEN
 description: Provides the default type used to interpret the contents of the vector register file.
 definedBy:
   extension:
@@ -36,6 +36,25 @@ fields:
     type: RO-H
     reset_value(): |
       return (FOLLOW_VTYPE_RESET_RECOMMENDATION)? 1 : UNDEFINED_LEGAL;
+  ALTFMT:
+    location: 8
+    description: |
+      Selects the alternate floating-point format for vector floating-point instructions.
+
+      When ALTFMT is zero, the hart behaves as though Zvfbfa were not implemented.
+
+      Setting ALTFMT to one when SEW is greater than or equal to 32 is reserved.
+
+      [NOTE]
+      Implementations should set VILL when a reserved combination of ALTFMT and SEW is selected.
+
+      It is recommended that at reset, vill is set, and the remaining bits in vtype are zero.
+    definedBy:
+      extension:
+        name: Zvfbfa
+    type: RO-H
+    reset_value(): |
+      return (FOLLOW_VTYPE_RESET_RECOMMENDATION)? 0 : UNDEFINED_LEGAL;
   VMA:
     location: 7
     description: |

data/.data/spec/std/isa/csr/V/vxrm.yaml

@@ -10,7 +10,7 @@ long_name: Vector Fixed-Point Rounding Mode
 address: 0x00A
 writable: true
 priv_mode: U
-length: MXLEN
+length: XLEN
 description: Holds a 2-bit read-write rounding-mode field in the least-significant bits
 definedBy:
   extension:

data/.data/spec/std/isa/csr/V/vxsat.yaml

@@ -10,7 +10,7 @@ long_name: Vector Fixed-Point Saturate Flag
 address: 0x009
 writable: true
 priv_mode: U
-length: MXLEN
+length: XLEN
 description: Indicates if a fixed-point instruction has had to saturate an output value to fit into a destination format
 definedBy:
   extension:

data/.data/spec/std/isa/csr/Zicntr/mcountinhibit.layout

@@ -53,9 +53,6 @@ definedBy:
 fields:
   CY:
     location: 0
-    definedBy:
-      extension:
-        name: Sm
     description: When set, `mcycle.COUNT` stops counting in all privilege modes.
     type(): |
       return COUNTINHIBIT_EN[0] ? CsrFieldType::RW : CsrFieldType::RO;
@@ -63,9 +60,6 @@ fields:
       return COUNTINHIBIT_EN[0] ? UNDEFINED_LEGAL : 0;
   IR:
     location: 2
-    definedBy:
-      extension:
-        name: Sm
     description: When set, `minstret.COUNT` stops counting in all privilege modes.
     type(): |
       return COUNTINHIBIT_EN[2] ? CsrFieldType::RW : CsrFieldType::RO;
@@ -74,20 +68,12 @@ fields:
   <%- (3..31).each do |hpm_num| -%>
   HPM<%= hpm_num %>:
     location: <%= hpm_num %>
-    definedBy:
-      allOf:
-        - extension:
-            name: Sm
-        - param:
-            name: HPM_COUNTER_EN
-            index: <%= hpm_num %>
-            equal: true
     description: |
       [when="COUNTINHIBIT_EN[<%= hpm_num %>] == true"]
       When set, `hpmcounter<%= hpm_num %>.COUNT` stops counting in all privilege modes.
 
       [when="COUNTINHIBIT_EN[<%= hpm_num %>] == false"]
-      Since hpmcounter<%= hpm_num %> is not implemented, this field is read-only zero.
+      Since `mcountinhibit.HPM<%= hpm_num %>` is not writable, this field is read-only zero.
     type(): |
       return COUNTINHIBIT_EN[<%= hpm_num %>] ? CsrFieldType::RW : CsrFieldType::RO;
     reset_value(): |