ruby-vpi 16.0.1 → 17.0.0

data/samp/pipelined_alu/hw5_unit_test_bench.rb

@@ -1,86 +0,0 @@
-# This file is the Ruby side of the bench.
-
-require 'rubygems'
-require 'ruby-vpi'
-
-RubyVpi.init_bench :Hw5_unit, :xUnit do
-  ##
-  # This block is executed whenever Vpi::simulate is invoked.
-  #
-  # It simulates the design under test by (typically) toggling
-  # the clock signal, as demonstrated below.
-  ##
-
-  ##
-  # We are currently here (marked by the ! signs):
-  #
-  #    !
-  #    !
-  #    ! ____      ____      ____      ____
-  # ___!/    \____/    \____/    \____/    \
-  #    !
-  #    !
-  #
-  ##
-
-  Hw5_unit.clk.intVal = 1
-
-  ##
-  # After setting the clock signal to high, we are here:
-  #
-  #      !
-  #      !
-  #      !____      ____      ____      ____
-  # ____/!    \____/    \____/    \____/    \
-  #      !
-  #      !
-  #
-  ##
-
-  advance_time
-
-  ##
-  # After advancing the time, we are here:
-  #
-  #          !
-  #          !
-  #      ____!      ____      ____      ____
-  # ____/    !\____/    \____/    \____/    \
-  #          !
-  #          !
-  #
-  ##
-
-  Hw5_unit.clk.intVal = 0
-
-  ##
-  # After setting the clock signal to low, we are here:
-  #
-  #           !
-  #           !
-  #      ____ !     ____      ____      ____
-  # ____/    \!____/    \____/    \____/    \
-  #           !
-  #           !
-  #
-  ##
-
-  advance_time
-
-  ##
-  # After advancing the time, we are here:
-  #
-  #
-  #               !
-  #               !
-  #      ____     ! ____      ____      ____
-  # ____/    \____!/    \____/    \____/    \
-  #               !
-  #               !
-  #
-  ##
-
-  ##
-  # This process repeats when Vpi::simulate is invoked again.
-  ##
-end

data/samp/pipelined_alu/hw5_unit_test_bench.v

@@ -1,14 +0,0 @@
-// This file is the Verilog side of the bench.
-module hw5_unit_test_bench;
-  reg  clk;
-  reg  reset;
-  reg [`DATABITS-1:0] in_databits;
-  reg [`WIDTH-1:0] a;
-  reg [`WIDTH-1:0] b;
-  reg [1:0] in_op;
-  wire [`WIDTH-1:0] res;
-  wire [`DATABITS-1:0] out_databits;
-  wire [1:0] out_op;
-
-  hw5_unit  hw5_unit_test_bench_design(.clk(clk), .reset(reset), .in_databits(in_databits), .a(a), .b(b), .in_op(in_op), .res(res), .out_databits(out_databits), .out_op(out_op));
-endmodule

data/samp/pipelined_alu/hw5_unit_test_design.rb

@@ -1,61 +0,0 @@
-# This is a Ruby interface to the design under test.
-
-WIDTH = 32
-DATABITS = 7
-OP_NOP = 0
-OP_ADD = 1
-OP_SUB = 2
-OP_MULT = 3
-OPERATIONS = (OP_NOP..OP_MULT).to_a
-
-# Number of cycles needed to reset this design.
-RESET_DELAY = 5
-
-# This method resets the design under test.
-def Hw5_unit.reset!
-  reset.hexStrVal = 'x'
-  in_databits.hexStrVal = 'x'
-  a.hexStrVal = 'x'
-  b.hexStrVal = 'x'
-  in_op.hexStrVal = 'x'
-
-
-  reset.intVal = 1
-
-  RESET_DELAY.times do
-    simulate
-  end
-
-  reset.intVal = 0
-end
-
-
-# Represents an ALU operation.
-class Operation
-  attr_accessor :type, :tag, :arg1, :arg2, :stage, :result
-
-  def initialize(type, tag, arg1 = 0, arg2 = 0)
-    raise ArgumentError unless OPERATIONS.include? type
-
-    @type = type
-    @tag = tag
-    @arg1 = arg1
-    @arg2 = arg2
-
-    @stage = 0
-  end
-
-  # Computes the result of this operation.
-  def compute
-    case @type
-      when OP_ADD
-        @arg1 + @arg2
-
-      when OP_SUB
-        @arg1 - @arg2
-
-      when OP_MULT
-        @arg1 * @arg2
-    end
-  end
-end

data/samp/pipelined_alu/hw5_unit_test_proto.rb

@@ -1,7 +0,0 @@
-# This is a prototype of the design under test.
-
-# When prototyping is enabled, Vpi::advance_time invokes this
-# method instead of transferring control to the Verilog simulator.
-def Hw5_unit.simulate!
-  raise NotImplementedError, "Prototype is not yet implemented."
-end

data/samp/pipelined_alu/hw5_unit_test_runner.rake

@@ -1,52 +0,0 @@
-# This file runs the test.
-
-# These are Verilog source files that need to be loaded
-# by the simulator before they can be simulated.
-SIMULATOR_SOURCES = [
-  'hw5_unit.v',
-  'hw5_unit_test_bench.v',
-]
-
-# These are paths to directories which contain the
-# sources listed above, the files they `include, or both.
-SIMULATOR_INCLUDES = []
-
-# This specifies the "top module" that is to be simulated.
-SIMULATOR_TARGET = 'hw5_unit_test_bench'
-
-# These are command-line arguments for the simulator.
-# They can be specified as a string or an array of strings:
-#
-#   :cver => "this is one single argument",
-#   :cver => ['these', 'are', 'separate', 'arguments'],
-#   :cver => %w[these are also separate arguments],
-#
-SIMULATOR_ARGUMENTS = {
-  # GPL Cver
-  :cver => '',
-
-  # Icarus Verilog
-  :ivl => '',
-
-  # Synopsys VCS
-  :vcs => '',
-
-  # Mentor Modelsim
-  :vsim => '',
-
-  # Cadence NC-Sim
-  :ncsim => '',
-
-}
-
-# This task is invoked _before_ the simulator runs.
-# It can be used to make preprations, such as converting
-# Verilog header files into Ruby, for the simulation.
-task :setup do
-  # To learn how to write Rake tasks, please see:
-  # http://docs.rubyrake.org/read/chapter/4#page16
-end
-
-# This command loads the Ruby-VPI runner template, which
-# runs the simulator according to the information above.
-require 'ruby-vpi/runner'

data/samp/pipelined_alu/hw5_unit_test_spec.rb

@@ -1,68 +0,0 @@
-# This file is a behavioral specification for the design under test.
-#--
-# Copyright 2006 Suraj N. Kurapati
-# See the file named LICENSE for details.
-
-require 'int_gen'
-
-class Hw5_unit_test_spec < Test::Unit::TestCase
-  # Number of input sequences to test.
-  NUM_TESTS = 4000
-
-  # Bitmask capable of capturing ALU result.
-  ALU_RESULT_MASK = (2 ** WIDTH) - 1
-
-  # Upper limit of values allowed for an operation's tag.
-  OPERATION_TAG_LIMIT = 2 ** DATABITS
-
-  def setup
-    Hw5_unit.reset!
-    @intGen = IntegerGenerator.new(WIDTH)
-  end
-
-  def test_pipeline
-    issuedOps = []
-    numIssued = numVerified = 0
-
-    until numVerified == NUM_TESTS
-      # issue a new operation
-        if numIssued < NUM_TESTS
-          op = Operation.new(
-            OPERATIONS[rand(OPERATIONS.size)],
-            numIssued % OPERATION_TAG_LIMIT,
-            @intGen.random,
-            @intGen.random
-          )
-
-          Hw5_unit.a.intVal = op.arg1
-          Hw5_unit.b.intVal = op.arg2
-          Hw5_unit.in_op.intVal = op.type
-          Hw5_unit.in_databits.intVal = op.tag
-
-          issuedOps << op
-          numIssued += 1
-        end
-
-      simulate
-
-      # verify result of finished operation
-        unless Hw5_unit.out_databits.x?
-          finishedOp = Operation.new(
-            Hw5_unit.out_op.intVal,
-            Hw5_unit.out_databits.intVal
-          )
-          finishedOp.result = Hw5_unit.res.intVal & ALU_RESULT_MASK
-
-          expectedOp = issuedOps.shift
-          assert_equal expectedOp.type, finishedOp.type, "incorrect operation"
-          assert_equal expectedOp.tag, finishedOp.tag, "incorrect tag"
-
-          unless finishedOp.type == OP_NOP
-            assert_equal expectedOp.compute & ALU_RESULT_MASK, finishedOp.result, "incorrect result"
-          end
-
-          numVerified += 1
-        end
-    end
-  end
-end