ruby-vpi 16.0.1 → 17.0.0

metadata

@@ -3,8 +3,8 @@ rubygems_version: 0.9.4
 specification_version: 1
 name: ruby-vpi
 version: !ruby/object:Gem::Version 
-  version: 16.0.1
-date: 2007-05-27 00:00:00 -07:00
+  version: 17.0.0
+date: 2007-07-22 00:00:00 -07:00
 summary: Ruby interface to IEEE 1364-2005 Verilog VPI
 require_paths: 
 - lib
@@ -31,7 +31,6 @@ authors: []
 files: 
 - LICENSE
 - ext
-- README
 - bin
 - lib
 - Rakefile
@@ -39,6 +38,7 @@ files:
 - index.html
 - samp
 - gem_extconf.rb
+- README
 - ref
 - ext/swig_vpi.i
 - ext/vlog.c
@@ -47,27 +47,27 @@ files:
 - ext/extconf.rb
 - ext/relay.h
 - ext/main.h
-- ext/main.c
 - ext/verilog.h
 - ext/vlog.h
 - ext/relay.c
 - ext/Doxyfile
 - ext/vpi_user.h
+- ext/main.c
 - ext/swig_vpi.h
 - ext/swig_wrap.cin
-- bin/generate_test.rb
-- bin/generate_test_tpl
-- bin/header_to_ruby.rb
-- bin/generate_test_tpl/runner.rake
-- bin/generate_test_tpl/bench.rb
-- bin/generate_test_tpl/bench.v
-- bin/generate_test_tpl/design.rb
-- bin/generate_test_tpl/proto.rb
-- bin/generate_test_tpl/spec.rb
+- bin/generate
+- bin/convert.rb
+- bin/ruby-vpi
+- bin/generate.rb
+- bin/generate/runner.rake
+- bin/generate/design.rb
+- bin/generate/proto.rb
+- bin/generate/spec.rb
 - lib/ruby-vpi.rb
 - lib/ruby-vpi
 - lib/ruby-vpi/erb.rb
 - lib/ruby-vpi/rake.rb
+- lib/ruby-vpi/util.rb
 - lib/ruby-vpi/runner.rb
 - lib/ruby-vpi/integer.rb
 - lib/ruby-vpi/rdoc.rb
@@ -76,6 +76,8 @@ files:
 - lib/ruby-vpi/rcov.rb
 - lib/ruby-vpi/vpi.rb
 - lib/ruby-vpi/verilog_parser.rb
+- lib/ruby-vpi/runner_boot_loader.rb
+- doc/common.inc
 - doc/Rakefile
 - doc/figures
 - doc/images
@@ -83,15 +85,16 @@ files:
 - doc/memo.doc
 - doc/manual.doc
 - doc/history.doc
-- doc/README
 - doc/common.css
 - doc/readme.doc
 - doc/common.tpl
 - doc/history.rb
 - doc/intro.inc
 - doc/lib
+- doc/README
 - doc/print.css
 - doc/history.yaml
+- doc/history.inc
 - doc/memo.html
 - doc/manual.html
 - doc/history.html
@@ -133,32 +136,41 @@ files:
 - doc/lib/erb_proxy.rb
 - samp/pipelined_alu
 - samp/counter
+- samp/register_file
 - samp/pipelined_alu/TestHw5UnitModel.rb
 - samp/pipelined_alu/Hw5UnitModel.rb
 - samp/pipelined_alu/README
 - samp/pipelined_alu/int_gen.rb
 - samp/pipelined_alu/hw5_unit.v
 - samp/pipelined_alu/Rakefile
-- samp/pipelined_alu/hw5_unit_test_spec.rb
-- samp/pipelined_alu/hw5_unit_test_bench.v
-- samp/pipelined_alu/hw5_unit_test_runner.rake
-- samp/pipelined_alu/hw5_unit_test_bench.rb
-- samp/pipelined_alu/hw5_unit_test_design.rb
-- samp/pipelined_alu/hw5_unit_test_proto.rb
+- samp/pipelined_alu/hw5_unit_design.rb
+- samp/pipelined_alu/hw5_unit_spec.rb
+- samp/pipelined_alu/hw5_unit_proto.rb
+- samp/pipelined_alu/hw5_unit_runner.rake
 - samp/counter/counter.v
-- samp/counter/counter_rspec_bench.rb
-- samp/counter/counter_rspec_bench.v
+- samp/counter/xUnit
 - samp/counter/Rakefile
-- samp/counter/counter_rspec_spec.rb
-- samp/counter/counter_rspec_design.rb
-- samp/counter/counter_xunit_bench.rb
-- samp/counter/counter_xunit_bench.v
-- samp/counter/counter_rspec_proto.rb
-- samp/counter/counter_rspec_runner.rake
-- samp/counter/counter_xunit_design.rb
-- samp/counter/counter_xunit_proto.rb
-- samp/counter/counter_xunit_runner.rake
-- samp/counter/counter_xunit_spec.rb
+- samp/counter/RSpec
+- samp/counter/xUnit/counter_bench.rb
+- samp/counter/xUnit/counter_bench.v
+- samp/counter/xUnit/counter_design.rb
+- samp/counter/xUnit/counter_proto.rb
+- samp/counter/xUnit/counter_runner.rake
+- samp/counter/xUnit/counter_spec.rb
+- samp/counter/xUnit/Rakefile
+- samp/counter/RSpec/counter_design.rb
+- samp/counter/RSpec/counter_proto.rb
+- samp/counter/RSpec/counter_runner.rake
+- samp/counter/RSpec/counter_spec.rb
+- samp/counter/RSpec/Rakefile
+- samp/register_file/LICENSE
+- samp/register_file/Rakefile
+- samp/register_file/README
+- samp/register_file/register_file.v
+- samp/register_file/register_file_design.rb
+- samp/register_file/register_file_proto.rb
+- samp/register_file/register_file_runner.rake
+- samp/register_file/register_file_spec.rb
 - ref/c
 - ref/ruby
 - ref/c/doxygen.png
@@ -219,14 +231,14 @@ files:
 - ref/ruby/fr_class_index.html
 - ref/ruby/fr_method_index.html
 - ref/ruby/index.html
-- ref/ruby/files/bin
 - ref/ruby/files/lib
-- ref/ruby/files/bin/generate_test_rb.html
-- ref/ruby/files/bin/header_to_ruby_rb.html
-- ref/ruby/files/lib/ruby-vpi_rb.html
+- ref/ruby/files/bin
 - ref/ruby/files/lib/ruby-vpi
+- ref/ruby/files/lib/ruby-vpi_rb.html
+- ref/ruby/files/lib/ruby-vpi/runner_boot_loader_rb.src
 - ref/ruby/files/lib/ruby-vpi/erb_rb.html
 - ref/ruby/files/lib/ruby-vpi/rake_rb.html
+- ref/ruby/files/lib/ruby-vpi/util_rb.html
 - ref/ruby/files/lib/ruby-vpi/runner_rb.html
 - ref/ruby/files/lib/ruby-vpi/integer_rb.html
 - ref/ruby/files/lib/ruby-vpi/rdoc_rb.html
@@ -235,6 +247,11 @@ files:
 - ref/ruby/files/lib/ruby-vpi/rcov_rb.html
 - ref/ruby/files/lib/ruby-vpi/vpi_rb.html
 - ref/ruby/files/lib/ruby-vpi/verilog_parser_rb.html
+- ref/ruby/files/lib/ruby-vpi/runner_boot_loader_rb.html
+- ref/ruby/files/lib/ruby-vpi/runner_boot_loader_rb.src/M000001.html
+- ref/ruby/files/lib/ruby-vpi/runner_boot_loader_rb.src/M000002.html
+- ref/ruby/files/bin/convert_rb.html
+- ref/ruby/files/bin/generate_rb.html
 - ref/ruby/classes/VerilogParser.src
 - ref/ruby/classes/VerilogParser
 - ref/ruby/classes/Integer.src
@@ -242,7 +259,6 @@ files:
 - ref/ruby/classes/String.src
 - ref/ruby/classes/ERB.src
 - ref/ruby/classes/FileUtils.src
-- ref/ruby/classes/RubyVpi.src
 - ref/ruby/classes/Vpi.src
 - ref/ruby/classes/Vpi
 - ref/ruby/classes/RDoc.src
@@ -252,56 +268,50 @@ files:
 - ref/ruby/classes/String.html
 - ref/ruby/classes/ERB.html
 - ref/ruby/classes/FileUtils.html
-- ref/ruby/classes/RubyVpi.html
-- ref/ruby/classes/RubyVpi
+- ref/ruby/classes/RubyVPI.html
 - ref/ruby/classes/Vpi.html
 - ref/ruby/classes/RDoc.html
-- ref/ruby/classes/VerilogParser.src/M000001.html
+- ref/ruby/classes/VerilogParser.src/M000004.html
 - ref/ruby/classes/VerilogParser/Module.src
 - ref/ruby/classes/VerilogParser/Module
 - ref/ruby/classes/VerilogParser/Module.html
-- ref/ruby/classes/VerilogParser/Module.src/M000002.html
+- ref/ruby/classes/VerilogParser/Module.src/M000005.html
 - ref/ruby/classes/VerilogParser/Module/Port.src
-- ref/ruby/classes/VerilogParser/Module/Parameter.src
 - ref/ruby/classes/VerilogParser/Module/Port.html
-- ref/ruby/classes/VerilogParser/Module/Parameter.html
-- ref/ruby/classes/VerilogParser/Module/Port.src/M000003.html
-- ref/ruby/classes/VerilogParser/Module/Port.src/M000004.html
-- ref/ruby/classes/VerilogParser/Module/Port.src/M000005.html
 - ref/ruby/classes/VerilogParser/Module/Port.src/M000006.html
-- ref/ruby/classes/VerilogParser/Module/Parameter.src/M000007.html
-- ref/ruby/classes/Integer.src/M000008.html
+- ref/ruby/classes/VerilogParser/Module/Port.src/M000007.html
+- ref/ruby/classes/VerilogParser/Module/Port.src/M000008.html
 - ref/ruby/classes/Integer.src/M000009.html
 - ref/ruby/classes/Integer.src/M000010.html
 - ref/ruby/classes/Integer.src/M000011.html
 - ref/ruby/classes/Integer.src/M000012.html
 - ref/ruby/classes/Integer.src/M000013.html
-- ref/ruby/classes/Integer.src/M000016.html
+- ref/ruby/classes/Integer.src/M000014.html
 - ref/ruby/classes/Integer.src/M000017.html
 - ref/ruby/classes/Integer.src/M000018.html
 - ref/ruby/classes/Integer.src/M000019.html
-- ref/ruby/classes/Float.src/M000020.html
-- ref/ruby/classes/String.src/M000021.html
+- ref/ruby/classes/Integer.src/M000020.html
+- ref/ruby/classes/Float.src/M000021.html
 - ref/ruby/classes/String.src/M000022.html
 - ref/ruby/classes/String.src/M000023.html
-- ref/ruby/classes/ERB.src/M000024.html
-- ref/ruby/classes/FileUtils.src/M000025.html
-- ref/ruby/classes/FileUtils.src/M000026.html
-- ref/ruby/classes/RubyVpi.src/M000027.html
-- ref/ruby/classes/Vpi.src/M000028.html
+- ref/ruby/classes/String.src/M000024.html
+- ref/ruby/classes/String.src/M000025.html
+- ref/ruby/classes/ERB.src/M000026.html
+- ref/ruby/classes/FileUtils.src/M000027.html
+- ref/ruby/classes/FileUtils.src/M000028.html
 - ref/ruby/classes/Vpi.src/M000029.html
 - ref/ruby/classes/Vpi.src/M000030.html
 - ref/ruby/classes/Vpi.src/M000031.html
-- ref/ruby/classes/Vpi.src/M000032.html
 - ref/ruby/classes/Vpi/S_vpi_value.src
 - ref/ruby/classes/Vpi/Handle.src
 - ref/ruby/classes/Vpi/S_vpi_time.src
 - ref/ruby/classes/Vpi/S_vpi_value.html
 - ref/ruby/classes/Vpi/Handle.html
 - ref/ruby/classes/Vpi/S_vpi_time.html
+- ref/ruby/classes/Vpi/S_vpi_value.src/M000032.html
 - ref/ruby/classes/Vpi/S_vpi_value.src/M000033.html
 - ref/ruby/classes/Vpi/S_vpi_value.src/M000034.html
-- ref/ruby/classes/Vpi/S_vpi_value.src/M000035.html
+- ref/ruby/classes/Vpi/Handle.src/M000035.html
 - ref/ruby/classes/Vpi/Handle.src/M000036.html
 - ref/ruby/classes/Vpi/Handle.src/M000037.html
 - ref/ruby/classes/Vpi/Handle.src/M000038.html
@@ -313,12 +323,15 @@ files:
 - ref/ruby/classes/Vpi/Handle.src/M000044.html
 - ref/ruby/classes/Vpi/Handle.src/M000045.html
 - ref/ruby/classes/Vpi/Handle.src/M000046.html
+- ref/ruby/classes/Vpi/Handle.src/M000047.html
 - ref/ruby/classes/Vpi/Handle.src/M000048.html
-- ref/ruby/classes/Vpi/Handle.src/M000049.html
-- ref/ruby/classes/Vpi/S_vpi_time.src/M000050.html
-- ref/ruby/classes/Vpi/S_vpi_time.src/M000051.html
-- ref/ruby/classes/RDoc.src/M000053.html
-- ref/ruby/classes/RubyVpi/Config.html
+- ref/ruby/classes/Vpi/Handle.src/M000050.html
+- ref/ruby/classes/Vpi/Handle.src/M000051.html
+- ref/ruby/classes/Vpi/Handle.src/M000053.html
+- ref/ruby/classes/Vpi/Handle.src/M000054.html
+- ref/ruby/classes/Vpi/S_vpi_time.src/M000055.html
+- ref/ruby/classes/Vpi/S_vpi_time.src/M000056.html
+- ref/ruby/classes/RDoc.src/M000058.html
 test_files: []
 
 rdoc_options: []
@@ -326,8 +339,7 @@ rdoc_options: []
 extra_rdoc_files: []
 
 executables: 
-- generate_test.rb
-- header_to_ruby.rb
+- ruby-vpi
 extensions: 
 - gem_extconf.rb
 requirements: 
@@ -350,7 +362,7 @@ dependencies:
     requirements: 
     - - ">="
       - !ruby/object:Gem::Version 
-        version: 0.7.0
+        version: 1.0.0
     version: 
 - !ruby/object:Gem::Dependency 
   name: rcov

data/bin/generate_test.rb

@@ -1,200 +0,0 @@
-# Generates Ruby-VPI tests from Verilog 2001 module declarations.
-#
-# * The standard input stream is read if no input files are specified.
-#
-# * The first input signal in a module's declaration is assumed to be the
-#   clocking signal.
-#
-#
-# = Progress indicators
-#
-# module:: A Verilog module has been identified.
-#
-# create:: A file is being created because it does not exist.
-#
-# skip:: A file is being skipped because it is already up to date.
-#
-# update::  A file will be updated because it is out of date. A text merging
-#           tool (see MERGER) will be launched to transfer content from the old
-#           file (*.old) and the new file (*.new) to the out of date file. If a
-#           text merging tool is not specified, then you will have to do the
-#           merging by hand.
-#
-#
-# = Environment variables
-#
-# MERGER::  A command that invokes a text merging tool with three arguments: (1)
-#           old file, (2) new file, (3) output file. The tool's output should be
-#           written to the output file.
-#
-#--
-# Copyright 2006 Suraj N. Kurapati
-# See the file named LICENSE for details.
-
-require 'ruby-vpi' # for project info
-require 'ruby-vpi/verilog_parser'
-require 'fileutils'
-require 'digest/md5'
-
-
-# Notify the user about some action being performed.
-def notify *args # :nodoc:
-  printf "%8s  %s\n", *args
-end
-
-# Writes the given contents to the file at the given path. If the given path
-# already exists, then a backup is created before invoking the merging tool.
-def write_file aPath, aContent # :nodoc:
-  if File.exist? aPath
-    oldDigest = Digest::MD5.digest(File.read(aPath))
-    newDigest = Digest::MD5.digest(aContent)
-
-    if oldDigest == newDigest
-      notify :skip, aPath
-    else
-      notify :update, aPath
-      cur, old, new = aPath, "#{aPath}.old", "#{aPath}.new"
-
-      FileUtils.cp cur, old, :preserve => true
-      File.open(new, 'w') {|f| f << aContent}
-
-      if m = ENV['MERGER']
-        system "#{m} #{old.inspect} #{new.inspect} #{cur.inspect}"
-      end
-    end
-  else
-    notify :create, aPath
-    File.open(aPath, 'w') {|f| f << aContent}
-  end
-end
-
-
-require 'ruby-vpi/erb'
-
-# Template used for generating output.
-class Template < ERB # :nodoc:
-  TEMPLATE_PATH = __FILE__.sub %r{\.rb$}, '_tpl'
-
-  def initialize aName
-    super File.read(File.join(TEMPLATE_PATH, aName))
-  end
-end
-
-
-
-# Holds information about the output destinations of a parsed Verilog module.
-class OutputInfo # :nodoc:
-  RUBY_EXT = '.rb'
-  VERILOG_EXT = '.v'
-  RUNNER_EXT = '.rake'
-
-  SPEC_FORMATS = [:rSpec, :tSpec, :xUnit, :generic]
-
-  attr_reader :verilogBenchName, :verilogBenchPath, :rubyBenchName, :rubyBenchPath, :designName, :designClassName, :designPath, :specName, :specClassName, :specFormat, :specPath, :rubyVpiPath, :runnerName, :runnerPath, :protoName, :protoPath
-
-  attr_reader :testName, :suffix, :benchSuffix, :designSuffix, :specSuffix, :runnerSuffix, :protoSuffix
-
-  def initialize aModuleName, aSpecFormat, aTestName, aRubyVpiPath
-    raise ArgumentError unless SPEC_FORMATS.include? aSpecFormat
-    @specFormat = aSpecFormat
-    @testName = aTestName
-
-    @suffix = '_' + @testName
-    @benchSuffix = @suffix + '_bench'
-    @designSuffix = @suffix + '_design'
-    @specSuffix = @suffix + '_spec'
-    @runnerSuffix = @suffix + '_runner'
-    @protoSuffix = @suffix + '_proto'
-
-    @rubyVpiPath = aRubyVpiPath
-
-    @verilogBenchName = aModuleName + @benchSuffix
-    @verilogBenchPath = @verilogBenchName + VERILOG_EXT
-
-    @rubyBenchName = aModuleName + @benchSuffix
-    @rubyBenchPath = @rubyBenchName + RUBY_EXT
-
-    @designName = aModuleName + @designSuffix
-    @designPath = @designName + RUBY_EXT
-
-    @protoName = aModuleName + @protoSuffix
-    @protoPath = @protoName + RUBY_EXT
-
-    @specName = aModuleName + @specSuffix
-    @specPath = @specName + RUBY_EXT
-
-    @designClassName = aModuleName.to_ruby_const_name
-    @specClassName = @specName.to_ruby_const_name
-
-    @runnerName = aModuleName + @runnerSuffix
-    @runnerPath = @runnerName + RUNNER_EXT
-  end
-end
-
-
-
-if File.basename($0) == File.basename(__FILE__)
-  # obtain templates for output generation
-    VERILOG_BENCH_TEMPLATE = Template.new('bench.v')
-    RUBY_BENCH_TEMPLATE = Template.new('bench.rb')
-    DESIGN_TEMPLATE = Template.new('design.rb')
-    PROTO_TEMPLATE = Template.new('proto.rb')
-    SPEC_TEMPLATE = Template.new('spec.rb')
-    RUNNER_TEMPLATE = Template.new('runner.rake')
-
-
-  # parse command-line options
-    require 'optparse'
-
-    optSpecFmt = :generic
-    optTestName = 'test'
-
-    opts = OptionParser.new
-    opts.banner = "Usage: #{File.basename __FILE__} [options] [files]"
-
-    opts.on '-h', '--help', 'show this help message' do
-      require 'ruby-vpi/rdoc'
-      RDoc.usage_from_file __FILE__
-
-      puts opts
-      exit
-    end
-
-    opts.on '--xunit', '--test-unit', 'use xUnit (Test::Unit) specification format' do |val|
-      optSpecFmt = :xUnit if val
-    end
-
-    opts.on '--rspec', 'use rSpec specification format' do |val|
-      optSpecFmt = :rSpec if val
-    end
-
-    opts.on '--tspec', '--test-spec', 'use test/spec specification format' do |val|
-      optSpecFmt = :tSpec if val
-    end
-
-    opts.on '-n', '--name NAME', 'insert NAME into the names of generated files' do |val|
-      optTestName = val
-    end
-
-    opts.parse! ARGV
-
-
-  v = VerilogParser.new(ARGF.read)
-
-  v.modules.each do |m|
-    puts
-    notify :module, m.name
-
-    o = OutputInfo.new(m.name, optSpecFmt, optTestName, File.dirname(File.dirname(__FILE__)))
-
-    # generate output
-      aParseInfo, aModuleInfo, aOutputInfo = v.freeze, m.freeze, o.freeze
-
-      write_file o.runnerPath, RUNNER_TEMPLATE.result(binding)
-      write_file o.verilogBenchPath, VERILOG_BENCH_TEMPLATE.result(binding)
-      write_file o.rubyBenchPath, RUBY_BENCH_TEMPLATE.result(binding)
-      write_file o.designPath, DESIGN_TEMPLATE.result(binding)
-      write_file o.protoPath, PROTO_TEMPLATE.result(binding)
-      write_file o.specPath, SPEC_TEMPLATE.result(binding)
-  end
-end

data/bin/generate_test_tpl/bench.rb

@@ -1,89 +0,0 @@
-<%
-  clock = aOutputInfo.designClassName + '.' + aModuleInfo.ports.first.name
-%>
-# This file is the Ruby side of the bench.
-
-require 'rubygems'
-require 'ruby-vpi'
-
-RubyVpi.init_bench :<%= aOutputInfo.designClassName %>, :<%= aOutputInfo.specFormat %> do
-  ##
-  # This block is executed whenever Vpi::simulate is invoked.
-  #
-  # It simulates the design under test. This is typically done
-  # by toggling the clock signal, as demonstrated below.
-  ##
-
-  ##
-  # We are currently here (marked by the ! signs):
-  #
-  #    !
-  #    !
-  #    ! ____      ____      ____      ____
-  # ___!/    \____/    \____/    \____/    \
-  #    !
-  #    !
-  #
-  ##
-
-  <%= clock %>.intVal = 1
-
-  ##
-  # After setting the clock signal to high, we are here:
-  #
-  #      !
-  #      !
-  #      !____      ____      ____      ____
-  # ____/!    \____/    \____/    \____/    \
-  #      !
-  #      !
-  #
-  ##
-
-  advance_time
-
-  ##
-  # After advancing the time, we are here:
-  #
-  #          !
-  #          !
-  #      ____!      ____      ____      ____
-  # ____/    !\____/    \____/    \____/    \
-  #          !
-  #          !
-  #
-  ##
-
-  <%= clock %>.intVal = 0
-
-  ##
-  # After setting the clock signal to low, we are here:
-  #
-  #           !
-  #           !
-  #      ____ !     ____      ____      ____
-  # ____/    \!____/    \____/    \____/    \
-  #           !
-  #           !
-  #
-  ##
-
-  advance_time
-
-  ##
-  # After advancing the time, we are here:
-  #
-  #
-  #               !
-  #               !
-  #      ____     ! ____      ____      ____
-  # ____/    \____!/    \____/    \____/    \
-  #               !
-  #               !
-  #
-  ##
-
-  ##
-  # This process repeats when Vpi::simulate is invoked again.
-  ##
-end

data/bin/generate_test_tpl/bench.v

@@ -1,26 +0,0 @@
-<%
-  # Returns a comma-separated string of parameter declarations in Verilog module instantiation format.
-  def make_inst_param_decl aParams
-    aParams.map do |param|
-      ".#{param.name}(#{param.name})"
-    end.join(', ')
-  end
-%>
-// This file is the Verilog side of the bench.
-module <%= aOutputInfo.verilogBenchName %>;
-<% aModuleInfo.parameters.each do |param| %>
-  parameter <%= param.decl %>;
-<% end %>
-<% aModuleInfo.ports.each do |port| %>
-  <%= port.input? ? 'reg' : 'wire' %> <%= port.size %> <%= port.name %>;
-<% end %>
-
-  <%= aModuleInfo.name %> <%
-    instConfigDecl = make_inst_param_decl(aModuleInfo.parameters)
-
-    unless instConfigDecl.empty?
-    %>#(<%= instConfigDecl %>)<%
-    end
-
-  %> <%= aOutputInfo.verilogBenchName %>_design(<%= make_inst_param_decl(aModuleInfo.ports) %>);
-endmodule

data/bin/generate_test_tpl/design.rb

@@ -1,11 +0,0 @@
-# This is a Ruby interface to the design under test.
-<% aParseInfo.constants.each do |var| %>
-<%= var.name.to_ruby_const_name %> = <%= var.value.verilog_to_ruby %>
-<% end %>
-
-# This method resets the design under test.
-def <%= aOutputInfo.designClassName %>.reset!
-<% aModuleInfo.ports.select { |p| p.input? }[1..-1].each do |port| # using [1..] because the first signal is the clock %>
-  <%= port.name %>.hexStrVal = 'x'
-<% end %>
-end

data/bin/generate_test_tpl/proto.rb

@@ -1,16 +0,0 @@
-# This is a prototype of the design under test.
-
-# When prototyping is enabled, Vpi::advance_time invokes this
-# method instead of transferring control to the Verilog simulator.
-def <%= aOutputInfo.designClassName %>.simulate!
-  if <%= aModuleInfo.ports.first.name %>.intVal == 1
-    # discard old outputs
-<% aModuleInfo.ports.reject { |p| p.input? }.each do |port| %>
-      <%= port.name %>.hexStrVal = 'x'
-<% end %>
-
-    # process new inputs
-
-    # produce new outputs
-  end
-end

data/bin/generate_test_tpl/runner.rake

@@ -1,42 +0,0 @@
-# This file runs the test.
-
-# These are Verilog source files that need to be loaded
-# by the simulator before they can be simulated.
-SIMULATOR_SOURCES = [
-  '<%= aModuleInfo.name %>.v',
-  '<%= aOutputInfo.verilogBenchPath %>',
-]
-
-# These are paths to directories which contain the
-# sources listed above, the files they `include, or both.
-SIMULATOR_INCLUDES = []
-
-# This specifies the "top module" that is to be simulated.
-SIMULATOR_TARGET = '<%= aOutputInfo.verilogBenchName %>'
-
-# These are command-line arguments for the simulator.
-# They can be specified as a string or an array of strings:
-#
-#   :cver => "this is one single argument",
-#   :cver => ['these', 'are', 'separate', 'arguments'],
-#   :cver => %w[these are also separate arguments],
-#
-SIMULATOR_ARGUMENTS = {
-<% RubyVpi::Config::SIMULATORS.each_pair do |id, sim| %>
-  # <%= sim.name %>
-  :<%= id %> => '',
-
-<% end %>
-}
-
-# This task is invoked _before_ the simulator runs.
-# It can be used to make preprations, such as converting
-# Verilog header files into Ruby, for the simulation.
-task :setup do
-  # To learn how to write Rake tasks, please see:
-  # http://docs.rubyrake.org/read/chapter/4#page16
-end
-
-# This command loads the Ruby-VPI runner template, which
-# runs the simulator according to the information above.
-require 'ruby-vpi/runner'