ruby-vpi 16.0.1 → 17.0.0

data/samp/counter/xUnit/counter_runner.rake

@@ -0,0 +1,44 @@
+# Array of paths and shell globs (see the Dir.glob method's documentation for
+# details) to source files and directories that contain source files.  These
+# source files will be loaded by the simulator before the simulation begins.
+SIMULATOR_SOURCES = FileList[
+  'counter.v',
+  '..'
+]
+
+# Command-line arguments for the simulator.  These arguments can be
+# specified as a string or an array of strings, as demonstrated below:
+#
+#   :cver => "this is a single string argument",
+#   :cver => ["these", "are", "separate", "arguments"],
+#   :cver => %w[these are also separate arguments],
+#
+SIMULATOR_ARGUMENTS = {
+  # GPL Cver
+  :cver => "",
+
+  # Icarus Verilog
+  :ivl => "",
+
+  # Synopsys VCS
+  :vcs => "",
+
+  # Mentor Modelsim
+  :vsim => "",
+
+  # Cadence NC-Sim
+  :ncsim => "",
+
+}
+
+# This task is invoked before the simulator runs.  It
+# can be used to make preprations, such as converting
+# Verilog header files into Ruby, for the simulation.
+task :setup do
+  # To learn how to write Rake tasks, please see:
+  # http://docs.rubyrake.org/read/chapter/4#page16
+end
+
+# This command loads the Ruby-VPI runner template,
+# which runs the simulator using the above parameters.
+require 'ruby-vpi/runner'

data/samp/counter/{counter_xunit_spec.rb → xUnit/counter_spec.rb}

@@ -1,7 +1,7 @@
-# This file is a behavioral specification for the design under test.
+require 'test/unit'
 
 # lowest upper bound of counter's value
-LIMIT = 2 ** Counter.Size.intVal
+LIMIT = 2 ** Counter::Size
 
 # maximum allowed value for a counter
 MAX = LIMIT - 1
@@ -12,13 +12,13 @@ class ResettedCounterValue < Test::Unit::TestCase
   end
 
   def test_zero
-    assert_equal 0, Counter.count.intVal
+    assert_equal( 0, Counter.count.intVal )
   end
 
   def test_increment
     LIMIT.times do |i|
-      assert_equal i, Counter.count.intVal
-      simulate # increment the counter
+      assert_equal( i, Counter.count.intVal )
+      Counter.cycle! # increment the counter
     end
   end
 end
@@ -28,12 +28,12 @@ class MaximumCounterValue < Test::Unit::TestCase
     Counter.reset!
 
     # increment the counter to maximum value
-    MAX.times {simulate}
-    assert_equal MAX, Counter.count.intVal
+    MAX.times { Counter.cycle! }
+    assert_equal( MAX, Counter.count.intVal )
   end
 
   def test_overflow
-    simulate # increment the counter
-    assert_equal 0, Counter.count.intVal
+    Counter.cycle! # increment the counter
+    assert_equal( 0, Counter.count.intVal )
   end
 end

data/samp/pipelined_alu/Rakefile

@@ -1 +1 @@
-require 'ruby-vpi/runner_proxy'
+require 'ruby-vpi/runner_proxy'

data/samp/pipelined_alu/TestHw5UnitModel.rb

@@ -2,17 +2,16 @@
 # Copyright 2006 Suraj N. Kurapati
 # See the file named LICENSE for details.
 
-require 'InputGenerator'
+require 'int_gen'
 require 'Hw5UnitModel'
 require 'test/unit'
-require 'pp'
 
 class TestHw5UnitModel < Test::Unit::TestCase
   NUM_VECTORS = 4000
 
   def setup
     @model = Hw5UnitModel.new
-    @ingen = InputGenerator.new 32
+    @ingen = IntegerGenerator.new 32
   end
 
   def test_reset
@@ -28,8 +27,8 @@ class TestHw5UnitModel < Test::Unit::TestCase
       inputQueue << Hw5UnitModel::Operation.new(
         Hw5UnitModel::OPERATIONS[rand(Hw5UnitModel::OPERATIONS.size)],
         i,
-        @ingen.gen.abs,
-        @ingen.gen.abs
+        @ingen.random.abs,
+        @ingen.random.abs
       )
     end
 

data/samp/pipelined_alu/hw5_unit.v

@@ -3,161 +3,131 @@
   See the file named LICENSE for details.
 */
 
-`define WIDTH 32
-`define DATABITS 7
-`define OP_NOP	0
-`define OP_ADD 1
-`define OP_SUB	2
-`define OP_MULT 3
-
-module hw5_unit(
-  input clk
-  , input reset
-
-  // inputs
-  , input [`DATABITS-1:0] in_databits
-  , input [`WIDTH-1:0] a
-  , input [`WIDTH-1:0] b
-  , input [1:0] in_op
-
-  // outputs
-  , output reg [`WIDTH-1:0] res
-  , output reg [`DATABITS-1:0] out_databits
-  , output reg [1:0] out_op
+module hw5_unit
+#(parameter                 WIDTH    = 32,
+  parameter                 DATABITS = 7,
+  parameter                 OP_NOP   = 0,
+  parameter                 OP_ADD   = 1,
+  parameter                 OP_SUB   = 2,
+  parameter                 OP_MULT  = 3)
+( input                     clk,
+  input                     reset,
+
+  input      [DATABITS-1:0] in_databits,
+  input      [WIDTH-1:0]    a,
+  input      [WIDTH-1:0]    b,
+  input      [1:0]          in_op,
+
+  output reg [WIDTH-1:0]    res,
+  output reg [DATABITS-1:0] out_databits,
+  output reg [1:0]          out_op
 );
 
 
   /* PHASE 0: perform the ALU operations */
 
   // operation ID
-    reg [`DATABITS-1:0] in_databits_phase0;
-    reg [1:0] in_op_phase0;
+    reg [DATABITS-1:0]     in_databits_phase0;
+    reg [1:0]              in_op_phase0;
 
     always @(*) begin
-      in_databits_phase0	= in_databits;
-      in_op_phase0 = in_op;
+      in_databits_phase0 = in_databits;
+      in_op_phase0       = in_op;
     end
 
   // addition
-    reg [`WIDTH-1:0] add_result_phase0;
+    reg [WIDTH-1:0] add_result_phase0;
 
     always @(*) begin
       add_result_phase0 = a + b;
     end
 
   // subtraction
-    reg [`WIDTH-1:0] sub_result_phase0;
+    reg [WIDTH-1:0] sub_result_phase0;
 
     always @(*) begin
       sub_result_phase0 = a - b;
     end
 
   // multiplication
-    reg [`WIDTH-1:0] mul_result_phase0;
+    reg [WIDTH-1:0] mul_result_phase0;
 
     always @(*) begin
       mul_result_phase0 = a * b;
     end
 
 
-  // always @(posedge clk) begin
-  // 	$display("in_databits_phase0 => %d", in_databits_phase0);
-  // 	$display("in_op_phase0 => %d", in_op_phase0);
-  // 	$display("add_result_phase0 => %d", add_result_phase0);
-  // 	$display("sub_result_phase0 => %d", sub_result_phase0);
-  // 	$display("mul_result_phase0 => %d", mul_result_phase0);
-  // end
-
-
   /* PHASE 1: delay the ALU results */
 
-    reg [`DATABITS-1:0] in_databits_phase1;
-    reg [1:0] in_op_phase1;
+    reg  [DATABITS-1:0]  in_databits_phase1;
+    reg  [1:0]           in_op_phase1;
 
-    reg [`WIDTH-1:0] add_result_phase1;
-    reg [`WIDTH-1:0] sub_result_phase1;
-    reg [`WIDTH-1:0] mul_result_phase1;
+    reg  [WIDTH-1:0]     add_result_phase1;
+    reg  [WIDTH-1:0]     sub_result_phase1;
+    reg  [WIDTH-1:0]     mul_result_phase1;
 
     always @(posedge clk) begin
       in_databits_phase1 <= in_databits_phase0;
-      in_op_phase1 <= in_op_phase0;
+      in_op_phase1       <= in_op_phase0;
 
-      add_result_phase1 <= add_result_phase0;
-      sub_result_phase1 <= sub_result_phase0;
-      mul_result_phase1 <= mul_result_phase0;
+      add_result_phase1  <= add_result_phase0;
+      sub_result_phase1  <= sub_result_phase0;
+      mul_result_phase1  <= mul_result_phase0;
     end
 
-    // always @(posedge clk) begin
-    // 	$display("in_databits_phase1 => %d", in_databits_phase1);
-    // 	$display("in_op_phase1 => %d", in_op_phase1);
-    // 	$display("add_result_phase1 => %d", add_result_phase1);
-    // 	$display("sub_result_phase1 => %d", sub_result_phase1);
-    // 	$display("mul_result_phase1 => %d", mul_result_phase1);
-    // end
-
 
   /* PHASE 2: delay the ALU results */
 
-    reg [`DATABITS-1:0] in_databits_phase2;
-    reg [1:0] in_op_phase2;
+    reg [DATABITS-1:0] in_databits_phase2;
+    reg [1:0]          in_op_phase2;
 
-    reg [`WIDTH-1:0] add_result_phase2;
-    reg [`WIDTH-1:0] sub_result_phase2;
-    reg [`WIDTH-1:0] mul_result_phase2;
+    reg [WIDTH-1:0]    add_result_phase2;
+    reg [WIDTH-1:0]    sub_result_phase2;
+    reg [WIDTH-1:0]    mul_result_phase2;
 
     always @(posedge clk) begin
       in_databits_phase2 <= in_databits_phase1;
-      in_op_phase2 <= in_op_phase1;
+      in_op_phase2       <= in_op_phase1;
 
-      add_result_phase2 <= add_result_phase1;
-      sub_result_phase2 <= sub_result_phase1;
-      mul_result_phase2 <= mul_result_phase1;
+      add_result_phase2  <= add_result_phase1;
+      sub_result_phase2  <= sub_result_phase1;
+      mul_result_phase2  <= mul_result_phase1;
     end
 
-    // always @(posedge clk) begin
-    // 	$display("in_databits_phase2 => %d", in_databits_phase2);
-    // 	$display("in_op_phase2 => %d", in_op_phase2);
-    // 	$display("add_result_phase2 => %d", add_result_phase2);
-    // 	$display("sub_result_phase2 => %d", sub_result_phase2);
-    // 	$display("mul_result_phase2 => %d", mul_result_phase2);
-    // end
-
 
   /* PHASE 3: produce the outputs */
 
-    reg [`DATABITS-1:0] out_databits_next;
-    reg [1:0] out_op_next;
-    reg [`WIDTH-1:0] res_next;
+    reg [DATABITS-1:0] out_databits_next;
+    reg [1:0]          out_op_next;
+    reg [WIDTH-1:0]    res_next;
 
     always @(*) begin
-      if (reset) begin
-        out_op_next = `OP_NOP;
-      end else begin
+      if (reset)
+        out_op_next = OP_NOP;
+      else
         out_op_next = in_op_phase2;
-      end
 
       out_databits_next = in_databits_phase2;
 
       case (in_op_phase2)
-        `OP_NOP:
+        OP_NOP:
           res_next = 0;
 
-        `OP_ADD:
+        OP_ADD:
           res_next = add_result_phase2;
 
-        `OP_SUB:
+        OP_SUB:
           res_next = sub_result_phase2;
 
-        `OP_MULT:
+        OP_MULT:
           res_next = mul_result_phase2;
       endcase
     end
 
     always @(posedge clk) begin
-      res <= res_next;
-      out_op <= out_op_next;
+      res          <= res_next;
+      out_op       <= out_op_next;
       out_databits <= out_databits_next;
     end
 
 endmodule
-

data/samp/pipelined_alu/hw5_unit_design.rb

@@ -0,0 +1,51 @@
+# Simulates the design under test for one clock cycle.
+def cycle!
+  clk.high!
+  advance_time
+  clk.low!
+  advance_time
+end
+
+# Brings the design under test into a blank state.
+def reset!
+  clk.x!
+  reset.x!
+  in_databits.x!
+  a.x!
+  b.x!
+  in_op.x!
+
+  reset.high!
+  5.times { cycle! }
+  reset.low!
+end
+
+OPERATIONS = (OP_NOP .. OP_MULT).to_a
+
+# Represents an ALU operation.
+class Operation
+  attr_accessor :type, :tag, :arg1, :arg2, :result
+
+  def initialize(type, tag, arg1 = 0, arg2 = 0)
+    raise ArgumentError unless OPERATIONS.include? type
+
+    @type = type
+    @tag  = tag
+    @arg1 = arg1
+    @arg2 = arg2
+  end
+
+  # Computes the result of this operation.
+  def compute
+    case @type
+      when OP_ADD
+        @arg1 + @arg2
+
+      when OP_SUB
+        @arg1 - @arg2
+
+      when OP_MULT
+        @arg1 * @arg2
+    end
+  end
+end

data/samp/pipelined_alu/hw5_unit_proto.rb

@@ -0,0 +1,4 @@
+# Ruby prototype of the design under test's Verilog implementation.
+def feign!
+  raise NotImplementedError, "Prototype is not yet implemented."
+end

data/samp/pipelined_alu/hw5_unit_runner.rake

@@ -0,0 +1,43 @@
+# Array of paths and shell globs (see the Dir.glob method's documentation for
+# details) to source files and directories that contain source files.  These
+# source files will be loaded by the simulator before the simulation begins.
+SIMULATOR_SOURCES = FileList[
+  'hw5_unit.v',
+]
+
+# Command-line arguments for the simulator.  These arguments can be
+# specified as a string or an array of strings, as demonstrated below:
+#
+#   :cver => "this is a single string argument",
+#   :cver => ["these", "are", "separate", "arguments"],
+#   :cver => %w[these are also separate arguments],
+#
+SIMULATOR_ARGUMENTS = {
+  # GPL Cver
+  :cver => "",
+
+  # Icarus Verilog
+  :ivl => "",
+
+  # Synopsys VCS
+  :vcs => "",
+
+  # Mentor Modelsim
+  :vsim => "",
+
+  # Cadence NC-Sim
+  :ncsim => "",
+
+}
+
+# This task is invoked before the simulator runs.  It
+# can be used to make preprations, such as converting
+# Verilog header files into Ruby, for the simulation.
+task :setup do
+  # To learn how to write Rake tasks, please see:
+  # http://docs.rubyrake.org/read/chapter/4#page16
+end
+
+# This command loads the Ruby-VPI runner template,
+# which runs the simulator using the above parameters.
+require 'ruby-vpi/runner'

data/samp/pipelined_alu/hw5_unit_spec.rb

@@ -0,0 +1,64 @@
+require 'test/unit'
+require 'int_gen'
+
+class Hw5_unit_spec < Test::Unit::TestCase
+  # Number of input sequences to test.
+  NUM_TESTS = 4000
+
+  # Bitmask capable of capturing ALU result.
+  ALU_RESULT_MASK = (2 ** Hw5_unit::WIDTH) - 1
+
+  # Upper limit of values allowed for an operation's tag.
+  OPERATION_TAG_LIMIT = 2 ** Hw5_unit::DATABITS
+
+  def setup
+    Hw5_unit.reset!
+    @intGen = IntegerGenerator.new(Hw5_unit::WIDTH)
+  end
+
+  def test_pipeline
+    issuedOps = []
+    numIssued = numVerified = 0
+
+    until numVerified == NUM_TESTS
+      # issue a new operation
+      if numIssued < NUM_TESTS
+        op = Hw5_unit::Operation.new(
+          Hw5_unit::OPERATIONS[rand(Hw5_unit::OPERATIONS.size)],
+          numIssued % OPERATION_TAG_LIMIT,
+          @intGen.random,
+          @intGen.random
+        )
+
+        Hw5_unit.a.intVal           = op.arg1
+        Hw5_unit.b.intVal           = op.arg2
+        Hw5_unit.in_op.intVal       = op.type
+        Hw5_unit.in_databits.intVal = op.tag
+
+        issuedOps << op
+        numIssued += 1
+      end
+
+      Hw5_unit.cycle!
+
+      # verify result of finished operation
+      unless Hw5_unit.out_databits.x?
+        finishedOp = Hw5_unit::Operation.new(
+          Hw5_unit.out_op.intVal,
+          Hw5_unit.out_databits.intVal
+        )
+        finishedOp.result = Hw5_unit.res.intVal & ALU_RESULT_MASK
+
+        expectedOp = issuedOps.shift
+        assert_equal expectedOp.type, finishedOp.type, "incorrect operation"
+        assert_equal expectedOp.tag, finishedOp.tag, "incorrect tag"
+
+        unless finishedOp.type == Hw5_unit::OP_NOP
+          assert_equal expectedOp.compute & ALU_RESULT_MASK, finishedOp.result, "incorrect result"
+        end
+
+        numVerified += 1
+      end
+    end
+  end
+end

data/samp/register_file/LICENSE

@@ -0,0 +1,20 @@
+Copyright (c) 2007 Jacinto Shy II
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice shall be
+included in all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

data/samp/register_file/README

@@ -0,0 +1,4 @@
+This sample Ruby-VPI test was originally written by Jacinto Shy II:
+http://jacintoshy.blogspot.com/2007/05/hacking-verilog-with-ruby-part-2.html
+
+It has undergone some minor changes to work with the latest Ruby-VPI release.

data/samp/register_file/Rakefile

@@ -0,0 +1 @@
+require 'ruby-vpi/runner_proxy'

data/samp/register_file/register_file.v

@@ -0,0 +1,18 @@
+module register_file (
+  input wire [1:0] rdReg,
+  input wire [1:0] wtReg,
+  input wire       rw,
+  input wire       enable,
+  input wire [3:0] inBus,
+  output reg [3:0] outBus
+);
+  reg [3:0] register [0:3];
+
+  always @(*) begin
+    if (rw == 0) begin
+      outBus = register[rdReg];
+    end else if (enable) begin
+      register[wtReg] = inBus;
+    end
+  end
+endmodule

data/samp/register_file/register_file_design.rb

@@ -0,0 +1,11 @@
+# Simulates the design under test for one clock cycle.
+def cycle!
+  advance_time
+end
+
+# Brings the design under test into a blank state.
+def reset!
+  register.each_memoryWord do |word|
+    word.x!
+  end
+end

data/samp/register_file/register_file_proto.rb

@@ -0,0 +1,11 @@
+# Ruby prototype of the design under test's Verilog implementation.
+def feign!
+  if rw.low?
+    reg           = register.memoryWord_a[rdReg.intVal]
+    outBus.intVal = reg.intVal
+
+  elsif enable.high?
+    reg           = register.memoryWord_a[wtReg.intVal]
+    reg.intVal    = inBus.intVal
+  end
+end

data/samp/register_file/register_file_runner.rake

@@ -0,0 +1,43 @@
+# Array of paths and shell globs (see the Dir.glob method's documentation for
+# details) to source files and directories that contain source files.  These
+# source files will be loaded by the simulator before the simulation begins.
+SIMULATOR_SOURCES = FileList[
+  'register_file.v',
+]
+
+# Command-line arguments for the simulator.  These arguments can be
+# specified as a string or an array of strings, as demonstrated below:
+#
+#   :cver => "this is a single string argument",
+#   :cver => ["these", "are", "separate", "arguments"],
+#   :cver => %w[these are also separate arguments],
+#
+SIMULATOR_ARGUMENTS = {
+  # GPL Cver
+  :cver => "",
+
+  # Icarus Verilog
+  :ivl => "",
+
+  # Synopsys VCS
+  :vcs => "",
+
+  # Mentor Modelsim
+  :vsim => "",
+
+  # Cadence NC-Sim
+  :ncsim => "",
+
+}
+
+# This task is invoked before the simulator runs.  It
+# can be used to make preprations, such as converting
+# Verilog header files into Ruby, for the simulation.
+task :setup do
+  # To learn how to write Rake tasks, please see:
+  # http://docs.rubyrake.org/read/chapter/4#page16
+end
+
+# This command loads the Ruby-VPI runner template,
+# which runs the simulator using the above parameters.
+require 'ruby-vpi/runner'

data/samp/register_file/register_file_spec.rb

@@ -0,0 +1,58 @@
+require 'spec'
+
+module RegisterInterface
+  MAX_INDEX = Register_file.register.size - 1
+
+  def set_registers(vals)
+    Register_file.rw.intVal = 1
+
+    0.upto(MAX_INDEX) do |i|
+      Register_file.wtReg.intVal = i
+      Register_file.inBus.intVal = vals[i]
+      Register_file.cycle!
+    end
+  end
+
+  def expect_registers(vals)
+    Register_file.rw.intVal = 0
+
+    MAX_INDEX.downto(0) do |i|
+      Register_file.rdReg.intVal = i
+      Register_file.cycle!
+      Register_file.outBus.intVal.should == vals[i]
+    end
+  end
+end
+
+describe "An enabled register file" do
+  include RegisterInterface
+
+  before do
+    Register_file.reset!
+    Register_file.enable.intVal = 1
+  end
+
+  it "should be able to write and then read registers" do
+    testVals = [1, 7, 3, 12]
+
+    set_registers(testVals)
+    expect_registers(testVals)
+  end
+end
+
+describe "A disabled register file" do
+  include RegisterInterface
+
+  before do
+    Register_file.reset!
+    Register_file.enable.intVal = 0
+  end
+
+  it "should not write new values" do
+    zeros    = [0, 0, 0, 0]
+    testVals = [1, 7, 3, 12]
+
+    set_registers(testVals)
+    expect_registers(zeros)
+  end
+end