ruby-vpi 16.0.1 → 17.0.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- data/LICENSE +19 -19
- data/README +1 -1
- data/Rakefile +35 -32
- data/bin/convert.rb +28 -0
- data/bin/generate/design.rb +16 -0
- data/bin/generate/proto.rb +13 -0
- data/bin/generate/runner.rake +33 -0
- data/bin/generate/spec.rb +45 -0
- data/bin/generate.rb +177 -0
- data/bin/ruby-vpi +56 -0
- data/doc/Rakefile +20 -4
- data/doc/common.css +92 -33
- data/doc/common.inc +13 -0
- data/doc/common.tpl +42 -28
- data/doc/history.doc +11 -11
- data/doc/history.html +769 -248
- data/doc/history.inc +909 -0
- data/doc/history.rb +9 -0
- data/doc/history.yaml +69 -0
- data/doc/intro.inc +170 -178
- data/doc/lib/doc_format.rb +57 -144
- data/doc/lib/doc_proxy.rb +504 -88
- data/doc/lib/erb_content.rb +8 -8
- data/doc/lib/erb_proxy.rb +17 -17
- data/doc/manual.doc +626 -777
- data/doc/manual.html +1541 -1031
- data/doc/memo.doc +38 -36
- data/doc/memo.html +64 -28
- data/doc/readme.doc +4 -31
- data/doc/readme.html +221 -163
- data/doc/rss.erb +1 -1
- data/doc/rss.xml +73 -1761
- data/ext/Rakefile +6 -5
- data/ext/main.c +17 -15
- data/ext/relay.c +4 -7
- data/ext/relay.h +2 -2
- data/ext/swig_vpi.h +2 -2
- data/ext/swig_vpi.i +1 -2
- data/ext/swig_wrap.cin +12 -16
- data/ext/vlog.c +5 -5
- data/ext/vlog.h +2 -2
- data/lib/ruby-vpi/erb.rb +3 -3
- data/lib/ruby-vpi/float.rb +2 -2
- data/lib/ruby-vpi/rcov.rb +5 -7
- data/lib/ruby-vpi/runner.rb +43 -41
- data/lib/ruby-vpi/runner_boot_loader.rb +117 -0
- data/lib/ruby-vpi/runner_proxy.rb +6 -8
- data/lib/ruby-vpi/util.rb +10 -0
- data/lib/ruby-vpi/verilog_parser.rb +28 -56
- data/lib/ruby-vpi/vpi.rb +168 -123
- data/lib/ruby-vpi.rb +22 -143
- data/ref/c/annotated.html +1 -1
- data/ref/c/common_8h.html +1 -1
- data/ref/c/files.html +1 -1
- data/ref/c/functions.html +1 -1
- data/ref/c/functions_vars.html +1 -1
- data/ref/c/globals.html +1 -1
- data/ref/c/globals_0x63.html +1 -1
- data/ref/c/globals_0x65.html +1 -1
- data/ref/c/globals_0x66.html +1 -1
- data/ref/c/globals_0x6d.html +1 -1
- data/ref/c/globals_0x70.html +1 -1
- data/ref/c/globals_0x72.html +1 -1
- data/ref/c/globals_0x73.html +1 -1
- data/ref/c/globals_0x74.html +1 -1
- data/ref/c/globals_0x76.html +1 -1
- data/ref/c/globals_0x78.html +1 -1
- data/ref/c/globals_defs.html +1 -1
- data/ref/c/globals_defs_0x65.html +1 -1
- data/ref/c/globals_defs_0x70.html +1 -1
- data/ref/c/globals_defs_0x76.html +1 -1
- data/ref/c/globals_defs_0x78.html +1 -1
- data/ref/c/globals_enum.html +1 -1
- data/ref/c/globals_eval.html +1 -1
- data/ref/c/globals_func.html +1 -1
- data/ref/c/globals_type.html +1 -1
- data/ref/c/globals_vars.html +1 -1
- data/ref/c/index.html +1 -1
- data/ref/c/main_8c.html +1 -1
- data/ref/c/main_8h.html +1 -1
- data/ref/c/relay_8c.html +1 -1
- data/ref/c/relay_8h.html +1 -1
- data/ref/c/structt__cb__data.html +1 -1
- data/ref/c/structt__vpi__delay.html +1 -1
- data/ref/c/structt__vpi__error__info.html +1 -1
- data/ref/c/structt__vpi__strengthval.html +1 -1
- data/ref/c/structt__vpi__systf__data.html +1 -1
- data/ref/c/structt__vpi__time.html +1 -1
- data/ref/c/structt__vpi__value.html +1 -1
- data/ref/c/structt__vpi__vecval.html +1 -1
- data/ref/c/structt__vpi__vlog__info.html +1 -1
- data/ref/c/verilog_8h.html +1 -1
- data/ref/c/vlog_8c.html +1 -1
- data/ref/c/vlog_8h.html +1 -1
- data/ref/c/vpi__user_8h.html +1 -1
- data/ref/ruby/classes/ERB.html +5 -5
- data/ref/ruby/classes/ERB.src/{M000024.html → M000026.html} +0 -0
- data/ref/ruby/classes/FileUtils.html +11 -11
- data/ref/ruby/classes/FileUtils.src/{M000025.html → M000027.html} +0 -0
- data/ref/ruby/classes/FileUtils.src/{M000026.html → M000028.html} +0 -0
- data/ref/ruby/classes/Float.html +6 -6
- data/ref/ruby/classes/Float.src/{M000020.html → M000021.html} +0 -0
- data/ref/ruby/classes/Integer.html +65 -65
- data/ref/ruby/classes/Integer.src/M000009.html +12 -5
- data/ref/ruby/classes/Integer.src/M000010.html +5 -5
- data/ref/ruby/classes/Integer.src/M000011.html +5 -5
- data/ref/ruby/classes/Integer.src/M000012.html +5 -5
- data/ref/ruby/classes/Integer.src/M000013.html +5 -5
- data/ref/ruby/classes/Integer.src/M000014.html +18 -0
- data/ref/ruby/classes/Integer.src/M000017.html +12 -18
- data/ref/ruby/classes/Integer.src/M000018.html +18 -12
- data/ref/ruby/classes/Integer.src/M000019.html +12 -17
- data/ref/ruby/classes/Integer.src/M000020.html +30 -0
- data/ref/ruby/classes/RDoc.html +5 -5
- data/ref/ruby/classes/RDoc.src/{M000053.html → M000058.html} +0 -0
- data/ref/ruby/classes/{RubyVpi/Config.html → RubyVPI.html} +20 -6
- data/ref/ruby/classes/String.html +34 -15
- data/ref/ruby/classes/String.src/M000022.html +5 -28
- data/ref/ruby/classes/String.src/M000023.html +5 -5
- data/ref/ruby/classes/String.src/{M000021.html → M000024.html} +0 -0
- data/ref/ruby/classes/String.src/M000025.html +41 -0
- data/ref/ruby/classes/VerilogParser/Module/Port.html +16 -36
- data/ref/ruby/classes/VerilogParser/Module/Port.src/M000006.html +10 -5
- data/ref/ruby/classes/VerilogParser/Module/Port.src/{M000004.html → M000007.html} +4 -4
- data/ref/ruby/classes/VerilogParser/Module/Port.src/{M000005.html → M000008.html} +4 -4
- data/ref/ruby/classes/VerilogParser/Module.html +28 -9
- data/ref/ruby/classes/VerilogParser/Module.src/M000005.html +29 -0
- data/ref/ruby/classes/VerilogParser.html +5 -39
- data/ref/ruby/classes/VerilogParser.src/M000004.html +26 -0
- data/ref/ruby/classes/Vpi/Handle.html +179 -77
- data/ref/ruby/classes/Vpi/Handle.src/M000035.html +18 -0
- data/ref/ruby/classes/Vpi/Handle.src/M000036.html +5 -5
- data/ref/ruby/classes/Vpi/Handle.src/M000037.html +5 -5
- data/ref/ruby/classes/Vpi/Handle.src/M000038.html +5 -5
- data/ref/ruby/classes/Vpi/Handle.src/M000039.html +5 -5
- data/ref/ruby/classes/Vpi/Handle.src/M000040.html +5 -8
- data/ref/ruby/classes/Vpi/Handle.src/M000041.html +5 -8
- data/ref/ruby/classes/Vpi/Handle.src/M000042.html +5 -9
- data/ref/ruby/classes/Vpi/Handle.src/M000043.html +8 -31
- data/ref/ruby/classes/Vpi/Handle.src/M000044.html +8 -74
- data/ref/ruby/classes/Vpi/Handle.src/M000045.html +9 -17
- data/ref/ruby/classes/Vpi/Handle.src/M000046.html +31 -11
- data/ref/ruby/classes/Vpi/Handle.src/M000047.html +86 -0
- data/ref/ruby/classes/Vpi/Handle.src/M000048.html +17 -18
- data/ref/ruby/classes/Vpi/Handle.src/M000050.html +18 -0
- data/ref/ruby/classes/Vpi/Handle.src/M000051.html +24 -0
- data/ref/ruby/classes/Vpi/Handle.src/M000053.html +31 -0
- data/ref/ruby/classes/Vpi/Handle.src/M000054.html +89 -0
- data/ref/ruby/classes/Vpi/S_vpi_time.html +16 -16
- data/ref/ruby/classes/Vpi/S_vpi_time.src/{M000050.html → M000055.html} +4 -4
- data/ref/ruby/classes/Vpi/S_vpi_time.src/{M000051.html → M000056.html} +5 -5
- data/ref/ruby/classes/Vpi/S_vpi_value.html +15 -15
- data/ref/ruby/classes/Vpi/S_vpi_value.src/{M000035.html → M000032.html} +5 -5
- data/ref/ruby/classes/Vpi/S_vpi_value.src/M000033.html +5 -5
- data/ref/ruby/classes/Vpi/S_vpi_value.src/M000034.html +5 -5
- data/ref/ruby/classes/Vpi.html +6 -42
- data/ref/ruby/classes/Vpi.src/M000029.html +15 -5
- data/ref/ruby/classes/Vpi.src/M000030.html +24 -24
- data/ref/ruby/classes/Vpi.src/M000031.html +6 -8
- data/ref/ruby/created.rid +1 -1
- data/ref/ruby/files/bin/{header_to_ruby_rb.html → convert_rb.html} +5 -5
- data/ref/ruby/files/bin/{generate_test_rb.html → generate_rb.html} +8 -21
- data/ref/ruby/files/lib/ruby-vpi/erb_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/float_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/integer_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/rake_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/rcov_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/rdoc_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/runner_boot_loader_rb.html +197 -0
- data/ref/ruby/files/lib/ruby-vpi/runner_boot_loader_rb.src/M000001.html +17 -0
- data/ref/ruby/files/lib/ruby-vpi/runner_boot_loader_rb.src/M000002.html +18 -0
- data/ref/ruby/files/lib/ruby-vpi/runner_proxy_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/runner_rb.html +6 -19
- data/ref/ruby/files/lib/ruby-vpi/util_rb.html +101 -0
- data/ref/ruby/files/lib/ruby-vpi/verilog_parser_rb.html +8 -1
- data/ref/ruby/files/lib/ruby-vpi/vpi_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi_rb.html +2 -14
- data/ref/ruby/fr_class_index.html +1 -3
- data/ref/ruby/fr_file_index.html +4 -2
- data/ref/ruby/fr_method_index.html +56 -51
- data/ref/ruby/index.html +1 -1
- data/samp/counter/RSpec/Rakefile +1 -0
- data/samp/counter/RSpec/counter_design.rb +15 -0
- data/samp/counter/RSpec/counter_proto.rb +10 -0
- data/samp/counter/RSpec/counter_runner.rake +44 -0
- data/samp/counter/RSpec/counter_spec.rb +39 -0
- data/samp/counter/Rakefile +1 -1
- data/samp/counter/counter.v +7 -7
- data/samp/counter/xUnit/Rakefile +1 -0
- data/samp/counter/xUnit/counter_bench.rb +95 -0
- data/samp/counter/{counter_xunit_bench.v → xUnit/counter_bench.v} +0 -0
- data/samp/counter/xUnit/counter_design.rb +15 -0
- data/samp/counter/xUnit/counter_proto.rb +10 -0
- data/samp/counter/xUnit/counter_runner.rake +44 -0
- data/samp/counter/{counter_xunit_spec.rb → xUnit/counter_spec.rb} +9 -9
- data/samp/pipelined_alu/Rakefile +1 -1
- data/samp/pipelined_alu/TestHw5UnitModel.rb +4 -5
- data/samp/pipelined_alu/hw5_unit.v +55 -85
- data/samp/pipelined_alu/hw5_unit_design.rb +51 -0
- data/samp/pipelined_alu/hw5_unit_proto.rb +4 -0
- data/samp/pipelined_alu/hw5_unit_runner.rake +43 -0
- data/samp/pipelined_alu/hw5_unit_spec.rb +64 -0
- data/samp/register_file/LICENSE +20 -0
- data/samp/register_file/README +4 -0
- data/samp/register_file/Rakefile +1 -0
- data/samp/register_file/register_file.v +18 -0
- data/samp/register_file/register_file_design.rb +11 -0
- data/samp/register_file/register_file_proto.rb +11 -0
- data/samp/register_file/register_file_runner.rake +43 -0
- data/samp/register_file/register_file_spec.rb +58 -0
- metadata +78 -66
- data/bin/generate_test.rb +0 -200
- data/bin/generate_test_tpl/bench.rb +0 -89
- data/bin/generate_test_tpl/bench.v +0 -26
- data/bin/generate_test_tpl/design.rb +0 -11
- data/bin/generate_test_tpl/proto.rb +0 -16
- data/bin/generate_test_tpl/runner.rake +0 -42
- data/bin/generate_test_tpl/spec.rb +0 -37
- data/bin/header_to_ruby.rb +0 -27
- data/ref/ruby/classes/Integer.src/M000008.html +0 -25
- data/ref/ruby/classes/Integer.src/M000016.html +0 -25
- data/ref/ruby/classes/RubyVpi.html +0 -199
- data/ref/ruby/classes/RubyVpi.src/M000027.html +0 -121
- data/ref/ruby/classes/VerilogParser/Module/Parameter.html +0 -160
- data/ref/ruby/classes/VerilogParser/Module/Parameter.src/M000007.html +0 -19
- data/ref/ruby/classes/VerilogParser/Module/Port.src/M000003.html +0 -21
- data/ref/ruby/classes/VerilogParser/Module.src/M000002.html +0 -34
- data/ref/ruby/classes/VerilogParser.src/M000001.html +0 -34
- data/ref/ruby/classes/Vpi/Handle.src/M000049.html +0 -69
- data/ref/ruby/classes/Vpi.src/M000028.html +0 -28
- data/ref/ruby/classes/Vpi.src/M000032.html +0 -22
- data/samp/counter/counter_rspec_bench.rb +0 -86
- data/samp/counter/counter_rspec_bench.v +0 -9
- data/samp/counter/counter_rspec_design.rb +0 -8
- data/samp/counter/counter_rspec_proto.rb +0 -13
- data/samp/counter/counter_rspec_runner.rake +0 -52
- data/samp/counter/counter_rspec_spec.rb +0 -39
- data/samp/counter/counter_xunit_bench.rb +0 -86
- data/samp/counter/counter_xunit_design.rb +0 -8
- data/samp/counter/counter_xunit_proto.rb +0 -13
- data/samp/counter/counter_xunit_runner.rake +0 -52
- data/samp/pipelined_alu/hw5_unit_test_bench.rb +0 -86
- data/samp/pipelined_alu/hw5_unit_test_bench.v +0 -14
- data/samp/pipelined_alu/hw5_unit_test_design.rb +0 -61
- data/samp/pipelined_alu/hw5_unit_test_proto.rb +0 -7
- data/samp/pipelined_alu/hw5_unit_test_runner.rake +0 -52
- data/samp/pipelined_alu/hw5_unit_test_spec.rb +0 -68
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<pre> <span class="ruby-comment cmt"># File lib/ruby-vpi/verilog_parser.rb, line 36</span>
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36: <span class="ruby-keyword kw">def</span> <span class="ruby-identifier">initialize</span> <span class="ruby-identifier">aDecl</span>
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<pre> <span class="ruby-comment cmt"># File lib/ruby-vpi/verilog_parser.rb, line 10</span>
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10: <span class="ruby-keyword kw">def</span> <span class="ruby-identifier">initialize</span> <span class="ruby-identifier">aInput</span>
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17: <span class="ruby-ivar">@modules</span> = <span class="ruby-identifier">input</span>.<span class="ruby-identifier">scan</span>(<span class="ruby-regexp re">%r{module.*?;}</span><span class="ruby-identifier">m</span>).<span class="ruby-identifier">map!</span> <span class="ruby-keyword kw">do</span> <span class="ruby-operator">|</span><span class="ruby-identifier">decl</span><span class="ruby-operator">|</span>
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25: <span class="ruby-ivar">@includes</span> = <span class="ruby-identifier">input</span>.<span class="ruby-identifier">scan</span>(<span class="ruby-regexp re">%r{(`include\s*(\S+))}</span>).<span class="ruby-identifier">map!</span> <span class="ruby-keyword kw">do</span> <span class="ruby-operator">|</span><span class="ruby-identifier">matches</span><span class="ruby-operator">|</span>
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270: <span class="ruby-keyword kw">def</span> <span class="ruby-identifier">method_missing</span> <span class="ruby-identifier">aMeth</span>, <span class="ruby-operator">*</span><span class="ruby-identifier">aArgs</span>, <span class="ruby-operator">&</span><span class="ruby-identifier">aBlockArg</span>
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271: <span class="ruby-keyword kw">if</span> <span class="ruby-identifier">child</span> = <span class="ruby-identifier">vpi_handle_by_name</span>(<span class="ruby-identifier">aMeth</span>.<span class="ruby-identifier">to_s</span>, <span class="ruby-keyword kw">self</span>)
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272: <span class="ruby-comment cmt"># cache the child for future accesses, in order to cut down number of</span>
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273: <span class="ruby-comment cmt"># calls to method_missing</span>
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274: (<span class="ruby-keyword kw">class</span> <span class="ruby-operator"><<</span> <span class="ruby-keyword kw">self</span>; <span class="ruby-keyword kw">self</span>; <span class="ruby-keyword kw">end</span>).<span class="ruby-identifier">class_eval</span> <span class="ruby-keyword kw">do</span>
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275: <span class="ruby-identifier">define_method</span> <span class="ruby-identifier">aMeth</span> <span class="ruby-keyword kw">do</span>
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286: <span class="ruby-keyword kw">self</span>.<span class="ruby-identifier">send</span>(<span class="ruby-identifier">prop</span>.<span class="ruby-identifier">operation</span>, <span class="ruby-identifier">prop</span>.<span class="ruby-identifier">type</span>, <span class="ruby-operator">*</span><span class="ruby-identifier">aArgs</span>, <span class="ruby-operator">&</span><span class="ruby-identifier">aBlockArg</span>)
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290: <span class="ruby-keyword kw">when</span> <span class="ruby-identifier">:d</span> <span class="ruby-comment cmt"># delay values</span>
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292: <span class="ruby-comment cmt"># TODO: vpi_put_delays</span>
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293: <span class="ruby-comment cmt"># TODO: vpi_get_delays</span>
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294:
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295: <span class="ruby-keyword kw">when</span> <span class="ruby-identifier">:l</span> <span class="ruby-comment cmt"># logic values</span>
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296: <span class="ruby-keyword kw">if</span> <span class="ruby-identifier">prop</span>.<span class="ruby-identifier">assignment</span>
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297: <span class="ruby-identifier">value</span> = <span class="ruby-identifier">aArgs</span>.<span class="ruby-identifier">shift</span>
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298: <span class="ruby-identifier">put_value</span>(<span class="ruby-identifier">value</span>, <span class="ruby-identifier">prop</span>.<span class="ruby-identifier">type</span>, <span class="ruby-operator">*</span><span class="ruby-identifier">aArgs</span>)
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299: <span class="ruby-keyword kw">else</span>
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302:
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304: <span class="ruby-identifier">vpi_get</span>(<span class="ruby-identifier">prop</span>.<span class="ruby-identifier">type</span>, <span class="ruby-keyword kw">self</span>) <span class="ruby-keyword kw">unless</span> <span class="ruby-identifier">prop</span>.<span class="ruby-identifier">assignment</span>
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305:
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309: <span class="ruby-identifier">value</span> <span class="ruby-operator">&&</span> (<span class="ruby-identifier">value</span> <span class="ruby-operator">!=</span> <span class="ruby-value">0</span>) <span class="ruby-comment cmt"># zero is false in C</span>
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310: <span class="ruby-keyword kw">end</span>
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311:
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312: <span class="ruby-keyword kw">when</span> <span class="ruby-identifier">:s</span> <span class="ruby-comment cmt"># string values</span>
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313: <span class="ruby-identifier">vpi_get_str</span>(<span class="ruby-identifier">prop</span>.<span class="ruby-identifier">type</span>, <span class="ruby-keyword kw">self</span>) <span class="ruby-keyword kw">unless</span> <span class="ruby-identifier">prop</span>.<span class="ruby-identifier">assignment</span>
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314:
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315: <span class="ruby-keyword kw">when</span> <span class="ruby-identifier">:h</span> <span class="ruby-comment cmt"># handle values</span>
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316: <span class="ruby-identifier">vpi_handle</span>(<span class="ruby-identifier">prop</span>.<span class="ruby-identifier">type</span>, <span class="ruby-keyword kw">self</span>) <span class="ruby-keyword kw">unless</span> <span class="ruby-identifier">prop</span>.<span class="ruby-identifier">assignment</span>
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317:
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318: <span class="ruby-keyword kw">else</span>
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319: <span class="ruby-identifier">raise</span> <span class="ruby-constant">NoMethodError</span>, <span class="ruby-node">"unable to access VPI property #{prop.name.inspect} through method #{aMeth.inspect} with arguments #{aArgs.inspect} for handle #{self}"</span>
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320: <span class="ruby-keyword kw">end</span>
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322: <span class="ruby-keyword kw">end</span>
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323: <span class="ruby-keyword kw">end</span></pre>
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<pre> <span class="ruby-comment cmt"># File lib/ruby-vpi/vpi.rb, line 424</span>
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424: <span class="ruby-keyword kw">def</span> <span class="ruby-identifier">vpi_register_cb</span> <span class="ruby-identifier">aData</span>, <span class="ruby-operator">&</span><span class="ruby-identifier">aHandler</span> <span class="ruby-comment cmt"># :yields: Vpi::S_cb_data</span>
|
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425: <span class="ruby-identifier">raise</span> <span class="ruby-constant">ArgumentError</span>, <span class="ruby-value str">"block must be given"</span> <span class="ruby-keyword kw">unless</span> <span class="ruby-identifier">block_given?</span>
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426:
|
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427: <span class="ruby-identifier">key</span> = <span class="ruby-identifier">aHandler</span>.<span class="ruby-identifier">object_id</span>.<span class="ruby-identifier">to_s</span>
|
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428:
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429: <span class="ruby-comment cmt"># register the callback with Verilog</span>
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430: <span class="ruby-identifier">aData</span>.<span class="ruby-identifier">user_data</span> = <span class="ruby-identifier">key</span>
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431: <span class="ruby-identifier">aData</span>.<span class="ruby-identifier">cb_rtn</span> = <span class="ruby-constant">Vlog_relay_ruby</span>
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432: <span class="ruby-identifier">token</span> = <span class="ruby-identifier">vpi_register_cb_old</span>(<span class="ruby-identifier">aData</span>)
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433:
|
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434: <span class="ruby-ivar">@@callbacks</span>[<span class="ruby-identifier">key</span>] = <span class="ruby-constant">Callback</span>.<span class="ruby-identifier">new</span>(<span class="ruby-identifier">aHandler</span>, <span class="ruby-identifier">token</span>)
|
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435: <span class="ruby-identifier">token</span>
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436: <span class="ruby-keyword kw">end</span></pre>
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<pre> <span class="ruby-comment cmt"># File lib/ruby-vpi/vpi.rb, line 552</span>
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552: <span class="ruby-keyword kw">def</span> <span class="ruby-identifier">initialize</span> <span class="ruby-identifier">aMembers</span> = {}
|
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|
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554:
|
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555: <span class="ruby-identifier">aMembers</span>.<span class="ruby-identifier">each_pair</span> <span class="ruby-keyword kw">do</span> <span class="ruby-operator">|</span><span class="ruby-identifier">k</span>, <span class="ruby-identifier">v</span><span class="ruby-operator">|</span>
|
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556: <span class="ruby-identifier">__send__</span> <span class="ruby-node">"#{k}="</span>, <span class="ruby-identifier">v</span>
|
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|
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558: <span class="ruby-keyword kw">end</span></pre>
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# This file is the Ruby side of the bench.
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|
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|
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RubyVpi.init_bench :Counter, :rSpec do
|
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##
|
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# This block is executed whenever Vpi::simulate is invoked.
|
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#
|
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# It simulates the design under test. This is typically done
|
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# by toggling the clock signal, as demonstrated below.
|
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##
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##
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# We are currently here (marked by the ! signs):
|
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#
|
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# !
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# !
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# !
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#
|
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##
|
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|
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Counter.clock.intVal = 1
|
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##
|
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# After setting the clock signal to high, we are here:
|
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#
|
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# !
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# !
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# !____ ____ ____ ____
|
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|
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# !
|
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# !
|
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#
|
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##
|
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|
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|
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|
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advance_time
|
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|
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##
|
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# After advancing the time, we are here:
|
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#
|
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# !
|
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# !
|
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# ____! ____ ____ ____
|
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# ____/ !\____/ \____/ \____/ \
|
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# !
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# !
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#
|
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##
|
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|
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Counter.clock.intVal = 0
|
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|
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|
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|
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##
|
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# After setting the clock signal to low, we are here:
|
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#
|
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# !
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# !
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# ____ ! ____ ____ ____
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# ____/ \!____/ \____/ \____/ \
|
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# !
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# !
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#
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##
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advance_time
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##
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# After advancing the time, we are here:
|
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#
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#
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# !
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# !
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# ____ ! ____ ____ ____
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# ____/ \____!/ \____/ \____/ \
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# !
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# !
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#
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##
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##
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# This process repeats when Vpi::simulate is invoked again.
|
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##
|
86
|
-
end
|
@@ -1,9 +0,0 @@
|
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// This file is the Verilog side of the bench.
|
2
|
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module counter_rspec_bench;
|
3
|
-
parameter Size = 5;
|
4
|
-
reg clock;
|
5
|
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reg reset;
|
6
|
-
wire [Size - 1 : 0] count;
|
7
|
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|
8
|
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counter #(.Size(Size)) counter_rspec_bench_design(.clock(clock), .reset(reset), .count(count));
|
9
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-
endmodule
|
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|
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# This is a prototype of the design under test.
|
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|
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# When prototyping is enabled, Vpi::advance_time invokes this
|
4
|
-
# method instead of transferring control to the Verilog simulator.
|
5
|
-
def Counter.simulate!
|
6
|
-
if clock.posedge?
|
7
|
-
if reset.intVal == 1
|
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|
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count.intVal = 0
|
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else
|
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count.intVal += 1
|
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end
|
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end
|
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end
|
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|
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# This file runs the test.
|
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|
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# These are Verilog source files that need to be loaded
|
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# by the simulator before they can be simulated.
|
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SIMULATOR_SOURCES = [
|
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'counter.v',
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'counter_rspec_bench.v',
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]
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# These are paths to directories which contain the
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# sources listed above, the files they `include, or both.
|
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SIMULATOR_INCLUDES = []
|
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|
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# This specifies the "top module" that is to be simulated.
|
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SIMULATOR_TARGET = 'counter_rspec_bench'
|
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# These are command-line arguments for the simulator.
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# They can be specified as a string or an array of strings:
|
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#
|
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# :cver => "this is one single argument",
|
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# :cver => ['these', 'are', 'separate', 'arguments'],
|
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# :cver => %w[these are also separate arguments],
|
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-
#
|
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SIMULATOR_ARGUMENTS = {
|
25
|
-
# GPL Cver
|
26
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-
:cver => '',
|
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|
-
|
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# Icarus Verilog
|
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:ivl => '',
|
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|
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# Synopsys VCS
|
32
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:vcs => '',
|
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|
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# Mentor Modelsim
|
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:vsim => '',
|
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|
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# Cadence NC-Sim
|
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:ncsim => '',
|
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|
-
|
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-
}
|
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-
|
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# This task is invoked _before_ the simulator runs.
|
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# It can be used to make preprations, such as converting
|
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# Verilog header files into Ruby, for the simulation.
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task :setup do
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46
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-
# To learn how to write Rake tasks, please see:
|
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# http://docs.rubyrake.org/read/chapter/4#page16
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end
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49
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-
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50
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# This command loads the Ruby-VPI runner template, which
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51
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# runs the simulator according to the information above.
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require 'ruby-vpi/runner'
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@@ -1,39 +0,0 @@
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1
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# This file is a behavioral specification for the design under test.
|
2
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-
|
3
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# lowest upper bound of counter's value
|
4
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LIMIT = 2 ** Counter.Size.intVal
|
5
|
-
|
6
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# maximum allowed value for a counter
|
7
|
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MAX = LIMIT - 1
|
8
|
-
|
9
|
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context "A resetted counter's value" do
|
10
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setup do
|
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Counter.reset!
|
12
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end
|
13
|
-
|
14
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specify "should be zero" do
|
15
|
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Counter.count.intVal.should == 0
|
16
|
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end
|
17
|
-
|
18
|
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specify "should increment by one count upon each rising clock edge" do
|
19
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LIMIT.times do |i|
|
20
|
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Counter.count.intVal.should == i
|
21
|
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simulate # increment the counter
|
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end
|
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end
|
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end
|
25
|
-
|
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|
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context "A counter with the maximum value" do
|
27
|
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setup do
|
28
|
-
Counter.reset!
|
29
|
-
|
30
|
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# increment the counter to maximum value
|
31
|
-
MAX.times {simulate}
|
32
|
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Counter.count.intVal.should == MAX
|
33
|
-
end
|
34
|
-
|
35
|
-
specify "should overflow upon increment" do
|
36
|
-
simulate # increment the counter
|
37
|
-
Counter.count.intVal.should == 0
|
38
|
-
end
|
39
|
-
end
|
@@ -1,86 +0,0 @@
|
|
1
|
-
# This file is the Ruby side of the bench.
|
2
|
-
|
3
|
-
require 'rubygems'
|
4
|
-
require 'ruby-vpi'
|
5
|
-
|
6
|
-
RubyVpi.init_bench :Counter, :xUnit do
|
7
|
-
##
|
8
|
-
# This block is executed whenever Vpi::simulate is invoked.
|
9
|
-
#
|
10
|
-
# It simulates the design under test. This is typically done
|
11
|
-
# by toggling the clock signal, as demonstrated below.
|
12
|
-
##
|
13
|
-
|
14
|
-
##
|
15
|
-
# We are currently here (marked by the ! signs):
|
16
|
-
#
|
17
|
-
# !
|
18
|
-
# !
|
19
|
-
# ! ____ ____ ____ ____
|
20
|
-
# ___!/ \____/ \____/ \____/ \
|
21
|
-
# !
|
22
|
-
# !
|
23
|
-
#
|
24
|
-
##
|
25
|
-
|
26
|
-
Counter.clock.intVal = 1
|
27
|
-
|
28
|
-
##
|
29
|
-
# After setting the clock signal to high, we are here:
|
30
|
-
#
|
31
|
-
# !
|
32
|
-
# !
|
33
|
-
# !____ ____ ____ ____
|
34
|
-
# ____/! \____/ \____/ \____/ \
|
35
|
-
# !
|
36
|
-
# !
|
37
|
-
#
|
38
|
-
##
|
39
|
-
|
40
|
-
advance_time
|
41
|
-
|
42
|
-
##
|
43
|
-
# After advancing the time, we are here:
|
44
|
-
#
|
45
|
-
# !
|
46
|
-
# !
|
47
|
-
# ____! ____ ____ ____
|
48
|
-
# ____/ !\____/ \____/ \____/ \
|
49
|
-
# !
|
50
|
-
# !
|
51
|
-
#
|
52
|
-
##
|
53
|
-
|
54
|
-
Counter.clock.intVal = 0
|
55
|
-
|
56
|
-
##
|
57
|
-
# After setting the clock signal to low, we are here:
|
58
|
-
#
|
59
|
-
# !
|
60
|
-
# !
|
61
|
-
# ____ ! ____ ____ ____
|
62
|
-
# ____/ \!____/ \____/ \____/ \
|
63
|
-
# !
|
64
|
-
# !
|
65
|
-
#
|
66
|
-
##
|
67
|
-
|
68
|
-
advance_time
|
69
|
-
|
70
|
-
##
|
71
|
-
# After advancing the time, we are here:
|
72
|
-
#
|
73
|
-
#
|
74
|
-
# !
|
75
|
-
# !
|
76
|
-
# ____ ! ____ ____ ____
|
77
|
-
# ____/ \____!/ \____/ \____/ \
|
78
|
-
# !
|
79
|
-
# !
|
80
|
-
#
|
81
|
-
##
|
82
|
-
|
83
|
-
##
|
84
|
-
# This process repeats when Vpi::simulate is invoked again.
|
85
|
-
##
|
86
|
-
end
|
@@ -1,13 +0,0 @@
|
|
1
|
-
# This is a prototype of the design under test.
|
2
|
-
|
3
|
-
# When prototyping is enabled, Vpi::advance_time invokes this
|
4
|
-
# method instead of transferring control to the Verilog simulator.
|
5
|
-
def Counter.simulate!
|
6
|
-
if clock.posedge?
|
7
|
-
if reset.intVal == 1
|
8
|
-
count.intVal = 0
|
9
|
-
else
|
10
|
-
count.intVal += 1
|
11
|
-
end
|
12
|
-
end
|
13
|
-
end
|
@@ -1,52 +0,0 @@
|
|
1
|
-
# This file runs the test.
|
2
|
-
|
3
|
-
# These are Verilog source files that need to be loaded
|
4
|
-
# by the simulator before they can be simulated.
|
5
|
-
SIMULATOR_SOURCES = [
|
6
|
-
'counter.v',
|
7
|
-
'counter_xunit_bench.v',
|
8
|
-
]
|
9
|
-
|
10
|
-
# These are paths to directories which contain the
|
11
|
-
# sources listed above, the files they `include, or both.
|
12
|
-
SIMULATOR_INCLUDES = []
|
13
|
-
|
14
|
-
# This specifies the "top module" that is to be simulated.
|
15
|
-
SIMULATOR_TARGET = 'counter_xunit_bench'
|
16
|
-
|
17
|
-
# These are command-line arguments for the simulator.
|
18
|
-
# They can be specified as a string or an array of strings:
|
19
|
-
#
|
20
|
-
# :cver => "this is one single argument",
|
21
|
-
# :cver => ['these', 'are', 'separate', 'arguments'],
|
22
|
-
# :cver => %w[these are also separate arguments],
|
23
|
-
#
|
24
|
-
SIMULATOR_ARGUMENTS = {
|
25
|
-
# GPL Cver
|
26
|
-
:cver => '',
|
27
|
-
|
28
|
-
# Icarus Verilog
|
29
|
-
:ivl => '',
|
30
|
-
|
31
|
-
# Synopsys VCS
|
32
|
-
:vcs => '',
|
33
|
-
|
34
|
-
# Mentor Modelsim
|
35
|
-
:vsim => '',
|
36
|
-
|
37
|
-
# Cadence NC-Sim
|
38
|
-
:ncsim => '',
|
39
|
-
|
40
|
-
}
|
41
|
-
|
42
|
-
# This task is invoked _before_ the simulator runs.
|
43
|
-
# It can be used to make preprations, such as converting
|
44
|
-
# Verilog header files into Ruby, for the simulation.
|
45
|
-
task :setup do
|
46
|
-
# To learn how to write Rake tasks, please see:
|
47
|
-
# http://docs.rubyrake.org/read/chapter/4#page16
|
48
|
-
end
|
49
|
-
|
50
|
-
# This command loads the Ruby-VPI runner template, which
|
51
|
-
# runs the simulator according to the information above.
|
52
|
-
require 'ruby-vpi/runner'
|