ruby-vpi 16.0.1 → 17.0.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- data/LICENSE +19 -19
- data/README +1 -1
- data/Rakefile +35 -32
- data/bin/convert.rb +28 -0
- data/bin/generate/design.rb +16 -0
- data/bin/generate/proto.rb +13 -0
- data/bin/generate/runner.rake +33 -0
- data/bin/generate/spec.rb +45 -0
- data/bin/generate.rb +177 -0
- data/bin/ruby-vpi +56 -0
- data/doc/Rakefile +20 -4
- data/doc/common.css +92 -33
- data/doc/common.inc +13 -0
- data/doc/common.tpl +42 -28
- data/doc/history.doc +11 -11
- data/doc/history.html +769 -248
- data/doc/history.inc +909 -0
- data/doc/history.rb +9 -0
- data/doc/history.yaml +69 -0
- data/doc/intro.inc +170 -178
- data/doc/lib/doc_format.rb +57 -144
- data/doc/lib/doc_proxy.rb +504 -88
- data/doc/lib/erb_content.rb +8 -8
- data/doc/lib/erb_proxy.rb +17 -17
- data/doc/manual.doc +626 -777
- data/doc/manual.html +1541 -1031
- data/doc/memo.doc +38 -36
- data/doc/memo.html +64 -28
- data/doc/readme.doc +4 -31
- data/doc/readme.html +221 -163
- data/doc/rss.erb +1 -1
- data/doc/rss.xml +73 -1761
- data/ext/Rakefile +6 -5
- data/ext/main.c +17 -15
- data/ext/relay.c +4 -7
- data/ext/relay.h +2 -2
- data/ext/swig_vpi.h +2 -2
- data/ext/swig_vpi.i +1 -2
- data/ext/swig_wrap.cin +12 -16
- data/ext/vlog.c +5 -5
- data/ext/vlog.h +2 -2
- data/lib/ruby-vpi/erb.rb +3 -3
- data/lib/ruby-vpi/float.rb +2 -2
- data/lib/ruby-vpi/rcov.rb +5 -7
- data/lib/ruby-vpi/runner.rb +43 -41
- data/lib/ruby-vpi/runner_boot_loader.rb +117 -0
- data/lib/ruby-vpi/runner_proxy.rb +6 -8
- data/lib/ruby-vpi/util.rb +10 -0
- data/lib/ruby-vpi/verilog_parser.rb +28 -56
- data/lib/ruby-vpi/vpi.rb +168 -123
- data/lib/ruby-vpi.rb +22 -143
- data/ref/c/annotated.html +1 -1
- data/ref/c/common_8h.html +1 -1
- data/ref/c/files.html +1 -1
- data/ref/c/functions.html +1 -1
- data/ref/c/functions_vars.html +1 -1
- data/ref/c/globals.html +1 -1
- data/ref/c/globals_0x63.html +1 -1
- data/ref/c/globals_0x65.html +1 -1
- data/ref/c/globals_0x66.html +1 -1
- data/ref/c/globals_0x6d.html +1 -1
- data/ref/c/globals_0x70.html +1 -1
- data/ref/c/globals_0x72.html +1 -1
- data/ref/c/globals_0x73.html +1 -1
- data/ref/c/globals_0x74.html +1 -1
- data/ref/c/globals_0x76.html +1 -1
- data/ref/c/globals_0x78.html +1 -1
- data/ref/c/globals_defs.html +1 -1
- data/ref/c/globals_defs_0x65.html +1 -1
- data/ref/c/globals_defs_0x70.html +1 -1
- data/ref/c/globals_defs_0x76.html +1 -1
- data/ref/c/globals_defs_0x78.html +1 -1
- data/ref/c/globals_enum.html +1 -1
- data/ref/c/globals_eval.html +1 -1
- data/ref/c/globals_func.html +1 -1
- data/ref/c/globals_type.html +1 -1
- data/ref/c/globals_vars.html +1 -1
- data/ref/c/index.html +1 -1
- data/ref/c/main_8c.html +1 -1
- data/ref/c/main_8h.html +1 -1
- data/ref/c/relay_8c.html +1 -1
- data/ref/c/relay_8h.html +1 -1
- data/ref/c/structt__cb__data.html +1 -1
- data/ref/c/structt__vpi__delay.html +1 -1
- data/ref/c/structt__vpi__error__info.html +1 -1
- data/ref/c/structt__vpi__strengthval.html +1 -1
- data/ref/c/structt__vpi__systf__data.html +1 -1
- data/ref/c/structt__vpi__time.html +1 -1
- data/ref/c/structt__vpi__value.html +1 -1
- data/ref/c/structt__vpi__vecval.html +1 -1
- data/ref/c/structt__vpi__vlog__info.html +1 -1
- data/ref/c/verilog_8h.html +1 -1
- data/ref/c/vlog_8c.html +1 -1
- data/ref/c/vlog_8h.html +1 -1
- data/ref/c/vpi__user_8h.html +1 -1
- data/ref/ruby/classes/ERB.html +5 -5
- data/ref/ruby/classes/ERB.src/{M000024.html → M000026.html} +0 -0
- data/ref/ruby/classes/FileUtils.html +11 -11
- data/ref/ruby/classes/FileUtils.src/{M000025.html → M000027.html} +0 -0
- data/ref/ruby/classes/FileUtils.src/{M000026.html → M000028.html} +0 -0
- data/ref/ruby/classes/Float.html +6 -6
- data/ref/ruby/classes/Float.src/{M000020.html → M000021.html} +0 -0
- data/ref/ruby/classes/Integer.html +65 -65
- data/ref/ruby/classes/Integer.src/M000009.html +12 -5
- data/ref/ruby/classes/Integer.src/M000010.html +5 -5
- data/ref/ruby/classes/Integer.src/M000011.html +5 -5
- data/ref/ruby/classes/Integer.src/M000012.html +5 -5
- data/ref/ruby/classes/Integer.src/M000013.html +5 -5
- data/ref/ruby/classes/Integer.src/M000014.html +18 -0
- data/ref/ruby/classes/Integer.src/M000017.html +12 -18
- data/ref/ruby/classes/Integer.src/M000018.html +18 -12
- data/ref/ruby/classes/Integer.src/M000019.html +12 -17
- data/ref/ruby/classes/Integer.src/M000020.html +30 -0
- data/ref/ruby/classes/RDoc.html +5 -5
- data/ref/ruby/classes/RDoc.src/{M000053.html → M000058.html} +0 -0
- data/ref/ruby/classes/{RubyVpi/Config.html → RubyVPI.html} +20 -6
- data/ref/ruby/classes/String.html +34 -15
- data/ref/ruby/classes/String.src/M000022.html +5 -28
- data/ref/ruby/classes/String.src/M000023.html +5 -5
- data/ref/ruby/classes/String.src/{M000021.html → M000024.html} +0 -0
- data/ref/ruby/classes/String.src/M000025.html +41 -0
- data/ref/ruby/classes/VerilogParser/Module/Port.html +16 -36
- data/ref/ruby/classes/VerilogParser/Module/Port.src/M000006.html +10 -5
- data/ref/ruby/classes/VerilogParser/Module/Port.src/{M000004.html → M000007.html} +4 -4
- data/ref/ruby/classes/VerilogParser/Module/Port.src/{M000005.html → M000008.html} +4 -4
- data/ref/ruby/classes/VerilogParser/Module.html +28 -9
- data/ref/ruby/classes/VerilogParser/Module.src/M000005.html +29 -0
- data/ref/ruby/classes/VerilogParser.html +5 -39
- data/ref/ruby/classes/VerilogParser.src/M000004.html +26 -0
- data/ref/ruby/classes/Vpi/Handle.html +179 -77
- data/ref/ruby/classes/Vpi/Handle.src/M000035.html +18 -0
- data/ref/ruby/classes/Vpi/Handle.src/M000036.html +5 -5
- data/ref/ruby/classes/Vpi/Handle.src/M000037.html +5 -5
- data/ref/ruby/classes/Vpi/Handle.src/M000038.html +5 -5
- data/ref/ruby/classes/Vpi/Handle.src/M000039.html +5 -5
- data/ref/ruby/classes/Vpi/Handle.src/M000040.html +5 -8
- data/ref/ruby/classes/Vpi/Handle.src/M000041.html +5 -8
- data/ref/ruby/classes/Vpi/Handle.src/M000042.html +5 -9
- data/ref/ruby/classes/Vpi/Handle.src/M000043.html +8 -31
- data/ref/ruby/classes/Vpi/Handle.src/M000044.html +8 -74
- data/ref/ruby/classes/Vpi/Handle.src/M000045.html +9 -17
- data/ref/ruby/classes/Vpi/Handle.src/M000046.html +31 -11
- data/ref/ruby/classes/Vpi/Handle.src/M000047.html +86 -0
- data/ref/ruby/classes/Vpi/Handle.src/M000048.html +17 -18
- data/ref/ruby/classes/Vpi/Handle.src/M000050.html +18 -0
- data/ref/ruby/classes/Vpi/Handle.src/M000051.html +24 -0
- data/ref/ruby/classes/Vpi/Handle.src/M000053.html +31 -0
- data/ref/ruby/classes/Vpi/Handle.src/M000054.html +89 -0
- data/ref/ruby/classes/Vpi/S_vpi_time.html +16 -16
- data/ref/ruby/classes/Vpi/S_vpi_time.src/{M000050.html → M000055.html} +4 -4
- data/ref/ruby/classes/Vpi/S_vpi_time.src/{M000051.html → M000056.html} +5 -5
- data/ref/ruby/classes/Vpi/S_vpi_value.html +15 -15
- data/ref/ruby/classes/Vpi/S_vpi_value.src/{M000035.html → M000032.html} +5 -5
- data/ref/ruby/classes/Vpi/S_vpi_value.src/M000033.html +5 -5
- data/ref/ruby/classes/Vpi/S_vpi_value.src/M000034.html +5 -5
- data/ref/ruby/classes/Vpi.html +6 -42
- data/ref/ruby/classes/Vpi.src/M000029.html +15 -5
- data/ref/ruby/classes/Vpi.src/M000030.html +24 -24
- data/ref/ruby/classes/Vpi.src/M000031.html +6 -8
- data/ref/ruby/created.rid +1 -1
- data/ref/ruby/files/bin/{header_to_ruby_rb.html → convert_rb.html} +5 -5
- data/ref/ruby/files/bin/{generate_test_rb.html → generate_rb.html} +8 -21
- data/ref/ruby/files/lib/ruby-vpi/erb_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/float_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/integer_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/rake_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/rcov_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/rdoc_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/runner_boot_loader_rb.html +197 -0
- data/ref/ruby/files/lib/ruby-vpi/runner_boot_loader_rb.src/M000001.html +17 -0
- data/ref/ruby/files/lib/ruby-vpi/runner_boot_loader_rb.src/M000002.html +18 -0
- data/ref/ruby/files/lib/ruby-vpi/runner_proxy_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi/runner_rb.html +6 -19
- data/ref/ruby/files/lib/ruby-vpi/util_rb.html +101 -0
- data/ref/ruby/files/lib/ruby-vpi/verilog_parser_rb.html +8 -1
- data/ref/ruby/files/lib/ruby-vpi/vpi_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi_rb.html +2 -14
- data/ref/ruby/fr_class_index.html +1 -3
- data/ref/ruby/fr_file_index.html +4 -2
- data/ref/ruby/fr_method_index.html +56 -51
- data/ref/ruby/index.html +1 -1
- data/samp/counter/RSpec/Rakefile +1 -0
- data/samp/counter/RSpec/counter_design.rb +15 -0
- data/samp/counter/RSpec/counter_proto.rb +10 -0
- data/samp/counter/RSpec/counter_runner.rake +44 -0
- data/samp/counter/RSpec/counter_spec.rb +39 -0
- data/samp/counter/Rakefile +1 -1
- data/samp/counter/counter.v +7 -7
- data/samp/counter/xUnit/Rakefile +1 -0
- data/samp/counter/xUnit/counter_bench.rb +95 -0
- data/samp/counter/{counter_xunit_bench.v → xUnit/counter_bench.v} +0 -0
- data/samp/counter/xUnit/counter_design.rb +15 -0
- data/samp/counter/xUnit/counter_proto.rb +10 -0
- data/samp/counter/xUnit/counter_runner.rake +44 -0
- data/samp/counter/{counter_xunit_spec.rb → xUnit/counter_spec.rb} +9 -9
- data/samp/pipelined_alu/Rakefile +1 -1
- data/samp/pipelined_alu/TestHw5UnitModel.rb +4 -5
- data/samp/pipelined_alu/hw5_unit.v +55 -85
- data/samp/pipelined_alu/hw5_unit_design.rb +51 -0
- data/samp/pipelined_alu/hw5_unit_proto.rb +4 -0
- data/samp/pipelined_alu/hw5_unit_runner.rake +43 -0
- data/samp/pipelined_alu/hw5_unit_spec.rb +64 -0
- data/samp/register_file/LICENSE +20 -0
- data/samp/register_file/README +4 -0
- data/samp/register_file/Rakefile +1 -0
- data/samp/register_file/register_file.v +18 -0
- data/samp/register_file/register_file_design.rb +11 -0
- data/samp/register_file/register_file_proto.rb +11 -0
- data/samp/register_file/register_file_runner.rake +43 -0
- data/samp/register_file/register_file_spec.rb +58 -0
- metadata +78 -66
- data/bin/generate_test.rb +0 -200
- data/bin/generate_test_tpl/bench.rb +0 -89
- data/bin/generate_test_tpl/bench.v +0 -26
- data/bin/generate_test_tpl/design.rb +0 -11
- data/bin/generate_test_tpl/proto.rb +0 -16
- data/bin/generate_test_tpl/runner.rake +0 -42
- data/bin/generate_test_tpl/spec.rb +0 -37
- data/bin/header_to_ruby.rb +0 -27
- data/ref/ruby/classes/Integer.src/M000008.html +0 -25
- data/ref/ruby/classes/Integer.src/M000016.html +0 -25
- data/ref/ruby/classes/RubyVpi.html +0 -199
- data/ref/ruby/classes/RubyVpi.src/M000027.html +0 -121
- data/ref/ruby/classes/VerilogParser/Module/Parameter.html +0 -160
- data/ref/ruby/classes/VerilogParser/Module/Parameter.src/M000007.html +0 -19
- data/ref/ruby/classes/VerilogParser/Module/Port.src/M000003.html +0 -21
- data/ref/ruby/classes/VerilogParser/Module.src/M000002.html +0 -34
- data/ref/ruby/classes/VerilogParser.src/M000001.html +0 -34
- data/ref/ruby/classes/Vpi/Handle.src/M000049.html +0 -69
- data/ref/ruby/classes/Vpi.src/M000028.html +0 -28
- data/ref/ruby/classes/Vpi.src/M000032.html +0 -22
- data/samp/counter/counter_rspec_bench.rb +0 -86
- data/samp/counter/counter_rspec_bench.v +0 -9
- data/samp/counter/counter_rspec_design.rb +0 -8
- data/samp/counter/counter_rspec_proto.rb +0 -13
- data/samp/counter/counter_rspec_runner.rake +0 -52
- data/samp/counter/counter_rspec_spec.rb +0 -39
- data/samp/counter/counter_xunit_bench.rb +0 -86
- data/samp/counter/counter_xunit_design.rb +0 -8
- data/samp/counter/counter_xunit_proto.rb +0 -13
- data/samp/counter/counter_xunit_runner.rake +0 -52
- data/samp/pipelined_alu/hw5_unit_test_bench.rb +0 -86
- data/samp/pipelined_alu/hw5_unit_test_bench.v +0 -14
- data/samp/pipelined_alu/hw5_unit_test_design.rb +0 -61
- data/samp/pipelined_alu/hw5_unit_test_proto.rb +0 -7
- data/samp/pipelined_alu/hw5_unit_test_runner.rake +0 -52
- data/samp/pipelined_alu/hw5_unit_test_spec.rb +0 -68
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<h1 style="margin-top: 0;"><a id="Ruby-VPI" href="#a-607628178">1</a> Ruby-VPI</h1>
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<li>Access the <em>entire</em> <a href="http://ieeexplore.ieee.org/xpl/standardstoc.jsp?isnumber=33945"><span class="caps">IEEE 1364</span>-2005 Verilog
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<li>Access the <em>entire</em> <a href="http://ieeexplore.ieee.org/xpl/standardstoc.jsp?isnumber=33945"><span class="caps">IEEE 1364</span>-2005 Verilog VPI</a> interface from Ruby.</li>
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<li>Perform <a href="http://ruby-vpi.rubyforge.org/papers/masters_thesis.html">specification-driven functional verification</a> (<a href="http://ruby-vpi.rubyforge.org/papers/masters_thesis.pdf">PDF version</a>).</li>
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<p>Here is a tiny sampling of code to whet your appetite. See <a href="manual.html#usage.tutorial">the tutorial</a> for more samples.</p>
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modifications made to the Derivatives. The Derivatives must be distributed
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either with the Code or, if the Code is obtainable for no more than the cost
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of distribution plus a nominal fee, with information on how to obtain the Code.</p>
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<div id="intro.license" class="section">
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<h1 class="title">
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<a href="#a-607558088">6</a>
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<span class="caps">FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT</span>. <span class="caps">IN NO EVENT SHALL</span>
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<span class="caps">THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM</span>, DAMAGES <span class="caps">OR OTHER</span>
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<span class="caps">LIABILITY</span>, WHETHER <span class="caps">IN AN ACTION OF CONTRACT</span>, TORT <span class="caps">OR OTHERWISE</span>, ARISING <span class="caps">FROM</span>,
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<span class="caps">OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN</span>
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<span class="caps">THE SOFTWARE</span>.</p>
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License
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</h1>
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<p>Copyright 2006 Suraj N. Kurapati <snk@gna.org></p>
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<h2 ><a id="intro.related-works" href="#a-607635258">1.7</a> Related works</h2>
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this software and associated documentation files (the "Software"), to deal in
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the Software without restriction, including without limitation the rights to
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use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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the Software, and to permit persons to whom the Software is furnished to do so,
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subject to the following conditions:</p>
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<
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<p>1. All modified and unmodified copies and substantial portions of the Software
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(the "Derivatives") and their corresponding machine-readable source code (the
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"Code") must include the above copyright notice and this permission notice.</p>
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<p>2. Upon distribution, the Derivatives must be accompanied either by the Code or,
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if the Code is obtainable for no more than the cost of distribution plus a
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nominal fee, by information on how to obtain the Code.</p>
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<p><span class="caps">THE SOFTWARE IS PROVIDED</span> "AS IS", <span class="caps">WITHOUT WARRANTY OF ANY KIND</span>, EXPRESS OR
|
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IMPLIED, INCLUDING <span class="caps">BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY</span>, FITNESS
|
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<span class="caps">FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT</span>. IN <span class="caps">NO EVENT SHALL THE AUTHORS OR</span>
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<span class="caps">COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM</span>, DAMAGES <span class="caps">OR OTHER LIABILITY</span>, WHETHER
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<span class="caps">IN AN ACTION OF CONTRACT</span>, TORT <span class="caps">OR OTHERWISE</span>, ARISING FROM, OUT <span class="caps">OF OR IN</span>
|
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<span class="caps">CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE</span>.</p>
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</div>
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</p>
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<p>
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<hr style="display: none"/>
|
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<div id="intro.related-works" class="section">
|
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<h1 class="title">
|
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<a href="#a-607563868">7</a>
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|
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Related works
|
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</h1>
|
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|
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<ul>
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<li><a href="http://jove.sourceforge.net">JOVE</a> is a Java interface to VPI.</li>
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<li><a href="http://teal.sourceforge.net">Teal</a> is a C++ interface to VPI.</li>
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<li><a href="http://embedded.eecs.berkeley.edu/Alumni/pinhong/scriptEDA/">ScriptEDA</a> is a Perl, Python, and Tcl interface to VPI.</li>
|
|
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<li><a href="http://rhdl.rubyforge.org">RHDL</a> is a hardware description and verification language based on Ruby.</li>
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<li><a href="http://myhdl.jandecaluwe.com">MyHDL</a> is a hardware description and verification language based on Python, which features conversion to Verilog and co-simulation.</li>
|
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</ul>
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<
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<p>
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<hr style="display: none"/>
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|
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|
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<div id="intro.related-works.pli" class="section">
|
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|
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<h2 class="title">
|
|
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|
+
<a href="#a-607560688">7.1</a>
|
|
379
426
|
|
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|
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|
|
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|
+
|
|
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|
+
|
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|
+
Ye olde PLI
|
|
430
|
+
</h2>
|
|
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|
+
|
|
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|
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The following projects utilize the archaic <strong>tf</strong> and <strong>acc</strong> PLI interfaces, which have been officially deprecated in IEEE Std 1364-2005.
|
|
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|
|
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|
|
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|
<ul>
|
|
384
|
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<li><a href="http://www.nelsim.com">ScriptSim</a> is a Perl, Python, and Tcl/Tk interface to
|
|
385
|
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<li><a href="http://www.veripool.com/verilog-pli.html">Verilog::Pli</a> is a Perl interface to
|
|
386
|
-
<li><a href="http://www.time-rover.com/jpli/"><span class="caps">JPLI</span></a> is a proprietary Java interface to <span class="caps">PLI</span>.</li>
|
|
436
|
+
<li><a href="http://www.nelsim.com">ScriptSim</a> is a Perl, Python, and Tcl/Tk interface to PLI.</li>
|
|
437
|
+
<li><a href="http://www.veripool.com/verilog-pli.html">Verilog::Pli</a> is a Perl interface to PLI.</li>
|
|
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|
</ul>
|
|
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|
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|
|
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|
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|
|
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|
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</div>
|
|
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|
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</p>
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|
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</div>
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