rggen 0.5.1 → 0.6.0

data/rtl/register/rggen_address_decoder.sv

@@ -1,37 +0,0 @@
-module rggen_address_decoder #(
-  parameter ADDRESS_WIDTH         = 16,
-  parameter START_ADDRESS         = 'h00,
-  parameter END_ADDRESS           = 'h00,
-  parameter INDIRECT_REGISTER     = 0,
-  parameter INDIRECT_INDEX_WIDTH  = 1,
-  parameter INDIRECT_INDEX_VALUE  = 'h00
-)(
-  input   [ADDRESS_WIDTH-1:0]         i_address,
-  input   [INDIRECT_INDEX_WIDTH-1:0]  i_indirect_index,
-  output                              o_select
-);
-  logic match_address;
-  logic match_indirect_index;
-
-  assign  o_select  = (match_address && match_indirect_index) ? 1'b1 : 1'b0;
-
-  generate
-    if (START_ADDRESS == END_ADDRESS) begin
-      assign  match_address = (i_address == START_ADDRESS) ? 1'b1 : 1'b0;
-    end
-    else begin
-      assign  match_address = (
-        (i_address >= START_ADDRESS) && (i_address <= END_ADDRESS)
-      ) ? 1'b1 : 1'b0;
-    end
-  endgenerate
-
-  generate
-    if (INDIRECT_REGISTER) begin
-      assign  match_indirect_index  = (i_indirect_index == INDIRECT_INDEX_VALUE) ? 1'b1 : 1'b0;
-    end
-    else begin
-      assign  match_indirect_index  = 1'b1;
-    end
-  endgenerate
-endmodule

data/rtl/register/rggen_bus_exporter.sv

@@ -1,96 +0,0 @@
-module rggen_bus_exporter #(
-  parameter DATA_WIDTH              = 32,
-  parameter LOCAL_ADDRESS_WIDTH     = 16,
-  parameter EXTERNAL_ADDRESS_WIDTH  = 8,
-  parameter START_ADDRESS           = 16'h0000
-)(
-  input                                 clk,
-  input                                 rst_n,
-  input                                 i_valid,
-  input                                 i_select,
-  input                                 i_write,
-  input                                 i_read,
-  input   [LOCAL_ADDRESS_WIDTH-1:0]     i_address,
-  input   [DATA_WIDTH/8-1:0]            i_strobe,
-  input   [DATA_WIDTH-1:0]              i_write_data,
-  output                                o_ready,
-  output  [DATA_WIDTH-1:0]              o_read_data,
-  output  [1:0]                         o_status,
-  output                                o_valid,
-  output                                o_write,
-  output                                o_read,
-  output  [EXTERNAL_ADDRESS_WIDTH-1:0]  o_address,
-  output  [DATA_WIDTH/8-1:0]            o_strobe,
-  output  [DATA_WIDTH-1:0]              o_write_data,
-  input                                 i_ready,
-  input   [DATA_WIDTH-1:0]              i_read_data,
-  input   [1:0]                         i_status
-);
-  logic                               access_done;
-  logic                               valid;
-  logic                               write;
-  logic                               read;
-  logic [EXTERNAL_ADDRESS_WIDTH-1:0]  address;
-  logic [DATA_WIDTH/8-1:0]            strobe;
-  logic [DATA_WIDTH-1:0]              write_data;
-
-  always_ff @(posedge clk or negedge rst_n) begin
-    if (!rst_n) begin
-      access_done <= 1'b0;
-    end
-    else if (valid && i_ready) begin
-      access_done <= 1'b1;
-    end
-    else begin
-      access_done <= 1'b0;
-    end
-  end
-
-  //  Internal -> External
-  assign  o_valid       = valid;
-  assign  o_write       = write;
-  assign  o_read        = read;
-  assign  o_address     = address;
-  assign  o_strobe      = strobe;
-  assign  o_write_data  = write_data;
-
-  always_ff @(posedge clk or negedge rst_n) begin
-    if (!rst_n) begin
-      valid       <= 1'b0;
-      write       <= 1'b0;
-      read        <= 1'b0;
-      address     <= '0;
-      strobe      <= '0;
-      write_data  <= '0;
-    end
-    else if (valid && i_ready) begin
-      valid       <= 1'b0;
-      write       <= 1'b0;
-      read        <= 1'b0;
-      address     <= '0;
-      strobe      <= '0;
-      write_data  <= '0;
-    end
-    else if (i_valid && i_select && (!valid) && (!access_done)) begin
-      valid       <= 1'b1;
-      write       <= i_write;
-      read        <= i_read;
-      address     <= calc_address(i_address);
-      strobe      <= i_strobe;
-      write_data  <= i_write_data;
-    end
-  end
-
-  function automatic logic [EXTERNAL_ADDRESS_WIDTH-1:0] calc_address(
-    input [LOCAL_ADDRESS_WIDTH-1:0] address
-  );
-    logic [LOCAL_ADDRESS_WIDTH-1:0] external_address;
-    external_address  = address - START_ADDRESS;
-    return external_address[EXTERNAL_ADDRESS_WIDTH-1:0];
-  endfunction
-
-  //  External -> Internal
-  assign  o_ready     = i_ready;
-  assign  o_read_data = i_read_data;
-  assign  o_status    = i_status;
-endmodule

data/rtl/register_block/rggen_host_if_apb.sv

@@ -1,42 +0,0 @@
-module rggen_host_if_apb #(
-  parameter DATA_WIDTH          = 32,
-  parameter HOST_ADDRESS_WIDTH  = 16,
-  parameter LOCAL_ADDRESS_WIDTH = 16
-)(
-  input                             clk,
-  input                             rst_n,
-  input   [HOST_ADDRESS_WIDTH-1:0]  i_paddr,
-  input   [2:0]                     i_pprot,
-  input                             i_psel,
-  input                             i_penable,
-  input                             i_pwrite,
-  input   [DATA_WIDTH-1:0]          i_pwdata,
-  input   [DATA_WIDTH/8-1:0]        i_pstrb,
-  output                            o_pready,
-  output  [DATA_WIDTH-1:0]          o_prdata,
-  output                            o_pslverr,
-  output                            o_command_valid,
-  output                            o_write,
-  output                            o_read,
-  output  [LOCAL_ADDRESS_WIDTH-1:0] o_address,
-  output  [DATA_WIDTH/8-1:0]        o_strobe,
-  output  [DATA_WIDTH-1:0]          o_write_data,
-  output  [DATA_WIDTH-1:0]          o_write_mask,
-  input                             i_response_ready,
-  input   [DATA_WIDTH-1:0]          i_read_data,
-  input   [1:0]                     i_status
-);
-  `include "rggen_host_if_common.svh"
-
-  assign  o_pready  = i_response_ready;
-  assign  o_prdata  = i_read_data;
-  assign  o_pslverr = i_status[0];
-
-  assign  o_command_valid = i_psel;
-  assign  o_write         = i_pwrite;
-  assign  o_read          = ~i_pwrite;
-  assign  o_address       = i_paddr[LOCAL_ADDRESS_WIDTH-1:0];
-  assign  o_strobe        = i_pstrb;
-  assign  o_write_data    = i_pwdata;
-  assign  o_write_mask    = get_write_mask(i_pstrb);
-endmodule

data/rtl/register_block/rggen_host_if_axi4lite.sv

@@ -1,257 +0,0 @@
-module rggen_host_if_axi4lite #(
-  parameter DATA_WIDTH          = 32,
-  parameter HOST_ADDRESS_WIDTH  = 16,
-  parameter LOCAL_ADDRESS_WIDTH = 16,
-  parameter WRITE_PRIORITY      = 1
-)(
-  input                             clk,
-  input                             rst_n,
-  input                             i_awvalid,
-  output                            o_awready,
-  input   [HOST_ADDRESS_WIDTH-1:0]  i_awaddr,
-  input   [2:0]                     i_awprot,
-  input                             i_wvalid,
-  output                            o_wready,
-  input   [DATA_WIDTH-1:0]          i_wdata,
-  input   [DATA_WIDTH/8-1:0]        i_wstrb,
-  output                            o_bvalid,
-  input                             i_bready,
-  output  [1:0]                     o_bresp,
-  input                             i_arvalid,
-  output                            o_arready,
-  input   [HOST_ADDRESS_WIDTH-1:0]  i_araddr,
-  input   [2:0]                     i_arprot,
-  output                            o_rvalid,
-  input                             i_rready,
-  output  [DATA_WIDTH-1:0]          o_rdata,
-  output  [1:0]                     o_rresp,
-  output                            o_command_valid,
-  output                            o_write,
-  output                            o_read,
-  output  [LOCAL_ADDRESS_WIDTH-1:0] o_address,
-  output  [DATA_WIDTH/8-1:0]        o_strobe,
-  output  [DATA_WIDTH-1:0]          o_write_data,
-  output  [DATA_WIDTH-1:0]          o_write_mask,
-  input                             i_response_ready,
-  input   [DATA_WIDTH-1:0]          i_read_data,
-  input   [1:0]                     i_status
-);
-  `include "rggen_host_if_common.svh"
-
-  typedef enum logic [5:0] {
-    IDLE              = 6'b000001,
-    WAIT_WDATA        = 6'b000010,
-    WRITE_IN_PROGRESS = 6'b000100,
-    WAIT_BRESP_READY  = 6'b001000,
-    READ_IN_PROGRESS  = 6'b010000,
-    WAIT_RDATA_READY  = 6'b100000
-  } e_state;
-
-  typedef enum logic [1:0] {
-    OKAY    = 2'b00,
-    EXOKAY  = 2'b01,
-    SLVERR  = 2'b10,
-    DECERR  = 2'b11
-  } e_resp;
-
-  function e_resp get_resp(logic [1:0] status);
-    case (1'b1)
-      status[0]:  return SLVERR;
-      status[1]:  return EXOKAY;
-      default:    return OKAY;
-    endcase
-  endfunction
-
-  e_state                         state;
-  logic                           awready;
-  logic                           wready;
-  logic                           bvalid;
-  e_resp                          bresp;
-  logic                           arready;
-  logic                           rvalid;
-  logic [DATA_WIDTH-1:0]          rdata;
-  e_resp                          rresp;
-  logic                           awack;
-  logic                           wack;
-  logic                           back;
-  logic                           arack;
-  logic                           rack;
-  logic                           command_valid;
-  logic                           local_done;
-  logic [LOCAL_ADDRESS_WIDTH-1:0] address;
-  logic [DATA_WIDTH/8-1:0]        strobe;
-  logic [DATA_WIDTH-1:0]          write_data;
-  logic [DATA_WIDTH-1:0]          write_mask;
-
-//--------------------------------------------------------------
-// State machine
-//--------------------------------------------------------------
-  always_ff @(posedge clk or negedge rst_n) begin
-    if (!rst_n) begin
-      state <= IDLE;
-    end
-    else begin
-      unique case (state)
-        IDLE: begin
-          if (awack && wack) begin
-            state <= WRITE_IN_PROGRESS;
-          end
-          else if (awack) begin
-            state <= WAIT_WDATA;
-          end
-          else if (arack) begin
-            state <= READ_IN_PROGRESS;
-          end
-        end
-        WAIT_WDATA: begin
-          if (wack) begin
-            state <= WRITE_IN_PROGRESS;
-          end
-        end
-        WRITE_IN_PROGRESS: begin
-          if (local_done) begin
-            state <= WAIT_BRESP_READY;
-          end
-        end
-        WAIT_BRESP_READY: begin
-          if (back) begin
-            state <= IDLE;
-          end
-        end
-        READ_IN_PROGRESS: begin
-          if (local_done) begin
-            state <= WAIT_RDATA_READY;
-          end
-        end
-        WAIT_RDATA_READY: begin
-          if (rack) begin
-            state <= IDLE;
-          end
-        end
-        default: begin
-          state <= IDLE;
-        end
-      endcase
-    end
-  end
-
-//--------------------------------------------------------------
-// AXI4-Lite
-//--------------------------------------------------------------
-  assign  o_awready = awready;
-  assign  o_wready  = wready;
-  assign  o_bvalid  = bvalid;
-  assign  o_bresp   = bresp;
-  assign  o_arready = arready;
-  assign  o_rvalid  = rvalid;
-  assign  o_rdata   = rdata;
-  assign  o_rresp   = rresp;
-
-  assign  awack = i_awvalid & awready;
-  assign  wack  = i_wvalid  & wready;
-  assign  back  = bvalid    & i_bready;
-  assign  arack = i_arvalid & arready;
-  assign  rack  = rvalid    & i_rready;
-
-  generate
-    if (WRITE_PRIORITY) begin
-      assign  awready = state[0];
-      assign  wready  = (state[0] || state[1]) ? 1'b1 : 1'b0;
-      assign  bvalid  = state[3];
-      assign  arready = (state[0] && (!i_awvalid)) ? 1'b1 : 1'b0;
-      assign  rvalid  = state[5];
-    end
-    else begin
-      assign  awready = (state[0] && (!i_arvalid)) ? 1'b1 : 1'b0;
-      assign  wready  = ((state[0] && (!i_arvalid)) || state[1]) ? 1'b1 : 1'b0;
-      assign  bvalid  = state[3];
-      assign  arready = state[0];
-      assign  rvalid  = state[5];
-    end
-  endgenerate
-
-  always_ff @(posedge clk or negedge rst_n) begin
-    if (!rst_n) begin
-      bresp <= OKAY;
-    end
-    else if (state[2] && local_done) begin
-      bresp <= get_resp(i_status);
-    end
-    else if (back) begin
-      bresp <= OKAY;
-    end
-  end
-
-  always_ff @(posedge clk or negedge rst_n) begin
-    if (!rst_n) begin
-      rdata <= '0;
-      rresp <= OKAY;
-    end
-    else if (state[4] && local_done) begin
-      rdata <= i_read_data;
-      rresp <= get_resp(i_status);
-    end
-    else if (rack) begin
-      rdata <= '0;
-      rresp <= OKAY;
-    end
-  end
-
-//--------------------------------------------------------------
-// Local bus
-//--------------------------------------------------------------
-  assign  o_command_valid = command_valid;
-  assign  o_write         = state[2];
-  assign  o_read          = state[4];
-  assign  o_address       = address;
-  assign  o_strobe        = strobe;
-  assign  o_write_data    = write_data;
-  assign  o_write_mask    = write_mask;
-
-  assign  local_done  = command_valid & i_response_ready;
-
-  always_ff @(posedge clk or negedge rst_n) begin
-    if (!rst_n) begin
-      command_valid <= 1'b0;
-    end
-    else if (wack || arack) begin
-      command_valid <= 1'b1;
-    end
-    else if (local_done) begin
-      command_valid <= 1'b0;
-    end
-  end
-
-  always_ff @(posedge clk or negedge rst_n) begin
-    if (!rst_n) begin
-      address <= '0;
-    end
-    else if (awack) begin
-      address <= i_awaddr[LOCAL_ADDRESS_WIDTH-1:0];
-    end
-    else if (arack) begin
-      address <= i_araddr[LOCAL_ADDRESS_WIDTH-1:0];
-    end
-    else if (local_done) begin
-      address <= '0;
-    end
-  end
-
-  always_ff @(posedge clk or negedge rst_n) begin
-    if (!rst_n) begin
-      strobe      <= '0;
-      write_data  <= '0;
-      write_mask  <= '0;
-    end
-    else if (wack) begin
-      strobe      <= i_wstrb;
-      write_data  <= i_wdata;
-      write_mask  <= get_write_mask(i_wstrb);
-    end
-    else if (local_done) begin
-      strobe      <= '0;
-      write_data  <= '0;
-      write_mask  <= '0;
-    end
-  end
-endmodule

data/rtl/register_block/rggen_host_if_common.svh

@@ -1,9 +0,0 @@
-function automatic logic [DATA_WIDTH-1:0] get_write_mask(
-  input [DATA_WIDTH/8-1:0]  strobe
-);
-  logic [DATA_WIDTH-1:0]  write_mask;
-  for (int i = 0;i < $size(strobe);i++) begin
-    write_mask[i*8+:8]  = {8{strobe[i]}};
-  end
-  return write_mask;
-endfunction

data/rtl/register_block/rggen_response_mux.sv

@@ -1,113 +0,0 @@
-module rggen_response_mux #(
-  parameter DATA_WIDTH                = 32,
-  parameter TOTAL_REGISTERS           = 1,
-  parameter TOTAL_EXTERNAL_REGISTERS  = 0,
-  parameter EXTERNAL_REGISTERS        = TOTAL_EXTERNAL_REGISTERS
-                                      + ((TOTAL_EXTERNAL_REGISTERS == 0) ? 1 : 0)
-)(
-  input                             clk,
-  input                             rst_n,
-  input                             i_command_valid,
-  input                             i_read,
-  output                            o_response_ready,
-  output  [DATA_WIDTH-1:0]          o_read_data,
-  output  [1:0]                     o_status,
-  input   [TOTAL_REGISTERS-1:0]     i_register_select,
-  input   [DATA_WIDTH-1:0]          i_register_read_data[TOTAL_REGISTERS],
-  input   [EXTERNAL_REGISTERS-1:0]  i_external_register_select,
-  input   [EXTERNAL_REGISTERS-1:0]  i_external_register_ready,
-  input   [1:0]                     i_external_register_status[EXTERNAL_REGISTERS]
-);
-  //  Response ready
-  logic internal_ready;
-  logic external_ready;
-  logic response_valid;
-  logic response_ready;
-
-  assign  internal_ready  = (TOTAL_EXTERNAL_REGISTERS > 0) ? ~|i_external_register_select : 1'b1;
-  assign  external_ready  = (TOTAL_EXTERNAL_REGISTERS > 0) ?  |i_external_register_ready  : 1'b0;
-  assign  response_valid  = i_command_valid & (internal_ready | external_ready) & (~response_ready);
-
-  assign  o_response_ready  = response_ready;
-  always_ff @(posedge clk or negedge rst_n) begin
-    if (!rst_n) begin
-      response_ready  <= 1'b0;
-    end
-    else if (response_valid) begin
-      response_ready  <= 1'b1;
-    end
-    else begin
-      response_ready  <= 1'b0;
-    end
-  end
-
-  //  Status
-  logic [1:0] status;
-
-  assign  o_status      = status;
-  always_ff @(posedge clk or negedge rst_n) begin
-    if (!rst_n) begin
-      status  <= 2'b00;
-    end
-    else if (response_valid) begin
-      status  <= get_internal_response(i_register_select)
-               | get_external_response(i_external_register_select, i_external_register_status);
-    end
-    else begin
-      status  <= 2'b00;
-    end
-  end
-
-  function automatic logic [1:0] get_internal_response(
-    input [TOTAL_REGISTERS-1:0] register_select
-  );
-    logic slave_error;
-    logic exokay;
-    slave_error = ~|register_select;
-    exokay      = 1'b0;
-    return {exokay, slave_error};
-  endfunction
-
-  function automatic logic [1:0] get_external_response(
-    input [EXTERNAL_REGISTERS-1:0]  external_register_select,
-    input [1:0]                     external_register_status[EXTERNAL_REGISTERS]
-  );
-    if (TOTAL_EXTERNAL_REGISTERS > 0) begin
-      logic [1:0] masked_status[TOTAL_EXTERNAL_REGISTERS];
-      for (int i = 0;i < TOTAL_EXTERNAL_REGISTERS;i++) begin
-        masked_status[i]  = {2{external_register_select[i]}} & external_register_status[i];
-      end
-      return masked_status.or();
-    end
-    else begin
-      return 2'b00;
-    end
-  endfunction
-
-  //  Read data
-  logic [DATA_WIDTH-1:0]  read_data;
-
-  assign  o_read_data = read_data;
-  always_ff @(posedge clk or negedge rst_n) begin
-    if (!rst_n)  begin
-      read_data <= '0;
-    end
-    else if (response_valid && i_read) begin
-      read_data <= get_read_data(i_register_select, i_register_read_data);
-    end
-    else begin
-      read_data <= '0;
-    end
-  end
-
-  function automatic logic [DATA_WIDTH-1:0] get_read_data(
-    input logic [TOTAL_REGISTERS-1:0] select,
-    input logic [DATA_WIDTH-1:0]      read_data[TOTAL_REGISTERS]
-  );
-    logic [DATA_WIDTH-1:0]  masked_read_data[TOTAL_REGISTERS];
-    for (int i = 0;i < TOTAL_REGISTERS;i++) begin
-      masked_read_data[i] = {DATA_WIDTH{select[i]}} & read_data[i];
-    end
-    return masked_read_data.or();
-  endfunction
-endmodule