rggen 0.5.1 → 0.6.0

data/lib/rggen/builtins/register/type.rb

@@ -173,6 +173,80 @@ list_item :register, :type do
     end
   end
 
+  rtl do
+    item_base do
+      export :register_if
+
+      delegate [:data_width, :byte_width] => :configuration
+      delegate [:local_address_width] => :register_block
+      delegate [:loop_variables, :local_index, :dimensions] => :register
+
+      build do
+        interface :register, :bit_field_if,
+                  type:       :rggen_bit_field_if,
+                  name:       :bit_field_if,
+                  parameters: [data_width] if total_bit_fields > 0
+      end
+
+      def register_if
+        register_block.register_if[register.index]
+      end
+
+      private
+
+      def actual_bit_fields
+        @non_reserved_bit_fields ||= register.bit_fields.reject(&:reserved?)
+      end
+
+      def total_bit_fields
+        actual_bit_fields.size
+      end
+
+      def start_address
+        address_code(register.start_address)
+      end
+
+      def end_address
+        return address_code(register.end_address) unless register.array?
+        address_code(
+          register.start_address + byte_width - 1
+        )
+      end
+
+      def address_code(address)
+        base  = hex(address, local_address_width)
+        if register.array? && register.multiple?
+          increment_value = hex(byte_width, local_address_width)
+          "#{base} + #{increment_value} * #{local_index}"
+        else
+          base
+        end
+      end
+
+      def valid_bits
+        hex(valid_bits_value, data_width)
+      end
+
+      def valid_bits_value
+        actual_bit_fields.inject(0) do |bits, bit_field|
+          bits |= (((1 << bit_field.width) - 1) << bit_field.lsb)
+        end
+      end
+    end
+
+    default_item do
+      generate_code :register do
+        process_template File.join(__dir__, 'types', 'default.erb')
+      end
+    end
+
+    factory do
+      def select_target_item(_, register)
+        @target_items[register.type]
+      end
+    end
+  end
+
   c_header do
     item_base do
       define_helpers do

data/lib/rggen/builtins/register/types/default.erb

@@ -0,0 +1,10 @@
+rggen_default_register #(
+  .ADDRESS_WIDTH  (<%= local_address_width %>),
+  .START_ADDRESS  (<%= start_address %>),
+  .END_ADDRESS    (<%= end_address %>),
+  .DATA_WIDTH     (<%= data_width %>),
+  .VALID_BITS     (<%= valid_bits %>)
+) u_<%= register.name %> (
+  .register_if  (<%= register.register_if %>),
+  .bit_field_if (<%= bit_field_if %>)
+);

data/lib/rggen/builtins/register/types/external.erb

@@ -0,0 +1,11 @@
+rggen_external_register #(
+  .ADDRESS_WIDTH  (<%= local_address_width %>),
+  .START_ADDRESS  (<%= start_address %>),
+  .END_ADDRESS    (<%= end_address %>),
+  .DATA_WIDTH     (<%= configuration.data_width %>)
+) u_<%= register.name %> (
+  .clk          (<%= register_block.clock %>),
+  .rst_n        (<%= register_block.reset %>),
+  .register_if  (<%= register.register_if %>),
+  .bus_if       (<%= bus_if %>)
+);

data/lib/rggen/builtins/register/types/external.rb

@@ -5,6 +5,17 @@ list_item :register, :type, :external do
     need_no_bit_fields
   end
 
+  rtl do
+    build do
+      interface_port :register_block, :bus_if,
+                     name:    "#{register.name}_bus_if",
+                     type:    :rggen_bus_if,
+                     modport: :master
+    end
+
+    generate_code_from_template :register
+  end
+
   c_header do
     delegate [:name, :byte_size] => :register
 

data/lib/rggen/builtins/register/types/indirect.erb

@@ -0,0 +1,13 @@
+rggen_indirect_register #(
+  .ADDRESS_WIDTH  (<%= local_address_width %>),
+  .START_ADDRESS  (<%= start_address %>),
+  .END_ADDRESS    (<%= end_address %>),
+  .INDEX_WIDTH    (<%= indirect_index_width %>),
+  .INDEX_VALUE    (<%= indirect_index_value %>),
+  .DATA_WIDTH     (<%= data_width %>),
+  .VALID_BITS     (<%= valid_bits %>)
+) u_<%= register.name %> (
+  .register_if  (<%= register.register_if %>),
+  .bit_field_if (<%= bit_field_if %>),
+  .i_index      (<%= indirect_index %>)
+);

data/lib/rggen/builtins/register/types/indirect.rb

@@ -126,6 +126,49 @@ list_item :register, :type, :indirect do
     end
   end
 
+  rtl do
+    build do
+      logic :register, :indirect_index, width: indirect_index_width
+    end
+
+    generate_code :register do |code|
+      code << indirect_index_assignment << nl
+      code << process_template
+    end
+
+    def indirect_index_fields
+      @indirect_index_fields  ||= register.indexes.map do |i|
+        register_block.bit_fields.find_by(name: i.name)
+      end
+    end
+
+    def indirect_index_assignment
+      assign(
+        indirect_index, concat(indirect_index_fields.map(&:value))
+      )
+    end
+
+    def indirect_index_width
+      indirect_index_fields.sum(0, &:width)
+    end
+
+    def indirect_index_value
+      concat(indirect_index_values)
+    end
+
+    def indirect_index_values
+      variables = loop_variables
+      register.indexes.map.with_index do |index, i|
+        if index.value
+          hex(index.value, indirect_index_fields[i].width)
+        else
+          variable  = variables.shift
+          variable[indirect_index_fields[i].width - 1, 0]
+        end
+      end
+    end
+  end
+
   c_header do
     address_struct_member do
       variable_declaration(name: register.name, data_type: data_type)

data/lib/rggen/builtins/register_block/clock_reset.rb

@@ -1,8 +1,8 @@
 simple_item :register_block, :clock_reset do
   rtl do
     build do
-      input :clock, name: 'clk'  , width: 1
-      input :reset, name: 'rst_n', width: 1
+      input :register_block, :clock, name: 'clk'  , width: 1
+      input :register_block, :reset, name: 'rst_n', width: 1
     end
   end
 end

data/lib/rggen/builtins/register_block/host_if.rb

@@ -40,19 +40,18 @@ list_item :register_block, :host_if do
     shared_context.enabled_host_ifs = @enabled_items
 
     item_base do
+      delegate [:local_address_width, :clock, :reset] => :register_block
+      delegate [:data_width] => :configuration
+
       build do
-        group(:host_if) do
-          logic :command_valid , width: 1
-          logic :write         , width: 1
-          logic :read          , width: 1
-          logic :address       , width: register_block.local_address_width
-          logic :strobe        , width: configuration.byte_width
-          logic :write_data    , width: configuration.data_width
-          logic :write_mask    , width: configuration.data_width
-          logic :response_ready, width: 1
-          logic :read_data     , width: configuration.data_width
-          logic :status        , width: 2
-        end
+        interface :register_block, :register_if,
+                  type: :rggen_register_if,
+                  parameters: [local_address_width, data_width],
+                  dimensions: [total_registers]
+      end
+
+      def total_registers
+        register_block.registers.sum(0, &:count)
       end
     end
 

data/lib/rggen/builtins/register_block/host_ifs/apb.erb

@@ -1,28 +1,10 @@
 rggen_host_if_apb #(
-  .DATA_WIDTH           (<%= configuration.data_width %>),
-  .HOST_ADDRESS_WIDTH   (<%= configuration.address_width %>),
-  .LOCAL_ADDRESS_WIDTH  (<%= register_block.local_address_width %>)
+  .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
+  .DATA_WIDTH           (<%= data_width %>),
+  .TOTAL_REGISTERS      (<%= total_registers %>)
 ) u_host_if (
-  .clk              (<%= register_block.clock %>),
-  .rst_n            (<%= register_block.reset %>),
-  .i_paddr          (<%= apb.paddr %>),
-  .i_pprot          (<%= apb.pprot %>),
-  .i_psel           (<%= apb.psel %>),
-  .i_penable        (<%= apb.penable %>),
-  .i_pwrite         (<%= apb.pwrite %>),
-  .i_pwdata         (<%= apb.pwdata %>),
-  .i_pstrb          (<%= apb.pstrb %>),
-  .o_pready         (<%= apb.pready %>),
-  .o_prdata         (<%= apb.prdata %>),
-  .o_pslverr        (<%= apb.pslverr %>),
-  .o_command_valid  (<%= host_if.command_valid %>),
-  .o_write          (<%= host_if.write %>),
-  .o_read           (<%= host_if.read %>),
-  .o_address        (<%= host_if.address %>),
-  .o_strobe         (<%= host_if.strobe %>),
-  .o_write_data     (<%= host_if.write_data %>),
-  .o_write_mask     (<%= host_if.write_mask %>),
-  .i_response_ready (<%= host_if.response_ready %>),
-  .i_read_data      (<%= host_if.read_data %>),
-  .i_status         (<%= host_if.status %>)
+  .clk          (<%= clock %>),
+  .rst_n        (<%= reset %>),
+  .apb_if       (<%= apb_if %>),
+  .register_if  (<%= register_if %>)
 );

data/lib/rggen/builtins/register_block/host_ifs/apb.rb

@@ -14,20 +14,11 @@ list_item :register_block, :host_if, :apb do
 
   rtl do
     build do
-      group(:apb) do
-        input  :paddr  , name: 'i_paddr'  , width: configuration.address_width
-        input  :pprot  , name: 'i_pprot'  , width: 3
-        input  :psel   , name: 'i_psel'   , width: 1
-        input  :penable, name: 'i_penable', width: 1
-        input  :pwrite , name: 'i_pwrite' , width: 1
-        input  :pwdata , name: 'i_pwdata' , width: configuration.data_width
-        input  :pstrb  , name: 'i_pstrb'  , width: configuration.byte_width
-        output :pready , name: 'o_pready' , width: 1
-        output :prdata , name: 'o_prdata' , width: configuration.data_width
-        output :pslverr, name: 'o_pslverr', width: 1
-      end
+      interface_port :register_block, :apb_if,
+                     type: :rggen_apb_if,
+                     modport: :slave
     end
 
-    generate_code_from_template :module_item
+    generate_code_from_template :register_block
   end
 end

data/lib/rggen/builtins/register_block/host_ifs/axi4lite.erb

@@ -1,38 +1,10 @@
 rggen_host_if_axi4lite #(
-  .DATA_WIDTH           (<%= data_width %>),
-  .HOST_ADDRESS_WIDTH   (<%= address_width %>),
   .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
-  .WRITE_PRIORITY       (<%= write_priority %>)
+  .DATA_WIDTH           (<%= data_width %>),
+  .ACCESS_PRIORITY      (<%= access_priority %>)
 ) u_host_if (
-  .clk              (<%= clock %>),
-  .rst_n            (<%= reset %>),
-  .i_awvalid        (<%= axi4lite.awvalid %>),
-  .o_awready        (<%= axi4lite.awready %>),
-  .i_awaddr         (<%= axi4lite.awaddr %>),
-  .i_awprot         (<%= axi4lite.awprot %>),
-  .i_wvalid         (<%= axi4lite.wvalid %>),
-  .o_wready         (<%= axi4lite.wready %>),
-  .i_wdata          (<%= axi4lite.wdata %>),
-  .i_wstrb          (<%= axi4lite.wstrb %>),
-  .o_bvalid         (<%= axi4lite.bvalid %>),
-  .i_bready         (<%= axi4lite.bready %>),
-  .o_bresp          (<%= axi4lite.bresp %>),
-  .i_arvalid        (<%= axi4lite.arvalid %>),
-  .o_arready        (<%= axi4lite.arready %>),
-  .i_araddr         (<%= axi4lite.araddr %>),
-  .i_arprot         (<%= axi4lite.arprot %>),
-  .o_rvalid         (<%= axi4lite.rvalid %>),
-  .i_rready         (<%= axi4lite.rready %>),
-  .o_rdata          (<%= axi4lite.rdata %>),
-  .o_rresp          (<%= axi4lite.rresp %>),
-  .o_command_valid  (<%= host_if.command_valid %>),
-  .o_write          (<%= host_if.write %>),
-  .o_read           (<%= host_if.read %>),
-  .o_address        (<%= host_if.address %>),
-  .o_strobe         (<%= host_if.strobe %>),
-  .o_write_data     (<%= host_if.write_data %>),
-  .o_write_mask     (<%= host_if.write_mask %>),
-  .i_response_ready (<%= host_if.response_ready %>),
-  .i_read_data      (<%= host_if.read_data %>),
-  .i_status         (<%= host_if.status %>)
+  .clk          (<%= clock %>),
+  .rst_n        (<%= reset %>),
+  .axi4lite_if  (<%= axi4lite_if %>),
+  .register_if  (<%= register_if %>)
 );

data/lib/rggen/builtins/register_block/host_ifs/axi4lite.rb

@@ -9,38 +9,16 @@ list_item :register_block, :host_if, :axi4lite do
   end
 
   rtl do
-    delegate [
-      :address_width, :data_width, :byte_width
-    ] => :configuration
-    delegate [
-      :local_address_width, :clock, :reset
-    ] => :register_block
-
     build do
-      parameter :write_priority, name: 'WRITE_PRIORITY', default: 1
-      group :axi4lite do
-        input  :awvalid, name: 'i_awvalid', width: 1
-        output :awready, name: 'o_awready', width: 1
-        input  :awaddr , name: 'i_awaddr' , width: address_width
-        input  :awprot , name: 'i_awprot' , width: 3
-        input  :wvalid , name: 'i_wvalid' , width: 1
-        output :wready , name: 'o_wready' , width: 1
-        input  :wdata  , name: 'i_wdata'  , width: data_width
-        input  :wstrb  , name: 'i_wstrb'  , width: byte_width
-        output :bvalid , name: 'o_bvalid' , width: 1
-        input  :bready , name: 'i_bready' , width: 1
-        output :bresp  , name: 'o_bresp'  , width: 2
-        input  :arvalid, name: 'i_arvalid', width: 1
-        output :arready, name: 'o_arready', width: 1
-        input  :araddr , name: 'i_araddr' , width: address_width
-        input  :arprot , name: 'i_arprot' , width: 3
-        output :rvalid , name: 'o_rvalid' , width: 1
-        input  :rready , name: 'i_rready' , width: 1
-        output :rdata  , name: 'o_rdata'  , width: data_width
-        output :rresp  , name: 'o_rresp'  , width: 2
-      end
+      parameter :register_block, :access_priority,
+                name:    'ACCESS_PRIORITY',
+                type:    :'rggen_rtl_pkg::rggen_direction',
+                default: :'rggen_rtl_pkg::RGGEN_WRITE'
+      interface_port :register_block, :axi4lite_if,
+                     type:    :rggen_axi4lite_if,
+                     modport: :slave
     end
 
-    generate_code_from_template :module_item
+    generate_code_from_template :register_block
   end
 end

data/lib/rggen/builtins/register_block/irq_controller.rb

@@ -3,12 +3,12 @@ simple_item :register_block, :irq_controller do
     available? { total_interrupts > 0 }
 
     build do
-      output :irq, width: 1               , name: 'o_irq'
-      logic  :ier, width: total_interrupts
-      logic  :isr, width: total_interrupts
+      output :register_block, :irq, width: 1               , name: 'o_irq'
+      logic  :register_block, :ier, width: total_interrupts
+      logic  :register_block, :isr, width: total_interrupts
     end
 
-    generate_code :module_item do |code|
+    generate_code :register_block do |code|
       code << assign_ier << nl
       code << assign_isr << nl
       code << process_template

data/lib/rggen/builtins/register_block/rtl_top.erb

@@ -0,0 +1,7 @@
+`define rggen_connect_bit_field_if(RIF, FIF, MSB, LSB) \
+  assign  FIF.read_access         = RIF.read_access; \
+  assign  FIF.write_access        = RIF.write_access; \
+  assign  FIF.write_data          = RIF.write_data[MSB:LSB]; \
+  assign  FIF.write_mask          = RIF.write_mask[MSB:LSB]; \
+  assign  RIF.value[MSB:LSB]      = FIF.value; \
+  assign  RIF.read_data[MSB:LSB]  = FIF.read_data;

data/lib/rggen/builtins/register_block/rtl_top.rb

@@ -0,0 +1,28 @@
+define_simple_item :register_block, :rtl_top do
+  rtl do
+    write_file '<%= register_block.name %>.sv' do |f|
+      f.body { source_file_body }
+    end
+
+    def source_file_body
+      module_definition register_block.name do |m|
+        m.parameters register_block.parameter_declarations(:register_block)
+        m.ports      register_block.port_declarations(:register_block)
+        m.signals    register_block.signal_declarations(:register_block)
+        m.body { |code| module_body(code) }
+      end
+    end
+
+    def module_body(code)
+      register_block.generate_code(:register_block, :top_down, code)
+    end
+
+    generate_pre_code :register_block do
+      process_template
+    end
+
+    generate_post_code :register_block do
+      :'`undef rggen_connect_bit_field_if'
+    end
+  end
+end