rggen 0.5.1 → 0.6.0

data/sample/sample_0_ral_pkg.sv

@@ -122,19 +122,19 @@ package sample_0_ral_pkg;
       super.new(name);
     endfunction
     function void create_sub_models();
-      `rggen_ral_create_reg_model(register_0, "register_0", '{}, 8'h00, "RW", 0, "")
-      `rggen_ral_create_reg_model(register_1, "register_1", '{}, 8'h04, "RW", 0, "")
-      `rggen_ral_create_reg_model(register_2, "register_2", '{}, 8'h08, "RW", 0, "")
-      `rggen_ral_create_reg_model(register_3, "register_3", '{}, 8'h0c, "RO", 0, "")
+      `rggen_ral_create_reg_model(register_0, "register_0", '{}, 8'h00, "RW", 0, "g_register_0")
+      `rggen_ral_create_reg_model(register_1, "register_1", '{}, 8'h04, "RW", 0, "g_register_1")
+      `rggen_ral_create_reg_model(register_2, "register_2", '{}, 8'h08, "RW", 0, "g_register_2")
+      `rggen_ral_create_reg_model(register_3, "register_3", '{}, 8'h0c, "RO", 0, "g_register_3")
       foreach (register_4[i]) begin
         `rggen_ral_create_reg_model(register_4[i], $sformatf("register_4[%0d]", i), '{i}, 8'h10 + 4 * i, "RW", 0, $sformatf("g_register_4.g[%0d]", i))
       end
       foreach (register_5[i, j]) begin
         `rggen_ral_create_reg_model(register_5[i][j], $sformatf("register_5[%0d][%0d]", i, j), '{i, j}, 8'h20, "RW", 1, $sformatf("g_register_5.g[%0d].g[%0d]", i, j))
       end
-      `rggen_ral_create_reg_model(register_6, "register_6", '{}, 8'h24, "RW", 0, "")
-      `rggen_ral_create_reg_model(register_7, "register_7", '{}, 8'h28, "RW", 0, "")
-      `rggen_ral_create_reg_model(register_8, "register_8", '{}, 8'h2c, "RW", 0, "")
+      `rggen_ral_create_reg_model(register_6, "register_6", '{}, 8'h24, "RW", 0, "g_register_6")
+      `rggen_ral_create_reg_model(register_7, "register_7", '{}, 8'h28, "RW", 0, "g_register_7")
+      `rggen_ral_create_reg_model(register_8, "register_8", '{}, 8'h2c, "RW", 0, "g_register_8")
       `rggen_ral_create_block_model(register_9, "register_9", 8'h80)
     endfunction
     function uvm_reg_map create_default_map();

data/sample/sample_1.sv

@@ -1,176 +1,118 @@
 module sample_1 (
   input clk,
   input rst_n,
-  input [15:0] i_paddr,
-  input [2:0] i_pprot,
-  input i_psel,
-  input i_penable,
-  input i_pwrite,
-  input [31:0] i_pwdata,
-  input [3:0] i_pstrb,
-  output o_pready,
-  output [31:0] o_prdata,
-  output o_pslverr,
+  rggen_apb_if.slave apb_if,
   output [15:0] o_bit_field_0_0,
   input [15:0] i_bit_field_0_1,
   output [31:0] o_bit_field_1_0,
   input i_bit_field_2_0,
   output o_bit_field_2_1
 );
-  logic command_valid;
-  logic write;
-  logic read;
-  logic [6:0] address;
-  logic [3:0] strobe;
-  logic [31:0] write_data;
-  logic [31:0] write_mask;
-  logic response_ready;
-  logic [31:0] read_data;
-  logic [1:0] status;
-  logic [2:0] register_select;
-  logic [31:0] register_read_data[3];
-  logic [15:0] bit_field_0_0_value;
-  logic [15:0] bit_field_0_1_value;
-  logic [31:0] bit_field_1_0_value;
-  logic bit_field_2_0_value;
-  logic bit_field_2_1_value;
+  rggen_register_if #(7, 32) register_if[3]();
+  `define rggen_connect_bit_field_if(RIF, FIF, MSB, LSB) \
+    assign  FIF.read_access         = RIF.read_access; \
+    assign  FIF.write_access        = RIF.write_access; \
+    assign  FIF.write_data          = RIF.write_data[MSB:LSB]; \
+    assign  FIF.write_mask          = RIF.write_mask[MSB:LSB]; \
+    assign  RIF.value[MSB:LSB]      = FIF.value; \
+    assign  RIF.read_data[MSB:LSB]  = FIF.read_data;
   rggen_host_if_apb #(
+    .LOCAL_ADDRESS_WIDTH  (7),
     .DATA_WIDTH           (32),
-    .HOST_ADDRESS_WIDTH   (16),
-    .LOCAL_ADDRESS_WIDTH  (7)
+    .TOTAL_REGISTERS      (3)
   ) u_host_if (
-    .clk              (clk),
-    .rst_n            (rst_n),
-    .i_paddr          (i_paddr),
-    .i_pprot          (i_pprot),
-    .i_psel           (i_psel),
-    .i_penable        (i_penable),
-    .i_pwrite         (i_pwrite),
-    .i_pwdata         (i_pwdata),
-    .i_pstrb          (i_pstrb),
-    .o_pready         (o_pready),
-    .o_prdata         (o_prdata),
-    .o_pslverr        (o_pslverr),
-    .o_command_valid  (command_valid),
-    .o_write          (write),
-    .o_read           (read),
-    .o_address        (address),
-    .o_strobe         (strobe),
-    .o_write_data     (write_data),
-    .o_write_mask     (write_mask),
-    .i_response_ready (response_ready),
-    .i_read_data      (read_data),
-    .i_status         (status)
-  );
-  rggen_response_mux #(
-    .DATA_WIDTH               (32),
-    .TOTAL_REGISTERS          (3),
-    .TOTAL_EXTERNAL_REGISTERS (0)
-  ) u_response_mux (
-    .clk                        (clk),
-    .rst_n                      (rst_n),
-    .i_command_valid            (command_valid),
-    .i_read                     (read),
-    .o_response_ready           (response_ready),
-    .o_read_data                (read_data),
-    .o_status                   (status),
-    .i_register_select          (register_select),
-    .i_register_read_data       (register_read_data),
-    .i_external_register_select (1'b0),
-    .i_external_register_ready  (1'b0),
-    .i_external_register_status ('{2'b00})
-  );
-  rggen_address_decoder #(
-    .ADDRESS_WIDTH        (5),
-    .START_ADDRESS        (5'h00),
-    .END_ADDRESS          (5'h00),
-    .INDIRECT_REGISTER    (0),
-    .INDIRECT_INDEX_WIDTH (1),
-    .INDIRECT_INDEX_VALUE (1'h0)
-  ) u_register_0_address_decoder (
-    .i_address        (address[6:2]),
-    .i_indirect_index (1'h0),
-    .o_select         (register_select[0])
-  );
-  assign register_read_data[0] = {bit_field_0_0_value, bit_field_0_1_value};
-  assign o_bit_field_0_0 = bit_field_0_0_value;
-  rggen_bit_field_rw #(
-    .WIDTH          (16),
-    .INITIAL_VALUE  (16'h0000)
-  ) u_bit_field_0_0 (
-    .clk              (clk),
-    .rst_n            (rst_n),
-    .i_command_valid  (command_valid),
-    .i_select         (register_select[0]),
-    .i_write          (write),
-    .i_write_data     (write_data[31:16]),
-    .i_write_mask     (write_mask[31:16]),
-    .o_value          (bit_field_0_0_value)
-  );
-  rggen_bit_field_ro #(
-    .WIDTH  (16)
-  ) u_bit_field_0_1 (
-    .i_value  (i_bit_field_0_1),
-    .o_value  (bit_field_0_1_value)
-  );
-  rggen_address_decoder #(
-    .ADDRESS_WIDTH        (5),
-    .START_ADDRESS        (5'h01),
-    .END_ADDRESS          (5'h01),
-    .INDIRECT_REGISTER    (0),
-    .INDIRECT_INDEX_WIDTH (1),
-    .INDIRECT_INDEX_VALUE (1'h0)
-  ) u_register_1_address_decoder (
-    .i_address        (address[6:2]),
-    .i_indirect_index (1'h0),
-    .o_select         (register_select[1])
-  );
-  assign register_read_data[1] = {bit_field_1_0_value};
-  assign o_bit_field_1_0 = bit_field_1_0_value;
-  rggen_bit_field_rw #(
-    .WIDTH          (32),
-    .INITIAL_VALUE  (32'h00000000)
-  ) u_bit_field_1_0 (
-    .clk              (clk),
-    .rst_n            (rst_n),
-    .i_command_valid  (command_valid),
-    .i_select         (register_select[1]),
-    .i_write          (write),
-    .i_write_data     (write_data[31:0]),
-    .i_write_mask     (write_mask[31:0]),
-    .o_value          (bit_field_1_0_value)
-  );
-  rggen_address_decoder #(
-    .ADDRESS_WIDTH        (5),
-    .START_ADDRESS        (5'h02),
-    .END_ADDRESS          (5'h02),
-    .INDIRECT_REGISTER    (0),
-    .INDIRECT_INDEX_WIDTH (1),
-    .INDIRECT_INDEX_VALUE (1'h0)
-  ) u_register_2_address_decoder (
-    .i_address        (address[6:2]),
-    .i_indirect_index (1'h0),
-    .o_select         (register_select[2])
-  );
-  assign register_read_data[2] = {15'h0000, bit_field_2_0_value, 15'h0000, bit_field_2_1_value};
-  rggen_bit_field_ro #(
-    .WIDTH  (1)
-  ) u_bit_field_2_0 (
-    .i_value  (i_bit_field_2_0),
-    .o_value  (bit_field_2_0_value)
-  );
-  assign o_bit_field_2_1 = bit_field_2_1_value;
-  rggen_bit_field_rw #(
-    .WIDTH          (1),
-    .INITIAL_VALUE  (1'h0)
-  ) u_bit_field_2_1 (
-    .clk              (clk),
-    .rst_n            (rst_n),
-    .i_command_valid  (command_valid),
-    .i_select         (register_select[2]),
-    .i_write          (write),
-    .i_write_data     (write_data[0]),
-    .i_write_mask     (write_mask[0]),
-    .o_value          (bit_field_2_1_value)
+    .clk          (clk),
+    .rst_n        (rst_n),
+    .apb_if       (apb_if),
+    .register_if  (register_if)
   );
+  generate if (1) begin : g_register_0
+    rggen_bit_field_if #(32) bit_field_if();
+    rggen_bit_field_if #(16) bit_field_0_0_if();
+    rggen_bit_field_if #(16) bit_field_0_1_if();
+    rggen_default_register #(
+      .ADDRESS_WIDTH  (7),
+      .START_ADDRESS  (7'h00),
+      .END_ADDRESS    (7'h03),
+      .DATA_WIDTH     (32),
+      .VALID_BITS     (32'hffffffff)
+    ) u_register_0 (
+      .register_if  (register_if[0]),
+      .bit_field_if (bit_field_if)
+    );
+    `rggen_connect_bit_field_if(bit_field_if, bit_field_0_0_if, 31, 16)
+    rggen_bit_field_rw #(
+      .WIDTH          (16),
+      .INITIAL_VALUE  (16'h0000)
+    ) u_bit_field_0_0 (
+      .clk          (clk),
+      .rst_n        (rst_n),
+      .bit_field_if (bit_field_0_0_if),
+      .o_value      (o_bit_field_0_0)
+    );
+    `rggen_connect_bit_field_if(bit_field_if, bit_field_0_1_if, 15, 0)
+    rggen_bit_field_ro #(
+      .WIDTH  (16)
+    ) u_bit_field_0_1 (
+      .bit_field_if (bit_field_0_1_if),
+      .i_value      (i_bit_field_0_1)
+    );
+  end endgenerate
+  generate if (1) begin : g_register_1
+    rggen_bit_field_if #(32) bit_field_if();
+    rggen_bit_field_if #(32) bit_field_1_0_if();
+    rggen_default_register #(
+      .ADDRESS_WIDTH  (7),
+      .START_ADDRESS  (7'h04),
+      .END_ADDRESS    (7'h07),
+      .DATA_WIDTH     (32),
+      .VALID_BITS     (32'hffffffff)
+    ) u_register_1 (
+      .register_if  (register_if[1]),
+      .bit_field_if (bit_field_if)
+    );
+    `rggen_connect_bit_field_if(bit_field_if, bit_field_1_0_if, 31, 0)
+    rggen_bit_field_rw #(
+      .WIDTH          (32),
+      .INITIAL_VALUE  (32'h00000000)
+    ) u_bit_field_1_0 (
+      .clk          (clk),
+      .rst_n        (rst_n),
+      .bit_field_if (bit_field_1_0_if),
+      .o_value      (o_bit_field_1_0)
+    );
+  end endgenerate
+  generate if (1) begin : g_register_2
+    rggen_bit_field_if #(32) bit_field_if();
+    rggen_bit_field_if #(1) bit_field_2_0_if();
+    rggen_bit_field_if #(1) bit_field_2_1_if();
+    rggen_default_register #(
+      .ADDRESS_WIDTH  (7),
+      .START_ADDRESS  (7'h08),
+      .END_ADDRESS    (7'h0b),
+      .DATA_WIDTH     (32),
+      .VALID_BITS     (32'h00010001)
+    ) u_register_2 (
+      .register_if  (register_if[2]),
+      .bit_field_if (bit_field_if)
+    );
+    `rggen_connect_bit_field_if(bit_field_if, bit_field_2_0_if, 16, 16)
+    rggen_bit_field_ro #(
+      .WIDTH  (1)
+    ) u_bit_field_2_0 (
+      .bit_field_if (bit_field_2_0_if),
+      .i_value      (i_bit_field_2_0)
+    );
+    `rggen_connect_bit_field_if(bit_field_if, bit_field_2_1_if, 0, 0)
+    rggen_bit_field_rw #(
+      .WIDTH          (1),
+      .INITIAL_VALUE  (1'h0)
+    ) u_bit_field_2_1 (
+      .clk          (clk),
+      .rst_n        (rst_n),
+      .bit_field_if (bit_field_2_1_if),
+      .o_value      (o_bit_field_2_1)
+    );
+  end endgenerate
+  `undef rggen_connect_bit_field_if
 endmodule

data/sample/sample_1_ral_pkg.sv

@@ -44,9 +44,9 @@ package sample_1_ral_pkg;
       super.new(name);
     endfunction
     function void create_sub_models();
-      `rggen_ral_create_reg_model(register_0, "register_0", '{}, 7'h00, "RW", 0, "")
-      `rggen_ral_create_reg_model(register_1, "register_1", '{}, 7'h04, "RW", 0, "")
-      `rggen_ral_create_reg_model(register_2, "register_2", '{}, 7'h08, "RW", 0, "")
+      `rggen_ral_create_reg_model(register_0, "register_0", '{}, 7'h00, "RW", 0, "g_register_0")
+      `rggen_ral_create_reg_model(register_1, "register_1", '{}, 7'h04, "RW", 0, "g_register_1")
+      `rggen_ral_create_reg_model(register_2, "register_2", '{}, 7'h08, "RW", 0, "g_register_2")
     endfunction
     function uvm_reg_map create_default_map();
       return create_map("default_map", 0, 4, UVM_LITTLE_ENDIAN, 1);

data/sample/sample_setup.rb

@@ -14,9 +14,9 @@ enable :register      , [:offset_address, :name, :array, :type, :uniquness_valid
 enable :register      , :type, [:indirect, :external]
 enable :bit_field     , [:bit_assignment, :name, :type, :initial_value, :reference]
 enable :bit_field     , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :rwl, :rwe, :foo, :reserved]
-enable :register_block, [:top_module, :clock_reset, :host_if, :response_mux, :irq_controller]
+enable :register_block, [:top_module, :clock_reset, :host_if, :irq_controller]
 enable :register_block, :host_if, [:apb, :bar]
-enable :register      , [:address_decoder, :read_data, :bus_exporter]
+enable :register      , :rtl_top
 enable :register_block, [:ral_package, :block_model, :constructor, :sub_model_creator, :default_map_creator]
 enable :register      , [:reg_model, :constructor, :field_model_creator, :indirect_index_configurator, :sub_block_model]
 enable :bit_field     , :field_model

data/setup/default.rb

@@ -4,10 +4,10 @@ enable :register      , [:offset_address, :name, :array, :type, :uniquness_valid
 enable :register      , :type, [:indirect, :external]
 enable :bit_field     , [:bit_assignment, :name, :type, :initial_value, :reference]
 enable :bit_field     , :type, [:rw, :ro, :w0c, :w1c, :w0s, :w1s, :rwl, :rwe, :reserved]
-enable :register_block, [:top_module, :clock_reset, :host_if, :response_mux, :irq_controller]
+enable :register_block, [:rtl_top, :clock_reset, :host_if, :irq_controller]
 enable :register_block, :host_if, [:apb, :axi4lite]
-enable :register      , [:address_decoder, :read_data, :bus_exporter]
+enable :register      , :rtl_top
 enable :register_block, [:ral_package, :block_model, :constructor, :sub_model_creator, :default_map_creator]
 enable :register      , [:reg_model, :constructor, :field_model_creator, :indirect_index_configurator, :sub_block_model]
 enable :bit_field     , :field_model
-enable :register_block, [:c_header_file, :address_struct]
+enable :register_block, [:c_header_file, :address_struct]

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen
 version: !ruby/object:Gem::Version
-  version: 0.5.1
+  version: 0.6.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2017-04-26 00:00:00.000000000 Z
+date: 2017-05-25 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: baby_erubis
@@ -123,7 +123,8 @@ files:
 - LICENSE.txt
 - README.md
 - bin/rggen
-- c/rggen.h
+- c_header/LICENSE
+- c_header/rggen.h
 - lib/rggen.rb
 - lib/rggen/base/component.rb
 - lib/rggen/base/component_factory.rb
@@ -167,21 +168,20 @@ files:
 - lib/rggen/builtins/loaders/register_map/csv_loader.rb
 - lib/rggen/builtins/loaders/register_map/xls_loader.rb
 - lib/rggen/builtins/loaders/register_map/xlsx_ods_loader.rb
-- lib/rggen/builtins/register/address_decoder.erb
-- lib/rggen/builtins/register/address_decoder.rb
 - lib/rggen/builtins/register/array.rb
-- lib/rggen/builtins/register/bus_exporter.erb
-- lib/rggen/builtins/register/bus_exporter.rb
 - lib/rggen/builtins/register/constructor.rb
 - lib/rggen/builtins/register/field_model_creator.rb
 - lib/rggen/builtins/register/indirect_index_configurator.rb
 - lib/rggen/builtins/register/name.rb
 - lib/rggen/builtins/register/offset_address.rb
-- lib/rggen/builtins/register/read_data.rb
 - lib/rggen/builtins/register/reg_model.rb
+- lib/rggen/builtins/register/rtl_top.rb
 - lib/rggen/builtins/register/sub_block_model.rb
 - lib/rggen/builtins/register/type.rb
+- lib/rggen/builtins/register/types/default.erb
+- lib/rggen/builtins/register/types/external.erb
 - lib/rggen/builtins/register/types/external.rb
+- lib/rggen/builtins/register/types/indirect.erb
 - lib/rggen/builtins/register/types/indirect.rb
 - lib/rggen/builtins/register/uniqueness_validator.rb
 - lib/rggen/builtins/register_block/address_struct.rb
@@ -201,10 +201,9 @@ files:
 - lib/rggen/builtins/register_block/irq_controller.rb
 - lib/rggen/builtins/register_block/name.rb
 - lib/rggen/builtins/register_block/ral_package.rb
-- lib/rggen/builtins/register_block/response_mux.erb
-- lib/rggen/builtins/register_block/response_mux.rb
+- lib/rggen/builtins/register_block/rtl_top.erb
+- lib/rggen/builtins/register_block/rtl_top.rb
 - lib/rggen/builtins/register_block/sub_model_creator.rb
-- lib/rggen/builtins/register_block/top_module.rb
 - lib/rggen/commands.rb
 - lib/rggen/core_components.rb
 - lib/rggen/core_components/c_header/item.rb
@@ -245,6 +244,9 @@ files:
 - lib/rggen/core_components/verilog_utility/class_definition.rb
 - lib/rggen/core_components/verilog_utility/declaration.rb
 - lib/rggen/core_components/verilog_utility/identifier.rb
+- lib/rggen/core_components/verilog_utility/interface_instantiation.rb
+- lib/rggen/core_components/verilog_utility/interface_port_declaration.rb
+- lib/rggen/core_components/verilog_utility/local_scope.rb
 - lib/rggen/core_components/verilog_utility/module_definition.rb
 - lib/rggen/core_components/verilog_utility/package_definition.rb
 - lib/rggen/core_components/verilog_utility/source_file.rb
@@ -272,6 +274,7 @@ files:
 - lib/rggen/output_base/template_engine.rb
 - lib/rggen/rggen_home.rb
 - lib/rggen/version.rb
+- ral/LICENSE
 - ral/compile.f
 - ral/rggen_ral_block.svh
 - ral/rggen_ral_field.svh
@@ -281,19 +284,28 @@ files:
 - ral/rggen_ral_map.svh
 - ral/rggen_ral_pkg.sv
 - ral/rggen_ral_reg.svh
-- rtl/bit_field/rggen_bit_field_common.svh
-- rtl/bit_field/rggen_bit_field_ro.sv
-- rtl/bit_field/rggen_bit_field_rw.sv
-- rtl/bit_field/rggen_bit_field_rwl_rwe.sv
-- rtl/bit_field/rggen_bit_field_w01s_w01c.sv
+- rtl/LICENSE
 - rtl/compile.f
-- rtl/register/rggen_address_decoder.sv
-- rtl/register/rggen_bus_exporter.sv
-- rtl/register_block/rggen_host_if_apb.sv
-- rtl/register_block/rggen_host_if_axi4lite.sv
-- rtl/register_block/rggen_host_if_common.svh
-- rtl/register_block/rggen_irq_controller.sv
-- rtl/register_block/rggen_response_mux.sv
+- rtl/rggen_address_decoder.sv
+- rtl/rggen_apb_if.sv
+- rtl/rggen_axi4lite_if.sv
+- rtl/rggen_bit_field_if.sv
+- rtl/rggen_bit_field_ro.sv
+- rtl/rggen_bit_field_rw.sv
+- rtl/rggen_bit_field_rwl_rwe.sv
+- rtl/rggen_bit_field_w01s_w01c.sv
+- rtl/rggen_bus_if.sv
+- rtl/rggen_bus_splitter.sv
+- rtl/rggen_default_register.sv
+- rtl/rggen_external_register.sv
+- rtl/rggen_host_if_apb.sv
+- rtl/rggen_host_if_axi4lite.sv
+- rtl/rggen_indirect_register.sv
+- rtl/rggen_irq_controller.sv
+- rtl/rggen_register_base.sv
+- rtl/rggen_register_if.sv
+- rtl/rggen_rtl_pkg.sv
+- sample/LICENSE
 - sample/sample.csv
 - sample/sample.json
 - sample/sample.xls