rggen 0.5.1 → 0.6.0

data/rtl/rggen_bus_if.sv

@@ -0,0 +1,43 @@
+interface rggen_bus_if #(
+  parameter int ADDRESS_WIDTH = 16,
+  parameter int DATA_WIDTH    = 32
+)();
+  import  rggen_rtl_pkg::*;
+
+  logic                     request;
+  logic [ADDRESS_WIDTH-1:0] address;
+  rggen_direction           direction;
+  logic [DATA_WIDTH-1:0]    write_data;
+  logic [DATA_WIDTH/8-1:0]  write_strobe;
+  logic                     done;
+  logic                     read_done;
+  logic                     write_done;
+  logic [DATA_WIDTH-1:0]    read_data;
+  rggen_status              status;
+
+  modport master (
+    output  request,
+    output  address,
+    output  direction,
+    output  write_data,
+    output  write_strobe,
+    input   done,
+    input   read_done,
+    input   write_done,
+    input   read_data,
+    input   status
+  );
+
+  modport slave (
+    input   request,
+    input   address,
+    input   direction,
+    input   write_data,
+    input   write_strobe,
+    output  done,
+    output  read_done,
+    output  write_done,
+    output  read_data,
+    output  status
+  );
+endinterface

data/rtl/rggen_bus_splitter.sv

@@ -0,0 +1,87 @@
+module rggen_bus_splitter #(
+  parameter int DATA_WIDTH      = 32,
+  parameter int TOTAL_REGISTERS = 1
+)(
+  input                     clk,
+  input                     rst_n,
+  rggen_bus_if.slave        bus_if,
+  rggen_register_if.master  register_if[TOTAL_REGISTERS]
+);
+  import  rggen_rtl_pkg::*;
+
+  localparam  INDEX_WIDTH   = $clog2(TOTAL_REGISTERS+1);
+
+  typedef struct packed {
+    logic [DATA_WIDTH-1:0]  read_data;
+    rggen_status            status;
+  } s_response;
+
+  logic [TOTAL_REGISTERS:0]   select;
+  logic [TOTAL_REGISTERS:0]   ready;
+  s_response                  response[TOTAL_REGISTERS+1];
+  logic                       response_ready;
+  logic                       no_register_selected;
+  logic                       done;
+  logic                       read_done;
+  logic                       write_done;
+  s_response                  selected_response;
+  genvar                      g_i;
+
+  assign  bus_if.done       = done;
+  assign  bus_if.read_done  = read_done;
+  assign  bus_if.write_done = write_done;
+  assign  bus_if.read_data  = selected_response.read_data;
+  assign  bus_if.status     = selected_response.status;
+
+  generate for (g_i = 0;g_i < TOTAL_REGISTERS;++g_i) begin : g
+    assign  register_if[g_i].request      = bus_if.request;
+    assign  register_if[g_i].address      = bus_if.address;
+    assign  register_if[g_i].direction    = bus_if.direction;
+    assign  register_if[g_i].write_data   = bus_if.write_data;
+    assign  register_if[g_i].write_strobe = bus_if.write_strobe;
+    assign  select[g_i]                   = register_if[g_i].select;
+    assign  ready[g_i]                    = register_if[g_i].ready;
+    assign  response[g_i].read_data       = register_if[g_i].read_data;
+    assign  response[g_i].status          = register_if[g_i].status;
+  end endgenerate
+
+  //  dummy response
+  assign  no_register_selected      = ~|select[TOTAL_REGISTERS-1:0];
+  assign  select[TOTAL_REGISTERS]   = no_register_selected;
+  assign  ready[TOTAL_REGISTERS]    = no_register_selected;
+  assign  response[TOTAL_REGISTERS] = '{read_data: '0, status: RGGEN_SLAVE_ERROR};
+
+  assign  response_ready  = |ready;
+  always_ff @(posedge clk, negedge rst_n) begin
+    if (!rst_n) begin
+      done              <= '0;
+      read_done         <= '0;
+      write_done        <= '0;
+      selected_response <= '{read_data: '0, status: RGGEN_OKAY};
+    end
+    else if (bus_if.request && response_ready && (!done)) begin
+      done              <= '1;
+      write_done        <= (bus_if.direction == RGGEN_WRITE) ? '1 : '0;
+      read_done         <= (bus_if.direction == RGGEN_READ ) ? '1 : '0;
+      selected_response <= response[calc_index()];
+    end
+    else begin
+      done              <= '0;
+      read_done         <= '0;
+      write_done        <= '0;
+      selected_response <= '{read_data: '0, status: RGGEN_OKAY};
+    end
+  end
+
+  function automatic logic [INDEX_WIDTH-1:0] calc_index();
+    logic [INDEX_WIDTH-1:0] index;
+    for (int i = 0;i < INDEX_WIDTH;++i) begin
+      logic [TOTAL_REGISTERS:0] temp;
+      for (int j = 0;j <= TOTAL_REGISTERS;++j) begin
+        temp[j] = j[i] & select[j];
+      end
+      index[i]  = |temp;
+    end
+    return index;
+  endfunction
+endmodule

data/rtl/rggen_default_register.sv

@@ -0,0 +1,15 @@
+module rggen_default_register #(
+  parameter int                     ADDRESS_WIDTH = 16,
+  parameter bit [ADDRESS_WIDTH-1:0] START_ADDRESS = '0,
+  parameter bit [ADDRESS_WIDTH-1:0] END_ADDRESS   = '0,
+  parameter int                     DATA_WIDTH    = 32,
+  parameter bit [DATA_WIDTH-1:0]    VALID_BITS    = '0
+)(
+  rggen_register_if.slave   register_if,
+  rggen_bit_field_if.master bit_field_if
+);
+  rggen_register_base #(
+    ADDRESS_WIDTH, START_ADDRESS, END_ADDRESS,
+    DATA_WIDTH, VALID_BITS
+  ) u_register_base (register_if, bit_field_if, 1'b1);
+endmodule

data/rtl/rggen_external_register.sv

@@ -0,0 +1,83 @@
+module rggen_external_register #(
+  parameter int                     ADDRESS_WIDTH = 16,
+  parameter bit [ADDRESS_WIDTH-1:0] START_ADDRESS = '0,
+  parameter bit [ADDRESS_WIDTH-1:0] END_ADDRESS   = '0,
+  parameter int                     DATA_WIDTH    = 32
+)(
+  input                     clk,
+  input                     rst_n,
+  rggen_register_if.slave   register_if,
+  rggen_bus_if.master       bus_if
+);
+  import  rggen_rtl_pkg::*;
+
+  localparam  int EXTERNAL_SIZE           = END_ADDRESS - START_ADDRESS + 1;
+  localparam  int EXTERNAL_ADDRESS_WIDTH  = $clog2(EXTERNAL_SIZE);
+
+  logic                               address_match;
+  logic                               request;
+  logic [EXTERNAL_ADDRESS_WIDTH-1:0]  address;
+  rggen_direction                     direction;
+  logic [DATA_WIDTH-1:0]              write_data;
+  logic [DATA_WIDTH/8-1:0]            write_strobe;
+  logic                               access_done;
+
+  rggen_address_decoder #(
+    ADDRESS_WIDTH, START_ADDRESS, END_ADDRESS, DATA_WIDTH
+  ) u_address_decoder (register_if.address, address_match);
+
+  always_ff @(posedge clk, negedge rst_n) begin
+    if (!rst_n) begin
+      access_done <= '0;
+    end
+    else if (request && bus_if.done) begin
+      access_done <= '1;
+    end
+    else begin
+      access_done <= '0;
+    end
+  end
+
+  //  Local -> External
+  assign  bus_if.request      = request;
+  assign  bus_if.address      = address;
+  assign  bus_if.direction    = direction;
+  assign  bus_if.write_data   = write_data;
+  assign  bus_if.write_strobe = write_strobe;
+  always_ff @(posedge clk, negedge rst_n) begin
+    if (!rst_n) begin
+      request       <= '0;
+      address       <= '0;
+      direction     <= RGGEN_READ;
+      write_data    <= '0;
+      write_strobe  <= '0;
+    end
+    else if (request && bus_if.done) begin
+      request       <= '0;
+      address       <= '0;
+      direction     <= RGGEN_READ;
+      write_data    <= '0;
+      write_strobe  <= '0;
+    end
+    else if (register_if.request && address_match && (!request) && (!access_done)) begin
+      request       <= '1;
+      address       <= calc_address(register_if.address);
+      direction     <= register_if.direction;
+      write_data    <= register_if.write_data;
+      write_strobe  <= register_if.write_strobe;
+    end
+  end
+
+  function automatic logic [EXTERNAL_ADDRESS_WIDTH-1:0] calc_address(input [ADDRESS_WIDTH-1:0] address);
+    logic [ADDRESS_WIDTH-1:0] external_address;
+    external_address  = address - START_ADDRESS;
+    return external_address[EXTERNAL_ADDRESS_WIDTH-1:0];
+  endfunction
+
+  //  External -> Local
+  assign  register_if.select    = address_match;
+  assign  register_if.ready     = bus_if.done;
+  assign  register_if.value     = bus_if.read_data;
+  assign  register_if.read_data = bus_if.read_data;
+  assign  register_if.status    = bus_if.status;
+endmodule

data/rtl/rggen_host_if_apb.sv

@@ -0,0 +1,29 @@
+module rggen_host_if_apb #(
+  parameter int LOCAL_ADDRESS_WIDTH = 16,
+  parameter int DATA_WIDTH          = 32,
+  parameter int TOTAL_REGISTERS     = 1
+)(
+  input                     clk,
+  input                     rst_n,
+  rggen_apb_if.slave        apb_if,
+  rggen_register_if.master  register_if[TOTAL_REGISTERS]
+);
+  import  rggen_rtl_pkg::*;
+
+  rggen_bus_if #(LOCAL_ADDRESS_WIDTH, DATA_WIDTH) bus_if();
+
+  assign  apb_if.pready       = bus_if.done;
+  assign  apb_if.prdata       = bus_if.read_data;
+  assign  apb_if.pslverr      = bus_if.status[1];
+  assign  bus_if.request      = apb_if.psel;
+  assign  bus_if.address      = apb_if.paddr[LOCAL_ADDRESS_WIDTH-1:0];
+  assign  bus_if.direction    = rggen_direction'(apb_if.pwrite);
+  assign  bus_if.write_data   = apb_if.pwdata;
+  assign  bus_if.write_strobe = apb_if.pstrb;
+
+  rggen_bus_splitter #(
+    DATA_WIDTH, TOTAL_REGISTERS
+  ) u_bus_splitter (
+    clk, rst_n, bus_if, register_if
+  );
+endmodule

data/rtl/rggen_host_if_axi4lite.sv

@@ -0,0 +1,14 @@
+module rggen_host_if_axi4lite
+  import  rggen_rtl_pkg::*;
+#(
+  parameter int             LOCAL_ADDRESS_WIDTH = 16,
+  parameter int             DATA_WIDTH          = 32,
+  parameter rggen_direction ACCESS_PRIORITY     = RGGEN_WRITE
+)(
+  input                   clk,
+  input                   rst_n,
+  rggen_axi4lite_if.slave axi4lite_if,
+  rggen_bus_if.master     bus_if
+);
+  //  TODO
+endmodule

data/rtl/rggen_indirect_register.sv

@@ -0,0 +1,21 @@
+module rggen_indirect_register #(
+  parameter int                     ADDRESS_WIDTH = 16,
+  parameter bit [ADDRESS_WIDTH-1:0] START_ADDRESS = '0,
+  parameter bit [ADDRESS_WIDTH-1:0] END_ADDRESS   = '0,
+  parameter int                     INDEX_WIDTH   = 1,
+  parameter bit [INDEX_WIDTH-1:0]   INDEX_VALUE   = '0,
+  parameter int                     DATA_WIDTH    = 32,
+  parameter bit [DATA_WIDTH-1:0]    VALID_BITS    = '0
+)(
+  rggen_register_if.slave   register_if,
+  rggen_bit_field_if.master bit_field_if,
+  input [INDEX_WIDTH-1:0]   i_index
+);
+  logic index_match;
+
+  assign  index_match = (i_index == INDEX_VALUE) ? 1'b1 : 1'b0;
+  rggen_register_base #(
+    ADDRESS_WIDTH, START_ADDRESS, END_ADDRESS,
+    DATA_WIDTH, VALID_BITS
+  ) u_register_base (register_if, bit_field_if, index_match);
+endmodule

data/rtl/rggen_register_base.sv

@@ -0,0 +1,57 @@
+module rggen_register_base #(
+  parameter int                     ADDRESS_WIDTH = 16,
+  parameter bit [ADDRESS_WIDTH-1:0] START_ADDRESS = '0,
+  parameter bit [ADDRESS_WIDTH-1:0] END_ADDRESS   = '0,
+  parameter int                     DATA_WIDTH    = 32,
+  parameter bit [DATA_WIDTH-1:0]    VALID_BITS    = '0
+)(
+  rggen_register_if.slave   register_if,
+  rggen_bit_field_if.master bit_field_if,
+  input logic               i_additional_match
+);
+  import  rggen_rtl_pkg::*;
+
+  logic   address_match;
+  logic   select;
+  genvar  g_i;
+
+  //  Decode Address
+  assign  select  = (address_match && i_additional_match) ? 1'b1 : 1'b0;
+  rggen_address_decoder #(
+    ADDRESS_WIDTH, START_ADDRESS, END_ADDRESS, DATA_WIDTH
+  ) u_address_decoder (register_if.address, address_match);
+
+  //  Drive Register IF
+  assign  register_if.select    = select;
+  assign  register_if.ready     = (register_if.request && select) ? 1'b1 : 1'b0;
+  assign  register_if.status    = RGGEN_OKAY;
+
+  generate for (g_i = 0;g_i < DATA_WIDTH;++g_i) begin : g
+    if (VALID_BITS[g_i]) begin
+      assign  register_if.value[g_i]      = bit_field_if.value[g_i];
+      assign  register_if.read_data[g_i]  = bit_field_if.read_data[g_i];
+    end
+    else begin
+      assign  register_if.value[g_i]      = '0;
+      assign  register_if.read_data[g_i]  = '0;
+    end
+  end endgenerate
+
+  //  Drive Bit Field IF
+  assign  bit_field_if.read_access  = (
+    register_if.request && select && (register_if.direction == RGGEN_READ)
+  ) ? 1'b1 : 1'b0;
+  assign  bit_field_if.write_access = (
+    register_if.request && select && (register_if.direction == RGGEN_WRITE)
+  ) ? 1'b1 : 1'b0;
+  assign  bit_field_if.write_data   = register_if.write_data;
+  assign  bit_field_if.write_mask   = get_write_mask(register_if.write_strobe);
+
+  function automatic logic [DATA_WIDTH-1:0] get_write_mask(logic [DATA_WIDTH/8-1:0] strobe);
+    logic [DATA_WIDTH-1:0]  mask;
+    for (int i= 0;i < DATA_WIDTH;i += 8) begin
+      mask[i+:8]  = {8{strobe[i/8]}};
+    end
+    return mask;
+  endfunction
+endmodule

data/rtl/rggen_register_if.sv

@@ -0,0 +1,42 @@
+interface rggen_register_if #(
+  parameter int ADDRESS_WIDTH = 16,
+  parameter int DATA_WIDTH    = 32
+)();
+  import  rggen_rtl_pkg::*;
+
+  logic                     request;
+  logic                     select;
+  logic [ADDRESS_WIDTH-1:0] address;
+  rggen_direction           direction;
+  logic [DATA_WIDTH-1:0]    write_data;
+  logic [DATA_WIDTH/8-1:0]  write_strobe;
+  logic                     ready;
+  logic [DATA_WIDTH-1:0]    read_data;
+  logic [DATA_WIDTH-1:0]    value;
+  rggen_status              status;
+
+  modport master (
+    output  request,
+    input   select,
+    output  address,
+    output  direction,
+    output  write_data,
+    output  write_strobe,
+    input   ready,
+    input   read_data,
+    input   status
+  );
+
+  modport slave (
+    input   request,
+    output  select,
+    input   address,
+    input   direction,
+    input   write_data,
+    input   write_strobe,
+    output  ready,
+    output  read_data,
+    output  status,
+    output  value
+  );
+endinterface

data/rtl/rggen_rtl_pkg.sv

@@ -0,0 +1,23 @@
+package rggen_rtl_pkg;
+  typedef enum logic {
+    RGGEN_READ  = 1'b0,
+    RGGEN_WRITE = 1'b1
+  } rggen_direction;
+
+  typedef enum logic [1:0] {
+    RGGEN_OKAY          = 2'b00,
+    RGGEN_EXOKAY        = 2'b01,
+    RGGEN_SLAVE_ERROR   = 2'b10,
+    RGGEN_DECODE_ERROR  = 2'b11
+  } rggen_status;
+
+  typedef enum bit {
+    RGGEN_SET_MODE    = 1'b0,
+    RGGEN_CLEAR_MODE  = 1'b1
+  } rggen_rwsc_mode;
+
+  typedef enum bit {
+    RGGEN_LOCK_MODE   = 1'b0,
+    RGGEN_ENABLE_MODE = 1'b1
+  } rggen_rwle_mode;
+endpackage

data/sample/LICENSE

@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2017 Taichi Ishitani
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.