rggen 0.5.1 → 0.6.0
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- checksums.yaml +4 -4
- data/c_header/LICENSE +21 -0
- data/{c → c_header}/rggen.h +0 -0
- data/lib/rggen/builtins.rb +2 -5
- data/lib/rggen/builtins/bit_field/type.rb +22 -7
- data/lib/rggen/builtins/bit_field/types/ro.erb +2 -2
- data/lib/rggen/builtins/bit_field/types/ro.rb +2 -2
- data/lib/rggen/builtins/bit_field/types/rw.erb +5 -9
- data/lib/rggen/builtins/bit_field/types/rw.rb +5 -5
- data/lib/rggen/builtins/bit_field/types/rwl_rwe.erb +3 -7
- data/lib/rggen/builtins/bit_field/types/rwl_rwe.rb +6 -7
- data/lib/rggen/builtins/bit_field/types/w0c_w1c.erb +8 -12
- data/lib/rggen/builtins/bit_field/types/w0c_w1c.rb +5 -2
- data/lib/rggen/builtins/bit_field/types/w0s_w1s.erb +8 -12
- data/lib/rggen/builtins/bit_field/types/w0s_w1s.rb +3 -6
- data/lib/rggen/builtins/register/array.rb +0 -93
- data/lib/rggen/builtins/register/reg_model.rb +1 -1
- data/lib/rggen/builtins/register/rtl_top.rb +68 -0
- data/lib/rggen/builtins/register/type.rb +74 -0
- data/lib/rggen/builtins/register/types/default.erb +10 -0
- data/lib/rggen/builtins/register/types/external.erb +11 -0
- data/lib/rggen/builtins/register/types/external.rb +11 -0
- data/lib/rggen/builtins/register/types/indirect.erb +13 -0
- data/lib/rggen/builtins/register/types/indirect.rb +43 -0
- data/lib/rggen/builtins/register_block/clock_reset.rb +2 -2
- data/lib/rggen/builtins/register_block/host_if.rb +11 -12
- data/lib/rggen/builtins/register_block/host_ifs/apb.erb +7 -25
- data/lib/rggen/builtins/register_block/host_ifs/apb.rb +4 -13
- data/lib/rggen/builtins/register_block/host_ifs/axi4lite.erb +6 -34
- data/lib/rggen/builtins/register_block/host_ifs/axi4lite.rb +8 -30
- data/lib/rggen/builtins/register_block/irq_controller.rb +4 -4
- data/lib/rggen/builtins/register_block/rtl_top.erb +7 -0
- data/lib/rggen/builtins/register_block/rtl_top.rb +28 -0
- data/lib/rggen/core_components.rb +3 -0
- data/lib/rggen/core_components/ral/item.rb +2 -6
- data/lib/rggen/core_components/rtl/component.rb +8 -8
- data/lib/rggen/core_components/rtl/item.rb +41 -38
- data/lib/rggen/core_components/verilog_utility.rb +23 -4
- data/lib/rggen/core_components/verilog_utility/declaration.rb +14 -4
- data/lib/rggen/core_components/verilog_utility/identifier.rb +19 -0
- data/lib/rggen/core_components/verilog_utility/interface_instantiation.rb +33 -0
- data/lib/rggen/core_components/verilog_utility/interface_port_declaration.rb +29 -0
- data/lib/rggen/core_components/verilog_utility/local_scope.rb +64 -0
- data/lib/rggen/core_extensions/facets.rb +1 -1
- data/lib/rggen/core_extensions/forwardable.rb +1 -1
- data/lib/rggen/version.rb +2 -2
- data/ral/LICENSE +21 -0
- data/ral/rggen_ral_macros.svh +1 -4
- data/ral/rggen_ral_reg.svh +35 -3
- data/rtl/LICENSE +21 -0
- data/rtl/compile.f +21 -6
- data/rtl/rggen_address_decoder.sv +23 -0
- data/rtl/rggen_apb_if.sv +41 -0
- data/rtl/rggen_axi4lite_if.sv +68 -0
- data/rtl/rggen_bit_field_if.sv +28 -0
- data/rtl/rggen_bit_field_ro.sv +9 -0
- data/rtl/rggen_bit_field_rw.sv +25 -0
- data/rtl/rggen_bit_field_rwl_rwe.sv +29 -0
- data/rtl/rggen_bit_field_w01s_w01c.sv +55 -0
- data/rtl/rggen_bus_if.sv +43 -0
- data/rtl/rggen_bus_splitter.sv +87 -0
- data/rtl/rggen_default_register.sv +15 -0
- data/rtl/rggen_external_register.sv +83 -0
- data/rtl/rggen_host_if_apb.sv +29 -0
- data/rtl/rggen_host_if_axi4lite.sv +14 -0
- data/rtl/rggen_indirect_register.sv +21 -0
- data/rtl/{register_block/rggen_irq_controller.sv → rggen_irq_controller.sv} +0 -0
- data/rtl/rggen_register_base.sv +57 -0
- data/rtl/rggen_register_if.sv +42 -0
- data/rtl/rggen_rtl_pkg.sv +23 -0
- data/sample/LICENSE +21 -0
- data/sample/sample_0.sv +315 -444
- data/sample/sample_0_ral_pkg.sv +7 -7
- data/sample/sample_1.sv +104 -162
- data/sample/sample_1_ral_pkg.sv +3 -3
- data/sample/sample_setup.rb +2 -2
- data/setup/default.rb +3 -3
- metadata +35 -23
- data/lib/rggen/builtins/register/address_decoder.erb +0 -12
- data/lib/rggen/builtins/register/address_decoder.rb +0 -82
- data/lib/rggen/builtins/register/bus_exporter.erb +0 -28
- data/lib/rggen/builtins/register/bus_exporter.rb +0 -52
- data/lib/rggen/builtins/register/read_data.rb +0 -61
- data/lib/rggen/builtins/register_block/response_mux.erb +0 -18
- data/lib/rggen/builtins/register_block/response_mux.rb +0 -47
- data/lib/rggen/builtins/register_block/top_module.rb +0 -20
- data/rtl/bit_field/rggen_bit_field_common.svh +0 -15
- data/rtl/bit_field/rggen_bit_field_ro.sv +0 -8
- data/rtl/bit_field/rggen_bit_field_rw.sv +0 -27
- data/rtl/bit_field/rggen_bit_field_rwl_rwe.sv +0 -49
- data/rtl/bit_field/rggen_bit_field_w01s_w01c.sv +0 -67
- data/rtl/register/rggen_address_decoder.sv +0 -37
- data/rtl/register/rggen_bus_exporter.sv +0 -96
- data/rtl/register_block/rggen_host_if_apb.sv +0 -42
- data/rtl/register_block/rggen_host_if_axi4lite.sv +0 -257
- data/rtl/register_block/rggen_host_if_common.svh +0 -9
- data/rtl/register_block/rggen_response_mux.sv +0 -113
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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1
1
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---
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2
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SHA1:
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-
metadata.gz:
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-
data.tar.gz:
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3
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+
metadata.gz: ad6fc3632abba4953ce0e0fe205a009db33e7b8d
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4
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+
data.tar.gz: '068dffc83856248d9042c658766e3eaa3423cb1e'
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5
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SHA512:
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-
metadata.gz:
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7
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data.tar.gz:
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6
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+
metadata.gz: 71fcd5f1de2247416ceecf9adfe5a32f0e1b8e9c130cc1b7ec562cec34288594eafd1d788edede1775e7dfbf2f939e6c7cc89cd2d048981ecfebeb030c17dcca
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7
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+
data.tar.gz: 7e9124eac17384c66e967beefa5da946e466e9798fb01d07270c6175c565d1af7e2fd28f2ff644c212a1f371f9141f9b330a00b7ae07b5ac3ba6e01de6811e4c
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data/c_header/LICENSE
ADDED
@@ -0,0 +1,21 @@
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1
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+
MIT License
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+
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3
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+
Copyright (c) 2017 Taichi Ishitani
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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+
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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+
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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+
SOFTWARE.
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data/{c → c_header}/rggen.h
RENAMED
File without changes
|
data/lib/rggen/builtins.rb
CHANGED
@@ -21,16 +21,14 @@ require_relative 'builtins/bit_field/types/w0s_w1s'
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21
21
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require_relative 'builtins/bit_field/types/wo'
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22
22
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require_relative 'builtins/bit_field/types/reserved'
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23
23
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24
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-
require_relative 'builtins/register/address_decoder'
|
25
24
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require_relative 'builtins/register/array'
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26
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-
require_relative 'builtins/register/bus_exporter'
|
27
25
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require_relative 'builtins/register/constructor'
|
28
26
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require_relative 'builtins/register/field_model_creator'
|
29
27
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require_relative 'builtins/register/indirect_index_configurator'
|
30
28
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require_relative 'builtins/register/offset_address'
|
31
29
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require_relative 'builtins/register/name'
|
32
|
-
require_relative 'builtins/register/read_data'
|
33
30
|
require_relative 'builtins/register/reg_model'
|
31
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+
require_relative 'builtins/register/rtl_top'
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34
32
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require_relative 'builtins/register/sub_block_model'
|
35
33
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require_relative 'builtins/register/type'
|
36
34
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require_relative 'builtins/register/types/external'
|
@@ -51,6 +49,5 @@ require_relative 'builtins/register_block/host_ifs/axi4lite'
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51
49
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require_relative 'builtins/register_block/irq_controller'
|
52
50
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require_relative 'builtins/register_block/name'
|
53
51
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require_relative 'builtins/register_block/ral_package'
|
54
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-
require_relative 'builtins/register_block/
|
52
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+
require_relative 'builtins/register_block/rtl_top'
|
55
53
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require_relative 'builtins/register_block/sub_model_creator'
|
56
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-
require_relative 'builtins/register_block/top_module'
|
@@ -166,18 +166,33 @@ list_item :bit_field, :type do
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166
166
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167
167
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rtl do
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168
168
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item_base do
|
169
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+
export :value
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170
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+
|
171
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delegate [
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172
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+
:name, :width, :msb, :lsb, :reserved?
|
173
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+
] => :bit_field
|
174
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+
delegate [
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175
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+
:dimensions, :index, :local_index, :loop_variables
|
176
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+
] => :register
|
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+
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available? { !bit_field.reserved? }
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+
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180
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build do
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170
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-
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-
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+
interface :register, :bit_field_if,
|
182
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+
type: :rggen_bit_field_if,
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183
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name: "#{name}_if",
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parameters: [width]
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185
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end
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186
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-
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-
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187
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+
generate_pre_code :register do |c|
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+
c << subroutine_call(:'`rggen_connect_bit_field_if', [
|
189
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+
register.bit_field_if, bit_field_if, msb, lsb
|
190
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+
]) << nl
|
176
191
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end
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192
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|
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-
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-
|
180
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-
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193
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+
def value
|
194
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+
register.register_if.value[msb, lsb]
|
195
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+
end
|
181
196
|
end
|
182
197
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183
198
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default_item do
|
@@ -5,13 +5,13 @@ list_item :bit_field, :type, :ro do
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5
5
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6
6
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rtl do
|
7
7
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build do
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8
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-
input :value_in,
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8
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+
input :register_block, :value_in,
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9
9
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name: "i_#{bit_field.name}",
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10
10
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width: width,
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11
11
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dimensions: dimensions
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12
12
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end
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13
13
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-
generate_code_from_template :
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+
generate_code_from_template :register
|
15
15
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end
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16
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ral do
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@@ -1,13 +1,9 @@
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1
1
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rggen_bit_field_rw #(
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-
.WIDTH (<%=
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2
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+
.WIDTH (<%= width %>),
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3
3
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.INITIAL_VALUE (<%= initial_value %>)
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4
4
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) u_<%= bit_field.name %> (
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-
.clk
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.rst_n
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-
.
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.
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-
.i_write (<%= register_block.host_if.write %>),
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10
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-
.i_write_data (<%= register_block.host_if.write_data[bit_field.msb, bit_field.lsb] %>),
|
11
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-
.i_write_mask (<%= register_block.host_if.write_mask[bit_field.msb, bit_field.lsb] %>),
|
12
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-
.o_value (<%= value[loop_variables] %>)
|
5
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+
.clk (<%= register_block.clock %>),
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6
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+
.rst_n (<%= register_block.reset %>),
|
7
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+
.bit_field_if (<%= bit_field_if %>),
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8
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+
.o_value (<%= value_out[loop_variables] %>)
|
13
9
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);
|
@@ -6,13 +6,13 @@ list_item :bit_field, :type, :rw do
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6
6
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7
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rtl do
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8
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build do
|
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output :
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9
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+
output :register_block, :value_out,
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name: port_name,
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11
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width: width,
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dimensions: dimensions
|
10
13
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end
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14
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12
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-
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-
buffer << assign(value_out[loop_variables], value[loop_variables]) << nl
|
14
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-
buffer << process_template
|
15
|
-
end
|
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+
generate_code_from_template :register
|
16
16
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def port_name
|
18
18
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"o_#{bit_field.name}"
|
@@ -1,15 +1,11 @@
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1
1
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rggen_bit_field_rwl_rwe #(
|
2
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-
.
|
2
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+
.MODE (rggen_rtl_pkg::<%= mode %>),
|
3
3
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.WIDTH (<%= width %>),
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4
4
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.INITIAL_VALUE (<%= initial_value %>)
|
5
5
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) u_<%= bit_field.name %> (
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6
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.clk (<%= register_block.clock %>),
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7
7
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.rst_n (<%= register_block.reset %>),
|
8
8
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.i_lock_or_enable (<%= lock_or_enable %>),
|
9
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-
.
|
10
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-
.
|
11
|
-
.i_write (<%= register_block.host_if.write %>),
|
12
|
-
.i_write_data (<%= register_block.host_if.write_data[bit_field.msb, bit_field.lsb] %>),
|
13
|
-
.i_write_mask (<%= register_block.host_if.write_mask[bit_field.msb, bit_field.lsb] %>),
|
14
|
-
.o_value (<%= value[loop_variables] %>)
|
9
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+
.bit_field_if (<%= bit_field_if %>),
|
10
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+
.o_value (<%= value_out[loop_variables] %>)
|
15
11
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);
|
@@ -7,19 +7,18 @@ list_item :bit_field, :type, [:rwl, :rwe] do
|
|
7
7
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8
8
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rtl do
|
9
9
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build do
|
10
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-
output :value_out,
|
10
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+
output :register_block, :value_out,
|
11
11
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name: "o_#{bit_field.name}",
|
12
12
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width: width,
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13
13
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dimensions: dimensions
|
14
14
|
end
|
15
15
|
|
16
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-
|
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-
code << assign(value_out[loop_variables], value[loop_variables]) << nl
|
18
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-
code << process_template
|
19
|
-
end
|
16
|
+
generate_code_from_template :register
|
20
17
|
|
21
|
-
def
|
22
|
-
{
|
18
|
+
def mode
|
19
|
+
{
|
20
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+
rwl: :RGGEN_LOCK_MODE, rwe: :RGGEN_ENABLE_MODE
|
21
|
+
}[bit_field.type]
|
23
22
|
end
|
24
23
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|
25
24
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def initial_value
|
@@ -1,16 +1,12 @@
|
|
1
1
|
rggen_bit_field_w01s_w01c #(
|
2
|
+
.MODE (rggen_rtl_pkg::RGGEN_CLEAR_MODE),
|
3
|
+
.SET_CLEAR_VALUE (<%= clear_value %>),
|
2
4
|
.WIDTH (<%= width %>),
|
3
|
-
.INITIAL_VALUE (<%= initial_value %>)
|
4
|
-
.SET_MODE (0),
|
5
|
-
.SET_CLEAR_VALUE (<%= clear_value %>)
|
5
|
+
.INITIAL_VALUE (<%= initial_value %>)
|
6
6
|
) u_<%= name%> (
|
7
|
-
.clk
|
8
|
-
.rst_n
|
9
|
-
.i_set_or_clear
|
10
|
-
.
|
11
|
-
.
|
12
|
-
.i_write (<%= register_block.host_if.write %>),
|
13
|
-
.i_write_data (<%= register_block.host_if.write_data[bit_field.msb, bit_field.lsb] %>),
|
14
|
-
.i_write_mask (<%= register_block.host_if.write_mask[bit_field.msb, bit_field.lsb] %>),
|
15
|
-
.o_value (<%= value[loop_variables] %>)
|
7
|
+
.clk (<%= register_block.clock %>),
|
8
|
+
.rst_n (<%= register_block.reset %>),
|
9
|
+
.i_set_or_clear (<%= set[loop_variables] %>),
|
10
|
+
.bit_field_if (<%= bit_field_if %>),
|
11
|
+
.o_value ()
|
16
12
|
);
|
@@ -10,10 +10,13 @@ list_item :bit_field, :type, [:w0c, :w1c] do
|
|
10
10
|
delegate [:name, :type] => :bit_field
|
11
11
|
|
12
12
|
build do
|
13
|
-
input :
|
13
|
+
input :register_block, :set,
|
14
|
+
name: "i_#{name}_set",
|
15
|
+
width: width,
|
16
|
+
dimensions: dimensions
|
14
17
|
end
|
15
18
|
|
16
|
-
generate_code_from_template :
|
19
|
+
generate_code_from_template :register
|
17
20
|
|
18
21
|
def initial_value
|
19
22
|
hex(bit_field.initial_value, width)
|
@@ -1,16 +1,12 @@
|
|
1
1
|
rggen_bit_field_w01s_w01c #(
|
2
|
+
.MODE (rggen_rtl_pkg::RGGEN_SET_MODE),
|
3
|
+
.SET_CLEAR_VALUE (<%= set_value %>),
|
2
4
|
.WIDTH (<%= width %>),
|
3
|
-
.INITIAL_VALUE (<%= initial_value %>)
|
4
|
-
.SET_MODE (1),
|
5
|
-
.SET_CLEAR_VALUE (<%= set_value %>)
|
5
|
+
.INITIAL_VALUE (<%= initial_value %>)
|
6
6
|
) u_<%= name %> (
|
7
|
-
.clk
|
8
|
-
.rst_n
|
9
|
-
.i_set_or_clear
|
10
|
-
.
|
11
|
-
.
|
12
|
-
.i_write (<%= register_block.host_if.write %>),
|
13
|
-
.i_write_data (<%= register_block.host_if.write_data[bit_field.msb, bit_field.lsb] %>),
|
14
|
-
.i_write_mask (<%= register_block.host_if.write_mask[bit_field.msb, bit_field.lsb] %>),
|
15
|
-
.o_value (<%= value[loop_variables] %>)
|
7
|
+
.clk (<%= register_block.clock %>),
|
8
|
+
.rst_n (<%= register_block.reset %>),
|
9
|
+
.i_set_or_clear (<%= clear[loop_variables] %>),
|
10
|
+
.bit_field_if (<%= bit_field_if %>),
|
11
|
+
.o_value (<%= value_out[loop_variables] %>)
|
16
12
|
);
|
@@ -8,20 +8,17 @@ list_item :bit_field, :type, [:w0s, :w1s] do
|
|
8
8
|
delegate [:name, :type] => :bit_field
|
9
9
|
|
10
10
|
build do
|
11
|
-
output :value_out,
|
11
|
+
output :register_block, :value_out,
|
12
12
|
name: "o_#{name}",
|
13
13
|
width: width,
|
14
14
|
dimensions: dimensions
|
15
|
-
input :clear,
|
15
|
+
input :register_block, :clear,
|
16
16
|
name: "i_#{name}_clear",
|
17
17
|
width: width,
|
18
18
|
dimensions: dimensions
|
19
19
|
end
|
20
20
|
|
21
|
-
|
22
|
-
code << assign(value_out[loop_variables], value[loop_variables]) << nl
|
23
|
-
code << process_template
|
24
|
-
end
|
21
|
+
generate_code_from_template :register
|
25
22
|
|
26
23
|
def initial_value
|
27
24
|
hex(bit_field.initial_value, width)
|
@@ -27,97 +27,4 @@ simple_item :register, :array do
|
|
27
27
|
end
|
28
28
|
end
|
29
29
|
end
|
30
|
-
|
31
|
-
rtl do
|
32
|
-
delegate [:array?, :dimensions] => :register
|
33
|
-
|
34
|
-
export :index
|
35
|
-
export :local_index
|
36
|
-
export :loop_variables
|
37
|
-
export :loop_variable
|
38
|
-
|
39
|
-
generate_pre_code :module_item do |code|
|
40
|
-
if array?
|
41
|
-
generate_header(code)
|
42
|
-
generate_for_headers(code)
|
43
|
-
end
|
44
|
-
end
|
45
|
-
|
46
|
-
generate_post_code :module_item do |code|
|
47
|
-
if array?
|
48
|
-
generate_for_footers(code)
|
49
|
-
generate_footer(code)
|
50
|
-
end
|
51
|
-
end
|
52
|
-
|
53
|
-
def index
|
54
|
-
(array? && "#{base_index}+#{local_index}") || base_index
|
55
|
-
end
|
56
|
-
|
57
|
-
def local_index
|
58
|
-
return nil unless array?
|
59
|
-
local_index_terms(0).join('+')
|
60
|
-
end
|
61
|
-
|
62
|
-
def loop_variables
|
63
|
-
return nil unless array?
|
64
|
-
Array.new(dimensions.size) { |l| loop_variable(l) }
|
65
|
-
end
|
66
|
-
|
67
|
-
def loop_variable(level)
|
68
|
-
return nil unless array? && level < dimensions.size
|
69
|
-
@loop_variables ||= Hash.new do |h, l|
|
70
|
-
h[l] = create_identifier("g_#{loop_index(l)}")
|
71
|
-
end
|
72
|
-
@loop_variables[level]
|
73
|
-
end
|
74
|
-
|
75
|
-
def base_index
|
76
|
-
former_registers.sum(0, &:count)
|
77
|
-
end
|
78
|
-
|
79
|
-
def former_registers
|
80
|
-
register_block.registers.take_while { |r| !register.equal?(r) }
|
81
|
-
end
|
82
|
-
|
83
|
-
def local_index_terms(level)
|
84
|
-
if level < (dimensions.size - 1)
|
85
|
-
partial_count = dimensions[(level + 1)..-1].inject(:*)
|
86
|
-
term = [partial_count, '*', loop_variable(level)].join
|
87
|
-
local_index_terms(level + 1).unshift(term)
|
88
|
-
else
|
89
|
-
[loop_variable(level)]
|
90
|
-
end
|
91
|
-
end
|
92
|
-
|
93
|
-
def generate_header(code)
|
94
|
-
code << "generate if (1) begin : g_#{register.name}" << nl
|
95
|
-
code.indent += 2
|
96
|
-
code << "genvar #{loop_variables.join(', ')};" << nl
|
97
|
-
end
|
98
|
-
|
99
|
-
def generate_for_headers(code)
|
100
|
-
dimensions.each_with_index do |dimension, level|
|
101
|
-
code << generate_for_header(dimension, level) << nl
|
102
|
-
code.indent += 2
|
103
|
-
end
|
104
|
-
end
|
105
|
-
|
106
|
-
def generate_for_header(dimension, level)
|
107
|
-
gv = loop_variable(level)
|
108
|
-
"for (#{gv} = 0;#{gv} < #{dimension};#{gv}++) begin : g"
|
109
|
-
end
|
110
|
-
|
111
|
-
def generate_for_footers(code)
|
112
|
-
dimensions.size.times do
|
113
|
-
code.indent -= 2
|
114
|
-
code << :end << nl
|
115
|
-
end
|
116
|
-
end
|
117
|
-
|
118
|
-
def generate_footer(code)
|
119
|
-
code.indent -= 2
|
120
|
-
code << :end << space << :endgenerate << nl
|
121
|
-
end
|
122
|
-
end
|
123
30
|
end
|
@@ -0,0 +1,68 @@
|
|
1
|
+
simple_item :register, :rtl_top do
|
2
|
+
rtl do
|
3
|
+
export :index
|
4
|
+
export :local_index
|
5
|
+
export :loop_variables
|
6
|
+
export :loop_variable
|
7
|
+
|
8
|
+
delegate [:array?, :dimensions] => :register
|
9
|
+
|
10
|
+
generate_code :register_block do
|
11
|
+
local_scope "g_#{register.name}" do |s|
|
12
|
+
s.signals register.signal_declarations(:register)
|
13
|
+
s.loops loops
|
14
|
+
s.body { |c| register.generate_code(:register, :top_down, c) }
|
15
|
+
end
|
16
|
+
end
|
17
|
+
|
18
|
+
def index
|
19
|
+
return base_index unless array?
|
20
|
+
"#{base_index}+#{local_index}"
|
21
|
+
end
|
22
|
+
|
23
|
+
def local_index
|
24
|
+
return nil unless array?
|
25
|
+
local_index_terms(0).join('+')
|
26
|
+
end
|
27
|
+
|
28
|
+
def loop_variables
|
29
|
+
return nil unless array?
|
30
|
+
dimensions.size.times.map(&method(:loop_variable))
|
31
|
+
end
|
32
|
+
|
33
|
+
def loop_variable(level)
|
34
|
+
return nil unless array?
|
35
|
+
return nil if level >= dimensions.size
|
36
|
+
@loop_variables ||= Hash.new do |h, l|
|
37
|
+
h[l] = create_identifier("g_#{loop_index(l)}")
|
38
|
+
end
|
39
|
+
@loop_variables[level]
|
40
|
+
end
|
41
|
+
|
42
|
+
private
|
43
|
+
|
44
|
+
def base_index
|
45
|
+
former_registers.sum(0, &:count)
|
46
|
+
end
|
47
|
+
|
48
|
+
def former_registers
|
49
|
+
register_block.registers.take_while { |r| !register.equal?(r) }
|
50
|
+
end
|
51
|
+
|
52
|
+
def local_index_terms(level)
|
53
|
+
if level < (dimensions.size - 1)
|
54
|
+
partial_count = dimensions[(level + 1)..-1].inject(&:*)
|
55
|
+
local_index_terms(level + 1).unshift(
|
56
|
+
[partial_count, :'*', loop_variable(level)].join
|
57
|
+
)
|
58
|
+
else
|
59
|
+
[loop_variable(level)]
|
60
|
+
end
|
61
|
+
end
|
62
|
+
|
63
|
+
def loops
|
64
|
+
return nil unless array?
|
65
|
+
Hash[*loop_variables.zip(dimensions).flatten]
|
66
|
+
end
|
67
|
+
end
|
68
|
+
end
|