rggen 0.5.1 → 0.6.0

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Files changed (97) hide show
  1. checksums.yaml +4 -4
  2. data/c_header/LICENSE +21 -0
  3. data/{c → c_header}/rggen.h +0 -0
  4. data/lib/rggen/builtins.rb +2 -5
  5. data/lib/rggen/builtins/bit_field/type.rb +22 -7
  6. data/lib/rggen/builtins/bit_field/types/ro.erb +2 -2
  7. data/lib/rggen/builtins/bit_field/types/ro.rb +2 -2
  8. data/lib/rggen/builtins/bit_field/types/rw.erb +5 -9
  9. data/lib/rggen/builtins/bit_field/types/rw.rb +5 -5
  10. data/lib/rggen/builtins/bit_field/types/rwl_rwe.erb +3 -7
  11. data/lib/rggen/builtins/bit_field/types/rwl_rwe.rb +6 -7
  12. data/lib/rggen/builtins/bit_field/types/w0c_w1c.erb +8 -12
  13. data/lib/rggen/builtins/bit_field/types/w0c_w1c.rb +5 -2
  14. data/lib/rggen/builtins/bit_field/types/w0s_w1s.erb +8 -12
  15. data/lib/rggen/builtins/bit_field/types/w0s_w1s.rb +3 -6
  16. data/lib/rggen/builtins/register/array.rb +0 -93
  17. data/lib/rggen/builtins/register/reg_model.rb +1 -1
  18. data/lib/rggen/builtins/register/rtl_top.rb +68 -0
  19. data/lib/rggen/builtins/register/type.rb +74 -0
  20. data/lib/rggen/builtins/register/types/default.erb +10 -0
  21. data/lib/rggen/builtins/register/types/external.erb +11 -0
  22. data/lib/rggen/builtins/register/types/external.rb +11 -0
  23. data/lib/rggen/builtins/register/types/indirect.erb +13 -0
  24. data/lib/rggen/builtins/register/types/indirect.rb +43 -0
  25. data/lib/rggen/builtins/register_block/clock_reset.rb +2 -2
  26. data/lib/rggen/builtins/register_block/host_if.rb +11 -12
  27. data/lib/rggen/builtins/register_block/host_ifs/apb.erb +7 -25
  28. data/lib/rggen/builtins/register_block/host_ifs/apb.rb +4 -13
  29. data/lib/rggen/builtins/register_block/host_ifs/axi4lite.erb +6 -34
  30. data/lib/rggen/builtins/register_block/host_ifs/axi4lite.rb +8 -30
  31. data/lib/rggen/builtins/register_block/irq_controller.rb +4 -4
  32. data/lib/rggen/builtins/register_block/rtl_top.erb +7 -0
  33. data/lib/rggen/builtins/register_block/rtl_top.rb +28 -0
  34. data/lib/rggen/core_components.rb +3 -0
  35. data/lib/rggen/core_components/ral/item.rb +2 -6
  36. data/lib/rggen/core_components/rtl/component.rb +8 -8
  37. data/lib/rggen/core_components/rtl/item.rb +41 -38
  38. data/lib/rggen/core_components/verilog_utility.rb +23 -4
  39. data/lib/rggen/core_components/verilog_utility/declaration.rb +14 -4
  40. data/lib/rggen/core_components/verilog_utility/identifier.rb +19 -0
  41. data/lib/rggen/core_components/verilog_utility/interface_instantiation.rb +33 -0
  42. data/lib/rggen/core_components/verilog_utility/interface_port_declaration.rb +29 -0
  43. data/lib/rggen/core_components/verilog_utility/local_scope.rb +64 -0
  44. data/lib/rggen/core_extensions/facets.rb +1 -1
  45. data/lib/rggen/core_extensions/forwardable.rb +1 -1
  46. data/lib/rggen/version.rb +2 -2
  47. data/ral/LICENSE +21 -0
  48. data/ral/rggen_ral_macros.svh +1 -4
  49. data/ral/rggen_ral_reg.svh +35 -3
  50. data/rtl/LICENSE +21 -0
  51. data/rtl/compile.f +21 -6
  52. data/rtl/rggen_address_decoder.sv +23 -0
  53. data/rtl/rggen_apb_if.sv +41 -0
  54. data/rtl/rggen_axi4lite_if.sv +68 -0
  55. data/rtl/rggen_bit_field_if.sv +28 -0
  56. data/rtl/rggen_bit_field_ro.sv +9 -0
  57. data/rtl/rggen_bit_field_rw.sv +25 -0
  58. data/rtl/rggen_bit_field_rwl_rwe.sv +29 -0
  59. data/rtl/rggen_bit_field_w01s_w01c.sv +55 -0
  60. data/rtl/rggen_bus_if.sv +43 -0
  61. data/rtl/rggen_bus_splitter.sv +87 -0
  62. data/rtl/rggen_default_register.sv +15 -0
  63. data/rtl/rggen_external_register.sv +83 -0
  64. data/rtl/rggen_host_if_apb.sv +29 -0
  65. data/rtl/rggen_host_if_axi4lite.sv +14 -0
  66. data/rtl/rggen_indirect_register.sv +21 -0
  67. data/rtl/{register_block/rggen_irq_controller.sv → rggen_irq_controller.sv} +0 -0
  68. data/rtl/rggen_register_base.sv +57 -0
  69. data/rtl/rggen_register_if.sv +42 -0
  70. data/rtl/rggen_rtl_pkg.sv +23 -0
  71. data/sample/LICENSE +21 -0
  72. data/sample/sample_0.sv +315 -444
  73. data/sample/sample_0_ral_pkg.sv +7 -7
  74. data/sample/sample_1.sv +104 -162
  75. data/sample/sample_1_ral_pkg.sv +3 -3
  76. data/sample/sample_setup.rb +2 -2
  77. data/setup/default.rb +3 -3
  78. metadata +35 -23
  79. data/lib/rggen/builtins/register/address_decoder.erb +0 -12
  80. data/lib/rggen/builtins/register/address_decoder.rb +0 -82
  81. data/lib/rggen/builtins/register/bus_exporter.erb +0 -28
  82. data/lib/rggen/builtins/register/bus_exporter.rb +0 -52
  83. data/lib/rggen/builtins/register/read_data.rb +0 -61
  84. data/lib/rggen/builtins/register_block/response_mux.erb +0 -18
  85. data/lib/rggen/builtins/register_block/response_mux.rb +0 -47
  86. data/lib/rggen/builtins/register_block/top_module.rb +0 -20
  87. data/rtl/bit_field/rggen_bit_field_common.svh +0 -15
  88. data/rtl/bit_field/rggen_bit_field_ro.sv +0 -8
  89. data/rtl/bit_field/rggen_bit_field_rw.sv +0 -27
  90. data/rtl/bit_field/rggen_bit_field_rwl_rwe.sv +0 -49
  91. data/rtl/bit_field/rggen_bit_field_w01s_w01c.sv +0 -67
  92. data/rtl/register/rggen_address_decoder.sv +0 -37
  93. data/rtl/register/rggen_bus_exporter.sv +0 -96
  94. data/rtl/register_block/rggen_host_if_apb.sv +0 -42
  95. data/rtl/register_block/rggen_host_if_axi4lite.sv +0 -257
  96. data/rtl/register_block/rggen_host_if_common.svh +0 -9
  97. data/rtl/register_block/rggen_response_mux.sv +0 -113
data/sample/sample_0.sv CHANGED
@@ -1,16 +1,7 @@
1
1
  module sample_0 (
2
2
  input clk,
3
3
  input rst_n,
4
- input [15:0] i_paddr,
5
- input [2:0] i_pprot,
6
- input i_psel,
7
- input i_penable,
8
- input i_pwrite,
9
- input [31:0] i_pwdata,
10
- input [3:0] i_pstrb,
11
- output o_pready,
12
- output [31:0] o_prdata,
13
- output o_pslverr,
4
+ rggen_apb_if.slave apb_if,
14
5
  output o_irq,
15
6
  output [15:0] o_bit_field_0_0,
16
7
  output [15:0] o_bit_field_0_1,
@@ -30,98 +21,30 @@ module sample_0 (
30
21
  input i_bit_field_7_1_clear,
31
22
  output [15:0] o_bit_field_8_0,
32
23
  output [15:0] o_bit_field_8_1,
33
- output o_register_9_valid,
34
- output o_register_9_write,
35
- output o_register_9_read,
36
- output [6:0] o_register_9_address,
37
- output [3:0] o_register_9_strobe,
38
- output [31:0] o_register_9_write_data,
39
- input i_register_9_ready,
40
- input [1:0] i_register_9_status,
41
- input [31:0] i_register_9_read_data
24
+ rggen_bus_if.master register_9_bus_if
42
25
  );
43
- logic command_valid;
44
- logic write;
45
- logic read;
46
- logic [7:0] address;
47
- logic [3:0] strobe;
48
- logic [31:0] write_data;
49
- logic [31:0] write_mask;
50
- logic response_ready;
51
- logic [31:0] read_data;
52
- logic [1:0] status;
53
- logic [19:0] register_select;
54
- logic [31:0] register_read_data[20];
55
- logic [0:0] external_register_select;
56
- logic [0:0] external_register_ready;
57
- logic [1:0] external_register_status[1];
26
+ rggen_register_if #(8, 32) register_if[20]();
58
27
  logic [1:0] ier;
59
28
  logic [1:0] isr;
60
- logic [15:0] bit_field_0_0_value;
61
- logic [15:0] bit_field_0_1_value;
62
- logic [31:0] bit_field_1_0_value;
63
- logic bit_field_2_0_value;
64
- logic bit_field_2_1_value;
65
- logic [31:0] bit_field_3_0_value;
66
- logic [15:0] bit_field_4_0_value[4];
67
- logic [15:0] bit_field_4_1_value[4];
68
- logic [32:0] register_5_indirect_index[2][4];
69
- logic [15:0] bit_field_5_0_value[2][4];
70
- logic [15:0] bit_field_5_1_value[2][4];
71
- logic bit_field_6_0_value;
72
- logic bit_field_6_1_value;
73
- logic bit_field_7_0_value;
74
- logic bit_field_7_1_value;
75
- logic [15:0] bit_field_8_0_value;
76
- logic [15:0] bit_field_8_1_value;
29
+ `define rggen_connect_bit_field_if(RIF, FIF, MSB, LSB) \
30
+ assign FIF.read_access = RIF.read_access; \
31
+ assign FIF.write_access = RIF.write_access; \
32
+ assign FIF.write_data = RIF.write_data[MSB:LSB]; \
33
+ assign FIF.write_mask = RIF.write_mask[MSB:LSB]; \
34
+ assign RIF.value[MSB:LSB] = FIF.value; \
35
+ assign RIF.read_data[MSB:LSB] = FIF.read_data;
77
36
  rggen_host_if_apb #(
37
+ .LOCAL_ADDRESS_WIDTH (8),
78
38
  .DATA_WIDTH (32),
79
- .HOST_ADDRESS_WIDTH (16),
80
- .LOCAL_ADDRESS_WIDTH (8)
39
+ .TOTAL_REGISTERS (20)
81
40
  ) u_host_if (
82
- .clk (clk),
83
- .rst_n (rst_n),
84
- .i_paddr (i_paddr),
85
- .i_pprot (i_pprot),
86
- .i_psel (i_psel),
87
- .i_penable (i_penable),
88
- .i_pwrite (i_pwrite),
89
- .i_pwdata (i_pwdata),
90
- .i_pstrb (i_pstrb),
91
- .o_pready (o_pready),
92
- .o_prdata (o_prdata),
93
- .o_pslverr (o_pslverr),
94
- .o_command_valid (command_valid),
95
- .o_write (write),
96
- .o_read (read),
97
- .o_address (address),
98
- .o_strobe (strobe),
99
- .o_write_data (write_data),
100
- .o_write_mask (write_mask),
101
- .i_response_ready (response_ready),
102
- .i_read_data (read_data),
103
- .i_status (status)
104
- );
105
- rggen_response_mux #(
106
- .DATA_WIDTH (32),
107
- .TOTAL_REGISTERS (20),
108
- .TOTAL_EXTERNAL_REGISTERS (1)
109
- ) u_response_mux (
110
- .clk (clk),
111
- .rst_n (rst_n),
112
- .i_command_valid (command_valid),
113
- .i_read (read),
114
- .o_response_ready (response_ready),
115
- .o_read_data (read_data),
116
- .o_status (status),
117
- .i_register_select (register_select),
118
- .i_register_read_data (register_read_data),
119
- .i_external_register_select (external_register_select),
120
- .i_external_register_ready (external_register_ready),
121
- .i_external_register_status (external_register_status)
41
+ .clk (clk),
42
+ .rst_n (rst_n),
43
+ .apb_if (apb_if),
44
+ .register_if (register_if)
122
45
  );
123
- assign ier = {bit_field_2_1_value, bit_field_2_1_value};
124
- assign isr = {bit_field_6_0_value, bit_field_6_1_value};
46
+ assign ier = {register_if[2].value[0], register_if[2].value[0]};
47
+ assign isr = {register_if[16].value[8], register_if[16].value[0]};
125
48
  rggen_irq_controller #(
126
49
  .TOTAL_INTERRUPTS (2)
127
50
  ) u_irq_controller (
@@ -131,381 +54,329 @@ module sample_0 (
131
54
  .i_isr (isr),
132
55
  .o_irq (o_irq)
133
56
  );
134
- rggen_address_decoder #(
135
- .ADDRESS_WIDTH (6),
136
- .START_ADDRESS (6'h00),
137
- .END_ADDRESS (6'h00),
138
- .INDIRECT_REGISTER (0),
139
- .INDIRECT_INDEX_WIDTH (1),
140
- .INDIRECT_INDEX_VALUE (1'h0)
141
- ) u_register_0_address_decoder (
142
- .i_address (address[7:2]),
143
- .i_indirect_index (1'h0),
144
- .o_select (register_select[0])
145
- );
146
- assign register_read_data[0] = {bit_field_0_0_value, bit_field_0_1_value};
147
- assign o_bit_field_0_0 = bit_field_0_0_value;
148
- rggen_bit_field_rw #(
149
- .WIDTH (16),
150
- .INITIAL_VALUE (16'h0000)
151
- ) u_bit_field_0_0 (
152
- .clk (clk),
153
- .rst_n (rst_n),
154
- .i_command_valid (command_valid),
155
- .i_select (register_select[0]),
156
- .i_write (write),
157
- .i_write_data (write_data[31:16]),
158
- .i_write_mask (write_mask[31:16]),
159
- .o_value (bit_field_0_0_value)
160
- );
161
- assign o_bit_field_0_1 = bit_field_0_1_value;
162
- rggen_bit_field_rw #(
163
- .WIDTH (16),
164
- .INITIAL_VALUE (16'h0000)
165
- ) u_bit_field_0_1 (
166
- .clk (clk),
167
- .rst_n (rst_n),
168
- .i_command_valid (command_valid),
169
- .i_select (register_select[0]),
170
- .i_write (write),
171
- .i_write_data (write_data[15:0]),
172
- .i_write_mask (write_mask[15:0]),
173
- .o_value (bit_field_0_1_value)
174
- );
175
- rggen_address_decoder #(
176
- .ADDRESS_WIDTH (6),
177
- .START_ADDRESS (6'h01),
178
- .END_ADDRESS (6'h01),
179
- .INDIRECT_REGISTER (0),
180
- .INDIRECT_INDEX_WIDTH (1),
181
- .INDIRECT_INDEX_VALUE (1'h0)
182
- ) u_register_1_address_decoder (
183
- .i_address (address[7:2]),
184
- .i_indirect_index (1'h0),
185
- .o_select (register_select[1])
186
- );
187
- assign register_read_data[1] = {bit_field_1_0_value};
188
- assign o_bit_field_1_0 = bit_field_1_0_value;
189
- rggen_bit_field_rw #(
190
- .WIDTH (32),
191
- .INITIAL_VALUE (32'h00000000)
192
- ) u_bit_field_1_0 (
193
- .clk (clk),
194
- .rst_n (rst_n),
195
- .i_command_valid (command_valid),
196
- .i_select (register_select[1]),
197
- .i_write (write),
198
- .i_write_data (write_data[31:0]),
199
- .i_write_mask (write_mask[31:0]),
200
- .o_value (bit_field_1_0_value)
201
- );
202
- rggen_address_decoder #(
203
- .ADDRESS_WIDTH (6),
204
- .START_ADDRESS (6'h02),
205
- .END_ADDRESS (6'h02),
206
- .INDIRECT_REGISTER (0),
207
- .INDIRECT_INDEX_WIDTH (1),
208
- .INDIRECT_INDEX_VALUE (1'h0)
209
- ) u_register_2_address_decoder (
210
- .i_address (address[7:2]),
211
- .i_indirect_index (1'h0),
212
- .o_select (register_select[2])
213
- );
214
- assign register_read_data[2] = {15'h0000, bit_field_2_0_value, 15'h0000, bit_field_2_1_value};
215
- rggen_bit_field_ro #(
216
- .WIDTH (1)
217
- ) u_bit_field_2_0 (
218
- .i_value (i_bit_field_2_0),
219
- .o_value (bit_field_2_0_value)
220
- );
221
- assign o_bit_field_2_1 = bit_field_2_1_value;
222
- rggen_bit_field_rw #(
223
- .WIDTH (1),
224
- .INITIAL_VALUE (1'h0)
225
- ) u_bit_field_2_1 (
226
- .clk (clk),
227
- .rst_n (rst_n),
228
- .i_command_valid (command_valid),
229
- .i_select (register_select[2]),
230
- .i_write (write),
231
- .i_write_data (write_data[0]),
232
- .i_write_mask (write_mask[0]),
233
- .o_value (bit_field_2_1_value)
234
- );
235
- rggen_address_decoder #(
236
- .ADDRESS_WIDTH (6),
237
- .START_ADDRESS (6'h03),
238
- .END_ADDRESS (6'h03),
239
- .INDIRECT_REGISTER (0),
240
- .INDIRECT_INDEX_WIDTH (1),
241
- .INDIRECT_INDEX_VALUE (1'h0)
242
- ) u_register_3_address_decoder (
243
- .i_address (address[7:2]),
244
- .i_indirect_index (1'h0),
245
- .o_select (register_select[3])
246
- );
247
- assign register_read_data[3] = {bit_field_3_0_value};
248
- rggen_bit_field_ro #(
249
- .WIDTH (32)
250
- ) u_bit_field_3_0 (
251
- .i_value (i_bit_field_3_0),
252
- .o_value (bit_field_3_0_value)
253
- );
57
+ generate if (1) begin : g_register_0
58
+ rggen_bit_field_if #(32) bit_field_if();
59
+ rggen_bit_field_if #(16) bit_field_0_0_if();
60
+ rggen_bit_field_if #(16) bit_field_0_1_if();
61
+ rggen_default_register #(
62
+ .ADDRESS_WIDTH (8),
63
+ .START_ADDRESS (8'h00),
64
+ .END_ADDRESS (8'h03),
65
+ .DATA_WIDTH (32),
66
+ .VALID_BITS (32'hffffffff)
67
+ ) u_register_0 (
68
+ .register_if (register_if[0]),
69
+ .bit_field_if (bit_field_if)
70
+ );
71
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_0_0_if, 31, 16)
72
+ rggen_bit_field_rw #(
73
+ .WIDTH (16),
74
+ .INITIAL_VALUE (16'h0000)
75
+ ) u_bit_field_0_0 (
76
+ .clk (clk),
77
+ .rst_n (rst_n),
78
+ .bit_field_if (bit_field_0_0_if),
79
+ .o_value (o_bit_field_0_0)
80
+ );
81
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_0_1_if, 15, 0)
82
+ rggen_bit_field_rw #(
83
+ .WIDTH (16),
84
+ .INITIAL_VALUE (16'h0000)
85
+ ) u_bit_field_0_1 (
86
+ .clk (clk),
87
+ .rst_n (rst_n),
88
+ .bit_field_if (bit_field_0_1_if),
89
+ .o_value (o_bit_field_0_1)
90
+ );
91
+ end endgenerate
92
+ generate if (1) begin : g_register_1
93
+ rggen_bit_field_if #(32) bit_field_if();
94
+ rggen_bit_field_if #(32) bit_field_1_0_if();
95
+ rggen_default_register #(
96
+ .ADDRESS_WIDTH (8),
97
+ .START_ADDRESS (8'h04),
98
+ .END_ADDRESS (8'h07),
99
+ .DATA_WIDTH (32),
100
+ .VALID_BITS (32'hffffffff)
101
+ ) u_register_1 (
102
+ .register_if (register_if[1]),
103
+ .bit_field_if (bit_field_if)
104
+ );
105
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_1_0_if, 31, 0)
106
+ rggen_bit_field_rw #(
107
+ .WIDTH (32),
108
+ .INITIAL_VALUE (32'h00000000)
109
+ ) u_bit_field_1_0 (
110
+ .clk (clk),
111
+ .rst_n (rst_n),
112
+ .bit_field_if (bit_field_1_0_if),
113
+ .o_value (o_bit_field_1_0)
114
+ );
115
+ end endgenerate
116
+ generate if (1) begin : g_register_2
117
+ rggen_bit_field_if #(32) bit_field_if();
118
+ rggen_bit_field_if #(1) bit_field_2_0_if();
119
+ rggen_bit_field_if #(1) bit_field_2_1_if();
120
+ rggen_default_register #(
121
+ .ADDRESS_WIDTH (8),
122
+ .START_ADDRESS (8'h08),
123
+ .END_ADDRESS (8'h0b),
124
+ .DATA_WIDTH (32),
125
+ .VALID_BITS (32'h00010001)
126
+ ) u_register_2 (
127
+ .register_if (register_if[2]),
128
+ .bit_field_if (bit_field_if)
129
+ );
130
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_2_0_if, 16, 16)
131
+ rggen_bit_field_ro #(
132
+ .WIDTH (1)
133
+ ) u_bit_field_2_0 (
134
+ .bit_field_if (bit_field_2_0_if),
135
+ .i_value (i_bit_field_2_0)
136
+ );
137
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_2_1_if, 0, 0)
138
+ rggen_bit_field_rw #(
139
+ .WIDTH (1),
140
+ .INITIAL_VALUE (1'h0)
141
+ ) u_bit_field_2_1 (
142
+ .clk (clk),
143
+ .rst_n (rst_n),
144
+ .bit_field_if (bit_field_2_1_if),
145
+ .o_value (o_bit_field_2_1)
146
+ );
147
+ end endgenerate
148
+ generate if (1) begin : g_register_3
149
+ rggen_bit_field_if #(32) bit_field_if();
150
+ rggen_bit_field_if #(32) bit_field_3_0_if();
151
+ rggen_default_register #(
152
+ .ADDRESS_WIDTH (8),
153
+ .START_ADDRESS (8'h0c),
154
+ .END_ADDRESS (8'h0f),
155
+ .DATA_WIDTH (32),
156
+ .VALID_BITS (32'hffffffff)
157
+ ) u_register_3 (
158
+ .register_if (register_if[3]),
159
+ .bit_field_if (bit_field_if)
160
+ );
161
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_3_0_if, 31, 0)
162
+ rggen_bit_field_ro #(
163
+ .WIDTH (32)
164
+ ) u_bit_field_3_0 (
165
+ .bit_field_if (bit_field_3_0_if),
166
+ .i_value (i_bit_field_3_0)
167
+ );
168
+ end endgenerate
254
169
  generate if (1) begin : g_register_4
255
170
  genvar g_i;
256
- for (g_i = 0;g_i < 4;g_i++) begin : g
257
- rggen_address_decoder #(
258
- .ADDRESS_WIDTH (6),
259
- .START_ADDRESS (6'h04 + g_i),
260
- .END_ADDRESS (6'h04 + g_i),
261
- .INDIRECT_REGISTER (0),
262
- .INDIRECT_INDEX_WIDTH (1),
263
- .INDIRECT_INDEX_VALUE (1'h0)
264
- ) u_register_4_address_decoder (
265
- .i_address (address[7:2]),
266
- .i_indirect_index (1'h0),
267
- .o_select (register_select[4+g_i])
171
+ for (g_i = 0;g_i < 4;++g_i) begin : g
172
+ rggen_bit_field_if #(32) bit_field_if();
173
+ rggen_bit_field_if #(16) bit_field_4_0_if();
174
+ rggen_bit_field_if #(16) bit_field_4_1_if();
175
+ rggen_default_register #(
176
+ .ADDRESS_WIDTH (8),
177
+ .START_ADDRESS (8'h10 + 8'h04 * g_i),
178
+ .END_ADDRESS (8'h13 + 8'h04 * g_i),
179
+ .DATA_WIDTH (32),
180
+ .VALID_BITS (32'hffffffff)
181
+ ) u_register_4 (
182
+ .register_if (register_if[4+g_i]),
183
+ .bit_field_if (bit_field_if)
268
184
  );
269
- assign register_read_data[4+g_i] = {bit_field_4_0_value[g_i], bit_field_4_1_value[g_i]};
185
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_4_0_if, 31, 16)
270
186
  rggen_bit_field_ro #(
271
187
  .WIDTH (16)
272
188
  ) u_bit_field_4_0 (
273
- .i_value (i_bit_field_4_0[g_i]),
274
- .o_value (bit_field_4_0_value[g_i])
189
+ .bit_field_if (bit_field_4_0_if),
190
+ .i_value (i_bit_field_4_0[g_i])
275
191
  );
276
- assign o_bit_field_4_1[g_i] = bit_field_4_1_value[g_i];
192
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_4_1_if, 15, 0)
277
193
  rggen_bit_field_rw #(
278
194
  .WIDTH (16),
279
195
  .INITIAL_VALUE (16'h0000)
280
196
  ) u_bit_field_4_1 (
281
- .clk (clk),
282
- .rst_n (rst_n),
283
- .i_command_valid (command_valid),
284
- .i_select (register_select[4+g_i]),
285
- .i_write (write),
286
- .i_write_data (write_data[15:0]),
287
- .i_write_mask (write_mask[15:0]),
288
- .o_value (bit_field_4_1_value[g_i])
197
+ .clk (clk),
198
+ .rst_n (rst_n),
199
+ .bit_field_if (bit_field_4_1_if),
200
+ .o_value (o_bit_field_4_1[g_i])
289
201
  );
290
202
  end
291
203
  end endgenerate
292
204
  generate if (1) begin : g_register_5
293
- genvar g_i, g_j;
294
- for (g_i = 0;g_i < 2;g_i++) begin : g
295
- for (g_j = 0;g_j < 4;g_j++) begin : g
296
- assign register_5_indirect_index[g_i][g_j] = {bit_field_2_1_value, bit_field_0_0_value, bit_field_0_1_value};
297
- rggen_address_decoder #(
298
- .ADDRESS_WIDTH (6),
299
- .START_ADDRESS (6'h08),
300
- .END_ADDRESS (6'h08),
301
- .INDIRECT_REGISTER (1),
302
- .INDIRECT_INDEX_WIDTH (33),
303
- .INDIRECT_INDEX_VALUE ({1'h1, g_i[15:0], g_j[15:0]})
304
- ) u_register_5_address_decoder (
305
- .i_address (address[7:2]),
306
- .i_indirect_index (register_5_indirect_index[g_i][g_j]),
307
- .o_select (register_select[8+4*g_i+g_j])
205
+ genvar g_i;
206
+ for (g_i = 0;g_i < 2;++g_i) begin : g
207
+ genvar g_j;
208
+ for (g_j = 0;g_j < 4;++g_j) begin : g
209
+ rggen_bit_field_if #(32) bit_field_if();
210
+ logic [32:0] indirect_index;
211
+ rggen_bit_field_if #(16) bit_field_5_0_if();
212
+ rggen_bit_field_if #(16) bit_field_5_1_if();
213
+ assign indirect_index = {register_if[2].value[0], register_if[0].value[31:16], register_if[0].value[15:0]};
214
+ rggen_indirect_register #(
215
+ .ADDRESS_WIDTH (8),
216
+ .START_ADDRESS (8'h20),
217
+ .END_ADDRESS (8'h23),
218
+ .INDEX_WIDTH (33),
219
+ .INDEX_VALUE ({1'h1, g_i[15:0], g_j[15:0]}),
220
+ .DATA_WIDTH (32),
221
+ .VALID_BITS (32'hffffffff)
222
+ ) u_register_5 (
223
+ .register_if (register_if[8+4*g_i+g_j]),
224
+ .bit_field_if (bit_field_if),
225
+ .i_index (indirect_index)
308
226
  );
309
- assign register_read_data[8+4*g_i+g_j] = {bit_field_5_0_value[g_i][g_j], bit_field_5_1_value[g_i][g_j]};
227
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_5_0_if, 31, 16)
310
228
  rggen_bit_field_ro #(
311
229
  .WIDTH (16)
312
230
  ) u_bit_field_5_0 (
313
- .i_value (i_bit_field_5_0[g_i][g_j]),
314
- .o_value (bit_field_5_0_value[g_i][g_j])
231
+ .bit_field_if (bit_field_5_0_if),
232
+ .i_value (i_bit_field_5_0[g_i][g_j])
315
233
  );
316
- assign o_bit_field_5_1[g_i][g_j] = bit_field_5_1_value[g_i][g_j];
234
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_5_1_if, 15, 0)
317
235
  rggen_bit_field_rw #(
318
236
  .WIDTH (16),
319
237
  .INITIAL_VALUE (16'h0000)
320
238
  ) u_bit_field_5_1 (
321
- .clk (clk),
322
- .rst_n (rst_n),
323
- .i_command_valid (command_valid),
324
- .i_select (register_select[8+4*g_i+g_j]),
325
- .i_write (write),
326
- .i_write_data (write_data[15:0]),
327
- .i_write_mask (write_mask[15:0]),
328
- .o_value (bit_field_5_1_value[g_i][g_j])
239
+ .clk (clk),
240
+ .rst_n (rst_n),
241
+ .bit_field_if (bit_field_5_1_if),
242
+ .o_value (o_bit_field_5_1[g_i][g_j])
329
243
  );
330
244
  end
331
245
  end
332
246
  end endgenerate
333
- rggen_address_decoder #(
334
- .ADDRESS_WIDTH (6),
335
- .START_ADDRESS (6'h09),
336
- .END_ADDRESS (6'h09),
337
- .INDIRECT_REGISTER (0),
338
- .INDIRECT_INDEX_WIDTH (1),
339
- .INDIRECT_INDEX_VALUE (1'h0)
340
- ) u_register_6_address_decoder (
341
- .i_address (address[7:2]),
342
- .i_indirect_index (1'h0),
343
- .o_select (register_select[16])
344
- );
345
- assign register_read_data[16] = {23'h000000, bit_field_6_0_value, 7'h00, bit_field_6_1_value};
346
- rggen_bit_field_w01s_w01c #(
347
- .WIDTH (1),
348
- .INITIAL_VALUE (1'h0),
349
- .SET_MODE (0),
350
- .SET_CLEAR_VALUE (0)
351
- ) u_bit_field_6_0 (
352
- .clk (clk),
353
- .rst_n (rst_n),
354
- .i_set_or_clear (i_bit_field_6_0_set),
355
- .i_command_valid (command_valid),
356
- .i_select (register_select[16]),
357
- .i_write (write),
358
- .i_write_data (write_data[8]),
359
- .i_write_mask (write_mask[8]),
360
- .o_value (bit_field_6_0_value)
361
- );
362
- rggen_bit_field_w01s_w01c #(
363
- .WIDTH (1),
364
- .INITIAL_VALUE (1'h0),
365
- .SET_MODE (0),
366
- .SET_CLEAR_VALUE (1)
367
- ) u_bit_field_6_1 (
368
- .clk (clk),
369
- .rst_n (rst_n),
370
- .i_set_or_clear (i_bit_field_6_1_set),
371
- .i_command_valid (command_valid),
372
- .i_select (register_select[16]),
373
- .i_write (write),
374
- .i_write_data (write_data[0]),
375
- .i_write_mask (write_mask[0]),
376
- .o_value (bit_field_6_1_value)
377
- );
378
- rggen_address_decoder #(
379
- .ADDRESS_WIDTH (6),
380
- .START_ADDRESS (6'h0a),
381
- .END_ADDRESS (6'h0a),
382
- .INDIRECT_REGISTER (0),
383
- .INDIRECT_INDEX_WIDTH (1),
384
- .INDIRECT_INDEX_VALUE (1'h0)
385
- ) u_register_7_address_decoder (
386
- .i_address (address[7:2]),
387
- .i_indirect_index (1'h0),
388
- .o_select (register_select[17])
389
- );
390
- assign register_read_data[17] = {23'h000000, bit_field_7_0_value, 7'h00, bit_field_7_1_value};
391
- assign o_bit_field_7_0 = bit_field_7_0_value;
392
- rggen_bit_field_w01s_w01c #(
393
- .WIDTH (1),
394
- .INITIAL_VALUE (1'h0),
395
- .SET_MODE (1),
396
- .SET_CLEAR_VALUE (0)
397
- ) u_bit_field_7_0 (
398
- .clk (clk),
399
- .rst_n (rst_n),
400
- .i_set_or_clear (i_bit_field_7_0_clear),
401
- .i_command_valid (command_valid),
402
- .i_select (register_select[17]),
403
- .i_write (write),
404
- .i_write_data (write_data[8]),
405
- .i_write_mask (write_mask[8]),
406
- .o_value (bit_field_7_0_value)
407
- );
408
- assign o_bit_field_7_1 = bit_field_7_1_value;
409
- rggen_bit_field_w01s_w01c #(
410
- .WIDTH (1),
411
- .INITIAL_VALUE (1'h0),
412
- .SET_MODE (1),
413
- .SET_CLEAR_VALUE (1)
414
- ) u_bit_field_7_1 (
415
- .clk (clk),
416
- .rst_n (rst_n),
417
- .i_set_or_clear (i_bit_field_7_1_clear),
418
- .i_command_valid (command_valid),
419
- .i_select (register_select[17]),
420
- .i_write (write),
421
- .i_write_data (write_data[0]),
422
- .i_write_mask (write_mask[0]),
423
- .o_value (bit_field_7_1_value)
424
- );
425
- rggen_address_decoder #(
426
- .ADDRESS_WIDTH (6),
427
- .START_ADDRESS (6'h0b),
428
- .END_ADDRESS (6'h0b),
429
- .INDIRECT_REGISTER (0),
430
- .INDIRECT_INDEX_WIDTH (1),
431
- .INDIRECT_INDEX_VALUE (1'h0)
432
- ) u_register_8_address_decoder (
433
- .i_address (address[7:2]),
434
- .i_indirect_index (1'h0),
435
- .o_select (register_select[18])
436
- );
437
- assign register_read_data[18] = {bit_field_8_0_value, bit_field_8_1_value};
438
- assign o_bit_field_8_0 = bit_field_8_0_value;
439
- rggen_bit_field_rwl_rwe #(
440
- .LOCK_MODE (1),
441
- .WIDTH (16),
442
- .INITIAL_VALUE (16'h0000)
443
- ) u_bit_field_8_0 (
444
- .clk (clk),
445
- .rst_n (rst_n),
446
- .i_lock_or_enable (bit_field_2_1_value),
447
- .i_command_valid (command_valid),
448
- .i_select (register_select[18]),
449
- .i_write (write),
450
- .i_write_data (write_data[31:16]),
451
- .i_write_mask (write_mask[31:16]),
452
- .o_value (bit_field_8_0_value)
453
- );
454
- assign o_bit_field_8_1 = bit_field_8_1_value;
455
- rggen_bit_field_rwl_rwe #(
456
- .LOCK_MODE (0),
457
- .WIDTH (16),
458
- .INITIAL_VALUE (16'h0000)
459
- ) u_bit_field_8_1 (
460
- .clk (clk),
461
- .rst_n (rst_n),
462
- .i_lock_or_enable (bit_field_2_1_value),
463
- .i_command_valid (command_valid),
464
- .i_select (register_select[18]),
465
- .i_write (write),
466
- .i_write_data (write_data[15:0]),
467
- .i_write_mask (write_mask[15:0]),
468
- .o_value (bit_field_8_1_value)
469
- );
470
- rggen_address_decoder #(
471
- .ADDRESS_WIDTH (6),
472
- .START_ADDRESS (6'h20),
473
- .END_ADDRESS (6'h3f),
474
- .INDIRECT_REGISTER (0),
475
- .INDIRECT_INDEX_WIDTH (1),
476
- .INDIRECT_INDEX_VALUE (1'h0)
477
- ) u_register_9_address_decoder (
478
- .i_address (address[7:2]),
479
- .i_indirect_index (1'h0),
480
- .o_select (register_select[19])
481
- );
482
- assign external_register_select[0] = register_select[19];
483
- rggen_bus_exporter #(
484
- .DATA_WIDTH (32),
485
- .LOCAL_ADDRESS_WIDTH (8),
486
- .EXTERNAL_ADDRESS_WIDTH (7),
487
- .START_ADDRESS (8'h80)
488
- ) u_register_9_bus_exporter (
489
- .clk (clk),
490
- .rst_n (rst_n),
491
- .i_valid (command_valid),
492
- .i_select (register_select[19]),
493
- .i_write (write),
494
- .i_read (read),
495
- .i_address (address),
496
- .i_strobe (strobe),
497
- .i_write_data (write_data),
498
- .o_ready (external_register_ready[0]),
499
- .o_read_data (register_read_data[19]),
500
- .o_status (external_register_status[0]),
501
- .o_valid (o_register_9_valid),
502
- .o_write (o_register_9_write),
503
- .o_read (o_register_9_read),
504
- .o_address (o_register_9_address),
505
- .o_strobe (o_register_9_strobe),
506
- .o_write_data (o_register_9_write_data),
507
- .i_ready (i_register_9_ready),
508
- .i_read_data (i_register_9_read_data),
509
- .i_status (i_register_9_status)
510
- );
247
+ generate if (1) begin : g_register_6
248
+ rggen_bit_field_if #(32) bit_field_if();
249
+ rggen_bit_field_if #(1) bit_field_6_0_if();
250
+ rggen_bit_field_if #(1) bit_field_6_1_if();
251
+ rggen_default_register #(
252
+ .ADDRESS_WIDTH (8),
253
+ .START_ADDRESS (8'h24),
254
+ .END_ADDRESS (8'h27),
255
+ .DATA_WIDTH (32),
256
+ .VALID_BITS (32'h00000101)
257
+ ) u_register_6 (
258
+ .register_if (register_if[16]),
259
+ .bit_field_if (bit_field_if)
260
+ );
261
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_6_0_if, 8, 8)
262
+ rggen_bit_field_w01s_w01c #(
263
+ .MODE (rggen_rtl_pkg::RGGEN_CLEAR_MODE),
264
+ .SET_CLEAR_VALUE (0),
265
+ .WIDTH (1),
266
+ .INITIAL_VALUE (1'h0)
267
+ ) u_bit_field_6_0 (
268
+ .clk (clk),
269
+ .rst_n (rst_n),
270
+ .i_set_or_clear (i_bit_field_6_0_set),
271
+ .bit_field_if (bit_field_6_0_if),
272
+ .o_value ()
273
+ );
274
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_6_1_if, 0, 0)
275
+ rggen_bit_field_w01s_w01c #(
276
+ .MODE (rggen_rtl_pkg::RGGEN_CLEAR_MODE),
277
+ .SET_CLEAR_VALUE (1),
278
+ .WIDTH (1),
279
+ .INITIAL_VALUE (1'h0)
280
+ ) u_bit_field_6_1 (
281
+ .clk (clk),
282
+ .rst_n (rst_n),
283
+ .i_set_or_clear (i_bit_field_6_1_set),
284
+ .bit_field_if (bit_field_6_1_if),
285
+ .o_value ()
286
+ );
287
+ end endgenerate
288
+ generate if (1) begin : g_register_7
289
+ rggen_bit_field_if #(32) bit_field_if();
290
+ rggen_bit_field_if #(1) bit_field_7_0_if();
291
+ rggen_bit_field_if #(1) bit_field_7_1_if();
292
+ rggen_default_register #(
293
+ .ADDRESS_WIDTH (8),
294
+ .START_ADDRESS (8'h28),
295
+ .END_ADDRESS (8'h2b),
296
+ .DATA_WIDTH (32),
297
+ .VALID_BITS (32'h00000101)
298
+ ) u_register_7 (
299
+ .register_if (register_if[17]),
300
+ .bit_field_if (bit_field_if)
301
+ );
302
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_7_0_if, 8, 8)
303
+ rggen_bit_field_w01s_w01c #(
304
+ .MODE (rggen_rtl_pkg::RGGEN_SET_MODE),
305
+ .SET_CLEAR_VALUE (0),
306
+ .WIDTH (1),
307
+ .INITIAL_VALUE (1'h0)
308
+ ) u_bit_field_7_0 (
309
+ .clk (clk),
310
+ .rst_n (rst_n),
311
+ .i_set_or_clear (i_bit_field_7_0_clear),
312
+ .bit_field_if (bit_field_7_0_if),
313
+ .o_value (o_bit_field_7_0)
314
+ );
315
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_7_1_if, 0, 0)
316
+ rggen_bit_field_w01s_w01c #(
317
+ .MODE (rggen_rtl_pkg::RGGEN_SET_MODE),
318
+ .SET_CLEAR_VALUE (1),
319
+ .WIDTH (1),
320
+ .INITIAL_VALUE (1'h0)
321
+ ) u_bit_field_7_1 (
322
+ .clk (clk),
323
+ .rst_n (rst_n),
324
+ .i_set_or_clear (i_bit_field_7_1_clear),
325
+ .bit_field_if (bit_field_7_1_if),
326
+ .o_value (o_bit_field_7_1)
327
+ );
328
+ end endgenerate
329
+ generate if (1) begin : g_register_8
330
+ rggen_bit_field_if #(32) bit_field_if();
331
+ rggen_bit_field_if #(16) bit_field_8_0_if();
332
+ rggen_bit_field_if #(16) bit_field_8_1_if();
333
+ rggen_default_register #(
334
+ .ADDRESS_WIDTH (8),
335
+ .START_ADDRESS (8'h2c),
336
+ .END_ADDRESS (8'h2f),
337
+ .DATA_WIDTH (32),
338
+ .VALID_BITS (32'hffffffff)
339
+ ) u_register_8 (
340
+ .register_if (register_if[18]),
341
+ .bit_field_if (bit_field_if)
342
+ );
343
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_8_0_if, 31, 16)
344
+ rggen_bit_field_rwl_rwe #(
345
+ .MODE (rggen_rtl_pkg::RGGEN_LOCK_MODE),
346
+ .WIDTH (16),
347
+ .INITIAL_VALUE (16'h0000)
348
+ ) u_bit_field_8_0 (
349
+ .clk (clk),
350
+ .rst_n (rst_n),
351
+ .i_lock_or_enable (register_if[2].value[0]),
352
+ .bit_field_if (bit_field_8_0_if),
353
+ .o_value (o_bit_field_8_0)
354
+ );
355
+ `rggen_connect_bit_field_if(bit_field_if, bit_field_8_1_if, 15, 0)
356
+ rggen_bit_field_rwl_rwe #(
357
+ .MODE (rggen_rtl_pkg::RGGEN_ENABLE_MODE),
358
+ .WIDTH (16),
359
+ .INITIAL_VALUE (16'h0000)
360
+ ) u_bit_field_8_1 (
361
+ .clk (clk),
362
+ .rst_n (rst_n),
363
+ .i_lock_or_enable (register_if[2].value[0]),
364
+ .bit_field_if (bit_field_8_1_if),
365
+ .o_value (o_bit_field_8_1)
366
+ );
367
+ end endgenerate
368
+ generate if (1) begin : g_register_9
369
+ rggen_external_register #(
370
+ .ADDRESS_WIDTH (8),
371
+ .START_ADDRESS (8'h80),
372
+ .END_ADDRESS (8'hff),
373
+ .DATA_WIDTH (32)
374
+ ) u_register_9 (
375
+ .clk (clk),
376
+ .rst_n (rst_n),
377
+ .register_if (register_if[19]),
378
+ .bus_if (register_9_bus_if)
379
+ );
380
+ end endgenerate
381
+ `undef rggen_connect_bit_field_if
511
382
  endmodule