rggen 0.5.1 → 0.6.0

data/lib/rggen/builtins/register/address_decoder.erb

@@ -1,12 +0,0 @@
-rggen_address_decoder #(
-  .ADDRESS_WIDTH        (<%= local_address_width - address_lsb %>),
-  .START_ADDRESS        (<%= start_address%>),
-  .END_ADDRESS          (<%= end_address %>),
-  .INDIRECT_REGISTER    (<%= indirect_register %>),
-  .INDIRECT_INDEX_WIDTH (<%= indirect_index_width %>),
-  .INDIRECT_INDEX_VALUE (<%= indirect_index_value %>)
-) u_<%= register.name%>_address_decoder (
-  .i_address        (<%= register_block.host_if.address[local_address_width - 1, address_lsb] %>),
-  .i_indirect_index (<%= (type?(:indirect) && indirect_index[loop_variables]) || indirect_index_value %>),
-  .o_select         (<%= register_block.register_select[register.index] %>)
-);

data/lib/rggen/builtins/register/address_decoder.rb

@@ -1,82 +0,0 @@
-simple_item :register, :address_decoder do
-  rtl do
-    build do
-      next unless type?(:indirect)
-      logic :indirect_index,
-            name:       "#{register.name}_indirect_index",
-            width:      indirect_index_width,
-            dimensions: register.dimensions
-    end
-
-    generate_code :module_item do |buffer|
-      buffer << indirect_index_assignment << nl if type?(:indirect)
-      buffer << process_template
-    end
-
-    delegate [:local_address_width] => :register_block
-    delegate [:array?, :type?, :multiple?] => :register
-    delegate [:indexes, :loop_variables] => :register
-
-    def address_lsb
-      Math.clog2(configuration.byte_width)
-    end
-
-    def start_address
-      address_code(register.start_address)
-    end
-
-    def end_address
-      if array?
-        address = register.start_address + configuration.byte_width - 1
-        address_code(address)
-      else
-        address_code(register.end_address)
-      end
-    end
-
-    def address_code(address)
-      shift = address_lsb
-      base  = hex(address >> shift, local_address_width - shift)
-      (array? && multiple? && "#{base} + #{register.local_index}") || base
-    end
-
-    def indirect_index_assignment
-      assign(
-        indirect_index[register.loop_variables],
-        concat(indirect_index_fields.map(&:value))
-      )
-    end
-
-    def indirect_register
-      (type?(:indirect) && 1) || 0
-    end
-
-    def indirect_index_width
-      return 1 unless type?(:indirect)
-      indirect_index_fields.sum(0, &:width)
-    end
-
-    def indirect_index_value
-      return hex(0, 1) unless type?(:indirect)
-      concat(indirect_index_values)
-    end
-
-    def indirect_index_fields
-      @indirect_index_fields ||= indexes.map do |index|
-        register_block.bit_fields.find_by(name: index.name)
-      end
-    end
-
-    def indirect_index_values
-      variables = loop_variables
-      indexes.map.with_index do |index, i|
-        if index.value
-          hex(index.value, indirect_index_fields[i].width)
-        else
-          loop_variable = variables.shift
-          loop_variable[indirect_index_fields[i].width - 1, 0]
-        end
-      end
-    end
-  end
-end

data/lib/rggen/builtins/register/bus_exporter.erb

@@ -1,28 +0,0 @@
-rggen_bus_exporter #(
-  .DATA_WIDTH             (<%= configuration.data_width %>),
-  .LOCAL_ADDRESS_WIDTH    (<%= register_block.local_address_width %>),
-  .EXTERNAL_ADDRESS_WIDTH (<%= address_width %>),
-  .START_ADDRESS          (<%= start_address %>)
-) u_<%= name %>_bus_exporter (
-  .clk          (<%= register_block.clock %>),
-  .rst_n        (<%= register_block.reset %>),
-  .i_valid      (<%= register_block.host_if.command_valid %>),
-  .i_select     (<%= register_block.register_select[index] %>),
-  .i_write      (<%= register_block.host_if.write %>),
-  .i_read       (<%= register_block.host_if.read %>),
-  .i_address    (<%= register_block.host_if.address %>),
-  .i_strobe     (<%= register_block.host_if.strobe %>),
-  .i_write_data (<%= register_block.host_if.write_data %>),
-  .o_ready      (<%= register_block.external_register_ready[external_index] %>),
-  .o_read_data  (<%= register_block.register_read_data[index] %>),
-  .o_status     (<%= register_block.external_register_status[external_index] %>),
-  .o_valid      (<%= valid %>),
-  .o_write      (<%= write %>),
-  .o_read       (<%= read %>),
-  .o_address    (<%= address %>),
-  .o_strobe     (<%= strobe %>),
-  .o_write_data (<%= write_data %>),
-  .i_ready      (<%= ready %>),
-  .i_read_data  (<%= read_data %>),
-  .i_status     (<%= status %>)
-);

data/lib/rggen/builtins/register/bus_exporter.rb

@@ -1,52 +0,0 @@
-simple_item :register, :bus_exporter do
-  rtl do
-    delegate [
-      :data_width, :byte_width
-    ] => :configuration
-    delegate [
-      :name, :byte_size, :index, :external_index
-    ] => :register
-
-    available? { register.type?(:external) }
-
-    build do
-      output :valid     , name: "o_#{name}_valid"     , width: 1
-      output :write     , name: "o_#{name}_write"     , width: 1
-      output :read      , name: "o_#{name}_read"      , width: 1
-      output :address   , name: "o_#{name}_address"   , width: address_width
-      output :strobe    , name: "o_#{name}_strobe"    , width: byte_width
-      output :write_data, name: "o_#{name}_write_data", width: data_width
-      input  :ready     , name: "i_#{name}_ready"     , width: 1
-      input  :status    , name: "i_#{name}_status"    , width: 2
-      input  :read_data , name: "i_#{name}_read_data" , width: data_width
-    end
-
-    generate_code :module_item do |code|
-      code << register_select_connection << nl
-      code << process_template
-    end
-
-    def address_width
-      Math.clog2(byte_size)
-    end
-
-    def register_select_connection
-      assign(
-        register_block.external_register_select[external_index],
-        register_block.register_select[index]
-      )
-    end
-
-    def start_address
-      hex(register.start_address, register_block.local_address_width)
-    end
-
-    def external_index
-      external_registers.index(&register.method(:equal?))
-    end
-
-    def external_registers
-      register_block.registers.select { |r| r.type?(:external) }
-    end
-  end
-end

data/lib/rggen/builtins/register/read_data.rb

@@ -1,61 +0,0 @@
-simple_item :register, :read_data do
-  rtl do
-    available? { !register.type?(:external) }
-
-    generate_code :module_item do |buffer|
-      buffer  << assign(register_read_data, read_data) << nl
-    end
-
-    define_struct :read_data_entry, [:lsb, :msb, :value, :dummy] do
-      def initialize(args)
-        self.lsb    = args[:lsb]
-        self.msb    = args[:msb]
-        self.value  = args[:value]
-        self.dummy  = args[:dummy] || false
-      end
-    end
-
-    delegate [:data_width] => :configuration
-    delegate [:loop_variables] => :register
-
-    def register_read_data
-      register_block.register_read_data[register.index]
-    end
-
-    def read_data
-      if register.readable?
-        concat(read_data_expressions)
-      else
-        hex(0, configuration.data_width)
-      end
-    end
-
-    def read_data_expressions
-      read_data_entries.each_cons(2).with_object([]) do |entries, expressions|
-        padding_bits  = entries[0].lsb - entries[1].msb - 1
-        expressions << hex(0, padding_bits) if padding_bits > 0
-        expressions << entries[1].value unless entries[1].dummy
-      end
-    end
-
-    def read_data_entries
-      [].tap do |entries|
-        entries << read_data_entry.new(lsb: data_width, dummy: true)
-        entries.concat(readable_field_entries)
-        entries << read_data_entry.new(msb: -1, dummy: true)
-      end
-    end
-
-    def readable_field_entries
-      readable_fields.map do |field|
-        read_data_entry.new(
-          lsb: field.lsb, msb: field.msb, value: field.value[loop_variables]
-        )
-      end
-    end
-
-    def readable_fields
-      register.bit_fields.select(&:readable?).sort_by(&:msb).reverse
-    end
-  end
-end

data/lib/rggen/builtins/register_block/response_mux.erb

@@ -1,18 +0,0 @@
-rggen_response_mux #(
-  .DATA_WIDTH               (<%= configuration.data_width %>),
-  .TOTAL_REGISTERS          (<%= total_registers %>),
-  .TOTAL_EXTERNAL_REGISTERS (<%= total_external_registers %>)
-) u_response_mux (
-  .clk                        (<%= register_block.clock %>),
-  .rst_n                      (<%= register_block.reset %>),
-  .i_command_valid            (<%= register_block.host_if.command_valid %>),
-  .i_read                     (<%= register_block.host_if.read %>),
-  .o_response_ready           (<%= register_block.host_if.response_ready %>),
-  .o_read_data                (<%= register_block.host_if.read_data %>),
-  .o_status                   (<%= register_block.host_if.status %>),
-  .i_register_select          (<%= register_select %>),
-  .i_register_read_data       (<%= register_read_data %>),
-  .i_external_register_select (<%= actual_external_register_select %>),
-  .i_external_register_ready  (<%= actual_external_register_ready %>),
-  .i_external_register_status (<%= actual_external_register_status %>)
-);

data/lib/rggen/builtins/register_block/response_mux.rb

@@ -1,47 +0,0 @@
-simple_item :register_block, :response_mux do
-  rtl do
-    build do
-      logic :register_select   , width: total_registers
-      logic :register_read_data,
-            width:      configuration.data_width,
-            dimensions: [total_registers]
-      if external_registers?
-        logic :external_register_select,
-              width:  total_external_registers,
-              vector: true
-        logic :external_register_ready ,
-              width:  total_external_registers,
-              vector: true
-        logic :external_register_status,
-              width:      2,
-              dimensions: [total_external_registers]
-      end
-    end
-
-    generate_code_from_template :module_item
-
-    def total_registers
-      register_block.registers.sum(0, &:count)
-    end
-
-    def external_registers?
-      register_block.registers.any? { |r| r.type?(:external) }
-    end
-
-    def total_external_registers
-      register_block.registers.count  { |r| r.type?(:external) }
-    end
-
-    def actual_external_register_select
-      (external_registers? && external_register_select) || bin(0, 1)
-    end
-
-    def actual_external_register_ready
-      (external_registers? && external_register_ready) || bin(0, 1)
-    end
-
-    def actual_external_register_status
-      (external_registers? && external_register_status)  || array(bin(0, 2))
-    end
-  end
-end

data/lib/rggen/builtins/register_block/top_module.rb

@@ -1,20 +0,0 @@
-define_simple_item :register_block, :top_module do
-  rtl do
-    write_file '<%= register_block.name %>.sv' do |f|
-      f.body { source_file_body }
-    end
-
-    def source_file_body
-      module_definition register_block.name do |m|
-        m.parameters register_block.parameter_declarations
-        m.ports      register_block.port_declarations
-        m.signals    register_block.signal_declarations
-        m.body { |code| module_body(code) }
-      end
-    end
-
-    def module_body(code)
-      register_block.generate_code(:module_item, :top_down, code)
-    end
-  end
-end

data/rtl/bit_field/rggen_bit_field_common.svh

@@ -1,15 +0,0 @@
-function automatic logic is_write_access(
-  input command_valid,
-  input select,
-  input write
-);
-  return (command_valid && select && write) ? 1'b1 : 1'b0;
-endfunction
-
-function automatic logic [WIDTH-1:0] get_write_data(
-  input [WIDTH-1:0] current_data,
-  input [WIDTH-1:0] write_data,
-  input [WIDTH-1:0] write_mask
-);
-  return (current_data & (~write_mask)) | (write_data & write_mask);
-endfunction

data/rtl/bit_field/rggen_bit_field_ro.sv

@@ -1,8 +0,0 @@
-module rggen_bit_field_ro #(
-  parameter WIDTH = 1
-)(
-  input   [WIDTH-1:0] i_value,
-  output  [WIDTH-1:0] o_value
-);
-  assign  o_value = i_value;
-endmodule

data/rtl/bit_field/rggen_bit_field_rw.sv

@@ -1,27 +0,0 @@
-module rggen_bit_field_rw #(
-  parameter WIDTH         = 1,
-  parameter INITIAL_VALUE = 0
-)(
-  input               clk,
-  input               rst_n,
-  input               i_command_valid,
-  input               i_select,
-  input               i_write,
-  input   [WIDTH-1:0] i_write_data,
-  input   [WIDTH-1:0] i_write_mask,
-  output  [WIDTH-1:0] o_value
-);
-  `include  "rggen_bit_field_common.svh"
-
-  logic [WIDTH-1:0] value;
-
-  assign  o_value = value;
-  always_ff @(posedge clk or negedge rst_n) begin
-    if (!rst_n) begin
-      value <= INITIAL_VALUE;
-    end
-    else if (is_write_access(i_command_valid, i_select, i_write)) begin
-      value <= get_write_data(value, i_write_data, i_write_mask);
-    end
-  end
-endmodule

data/rtl/bit_field/rggen_bit_field_rwl_rwe.sv

@@ -1,49 +0,0 @@
-module rggen_bit_field_rwl_rwe #(
-  parameter LOCK_MODE     = 1,
-  parameter WIDTH         = 1,
-  parameter INITIAL_VALUE = 0
-)(
-  input               clk,
-  input               rst_n,
-  input               i_lock_or_enable,
-  input               i_command_valid,
-  input               i_select,
-  input               i_write,
-  input   [WIDTH-1:0] i_write_data,
-  input   [WIDTH-1:0] i_write_mask,
-  output  [WIDTH-1:0] o_value
-);
-  `include  "rggen_bit_field_common.svh"
-
-  logic [WIDTH-1:0] value;
-
-  assign  o_value   = value;
-  always_ff @(posedge clk or negedge rst_n) begin
-    if (!rst_n) begin
-      value <= INITIAL_VALUE;
-    end
-    else if (
-      can_write(i_lock_or_enable, i_command_valid, i_select, i_write)
-    ) begin
-      value <= get_write_data(value, i_write_data, i_write_mask);
-    end
-  end
-
-  function automatic logic can_write(
-    input lock_or_enable,
-    input command_valid,
-    input select,
-    input write
-  );
-    if (LOCK_MODE) begin
-      return (
-        (!lock_or_enable) && is_write_access(command_valid, select, write)
-      ) ? 1'b1 : 1'b0;
-    end
-    else begin
-      return (
-        lock_or_enable && is_write_access(command_valid, select, write)
-      ) ? 1'b1 : 1'b0;
-    end
-  endfunction
-endmodule

data/rtl/bit_field/rggen_bit_field_w01s_w01c.sv

@@ -1,67 +0,0 @@
-module rggen_bit_field_w01s_w01c #(
-  parameter WIDTH           = 1,
-  parameter INITIAL_VALUE   = 0,
-  parameter SET_MODE        = 1,
-  parameter SET_CLEAR_VALUE = 0
-)(
-  input               clk,
-  input               rst_n,
-  input   [WIDTH-1:0] i_set_or_clear,
-  input               i_command_valid,
-  input               i_select,
-  input               i_write,
-  input   [WIDTH-1:0] i_write_data,
-  input   [WIDTH-1:0] i_write_mask,
-  output  [WIDTH-1:0] o_value
-);
-  `include  "rggen_bit_field_common.svh"
-
-  logic [WIDTH-1:0] value;
-
-  assign  o_value = value;
-  always_ff @(posedge clk or negedge rst_n) begin
-    if (!rst_n) begin
-      value <= INITIAL_VALUE;
-    end
-    else begin
-      value <= get_next_value(
-        i_set_or_clear,
-        value,
-        i_command_valid,
-        i_select,
-        i_write,
-        i_write_mask,
-        i_write_data
-      );
-    end
-  end
-
-  function automatic logic [WIDTH-1:0] get_next_value(
-    input [WIDTH-1:0] set_or_clear,
-    input [WIDTH-1:0] current_value,
-    input             command_valid,
-    input             select,
-    input             write,
-    input [WIDTH-1:0] write_mask,
-    input [WIDTH-1:0] write_data
-  );
-    logic [WIDTH-1:0] control_value;
-    logic [WIDTH-1:0] set;
-    logic [WIDTH-1:0] clear;
-    if (is_write_access(command_valid, select, write)) begin
-      control_value = write_mask & ((SET_CLEAR_VALUE) ? write_data : ~write_data);
-    end
-    else begin
-      control_value = '0;
-    end
-    if (SET_MODE) begin
-      set   = control_value;
-      clear = set_or_clear;
-    end
-    else begin
-      set   = set_or_clear;
-      clear = control_value;
-    end
-    return set | (current_value & (~clear));
-  endfunction
-endmodule