rggen 0.5.1 → 0.6.0

data/lib/rggen/version.rb

@@ -1,6 +1,6 @@
 module RgGen
   MAJOR   = 0
-  MINOR   = 5
-  TEENY   = 1
+  MINOR   = 6
+  TEENY   = 0
   VERSION = "#{MAJOR}.#{MINOR}.#{TEENY}".freeze
 end

data/ral/LICENSE

@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2017 Taichi Ishitani
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

data/ral/rggen_ral_macros.svh

@@ -3,12 +3,9 @@
 
 `define rggen_ral_create_field_model(handle, name, width, lsb, access, volatile, reset, has_reset, hdl_path) \
 begin \
-  string  __hdl_path  = hdl_path; \
   handle  = new(name); \
   handle.configure(this.cfg, this, width, lsb, access, volatile, reset, has_reset, 1, 1); \
-  if (__hdl_path.len() > 0) begin \
-    this.add_hdl_path_slice(__hdl_path, lsb, width); \
-  end \
+  this.add_field_hdl_path(hdl_path, lsb, width); \
 end
 
 `define rggen_ral_create_reg_model(handle, name, array_index, offset_address, rights, unmapped, hdl_path) \

data/ral/rggen_ral_reg.svh

@@ -3,6 +3,7 @@
 class rggen_ral_reg extends uvm_reg;
   protected int         indexes[$];
   protected uvm_object  cfg;
+  protected string      hdl_path_scopes[string];
 
   extern function new(string name, int unsigned n_bits, int has_coverage);
 
@@ -11,12 +12,16 @@ class rggen_ral_reg extends uvm_reg;
     uvm_reg_block blk_parent,
     uvm_reg_file  regfile_parent,
     int           indexes[$],
-    string        hdl_path = ""
+    string        hdl_path            = "",
+    bit           single_hdl_variable = 0
   );
   extern virtual function void build();
 
   extern virtual function uvm_reg_frontdoor create_frontdoor();
 
+  extern function void set_hdl_path_scope(string hdl_path_scope, string kind = "RTL");
+  extern function void add_field_hdl_path(string name, int offset, int size, string kind = "RTL", string separalor = ".");
+
   extern protected virtual function void set_cfg(uvm_object cfg);
   extern protected virtual function void create_fields();
 endclass
@@ -30,13 +35,20 @@ function void rggen_ral_reg::configure(
   uvm_reg_block blk_parent,
   uvm_reg_file  regfile_parent,
   int           indexes[$],
-  string        hdl_path
+  string        hdl_path,
+  bit           single_hdl_variable
 );
   foreach (indexes[i]) begin
     this.indexes.push_back(indexes[i]);
   end
   set_cfg(cfg);
-  super.configure(blk_parent, regfile_parent, hdl_path);
+  if (single_hdl_variable) begin
+    super.configure(blk_parent, regfile_parent, hdl_path);
+  end
+  else begin
+    super.configure(blk_parent, regfile_parent);
+    set_hdl_path_scope(hdl_path);
+  end
 endfunction
 
 function void rggen_ral_reg::build();
@@ -47,6 +59,26 @@ function uvm_reg_frontdoor rggen_ral_reg::create_frontdoor();
   return null;
 endfunction
 
+function void rggen_ral_reg::set_hdl_path_scope(string hdl_path_scope, string kind);
+  if (hdl_path_scope.len() > 0) begin
+    hdl_path_scopes[kind] = hdl_path_scope;
+  end
+endfunction
+
+function void rggen_ral_reg::add_field_hdl_path(string name, int offset, int size, string kind, string separalor);
+  string  path;
+  if (name.len() == 0) begin
+    return;
+  end
+  if (hdl_path_scopes.exists(kind) && (hdl_path_scopes[kind].len() > 0)) begin
+    path  = {hdl_path_scopes[kind], separalor, name};
+  end
+  else begin
+    path  = name;
+  end
+  add_hdl_path_slice(path, offset, size, 0, kind);
+endfunction
+
 function void rggen_ral_reg::set_cfg(uvm_object cfg);
   this.cfg  = cfg;
 endfunction

data/rtl/LICENSE

@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2017 Taichi Ishitani
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

data/rtl/compile.f

@@ -1,6 +1,21 @@
-+libext+.sv
-+incdir+${RGGEN_HOME}/rtl/register_block
-+incdir+${RGGEN_HOME}/rtl/bit_field
--y ${RGGEN_HOME}/rtl/bit_field
--y ${RGGEN_HOME}/rtl/register
--y ${RGGEN_HOME}/rtl/register_block
+${RGGEN_HOME}/rtl/rggen_rtl_pkg.sv
+${RGGEN_HOME}/rtl/rggen_bus_if.sv
+${RGGEN_HOME}/rtl/rggen_register_if.sv
+${RGGEN_HOME}/rtl/rggen_bit_field_if.sv
+${RGGEN_HOME}/rtl/rggen_bus_splitter.sv
+${RGGEN_HOME}/rtl/rggen_irq_controller.sv
+${RGGEN_HOME}/rtl/rggen_address_decoder.sv
+${RGGEN_HOME}/rtl/rggen_register_base.sv
+${RGGEN_HOME}/rtl/rggen_default_register.sv
+${RGGEN_HOME}/rtl/rggen_indirect_register.sv
+${RGGEN_HOME}/rtl/rggen_external_register.sv
+${RGGEN_HOME}/rtl/rggen_bit_field_ro.sv
+${RGGEN_HOME}/rtl/rggen_bit_field_rw.sv
+${RGGEN_HOME}/rtl/rggen_bit_field_rwl_rwe.sv
+${RGGEN_HOME}/rtl/rggen_bit_field_w01s_w01c.sv
+
+${RGGEN_HOME}/rtl/rggen_apb_if.sv
+${RGGEN_HOME}/rtl/rggen_host_if_apb.sv
+
+${RGGEN_HOME}/rtl/rggen_axi4lite_if.sv
+${RGGEN_HOME}/rtl/rggen_host_if_axi4lite.sv

data/rtl/rggen_address_decoder.sv

@@ -0,0 +1,23 @@
+module rggen_address_decoder #(
+  parameter int                     ADDRESS_WIDTH = 8,
+  parameter bit [ADDRESS_WIDTH-1:0] STAET_ADDRESS = '0,
+  parameter bit [ADDRESS_WIDTH-1:0] END_ADDRESS   = '0,
+  parameter int                     DATA_WIDTH    = 32
+)(
+  input   [ADDRESS_WIDTH-1:0] i_address,
+  output                      o_match
+);
+  localparam  int                         LSB       = $clog2(DATA_WIDTH / 8);
+  localparam  bit [ADDRESS_WIDTH-LSB-1:0] SADDRESS  = STAET_ADDRESS[ADDRESS_WIDTH-1:LSB];
+  localparam  bit [ADDRESS_WIDTH-LSB-1:0] EADDRESS  = END_ADDRESS[ADDRESS_WIDTH-1:LSB];
+
+  generate if (SADDRESS == EADDRESS) begin
+    assign  o_match = (i_address[ADDRESS_WIDTH-1:LSB] == SADDRESS) ? 1'b1 : 1'b0;
+  end
+  else begin
+    assign  o_match = (
+      (i_address[ADDRESS_WIDTH-1:LSB] >= SADDRESS) &&
+      (i_address[ADDRESS_WIDTH-1:LSB] <= EADDRESS)
+    ) ? 1'b1 : 1'b0;
+  end endgenerate
+endmodule

data/rtl/rggen_apb_if.sv

@@ -0,0 +1,41 @@
+interface rggen_apb_if #(
+  parameter int ADDRESS_WIDTH = 16,
+  parameter int DATA_WIDTH    = 32
+)();
+  logic                     psel;
+  logic                     penable;
+  logic [ADDRESS_WIDTH-1:0] paddr;
+  logic [2:0]               pprot;
+  logic                     pwrite;
+  logic [DATA_WIDTH-1:0]    pwdata;
+  logic [DATA_WIDTH/8-1:0]  pstrb;
+  logic                     pready;
+  logic [DATA_WIDTH-1:0]    prdata;
+  logic                     pslverr;
+
+  modport master (
+    output  psel,
+    output  penable,
+    output  paddr,
+    output  pprot,
+    output  pwrite,
+    output  pwdata,
+    output  pstrb,
+    input   pready,
+    input   prdata,
+    input   pslverr
+  );
+
+  modport slave (
+    input   psel,
+    input   penable,
+    input   paddr,
+    input   pprot,
+    input   pwrite,
+    input   pwdata,
+    input   pstrb,
+    output  pready,
+    output  prdata,
+    output  pslverr
+  );
+endinterface

data/rtl/rggen_axi4lite_if.sv

@@ -0,0 +1,68 @@
+interface rggen_axi4lite_if #(
+  parameter int ADDRESS_WIDTH = 16,
+  parameter int DATA_WIDTH    = 32
+)();
+  logic                     awvalid;
+  logic                     awready;
+  logic [ADDRESS_WIDTH-1:0] awaddr;
+  logic [2:0]               awprot;
+  logic                     wvalid;
+  logic                     wraedy;
+  logic [DATA_WIDTH-1:0]    wdata;
+  logic [DATA_WIDTH/8-1:0]  wstrb;
+  logic                     bvalid;
+  logic                     bready;
+  logic [1:0]               bresp;
+  logic                     arvalid;
+  logic                     arready;
+  logic [ADDRESS_WIDTH-1:0] araddr;
+  logic [2:0]               arprot;
+  logic                     rvalid;
+  logic                     rready;
+  logic [DATA_WIDTH-1:0]    rdata;
+  logic [1:0]               rresp;
+
+  modport master (
+    output  awvalid,
+    input   awready,
+    output  awaddr,
+    output  awprot,
+    output  wvalid,
+    input   wraedy,
+    output  wdata,
+    output  wstrb,
+    input   bvalid,
+    output  bready,
+    input   bresp,
+    output  arvalid,
+    input   arready,
+    output  araddr,
+    output  arprot,
+    input   rvalid,
+    output  rready,
+    input   rdata,
+    input   rresp
+  );
+
+  modport slave (
+      input   awvalid,
+      output  awready,
+      input   awaddr,
+      input   awprot,
+      input   wvalid,
+      output  wraedy,
+      input   wdata,
+      input   wstrb,
+      output  bvalid,
+      input   bready,
+      output  bresp,
+      input   arvalid,
+      output  arready,
+      input   araddr,
+      input   arprot,
+      output  rvalid,
+      input   rready,
+      output  rdata,
+      output  rresp
+    );
+endinterface

data/rtl/rggen_bit_field_if.sv

@@ -0,0 +1,28 @@
+interface rggen_bit_field_if #(
+  parameter int DATA_WIDTH  = 32
+)();
+  logic                   read_access;
+  logic                   write_access;
+  logic [DATA_WIDTH-1:0]  write_data;
+  logic [DATA_WIDTH-1:0]  write_mask;
+  logic [DATA_WIDTH-1:0]  value;
+  logic [DATA_WIDTH-1:0]  read_data;
+
+  modport master (
+    output  read_access,
+    output  write_access,
+    output  write_data,
+    output  write_mask,
+    input   value,
+    input   read_data
+  );
+
+  modport slave (
+    input   read_access,
+    input   write_access,
+    input   write_data,
+    input   write_mask,
+    output  value,
+    output  read_data
+  );
+endinterface

data/rtl/rggen_bit_field_ro.sv

@@ -0,0 +1,9 @@
+module rggen_bit_field_ro #(
+  parameter int WIDTH = 1
+)(
+  rggen_bit_field_if.slave  bit_field_if,
+  input logic [WIDTH-1:0]   i_value
+);
+  assign  bit_field_if.value      = i_value;
+  assign  bit_field_if.read_data  = i_value;
+endmodule

data/rtl/rggen_bit_field_rw.sv

@@ -0,0 +1,25 @@
+module rggen_bit_field_rw #(
+  parameter int             WIDTH         = 1,
+  parameter bit [WIDTH-1:0] INITIAL_VALUE = '0
+)(
+  input   logic             clk,
+  input   logic             rst_n,
+  rggen_bit_field_if.slave  bit_field_if,
+  output  logic [WIDTH-1:0] o_value
+);
+  logic [WIDTH-1:0] value;
+
+  assign  o_value                 = value;
+  assign  bit_field_if.value      = value;
+  assign  bit_field_if.read_data  = value;
+
+  always_ff @(posedge clk, negedge rst_n) begin
+    if (!rst_n) begin
+      value <= INITIAL_VALUE;
+    end
+    else if (bit_field_if.write_access) begin
+      value <= (value                   & (~bit_field_if.write_mask))
+             | (bit_field_if.write_data &   bit_field_if.write_mask );
+    end
+  end
+endmodule

data/rtl/rggen_bit_field_rwl_rwe.sv

@@ -0,0 +1,29 @@
+module rggen_bit_field_rwl_rwe
+  import rggen_rtl_pkg::*;
+#(
+  parameter rggen_rwle_mode   MODE          = RGGEN_LOCK_MODE,
+  parameter int               WIDTH         = 1,
+  parameter bit [WIDTH-1:0]   INITIAL_VALUE = '0
+)(
+  input   logic             clk,
+  input   logic             rst_n,
+  input   logic             i_lock_or_enable,
+  rggen_bit_field_if.slave  bit_field_if,
+  output  logic [WIDTH-1:0] o_value
+);
+  logic [WIDTH-1:0] value;
+
+  assign  o_value                 = value;
+  assign  bit_field_if.value      = value;
+  assign  bit_field_if.read_data  = value;
+
+  always_ff @(posedge clk, negedge rst_n) begin
+    if (!rst_n) begin
+      value <= INITIAL_VALUE;
+    end
+    else if ((i_lock_or_enable == MODE) && bit_field_if.write_access) begin
+      value <= (value                   & (~bit_field_if.write_mask))
+             | (bit_field_if.write_data &   bit_field_if.write_mask );
+    end
+  end
+endmodule

data/rtl/rggen_bit_field_w01s_w01c.sv

@@ -0,0 +1,55 @@
+module rggen_bit_field_w01s_w01c
+  import  rggen_rtl_pkg::*;
+#(
+  parameter rggen_rwsc_mode   MODE            = RGGEN_SET_MODE,
+  parameter bit               SET_CLEAR_VALUE = 1'b0,
+  parameter int               WIDTH           = 1,
+  parameter bit [WIDTH-1:0]   INITIAL_VALUE   = '0
+)(
+  input   logic             clk,
+  input   logic             rst_n,
+  input   logic [WIDTH-1:0] i_set_or_clear,
+  rggen_bit_field_if.slave  bit_field_if,
+  output  logic [WIDTH-1:0] o_value
+);
+  logic [WIDTH-1:0] value;
+
+  assign  o_value                           = value;
+  assign  bit_field_if.value[WIDTH-1:0]     = value;
+  assign  bit_field_if.read_data[WIDTH-1:0] = value;
+
+  always_ff @(posedge clk, negedge rst_n) begin
+    if (!rst_n) begin
+      value <= INITIAL_VALUE;
+    end
+    else begin
+      value <= get_next_value();
+    end
+  end
+
+  function automatic logic [WIDTH-1:0] get_next_value();
+    logic [WIDTH-1:0] write_data;
+    logic [WIDTH-1:0] write_mask;
+    logic [WIDTH-1:0] control_value;
+    logic [WIDTH-1:0] set;
+    logic [WIDTH-1:0] clear;
+
+    write_data  = bit_field_if.write_data;
+    write_mask  = bit_field_if.write_mask;
+    if (bit_field_if.write_access) begin
+      control_value = write_mask & ((SET_CLEAR_VALUE) ? write_data : ~write_data);
+    end
+    else begin
+      control_value = '0;
+    end
+    if (MODE == RGGEN_SET_MODE) begin
+      set   = control_value;
+      clear = i_set_or_clear;
+    end
+    else begin
+      set   = i_set_or_clear;
+      clear = control_value;
+    end
+    return set | (value & (~clear));
+  endfunction
+endmodule