badline 0.17.0 → 0.19.0

data/lib/badline/chips/m6809/plans.rb

@@ -0,0 +1,143 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class M6809
+      # The condition code bits.
+      CARRY = 0x01
+      OVERFLOW = 0x02
+      ZERO = 0x04
+      NEGATIVE = 0x08
+      IRQ_MASK = 0x10
+      HALF_CARRY = 0x20
+      FIRQ_MASK = 0x40
+      ENTIRE = 0x80
+
+      # What an opcode runs: the instruction method its *_exec step calls,
+      # the steps that work out its address, one a cycle, and the steps
+      # that follow them, and the group the undocumented stores immediate
+      # take their flags from when it ran before them. An indexed opcode's
+      # address steps end in the postbyte, which picks the rest from
+      # INDEXED_PLANS.
+      Entry = Struct.new(:operation, :plan, :tail, :group)
+
+      # The groups of David Banks' "Flags for unprefixed Store Immediate".
+      GROUP_OTHER = 0
+      GROUP_N0_Z1 = 1
+      GROUP_A_00 = 2
+      GROUP_A_FF = 3
+      GROUP_A_01 = 4
+      GROUP_B_01 = 5
+      GROUP_WORD_01 = 6
+      GROUP_LEA = 7
+      GROUPS = {
+        GROUP_N0_Z1 => %i[bita cmpa],
+        GROUP_A_00 => %i[lda ldd],
+        GROUP_A_FF => %i[adca adda anda eora ora sbca suba],
+        GROUP_A_01 => %i[asla asra coma daa deca inca lsra nega rola rora subd tsta xdeca xnca],
+        GROUP_B_01 => %i[sex],
+        GROUP_WORD_01 => %i[cmpd cmps cmpu cmpx cmpy xaddd xaddu],
+        GROUP_LEA => %i[leas leau leax leay]
+      }.flat_map { |group, operations| operations.map { |operation| [operation, group] } }.to_h.freeze
+
+      # The plan between instructions: the next cycle fetches an opcode.
+      FETCH_PLAN = %i[fetch].freeze
+
+      # The tail an instruction has once it is running its tail, never run.
+      # The empty tail, JUMP_TAIL, runs the instruction method as the
+      # address steps end.
+      NO_TAIL = %i[none].freeze
+      JUMP_TAIL = [].freeze
+
+      DIRECT_PLAN = %i[direct dead_v].freeze
+      EXTENDED_PLAN = %i[extended_hi extended_lo dead_v].freeze
+      INDEXED_PLAN = %i[postbyte].freeze
+
+      # The steps that read or write the address once it is known.
+      TAILS = {
+        read8: %i[read_exec],
+        read16: %i[read_hi read_lo_exec],
+        read16_dead: %i[read_hi read_lo_exec dead_v],
+        write8: %i[write_exec],
+        write16: %i[write_hi_exec write_lo],
+        rmw: %i[rmw_read dead_v rmw_write],
+        test: %i[read_exec dead_v dead_v],
+        jump: JUMP_TAIL,
+        subroutine: %i[dead_ea dead_v push_pcl push_pch_exec],
+        load_address: %i[dead_v_exec]
+      }.freeze
+
+      IMMEDIATE_TAILS = {
+        read8: %i[immediate_exec],
+        read16: %i[immediate_hi immediate_lo_exec],
+        read16_dead: %i[immediate_hi immediate_lo_exec dead_v]
+      }.freeze
+
+      # The 12 bytes SWI and the hardware interrupts other than FIRQ stack,
+      # in the order they go onto S.
+      PUSH_ALL = %i[push_pcl push_pch push_wl push_wh push_yl push_yh push_xl push_xh push_dp push_b push_a
+                    push_cc].freeze
+      VECTOR_STEPS = %i[dead_v vector_hi vector_lo dead_v].freeze
+
+      # SWI, SWI2, SWI3 and the undocumented XRES, XSWI2 and XFIRQ, after
+      # the opcode. The instruction method picks the vector.
+      SOFTWARE_INTERRUPT_TAIL = [:dead_pc, :dead_v_exec, *PUSH_ALL, *VECTOR_STEPS].freeze
+
+      # IRQ and NMI after the cycle that would have fetched the opcode, and
+      # FIRQ, which stacks only PC and CC.
+      INTERRUPT_PLAN = [:dead_pc, :dead_v_exec, *PUSH_ALL, *VECTOR_STEPS].freeze
+      FAST_INTERRUPT_PLAN = [:dead_pc, :dead_v_exec, :push_pcl, :push_pch, :push_cc, *VECTOR_STEPS].freeze
+
+      # The interrupt CWAI was waiting for: its vector, no more stacking.
+      WAITED_INTERRUPT_PLAN = %i[vector_hi vector_lo dead_v].freeze
+
+      # RTI after pulling CC, with E set and with E clear.
+      RETURN_ENTIRE_PLAN = %i[pull_a pull_b pull_dp pull_xh pull_xl pull_yh pull_yl pull_wh pull_wl pull_pch pull_pcl
+                              dead_stack].freeze
+      RETURN_FAST_PLAN = %i[pull_pch pull_pcl dead_stack].freeze
+
+      # The cycles after RESET goes high: two dead reads of $FFFE, the
+      # vector, and a dead cycle.
+      RESET_PLAN = %i[reset_dead reset_dead reset_hi reset_lo dead_v].freeze
+
+      LONG_BRANCH_TAKEN_PLAN = %i[dead_v_take].freeze
+      SYNC_END_PLAN = %i[idle].freeze
+
+      # PSH and PUL by postbyte: the bytes in the order they go onto or
+      # come off the stack, PC first on and last off.
+      PUSH_ORDER = [[0x80, %i[push_pcl push_pch]], [0x40, %i[push_wl push_wh]], [0x20, %i[push_yl push_yh]],
+                    [0x10, %i[push_xl push_xh]], [0x08, %i[push_dp]], [0x04, %i[push_b]], [0x02, %i[push_a]],
+                    [0x01, %i[push_cc]]].freeze
+      PULL_ORDER = [[0x01, %i[pull_cc]], [0x02, %i[pull_a]], [0x04, %i[pull_b]], [0x08, %i[pull_dp]],
+                    [0x10, %i[pull_xh pull_xl]], [0x20, %i[pull_yh pull_yl]], [0x40, %i[pull_wh pull_wl]],
+                    [0x80, %i[pull_pch pull_pcl]]].freeze
+      PUSH_PLANS = Array.new(256) do |mask|
+        [:dead_v, :dead_v, :dead_stack, *PUSH_ORDER.flat_map { |bit, steps| mask.nobits?(bit) ? [] : steps }].freeze
+      end.freeze
+      PULL_PLANS = Array.new(256) do |mask|
+        [:dead_v, :dead_v, *PULL_ORDER.flat_map { |bit, steps| mask.nobits?(bit) ? [] : steps }, :dead_stack].freeze
+      end.freeze
+
+      # The steps after the postbyte, by postbyte, Figure 17 sheet 4.
+      INDEXED_PLANS = Array.new(256) do |post|
+        next %i[dead_pc dead_v].freeze if post < 0x80
+
+        plan = case post & 0x0f
+               when 0x0, 0x2 then %i[dead_pc dead_v dead_v]
+               when 0x1, 0x3 then %i[dead_pc dead_v dead_v dead_v]
+               when 0x4 then %i[dead_pc]
+               when 0x5, 0x6 then %i[dead_pc dead_v]
+               when 0x8 then %i[offset8 dead_v]
+               when 0x9 then %i[offset_hi offset_lo_register dead_pc dead_v dead_v]
+               when 0xb then %i[dead_pc dead_pc_next dead_pc_next2 dead_v dead_v]
+               when 0xc then %i[offset8_pc dead_v]
+               when 0xd then %i[offset_hi offset_lo_pc dead_pc dead_v dead_v dead_v]
+               when 0xf then %i[offset_hi offset_lo_absolute dead_pc]
+               else []
+               end
+        plan += %i[indirect_hi indirect_lo dead_v] if post.anybits?(0x10)
+        plan.freeze
+      end.freeze
+    end
+  end
+end

data/lib/badline/chips/m6809/registers.rb

@@ -0,0 +1,82 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class M6809
+      # The programmer's registers, and the codes TFR and EXG and the
+      # indexed postbyte name them by.
+      module Registers
+        attr_accessor :a, :b, :x, :y, :u, :s, :pc, :dp, :cc
+
+        def d = (@a << 8) | @b
+
+        def d=(value)
+          @a = value >> 8
+          @b = value & 0xff
+        end
+
+        # Whether NMI is armed: a load of S since reset.
+        def nmi_armed? = @nmi_armed
+
+        private
+
+        def load_s(value)
+          @s = value
+          @nmi_armed = true
+        end
+
+        # The register bits 5 and 6 of an indexed postbyte name.
+        def index_register
+          case @post & 0x60
+          when 0x00 then @x
+          when 0x20 then @y
+          when 0x40 then @u
+          else @s
+          end
+        end
+
+        def index_register=(value)
+          case @post & 0x60
+          when 0x00 then @x = value
+          when 0x20 then @y = value
+          when 0x40 then @u = value
+          else load_s(value)
+          end
+        end
+
+        # A TFR or EXG register: D, X, Y, U, S and PC are 0 to 5, A, B, CC
+        # and DP 8 to 11. The other codes read as $FF or $FFFF.
+        def transfer_register(code)
+          case code
+          when 0x0 then d
+          when 0x1 then @x
+          when 0x2 then @y
+          when 0x3 then @u
+          when 0x4 then @s
+          when 0x5 then @pc
+          when 0x8 then @a
+          when 0x9 then @b
+          when 0xa then @cc
+          when 0xb then @dp
+          else code < 8 ? 0xffff : 0xff
+          end
+        end
+
+        def set_transfer_register(code, value)
+          case code
+          when 0x0 then self.d = value
+          when 0x1 then @x = value
+          when 0x2 then @y = value
+          when 0x3 then @u = value
+          when 0x4 then load_s(value)
+          when 0x5 then @pc = value
+          when 0x8 then @a = value
+          when 0x9 then @b = value
+          when 0xa then @cc = value
+          when 0xb then @dp = value
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/m6809/stack.rb

@@ -0,0 +1,140 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class M6809
+      # The stack steps of PSH, PUL, JSR, BSR, RTS, RTI, the software
+      # interrupts and the hardware ones. Each pushes onto or pulls off the
+      # stack @stack_u names: U for PSHU and PULU, S otherwise. The "other"
+      # stack pointer, w, is the one that isn't.
+      module Stack
+        private
+
+        def push(value)
+          if @stack_u
+            @u = (@u - 1) & 0xffff
+            @bus.write(@u, value)
+          else
+            @s = (@s - 1) & 0xffff
+            @bus.write(@s, value)
+          end
+        end
+
+        def pull
+          if @stack_u
+            value = @bus.read(@u)
+            @u = (@u + 1) & 0xffff
+          else
+            value = @bus.read(@s)
+            @s = (@s + 1) & 0xffff
+          end
+          value
+        end
+
+        def dead_stack = @bus.read(@stack_u ? @u : @s)
+
+        def other_stack = @stack_u ? @s : @u
+
+        def other_stack=(value)
+          @stack_u ? load_s(value) : @u = value
+        end
+
+        def push_s_post = stack_post(false, PUSH_PLANS)
+
+        def push_u_post = stack_post(true, PUSH_PLANS)
+
+        def pull_s_post = stack_post(false, PULL_PLANS)
+
+        def pull_u_post = stack_post(true, PULL_PLANS)
+
+        def stack_post(stack_u, plans)
+          @stack_u = stack_u
+          switch_to(plans[read_pc])
+        end
+
+        def push_pcl = push(@pc & 0xff)
+        def push_pch = push(@pc >> 8)
+        def push_wl = push(other_stack & 0xff)
+        def push_wh = push(other_stack >> 8)
+        def push_yl = push(@y & 0xff)
+        def push_yh = push(@y >> 8)
+        def push_xl = push(@x & 0xff)
+        def push_xh = push(@x >> 8)
+        def push_dp = push(@dp)
+        def push_b = push(@b)
+        def push_a = push(@a)
+        def push_cc = push(@cc)
+
+        def push_pch_exec
+          push_pch
+          execute
+        end
+
+        def pull_cc
+          @cc = pull
+        end
+
+        def pull_a
+          @a = pull
+        end
+
+        def pull_b
+          @b = pull
+        end
+
+        def pull_dp
+          @dp = pull
+        end
+
+        def pull_xh
+          @x = (pull << 8) | (@x & 0xff)
+        end
+
+        def pull_xl
+          @x = (@x & 0xff00) | pull
+        end
+
+        def pull_yh
+          @y = (pull << 8) | (@y & 0xff)
+        end
+
+        def pull_yl
+          @y = (@y & 0xff00) | pull
+        end
+
+        def pull_wh
+          self.other_stack = (pull << 8) | (other_stack & 0xff)
+        end
+
+        def pull_wl
+          self.other_stack = (other_stack & 0xff00) | pull
+        end
+
+        def pull_pch
+          @pc = (pull << 8) | (@pc & 0xff)
+        end
+
+        def pull_pcl
+          @pc = (@pc & 0xff00) | pull
+        end
+
+        # RTI after pulling CC: the whole state when E is set, else PC.
+        def return_cc
+          pull_cc
+          switch_to(@cc.nobits?(ENTIRE) ? RETURN_FAST_PLAN : RETURN_ENTIRE_PLAN)
+        end
+
+        # The vector of the interrupt or SWI being taken. The masks it sets
+        # take effect as its first byte is read.
+        def vector_hi
+          @value = @bus.read(@vector) << 8
+          @cc |= @interrupt_mask
+        end
+
+        def vector_lo
+          @pc = @value | @bus.read(@vector + 1)
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/m6809.rb

@@ -0,0 +1,13 @@
+# frozen_string_literal: true
+
+require "badline/chips/m6809/core"
+
+module Badline
+  module Chips
+    # The Motorola 6809E, which the SuperPET has beside its 6502. It is not
+    # part of badline/core, so a machine that has one requires it.
+    class M6809
+      include Core
+    end
+  end
+end

data/lib/badline/chips/riot/timer.rb

@@ -13,8 +13,12 @@ module Badline
       # reads N - 1 until cycle T, 0 until cycle N x T, and $FF with the flag
       # set on cycle N x T: 52 at ÷8 sets the flag on cycle 416. From there
       # the counter counts every cycle, so it tells how long ago the flag
-      # set, and each count through 0 sets the flag again. Only a write puts
-      # the prescaler back.
+      # set, and each count through 0 sets the flag again. On the 6532 only
+      # a write puts the prescaler back. On the 6530, as the KIM-1 User
+      # Manual's appendix H has it, a read of the counter after the flag
+      # set does too, and the counter counts on from where it is at the
+      # interval written: a 6530 builds its timer with
+      # read_restores_divider. No test program has confirmed it.
       #
       # Reading or writing the counter clears the flag, except for a read on
       # the cycle that sets it. Each access takes A3 as the interrupt enable.
@@ -24,7 +28,8 @@ module Badline
         attr_reader :counter, :flag
         attr_accessor :irq_enabled
 
-        def initialize
+        def initialize(read_restores_divider: false)
+          @read_restores_divider = read_restores_divider
           @counter = 0
           @divider = 1
           @prescale = 1
@@ -50,6 +55,7 @@ module Badline
         def read(irq_enabled)
           @irq_enabled = irq_enabled
           @flag = false unless @fired
+          restore_divider if @read_restores_divider && @expired
           @counter
         end
 
@@ -66,6 +72,11 @@ module Badline
 
         private
 
+        def restore_divider
+          @expired = false
+          @prescale = @divider
+        end
+
         def count
           @counter = (@counter - 1) & 0xff
           return unless @counter == 0xff

data/lib/badline/chips/rriot.rb

@@ -9,7 +9,9 @@ module Badline
     # of RAM, two 8-bit ports, A and B, each with a direction register, a 1
     # making the pin an output, and the 6532's interval timer (RIOT::Timer).
     # It has no edge detector. The 8050 and 8250's floppy controller has
-    # one, its ROM the controller's program.
+    # one, its ROM the controller's program, and the KIM-1 two. Its timer
+    # reads its counter as the 6532's does, but a read after the flag sets
+    # puts the prescaler back (RIOT::Timer).
     #
     # Which addresses select the ROM, the RAM and the registers is part of
     # the mask, so the board decodes them and calls read_rom (A9-A0),
@@ -36,7 +38,7 @@ module Badline
         @peripheral = peripheral
         @irq_on_pb7 = irq_on_pb7
         @ram = Array.new(64, 0)
-        @timer = RIOT::Timer.new
+        @timer = RIOT::Timer.new(read_restores_divider: true)
         reset!
       end
 
@@ -72,7 +74,10 @@ module Badline
 
       # Everything the RRIOT holds but its timer's counter, for comparing
       # it at two points.
-      def idle_state = [*@ram, @ora, @orb, @ddra, @ddrb, *@timer.state, @timer.flag]
+      def idle_state = [*@ram, *port_state]
+
+      # The ports and the timer but for its counter.
+      def port_state = [@ora, @orb, @ddra, @ddrb, *@timer.state, @timer.flag]
 
       def read_rom(addr) = @rom[addr & 0x3ff]
 

data/lib/badline/chips/sid/decimator.rb

@@ -21,7 +21,7 @@ module Badline
         end
 
         # Cycles until the current window closes, counting the next one as 1.
-        attr_reader :cycles_to_close
+        attr_reader :cycles_to_close, :rate, :clock_hz
 
         # How far the current window has got, in a keyed snapshot module
         # (Snapshot::Keyed) under `prefix`. The clock and the rate are the

data/lib/badline/chips/sid/filter.rb

@@ -195,7 +195,7 @@ module Badline
           @unfiltered = 0
           route_voice(voice1.output >> 7, 0x1)
           route_voice(voice2.output >> 7, 0x2)
-          if @routing & 0x4 != 0
+          if @routing.anybits?(0x4)
             @input += voice3.output >> 7
           elsif !@voice3_off
             @unfiltered += voice3.output >> 7
@@ -216,9 +216,9 @@ module Badline
 
         def filtered
           value = 0
-          value += @lowpass  if @mode & 0x1 != 0
-          value += @bandpass if @mode & 0x2 != 0
-          value += @highpass if @mode & 0x4 != 0
+          value += @lowpass  if @mode.anybits?(0x1)
+          value += @bandpass if @mode.anybits?(0x2)
+          value += @highpass if @mode.anybits?(0x4)
           value
         end
       end

data/lib/badline/chips/sid/keyed_parts.rb

@@ -221,7 +221,11 @@ module Badline
       # voice's under voice1. to voice3., and the filter's under filter.
       # and ext. Saving catches the DSP up first, so no span or deferred
       # write is left to save. What the registers decode to is worked out
-      # from them on load.
+      # from them on load. A recording SID also saves how far its recording
+      # has got under rec., with the rate, the clock and the filter chunk it
+      # records at: the samples' windows bound the filter's steps, so a SID
+      # loaded from it that records at the same rate and clock carries on
+      # from that window and integrates the steps the saved one does.
       module KeyedState
         def save_fields(out)
           catch_up
@@ -230,6 +234,8 @@ module Badline
           @voice2.save_fields(out, "voice2.")
           @voice3.save_fields(out, "voice3.")
           @filter.save_fields(out, "filter.")
+          recording = @decimator || @resumed_recording
+          save_recording(out, recording) if recording
           out
         end
 
@@ -243,23 +249,7 @@ module Badline
           @voice2.load_fields(input, "voice2.")
           @voice3.load_fields(input, "voice3.")
           @filter.load_fields(input, "filter.")
-        end
-
-        # How far the recording has got into the sample it is averaging,
-        # under `prefix`, for a host that carries on recording from a
-        # snapshot: it calls #record, then #load_recording_fields.
-        def save_recording_fields(out, prefix)
-          decimator = @decimator
-          raise ArgumentError, "the SID isn't recording" if decimator.nil?
-
-          decimator.save_fields(out, prefix)
-        end
-
-        def load_recording_fields(input, prefix)
-          decimator = @decimator
-          raise ArgumentError, "the SID isn't recording" if decimator.nil?
-
-          decimator.load_fields(input, prefix)
+          load_recording(input)
         end
 
         def restored!
@@ -272,6 +262,49 @@ module Badline
 
         private
 
+        def save_recording(out, decimator)
+          out.int("rec.rate", decimator.rate).int("rec.clock_hz", decimator.clock_hz)
+          out.int("rec.filter_chunk", @filter_chunk)
+          decimator.save_fields(out, "rec.")
+        end
+
+        # A SID recording already carries on from the loaded window when it
+        # records at its rate, clock and filter chunk, and starts a new
+        # window otherwise.
+        def load_recording(input)
+          @resumed_recording = nil
+          live = @decimator
+          loaded = loaded_recording(input)
+          chunk = loaded ? input.int("rec.filter_chunk", @filter_chunk) : @filter_chunk
+          if live.nil?
+            @filter_chunk = chunk
+            @resumed_recording = loaded
+          elsif loaded && chunk == @filter_chunk && loaded.rate == live.rate && loaded.clock_hz == live.clock_hz
+            @decimator = loaded
+          else
+            @decimator = Decimator.new(clock_hz: live.clock_hz, rate: live.rate)
+          end
+        end
+
+        def loaded_recording(input)
+          rate = input.int("rec.rate", 0)
+          return unless rate.positive?
+
+          decimator = Decimator.new(clock_hz: input.int("rec.clock_hz", Region::PAL.clock_hz), rate:)
+          decimator.load_fields(input, "rec.")
+          decimator
+        end
+
+        # The window a loaded snapshot's recording had got to, when this
+        # recording is at its rate, clock and filter chunk.
+        def resumed_recording(rate, filter_chunk, clock_hz)
+          resumed = @resumed_recording
+          @resumed_recording = nil
+          return if resumed.nil? || filter_chunk != @filter_chunk
+
+          resumed if resumed.rate == rate && resumed.clock_hz == clock_hz
+        end
+
         def restore_voice(voice, base)
           control = register(base + 4)
           voice.waveform.restore_registers(register(base) | (register(base + 1) << 8),

data/lib/badline/chips/sid/waveform.rb

@@ -234,7 +234,7 @@ module Badline
         def compare_pulse(phase = @accumulator >> 12) = (@pulse = @test || phase >= @pulse_width ? 0xfff : 0x000)
 
         # More than one bit set in the selection.
-        def combined?(selected) = selected & (selected - 1) != 0
+        def combined?(selected) = selected.anybits?(selected - 1)
 
         # The one point in the cycle where the waveform selector drives the DAC:
         # either it latches a fresh value, or nothing drives the line and the
@@ -274,8 +274,8 @@ module Badline
         def advance
           previous = @accumulator
           @accumulator = (previous + @frequency) & 0xffffff
-          @msb_rising = @accumulator & ~previous & MSB != 0
-          if @accumulator & ~previous & 0x080000 != 0
+          @msb_rising = (@accumulator & ~previous).anybits?(MSB)
+          if (@accumulator & ~previous).anybits?(0x080000)
             @shift_pipeline = 2
           elsif @shift_pipeline != 0 && (@shift_pipeline -= 1).zero?
             write_back_shift
@@ -292,12 +292,12 @@ module Badline
         # TriXOR = !Saw & ((!V3 & Ring) ^ bit23), where V3 is the modulating
         # voice's MSB (SID/ringmod).
         def inverted?(selected)
-          return false if selected & 0x2 != 0
+          return false if selected.anybits?(0x2)
 
-          msb = @accumulator & MSB != 0
+          msb = @accumulator.anybits?(MSB)
           return msb unless @ring
 
-          msb == (@sync_source.accumulator & MSB != 0)
+          msb == @sync_source.accumulator.anybits?(MSB)
         end
       end
     end

data/lib/badline/chips/sid.rb

@@ -70,6 +70,7 @@ module Badline
         @pending_cycles = 0
         @deferred_writes = []
         @decimator = nil
+        @resumed_recording = nil
         @samples = []
         @voice_samples = nil
         @filter_chunk = filter_chunk
@@ -120,12 +121,15 @@ module Badline
       # Starts collecting the output, averaged down to `rate` samples a
       # second, for #drain_samples. `filter_chunk` overrides the one the SID
       # was built with, for a machine that built its own. `clock_hz` is the
-      # rate the SID's cycles are taken to run at.
+      # rate the SID's cycles are taken to run at. A SID loaded from a
+      # recording one carries on from the window that one had got to, at the
+      # same rate, clock and filter chunk.
       def record(rate:, filter_chunk: @filter_chunk, clock_hz: Region::PAL.clock_hz)
         synthesize!
         catch_up
+        resumed = resumed_recording(rate, filter_chunk, clock_hz)
         @filter_chunk = filter_chunk
-        @decimator = Decimator.new(clock_hz:, rate:)
+        @decimator = resumed || Decimator.new(clock_hz:, rate:)
         @samples = []
       end