badline 0.17.0 → 0.19.0

data/lib/badline/drives/model4040/keyed_state.rb

@@ -0,0 +1,57 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model4040
+      class Disk
+        def image_format = @image.is_a?(Storage::D67Image) ? "d67" : "d64"
+
+        # The disk a BL-D8-DISK module holds, as Model8050::Disk's, from a
+        # .d64 or a .d67.
+        def self.from_fields(input, detached: false)
+          path = input.text("path", "")
+          read_only = input.bool("read_only", false) || detached
+          kind = input.choice("image.format", %w[d64 d67], "d64")
+          bytes = input.bytes("image", "".b).bytes
+          path = "" if detached || !File.file?(path)
+          image = if kind == "d67"
+                    Storage::D67Image.new(path, read_only:, bytes:)
+                  else
+                    Storage::D64Image.new(path, read_only:, bytes:)
+                  end
+          new(image).load_track_fields(input)
+        end
+      end
+
+      class Mechanism
+        # The drives' fields in a keyed snapshot module (BL-D8-MECH), a value
+        # a drive in each list: the heads' half tracks, the stepper counts,
+        # each disk's place in its turn and its bit clock and the motors,
+        # then byte ready, the byte on VIA port A and SYNC. The disks load
+        # from their own modules.
+        module KeyedState
+          def save_fields(out)
+            out.ints("half_tracks", @half_tracks).ints("phases", @phases).ints("positions", @positions)
+            out.ints("bit_clocks", @clocks)
+            out.ints("motors", @motors.map { |on| on ? 1 : 0 }).ints("syncs", @syncs.map { |low| low ? 1 : 0 })
+            out.bool("ca1_low", @ca1_low).int("data_in", @data_in)
+          end
+
+          def load_fields(input, disks)
+            @disks = disks
+            input.ints_into("half_tracks", @half_tracks)
+            input.ints_into("phases", @phases)
+            input.ints_into("positions", @positions)
+            input.ints_into("bit_clocks", @clocks)
+            @motors = input.ints("motors", [0, 0]).map { |on| on == 1 }
+            @syncs = input.ints("syncs", [0, 0]).map { |low| low == 1 }
+            @ca1_low = input.bool("ca1_low", @ca1_low)
+            @data_in = input.byte("data_in", @data_in)
+          end
+        end
+
+        include KeyedState
+      end
+    end
+  end
+end

data/lib/badline/drives/model4040/mechanism.rb

@@ -0,0 +1,195 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model4040
+      # The unit's two SA390 drives as the 6504 sees them through the VIA
+      # and the 6530 (schematic 320806, sheets 2 and 3).
+      #
+      # VIA port B runs the drives: PB5 drive 0's motor and PB4 drive 1's,
+      # each on while low, PB2-3 drive 0's stepper and PB0-1 drive 1's. The
+      # 6530's port B picks the drive on PB0 and the zone on PB1-2, and
+      # reads write protect on PB3, high while the disk can't be written,
+      # and SYNC on PB6, low while ten one bits sit in the shift register.
+      # Its port A holds the byte to write.
+      #
+      # Each stepper's two bits count in binary: one up moves the head half
+      # a track in, one down half a track out, and the controller steps
+      # once an interrupt, twice a track ($FF82), bumping the head against
+      # track 1 with 116 steps out.
+      #
+      # A turning disk passes one byte cell under the head every ten bit
+      # cells, at 16 MHz divided by 16 less the track's zone and then by 4,
+      # and the byte cells come round 300 times a minute (Disk). Each data
+      # cell ends in byte ready, which latches the byte into VIA port A
+      # through CA1; the controller has no SO pin and polls the VIA's
+      # interrupt flags for it. A sync cell holds SYNC low instead. While
+      # the VIA's CB2 is low the drive writes: each cell takes the 6530's
+      # port A, or a sync while CA2 is high, and still ends in byte ready.
+      # The format code holds CA2 high in pulse mode, which reading port A
+      # pulls low for a cycle.
+      class Mechanism
+        WRITE_PROTECT = 0x08
+        SYNC_LINE = 0x40
+
+        # The half tracks a head can reach: track 1 to 35.
+        HALF_TRACKS = 70
+
+        attr_reader :data_in, :half_tracks
+        attr_accessor :via, :rriot
+
+        def initialize
+          @via = nil
+          @rriot = nil
+          @disks = [nil, nil]
+          @half_tracks = [0, 0]
+          @phases = [0, 0]
+          @positions = [0, 0]
+          @clocks = [0, 0]
+          @motors = [false, false]
+          @data_in = 0xff
+          @syncs = [false, false]
+          @ca1_low = false
+        end
+
+        # The Disk in +drive+, 0 or 1, or nil.
+        def disk(drive = 0) = @disks[drive]
+
+        def insert(disk, drive = 0)
+          @disks[drive]&.flush
+          @disks[drive] = disk
+        end
+
+        def flush
+          @disks.each { |disk| disk&.flush }
+        end
+
+        def motor_on?(drive = 0) = @motors[drive]
+
+        # The track under +drive+'s head, 1 to 35.
+        def track(drive = 0) = (@half_tracks[drive] >> 1) + 1
+
+        def cycle!
+          if @ca1_low
+            @ca1_low = false
+            @via.ca1 = true
+          end
+          drives = @via.port_b_output
+          turn(0, drives.nobits?(0x20), (drives >> 2) & 0x03)
+          turn(1, drives.nobits?(0x10), drives & 0x03)
+        end
+
+        # Whether a cycle would change nothing: no byte ready under way, and
+        # each drive's motor off or turning with no disk in it, as both turn
+        # from the bump at boot until the run-down.
+        def quiet? = !@ca1_low && still?(0) && still?(1)
+
+        # What the drives hold, for comparing them at two points.
+        def idle_state = [*@half_tracks, *@phases, *@motors, *@syncs, @data_in]
+
+        # The 6530's port B inputs.
+        def status_lines
+          drive = selected_drive
+          lines = 0xff
+          lines &= ~WRITE_PROTECT unless @disks[drive]&.write_protected?
+          @syncs[drive] ? lines & ~SYNC_LINE : lines
+        end
+
+        private
+
+        def selected_drive = @rriot.port_b_output & 0x01
+
+        def still?(drive) = !@motors[drive] || @disks[drive].nil?
+
+        def turn(drive, motor, phase)
+          step(drive, phase) if phase != @phases[drive]
+          motor_off(drive) if @motors[drive] && !motor
+          @motors[drive] = motor
+          return @syncs[drive] = false unless motor && @disks[drive]
+
+          clock = @clocks[drive] + 2
+          byte = 5 * (16 - Disk.zone_of(track(drive)))
+          if clock >= byte
+            clock -= byte
+            pass_cell(drive)
+          end
+          @clocks[drive] = clock
+        end
+
+        def step(drive, phase)
+          change = (phase - @phases[drive]) & 0x03
+          @phases[drive] = phase
+          half_track = @half_tracks[drive]
+          if change == 1
+            half_track += 1
+          elsif change == 3
+            half_track -= 1
+          end
+          @half_tracks[drive] = half_track.clamp(0, HALF_TRACKS - 1)
+        end
+
+        def motor_off(drive)
+          @disks[drive]&.flush
+        end
+
+        # A cell has passed under +drive+'s head.
+        def pass_cell(drive)
+          disk = @disks[drive]
+          number = track(drive)
+          cells = disk.track(number)
+          return unless cells
+
+          position = @positions[drive] % cells.length
+          @positions[drive] = position + 1
+          return unless drive == selected_drive
+
+          writing? ? write_cell(drive, disk, number, cells, position) : read_cell(drive, cells, position)
+        end
+
+        def writing? = !@via.cb2_output
+
+        def read_cell(drive, cells, position)
+          cell = cells[position]
+          @syncs[drive] = cell == Disk::SYNC
+          byte_ready(cell) unless cell == Disk::SYNC
+        end
+
+        def write_cell(drive, disk, number, cells, position)
+          cells[position] = @via.ca2_output ? Disk::SYNC : @rriot.port_a_output
+          disk.written(number)
+          @syncs[drive] = false
+          byte_ready(@data_in)
+        end
+
+        def byte_ready(byte)
+          @data_in = byte
+          @via.ca1 = false
+          @ca1_low = true
+        end
+      end
+
+      # VIA port A reads the byte the last cell latched. Port B drives the
+      # drives only.
+      class ReadLines
+        def initialize(mechanism)
+          @mechanism = mechanism
+        end
+
+        def read_a(_lines) = @mechanism.data_in
+
+        def read_b(_lines) = 0xff
+      end
+
+      # The 6530's port B inputs from the drives.
+      class StatusLines
+        def initialize(mechanism)
+          @mechanism = mechanism
+        end
+
+        def read_a(_lines) = 0xff
+
+        def read_b(_lines) = @mechanism.status_lines
+      end
+    end
+  end
+end

data/lib/badline/drives/model4040/parts.rb

@@ -0,0 +1,20 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model4040
+      # The interface processor's 6502, UN1, on the 4040's IPBus.
+      class IPCPU
+        include Badline::Chips::CPU::Core
+        include Engine::IdleCPU
+      end
+
+      # The floppy controller's 6504, UH3, on the 8050's FDCBus. It has no
+      # SO pin.
+      class FDCCPU
+        include Badline::Chips::CPU::Core
+        include Engine::IdleCPU
+      end
+    end
+  end
+end

data/lib/badline/drives/model4040.rb

@@ -0,0 +1,195 @@
+# frozen_string_literal: true
+
+require "badline/drives/model8050"
+require "badline/drives/model4040/ip_bus"
+require "badline/drives/model4040/parts"
+require "badline/drives/model4040/disk"
+require "badline/drives/model4040/mechanism"
+require "badline/drives/model4040/keyed_state"
+
+module Badline
+  module Drives
+    # The 4040 dual disk drive of the PET and CBM-II, two Shugart SA390
+    # drives on one IEEE-488 unit (schematic 320806, the 8050's parent).
+    #
+    # The board is the 8050's (Model8050::Board) with an older floppy side.
+    # A 16 MHz crystal clocks both processors at 1 MHz on opposite phases.
+    # The interface processor runs DOS 2.1 from 12 KB of ROM at $D000, with
+    # the 8050's 6532s on the bus and the same common RAM, on a bus that
+    # doesn't decode A15 (IPBus). The floppy controller is a 6504, with no
+    # SO pin, on the 8050's map (Model8050::FDCBus): it runs the program in
+    # its 6530 (901466-04) and polls the VIA for byte ready, whose own
+    # interrupt line goes nowhere, so only the 6530's timer interrupts it
+    # (Mechanism). The disks are the 1541's, 35 tracks of 17 to 21
+    # sectors, a .d64 each (Disk).
+    #
+    # At reset the controller waits for the common RAM's $0400 to read 0,
+    # starts, and writes its timer's period there. The interface processor
+    # tests its RAM and ROMs, has the controller reset its drives, and
+    # bumps both heads to track 1. The motors run from then until the
+    # run-down after the first job, about 9.5 million host cycles in for a
+    # directory LOAD, or 8.8 million with no job. A motor turning with no
+    # disk in its drive changes nothing, so a unit with no disks sleeps
+    # from the bump on, and one with a disk only after the run-down.
+    class Model4040
+      include Model8050::Board
+      include Model8050::Idle
+      include Model8050::KeyedState
+
+      CLOCK_HZ = Model8050::CLOCK_HZ
+
+      # The host cycles by which a unit switched on with the machine has
+      # run the IP's tests and bumped both heads, and reads its jumpers.
+      BOOT_CYCLES = 2_500_000
+
+      # Where DOS 2.1's idle loop and the controller's job loop start over
+      # (Model8050::Idle).
+      IP_LOOP = 0xd4b7
+      FDC_LOOP = 0xfc54
+
+      def model_name = "4040"
+
+      def boot_cycles = BOOT_CYCLES
+
+      def sides = 1
+
+      # +dos_rom+ covers $D000-$FFFF and +fdc_rom+ is the 6530's mask, each
+      # defaulting to the image in the ROM path: the revised DOS 2.1 that
+      # xpet's 4040 runs, and 901466-04. +device+ is the number the jumpers
+      # set, 8 to 15.
+      def initialize(dos_rom: nil, fdc_rom: nil, host_clock_hz: CLOCK_HZ, device: 8)
+        @device = device
+        @host_clock_hz = host_clock_hz
+        @phase = 0
+        @cycles = 0
+        build_ip(dos_rom || ROM.load(dos_file, dos_start))
+        build_fdc(fdc_rom || ROM.read(fdc_file))
+        @ip_cpu = IPCPU.new(@ip_bus)
+        @ip_cpu.power_on!
+        @fdc_cpu = FDCCPU.new(@fdc_bus)
+        @fdc_cpu.power_on!
+        init_idle(ip_loop, fdc_loop)
+        @ieee_bus.attach(self)
+      end
+
+      # Puts in the .d64 image at +path+, or the DOS 1 disk a .d67 holds,
+      # write-protected with `read_only`.
+      def insert_image(path, drive: 0, read_only: false)
+        image = if File.extname(path).casecmp?(".d67")
+                  Storage::D67Image.new(path, read_only:)
+                else
+                  Storage::D64Image.new(path, read_only:)
+                end
+        insert(Disk.new(image), drive:)
+      end
+
+      private
+
+      def dos_file = "4040/dos-2.1-rev.rom"
+
+      def dos_start = 0xd000
+
+      def fdc_file = "4040/fdc-901466-04.rom"
+
+      def ip_loop = IP_LOOP
+
+      def fdc_loop = FDC_LOOP
+
+      def build_ip(rom)
+        @common = Memory.new([], length: 0x1000)
+        @ieee_bus = IEEEBus.new
+        @ieee_port = Model8050::IEEEPort.new(device: @device, bus: @ieee_bus)
+        @data_riot = Model8050::DataRIOT.new(peripheral: Model8050::DataLines.new(@ieee_port))
+        @control_riot = Model8050::ControlRIOT.new(peripheral: Model8050::ControlLines.new(@ieee_port))
+        @ieee_port.data_riot = @data_riot
+        @ieee_port.control_riot = @control_riot
+        @ip_bus = IPBus.new(rom:, common: @common, data_riot: @data_riot, control_riot: @control_riot)
+      end
+
+      def build_fdc(rom)
+        @mechanism = Mechanism.new
+        @via = Model8050::ControllerVIA.new(start: 0x0040, peripheral: ReadLines.new(@mechanism))
+        @rriot = Model8050::ControllerRRIOT.new(rom:, peripheral: StatusLines.new(@mechanism))
+        @fdc_bus = Model8050::FDCBus.new(common: @common, via: @via, rriot: @rriot)
+        @mechanism.via = @via
+        @mechanism.rriot = @rriot
+      end
+
+      # The disk a BL-D8-DISK module holds (Model8050::KeyedState).
+      def disk_from_fields(input, detached) = Disk.from_fields(input, detached:)
+
+      # One cycle of the board: the drives, then the chips, then the IP and
+      # the FDC, each in its own half of the cycle, as on the 8050. Only the
+      # 6530 pulls the FDC's IRQ, and the FDC finds byte ready by polling.
+      def step
+        @mechanism.cycle!
+        @control_riot.pa7 = @ieee_port.atn_low?
+        @data_riot.cycle!
+        @control_riot.cycle!
+        @via.cycle!
+        @rriot.cycle!
+        @ip_cpu.irq = @control_riot.irq?
+        @ip_cpu.cycle!
+        @fdc_cpu.irq = @rriot.irq?
+        @fdc_cpu.cycle!
+        @cycles += 1
+      end
+
+      # One cycle of the FDC's side alone, as step runs it (Model8050::Idle).
+      def fdc_step
+        @mechanism.cycle!
+        @via.cycle!
+        @rriot.cycle!
+        @fdc_cpu.irq = @rriot.irq?
+        @fdc_cpu.cycle!
+        @cycles += 1
+      end
+    end
+
+    # The 3040: the 4040's board with the first DOS 2.1, as xpet's 3040
+    # runs it, 901468-11 to -13.
+    class Model3040 < Model4040
+      # Where the first DOS 2.1's idle loop starts over.
+      IP_LOOP = 0xd4b8
+
+      def model_name = "3040"
+
+      private
+
+      def dos_file = "4040/dos-2.1.rom"
+
+      def ip_loop = IP_LOOP
+    end
+
+    # The 2040: the 4040's board with DOS 1.2 in the sockets at $E000 and
+    # $F000, UJ1 at $D000 left empty, and 901466-02 in the controller's
+    # 6530, as the 3040 with DOS 1 has it too. Its disks are DOS 1's .d67,
+    # with 20 sectors on tracks 18 to 24 (Storage::D67Image). The
+    # controller starts at once, with no handshake on the common RAM, and
+    # the interface processor leaves the common RAM alone at boot.
+    class Model2040 < Model4040
+      # Where DOS 1.2's idle loop and its controller's job loop start over.
+      IP_LOOP = 0xe27e
+      FDC_LOOP = 0xfc47
+
+      def model_name = "2040"
+
+      # Puts in the .d67 image at +path+, write-protected with `read_only`.
+      def insert_image(path, drive: 0, read_only: false)
+        insert(Disk.new(Storage::D67Image.new(path, read_only:)), drive:)
+      end
+
+      private
+
+      def dos_file = "4040/dos-1.2.rom"
+
+      def dos_start = 0xe000
+
+      def fdc_file = "4040/fdc-901466-02.rom"
+
+      def ip_loop = IP_LOOP
+
+      def fdc_loop = FDC_LOOP
+    end
+  end
+end

data/lib/badline/drives/model8050/board.rb

@@ -0,0 +1,79 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model8050
+      # The board of a unit with two processors on the IEEE-488 bus, as the
+      # 8050 family and the 4040 family share it: the DOS board's interface
+      # processor side (DOSBoard), and the floppy controller with its VIA
+      # and 6530 facing the drives. Each unit's class includes it, with
+      # Idle and KeyedState, and builds its own chips, so no call it makes
+      # on them is a union: the class sets DOSBoard's fields and @fdc_cpu,
+      # @fdc_bus, @rriot and @mechanism, and runs one cycle of the board in
+      # its own step. While both processors idle, it sleeps (Idle).
+      module Board
+        include DOSBoard
+
+        def fdc_cpu = settled(@fdc_cpu)
+
+        def fdc_bus = settled(@fdc_bus)
+
+        def rriot = settled(@rriot)
+
+        def mechanism = settled(@mechanism)
+
+        # Whether the unit is where VICE saves it: both processors between
+        # instructions, the FDC at the start of its idle loop.
+        def settled_for_vice?
+          fdc = fdc_cpu
+          ip_cpu.boundary? && fdc.boundary? && fdc.program_counter == @fdc_loop
+        end
+
+        # Whether a drive's LED is lit: of the LEDs, bit 0 is drive 1's,
+        # bit 1 drive 0's, and bit 2 the error LED.
+        def led_on? = leds.anybits?(0x03)
+
+        # Puts a Disk in +drive+, 0 or 1. Nil takes the disk out.
+        def insert(disk, drive: 0)
+          settle!
+          @mechanism.insert(disk, drive)
+        end
+
+        # The Disk in +drive+, or nil.
+        def disk(drive = 0) = @mechanism.disk(drive)
+
+        # Stores what the heads wrote in the disks' images, as the motors
+        # stopping do.
+        def flush
+          settle!
+          @mechanism.flush
+        end
+
+        # The bus's IFC line resets both processors and every chip. RAM keeps
+        # its contents.
+        def reset!
+          settle!
+          @data_riot.reset!
+          @control_riot.reset!
+          @via.reset!
+          @rriot.reset!
+          @ip_cpu.reset!
+          @fdc_cpu.reset!
+        end
+
+        def inspect
+          "#<#{self.class.name} cycles=#{@cycles} ip=(#{@ip_cpu.inspect}) fdc=(#{@fdc_cpu.inspect})>"
+        end
+
+        private
+
+        def run_cycle
+          return fdc_alone_cycle if @fdc_alone
+
+          step
+          watch_loops if @idle_skip
+        end
+      end
+    end
+  end
+end

data/lib/badline/drives/model8050/dos_board.rb

@@ -0,0 +1,134 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model8050
+      # The half of the DOS board every unit with an interface processor
+      # shares: the interface processor with its two 6532s on the IEEE-488
+      # bus, the common RAM, and the second processor's VIA, whichever side
+      # the second processor runs. Board adds the floppy controller's side
+      # to it, and Model9060 the SASI host's. Each unit's class sets
+      # @ip_cpu, @ip_bus, @common, @data_riot, @control_riot, @via,
+      # @ieee_bus and @ieee_port, and has its own run_cycle and settle!.
+      #
+      # The unit clocks against the host through a phase accumulator, as
+      # Drives::Engine::Core does: each host cycle adds 1 MHz of phase, and
+      # every whole host period in it runs a cycle of both processors. While
+      # both processors idle, it sleeps instead, and the readers of its
+      # parts catch it up first. Asleep, a host cycle only counts towards
+      # the one planned to wake the unit, which its own doze wakes, and a
+      # line the controller moves wakes it at once (host_written!).
+      module DOSBoard
+        attr_reader :device, :ieee_bus
+
+        def ip_cpu = settled(@ip_cpu)
+
+        def ip_bus = settled(@ip_bus)
+
+        def common = settled(@common)
+
+        def data_riot = settled(@data_riot)
+
+        def control_riot = settled(@control_riot)
+
+        def via = settled(@via)
+
+        def cycles
+          settle!
+          @cycles
+        end
+
+        attr_writer :host_clock_hz
+
+        # Plugs the unit into an IEEE-488 bus, leaving the one it was on.
+        def connect(ieee_bus)
+          settle!
+          @ieee_bus.detach(self)
+          @ieee_bus = ieee_bus
+          @ieee_port.bus = ieee_bus
+          ieee_bus.attach(self)
+        end
+
+        # The lines the unit pulls on the bus while ATN is low or not
+        # (IEEEPort).
+        def ieee_low_lines(atn) = @ieee_port.ieee_low_lines(atn)
+
+        # Which LEDs are lit, as the unit's port drives them. They hold
+        # still while the unit sleeps, so reading them leaves it asleep.
+        def leds = @ieee_port.leds
+
+        def power_led_on? = true
+
+        # Runs the drive cycles that fall in one host cycle, then takes the
+        # controller's lines for the next. Asleep, the unit owes the cycles
+        # instead, and wakes once the controller has moved a line, as it
+        # does with a processor owing cycles (dozing?).
+        def host_cycle!
+          return if slept_through?
+
+          phase = @phase + CLOCK_HZ
+          while phase >= @host_clock_hz
+            @asleep ? owe_cycle : run_cycle
+            phase -= @host_clock_hz
+          end
+          @phase = phase
+          settle! if dozing? && @ieee_port.lines_moved?
+          @ieee_port.latch_host
+          plan_sleep if @asleep
+        end
+
+        def cycle!
+          settle!
+          run_cycle
+        end
+
+        # The controller pushed its lines into the bus. A line it moved
+        # wakes a unit that owes cycles, which saw the lines as they stood.
+        def host_written!
+          settle! if dozing? && @ieee_port.lines_moved?
+        end
+
+        private
+
+        def settled(part)
+          settle!
+          part
+        end
+
+        # Asleep, a host cycle only counts towards the one planned to wake
+        # the unit (plan_sleep). Returns whether it did.
+        def slept_through?
+          return false unless @planned
+
+          @slept += 1
+          doze if @slept == @wake_at
+          true
+        end
+
+        # Plans the host cycle that brings the cycles owed up to the budget,
+        # once the unit has fallen asleep and the host cycle it fell asleep
+        # in is over.
+        def plan_sleep
+          return if @planned
+
+          @planned = true
+          @slept = 0
+          needed = ((@budget - @owed) * @host_clock_hz) - @phase
+          @wake_at = needed.positive? ? (needed + CLOCK_HZ - 1) / CLOCK_HZ : 1
+        end
+
+        # Turns the host cycles slept into cycles owed, through the phase
+        # accumulator.
+        def owe_slept
+          return unless @planned
+
+          @planned = false
+          phase = @phase + (@slept * CLOCK_HZ)
+          @owed += phase / @host_clock_hz
+          @phase = phase % @host_clock_hz
+          @slept = 0
+        end
+      end
+    end
+  end
+end