badline 0.17.0 → 0.19.0

data/lib/badline/pet/superpet/waterloo_traps.rb

@@ -0,0 +1,199 @@
+# frozen_string_literal: true
+
+module Badline
+  class PET
+    class SuperPET < PET
+      # The traps on the Waterloo 6809 ROM's IEEE-488 routines, which serve
+      # device 8 from the virtual drive (KernalTrap::DOS) the 6502's traps
+      # serve it from, after the ROM's source as Mike Naberezny hosts it
+      # (opsys-all-clean-20101210-src.txt). Other devices fall through to
+      # the ROM, which drives the bus.
+      #
+      # The routines take their argument in D and return with RTS: SetLstnr
+      # and SetTalkr a file control block, whose byte 9 is the device, byte
+      # 10 the secondary address and byte 0 the status, 3 after a timeout,
+      # SetLstnr with the command's offset pushed before the call ($F0 to
+      # open, $E0 to close, $60 for data), ByteOut_ the byte to send and
+      # the byte-in routine none, returning the byte in D and setting bit 0
+      # of the block's byte 12 at EOI. Each keeps the block's address at
+      # $02 and the bus at $77-$7A: $20 listening or $40 talking, the
+      # offset, the device and the secondary address. A language that hooks
+      # a routine through its flag at $0580 gets the ROM's routine, which
+      # calls the hook.
+      #
+      # The menu loads from "disk/1.", drive 1 of a dual drive. The virtual
+      # drive has one, so a name on drive 1 opens the file on drive 0.
+      class WaterlooTraps
+        BYTE_OUT = 0xbe6f
+        BYTE_IN = 0xbefb
+        SET_LISTENER = 0xc072
+        UNLISTEN = 0xc0d0
+        SET_TALKER = 0xc0dd
+        UNTALK = 0xc13c
+
+        # The routines' user hook numbers, whose flags sit at $0580 on.
+        HOOKS = { BYTE_OUT => 23, BYTE_IN => 24, SET_LISTENER => 27, UNLISTEN => 28, SET_TALKER => 29,
+                  UNTALK => 30 }.freeze
+
+        BLOCK = 0x02
+        ACTIVE = 0x77
+        LISTENING = 0x20
+        TALKING = 0x40
+        TIMED_OUT = 3
+
+        OPEN = 0xf0
+        CLOSE = 0xe0
+
+        # The device the traps serve, or nil to serve none.
+        attr_accessor :device
+
+        def initialize(cpu:, bus:, dos:)
+          @cpu = cpu
+          @bus = bus
+          @dos = dos
+          @device = KernalTrap::Routine::DEVICE
+          @listening = false
+          @talking = false
+          @channel = 0
+          @frame = 0
+          @buffer = []
+        end
+
+        def install
+          HOOKS.each_key { |address| @cpu.install_trap(address) { call(address) } }
+          self
+        end
+
+        def uninstall
+          HOOKS.each_key { |address| @cpu.remove_trap(address) }
+        end
+
+        # Whether a served device listens and talks, the channel and the
+        # command, and the bytes sent so far, for a checkpoint.
+        def state = [@listening ? 1 : 0, @talking ? 1 : 0, @channel, @frame, *@buffer]
+
+        private
+
+        def call(address)
+          return unless @bus.peek(0x0580 + HOOKS.fetch(address)).zero?
+
+          case address
+          when SET_LISTENER then set_listener
+          when BYTE_OUT then byte_out
+          when UNLISTEN then unlisten
+          when SET_TALKER then set_talker
+          when BYTE_IN then byte_in
+          else untalk
+          end
+        end
+
+        def served?(block) = !@device.nil? && @bus.peek(block + 9) == @device
+
+        def set_listener
+          block = @cpu.d
+          return unless served?(block)
+
+          offset = @bus.peek(@cpu.s + 3)
+          select(block, LISTENING, offset)
+          @listening = true
+          @frame = offset & 0xf0
+          @buffer = []
+          @dos.close(@channel) if @frame == CLOSE
+          return_from_routine
+        end
+
+        def set_talker
+          block = @cpu.d
+          return unless served?(block)
+
+          select(block, TALKING, 0x60)
+          @talking = true
+          return_from_routine
+        end
+
+        # Ends what the bus was doing, then addresses the block's device as
+        # the routine does.
+        def select(block, active, offset)
+          finish_listening if @listening
+          @talking = false
+          @bus.poke(BLOCK, block >> 8)
+          @bus.poke(BLOCK + 1, block & 0xff)
+          @bus.poke(ACTIVE, active)
+          @bus.poke(ACTIVE + 1, offset)
+          @bus.poke(ACTIVE + 2, @bus.peek(block + 9))
+          secondary = @bus.peek(block + 10)
+          @bus.poke(ACTIVE + 3, secondary)
+          @channel = secondary & 0x0f
+        end
+
+        def byte_out
+          return unless @listening
+
+          block = current_block
+          if @bus.peek(block).zero?
+            @buffer << (@cpu.d & 0xff)
+            @bus.poke(block, TIMED_OUT) unless accepted?
+          end
+          @cpu.d = 0x00ff
+          return_from_routine
+        end
+
+        def accepted? = [OPEN, CLOSE].include?(@frame) || @dos.listening?(@channel)
+
+        def unlisten
+          return unless @listening
+
+          finish_listening
+          @bus.poke(ACTIVE, 0)
+          return_from_routine
+        end
+
+        def finish_listening
+          @listening = false
+          case @frame
+          when OPEN then @dos.open(@channel, on_drive_zero(@buffer.pack("C*")))
+          when CLOSE then nil
+          else @dos.write(@channel, @buffer)
+          end
+          @buffer = []
+        end
+
+        def on_drive_zero(name) = name.start_with?("1:") ? "0:#{name[2..]}" : name
+
+        def byte_in
+          return unless @talking
+
+          block = current_block
+          byte = 0x0d
+          if @bus.peek(block).zero?
+            read, eoi = @dos.read(@channel)
+            if read.nil?
+              @bus.poke(block, TIMED_OUT)
+            else
+              byte = read
+              @bus.poke(block + 12, @bus.peek(block + 12) | 0x01) if eoi
+            end
+          end
+          @cpu.d = byte
+          return_from_routine
+        end
+
+        def untalk
+          return unless @talking
+
+          @talking = false
+          @bus.poke(ACTIVE, 0)
+          return_from_routine
+        end
+
+        def current_block = (@bus.peek(BLOCK) << 8) | @bus.peek(BLOCK + 1)
+
+        def return_from_routine
+          s = @cpu.s
+          @cpu.pc = (@bus.peek(s) << 8) | @bus.peek(s + 1)
+          @cpu.s = (s + 2) & 0xffff
+        end
+      end
+    end
+  end
+end

data/lib/badline/pet/superpet.rb

@@ -0,0 +1,221 @@
+# frozen_string_literal: true
+
+require "badline/chips/acia"
+require "badline/chips/m6809"
+require "badline/pet/superpet/dongle"
+require "badline/pet/superpet/acia"
+require "badline/pet/superpet/board"
+require "badline/pet/superpet/m6809"
+require "badline/pet/superpet/waterloo_traps"
+require "badline/pet/superpet/keyed_parts"
+require "badline/pet/superpet/keyed_modules"
+
+module Badline
+  class PET
+    # The SuperPET, the SP9000 or MMF 9000: an 8032 with the University of
+    # Waterloo's board in its CPU socket, with 64K of bank RAM, a 6551
+    # ACIA, the 6702 and a 6809E (Board). The board's ACIA pulls the PET's
+    # IRQ line with the PIAs and the VIA. Its character ROM, 901640-01,
+    # holds the 8032's in its first half and an ASCII and an APL set in
+    # its second, which the CRTC's MA13 picks.
+    #
+    # Both CPUs sit on the same bus at the same 1 MHz, and one runs at a
+    # time: SW2, the CPU switch, picks it, or with SW2 at PROG bit 0 of the
+    # system latch. The one that takes the bus over starts from its RESET
+    # (Fachat: "The 6502 does a RESET after being switched on"; on the
+    # 324037 schematic one-shots gate the 6809's RES), and the other stops
+    # where it is. The PET's IRQ line, the ACIA's with it, reaches both.
+    #
+    # The Waterloo ROMs hold only the menu, setup and the monitor. The
+    # menu loads every language, microBASIC, microAPL, FORTRAN, Pascal,
+    # COBOL, the editor and the development package, from disk into RAM,
+    # so 6809 mode needs a disk on device 8 to run one.
+    #
+    # In 6809 mode device 8 answers through traps on the Waterloo ROM's
+    # IEEE-488 routines (WaterlooTraps) as well as the KERNAL's, from the
+    # same disk, or a true drive on the bus answers. type_text types
+    # through the Waterloo ROM's key buffer, in ASCII, once its menu is up.
+    class SuperPET < PET
+      # The Waterloo ROM's key buffer: its read and write pointers, and the
+      # ring of bytes they run round.
+      KEYS_READ = 0x012c
+      KEYS_WRITE = 0x012e
+      KEYS_FIRST = 0x0130
+      KEYS_END = 0x0158
+
+      # The cycle by which the 6809 has put up the Waterloo menu, with a
+      # margin.
+      WATERLOO_BOOT = 600_000
+
+      attr_reader :board, :acia, :dongle, :m6809
+
+      # The traps on the Waterloo ROM's IEEE-488 routines, while a disk is
+      # on device 8 (WaterlooTraps).
+      attr_reader :waterloo_traps
+
+      # +cpu+ is SW2's position and +bank_ram+ SW1's, as Board names them.
+      # The other arguments are the PET's for an 8032, its true drive's too.
+      def initialize(refresh_hz: 50, debug: false, basic: nil, editor: nil, cpu: "6502", bank_ram: "rw",
+                     true_drive_model: Drives::IEEEModels::DEFAULT)
+        raise ArgumentError, "the CPU switch has no position #{cpu}" unless Board::CPU_SWITCH.include?(cpu)
+
+        super(model: "superpet", refresh_hz:, debug:, basic:, editor:, true_drive_model:)
+        @acia_irq = false
+        @acia_due = Chips::ACIA::NEVER
+        @acia = ACIA.new(self, 1_000_000)
+        @dongle = Dongle.new(self)
+        @board = Board.new(@bus, dongle: @dongle, acia: @acia, keyboard_ports: @keyboard_ports, cpu_switch: cpu,
+                                 ram_switch: bank_ram, refresh_hz: @refresh_hz)
+        @m6809 = M6809.new(@bus)
+        @m6809_running = @board.m6809?
+        @waterloo_traps = nil
+        @board.on_select { cpu_selected }
+        @bus.fit_board(@board)
+        @init_threshold = WATERLOO_BOOT if @m6809_running
+      end
+
+      # Whether an autostart finds BASIC: not while the 6809 runs.
+      def boots_basic? = !@m6809_running
+
+      # Device 8 through the traps, for the Waterloo ROM's routines too.
+      def mount(storage)
+        trap = super
+        @waterloo_traps ||= WaterlooTraps.new(cpu: @m6809, bus: @bus, dos: @dos).install
+        @waterloo_traps.device = trap_device
+        trap
+      end
+
+      def unmount
+        super
+        @waterloo_traps&.uninstall
+        @waterloo_traps = nil
+      end
+
+      def attach_ieee_drive(drive)
+        super
+        @waterloo_traps&.device = trap_device
+      end
+
+      def detach_ieee_drive
+        super
+        @waterloo_traps&.device = trap_device
+      end
+
+      # Types into the Waterloo ROM's key buffer, in ASCII, while the 6809
+      # runs, and into the editor's otherwise.
+      def type_text(text)
+        return super unless @m6809_running
+
+        type_on_init(text.bytes)
+      end
+
+      # Whether the 6809 has the bus, rather than the 6502.
+      def m6809_running? = @m6809_running
+
+      def superpet? = true
+
+      # Moves the CPU switch to +position+, one of Board::CPU_SWITCH, and
+      # resets the machine, so the CPU the switch picks starts from its
+      # RESET.
+      def switch_cpu(position)
+        @board.cpu_switch = position
+        reset!
+      end
+
+      # Moves the bank RAM switch to +position+, one of Board::RAM_SWITCH.
+      def switch_bank_ram(position)
+        @board.ram_switch = position
+      end
+
+      # Whether the picture shows the character ROM's APL set: its second
+      # half, which the CRTC's MA13 picks, with VIA CA2 high.
+      def apl_characters? = @crtc.registers[12].anybits?(0x20) && @via.ca2_output
+
+      # Drive 1 while the 6809 runs, where the Waterloo menu's "disk/1."
+      # looks, and drive 0 in 6502 mode.
+      def disk_drive_number = @m6809_running ? 1 : 0
+
+      # The 32K below $8000 and the 64K board.
+      def model_label = "SUPERPET, 96K RAM, #{@refresh_hz} HZ"
+
+      # The PET's cycle, with the ACIA run when it falls due and its IRQ
+      # on the CPU's.
+      def cycle!
+        handle_init if @cycles == @init_threshold
+        feed_keyboard if @pending_keys
+
+        @crtc.cycle!
+        drive_retrace(!@crtc.vsync?)
+        @pia1.cycle!
+        @pia2.cycle!
+        @via.cycle!
+        @sound.cycle! if @sound.recording?
+        @cassettes.cycle! if @tapes_running
+        @acia.run!(@cycles) if @cycles >= @acia_due
+        irq = @pia1.irq? || @pia2.irq? || @via.irq? || @acia_irq
+        if @m6809_running
+          @m6809.irq = irq
+          @m6809.cycle!
+        else
+          @cpu.irq = irq
+          @cpu.cycle!
+        end
+        clock_ieee_drives
+
+        @cycles += 1
+      end
+
+      # Whether the ACIA pulls the IRQ line.
+      def acia_irq? = @acia_irq
+
+      # The ACIA's IRQ line, and the cycle it next has something to do at.
+      def acia_changed(irq, due)
+        @acia_irq = irq
+        @acia_due = due
+      end
+
+      # The RES line reaches the board's latches, the 6702, the ACIA and
+      # both CPUs too.
+      def reset!
+        super
+        @acia.reset!
+        @m6809.reset!
+        @board.reset!
+      end
+
+      def power_cycle!
+        @board.power_on!
+        super
+      end
+
+      private
+
+      # The Waterloo ROM's ring takes keys until its write pointer would
+      # meet its read pointer.
+      def feed_keyboard
+        return super unless @m6809_running
+
+        read = word_at(KEYS_READ)
+        write = word_at(KEYS_WRITE)
+        until @pending_keys.empty?
+          following = write + 1 == KEYS_END ? KEYS_FIRST : write + 1
+          break if following == read
+
+          @bus.poke(write, @pending_keys.shift)
+          write = following
+        end
+        @bus.poke(KEYS_WRITE, write >> 8)
+        @bus.poke(KEYS_WRITE + 1, write & 0xff)
+        @pending_keys = nil if @pending_keys.empty?
+      end
+
+      def word_at(addr) = (@bus.peek(addr) << 8) | @bus.peek(addr + 1)
+
+      # The CPU the board picks takes the bus over from its RESET.
+      def cpu_selected
+        @m6809_running = @board.m6809?
+        @m6809_running ? @m6809.reset! : @cpu.reset!
+      end
+    end
+  end
+end

data/lib/badline/pet.rb

@@ -75,6 +75,8 @@ module Badline
 
     def family = :pet
 
+    def portless_board = nil
+
     # The datasette on cassette port #1, where a tape goes in (Cassettes).
     def datasette = @cassettes.datasette1
 
@@ -83,10 +85,13 @@ module Badline
     # model runs its 50 Hz editor, or its 60 Hz one for +refresh_hz+ 60.
     # +basic+, +editor+ and +characters+ name ROMs the board takes in place
     # of its own (Model.upgraded, Model.fitted), and +jumpers+ the 8296's
-    # board jumpers (ROMSets::JUMPERS).
+    # board jumpers (ROMSets::JUMPERS). +true_drive_model+ names the drive
+    # plug_true_drive plugs in (Drives::IEEEModels).
     def initialize(model: Model::DEFAULT, ram_kb: nil, refresh_hz: 50, debug: false, basic: nil, editor: nil,
-                   characters: nil, jumpers: [])
+                   characters: nil, jumpers: [], true_drive_model: Drives::IEEEModels::DEFAULT)
       @model = Model.fitted(Model.upgraded(Model.named(model), basic, editor), characters)
+      raise ArgumentError, "the SuperPET is built as PET::SuperPET" if @model.superpet? && !superpet?
+
       ram_kb ||= @model.ram_kb
       raise ArgumentError, "the #{@model.name} has no #{ram_kb}K RAM board" unless Model.ram_fits?(@model, ram_kb)
 
@@ -99,6 +104,7 @@ module Badline
       matrix = @model.keyboard == :business ? KeyboardPorts::BUSINESS_MATRIX : KeyboardPorts::GRAPHICS_MATRIX
       @keyboard = Input::Keyboard.new(matrix:)
       keyboard_ports = KeyboardPorts.new(@keyboard)
+      @keyboard_ports = keyboard_ports
       registers = Array.new(Chips::CRTC::MASKS.length, 0)
       @pia1 = Chips::PIA.new(peripheral: keyboard_ports)
       @ieee = IEEEPorts.new(Drives::IEEEBus.new)
@@ -125,16 +131,27 @@ module Badline
         ieee.lines_written
       end
       @cpu = CPU.new(@bus, debug:)
+      @cpu.power_on!
       @cycles = 0
       @init_handlers = []
       @pending_keys = nil
+      @init_keys = nil
       @dos = nil
       @ieee_trap = nil
       @capture_output = nil
-      init_ieee_drives
+      init_ieee_drives(true_drive_model)
       @init_threshold = boot_cycles(ram_kb)
     end
 
+    # Whether this is the SuperPET's board (SuperPET).
+    def superpet? = false
+
+    # Whether the picture shows the SuperPET's APL characters.
+    def apl_characters? = false
+
+    # Whether an autostart finds BASIC to type into.
+    def boots_basic? = true
+
     # The vertical drive line, high but in the retrace.
     def vertical_drive? = @vertical_drive
 
@@ -208,6 +225,7 @@ module Badline
     def power_cycle!
       @bus.power_on!
       reset!
+      @cpu.power_on!
     end
 
     # Puts a program file's bytes where its first two say, through the bus,
@@ -253,3 +271,5 @@ module Badline
     end
   end
 end
+
+require "badline/pet/superpet"

data/lib/badline/plus4/keyed_state.rb

@@ -28,6 +28,7 @@ module Badline
         out.int("cycles", @cycles)
         pending = @pending_keys
         out.ints("host.pending_keys", pending) if pending
+        save_init_keys(out)
         out.int("host.init_pending", booting? ? @init_handlers.length : 0)
         out.text("host.true_drive_model", @true_drive_model)
       end
@@ -36,6 +37,7 @@ module Badline
         @cycles = input.int("cycles", @cycles)
         pending = input.ints("host.pending_keys", [])
         @pending_keys = pending.empty? ? nil : pending.dup
+        load_init_keys(input)
         @init_handlers_lost = [input.int("host.init_pending", 0) - @init_handlers.length, 0].max
         @true_drive_model = input.choice("host.true_drive_model", TCBMDrive::TRUE_DRIVE_MODELS, @true_drive_model)
       end

data/lib/badline/plus4.rb

@@ -67,6 +67,8 @@ module Badline
 
     def family = :plus4
 
+    def portless_board = nil
+
     # The joysticks reach the TED's keyboard latch, so there are no C64
     # control ports to plug a pot device into.
     def control_ports = nil
@@ -139,11 +141,13 @@ module Badline
       @tias = tcbm ? [Chips::TIA.new, Chips::TIA.new] : []
       @bus.plug_tcbm(drive8: @tias[0], drive9: @tias[1]) if tcbm
       @cpu = CPU.new(@bus, debug:)
+      @cpu.power_on!
       @sound = Chips::TED::Sound.new(self, @model.ted.clock_hz)
       @ted.sound = @sound
       @sound_mix = @sid_card ? SoundMix.new(@sound, @sid_card) : nil
       @init_handlers = []
       @pending_keys = nil
+      @init_keys = nil
       @dos = nil
       @serial_trap = nil
       @save_trap = nil
@@ -201,6 +205,7 @@ module Badline
       @ted.power_on!
       @sound.power_on!
       reset!
+      @cpu.power_on!
     end
 
     # The ACIA's IRQ line, and the cycle it next has something to do at.