badline 0.17.0 → 0.19.0

data/lib/badline/pet/sound.rb

@@ -8,121 +8,21 @@ module Badline
     # added. CB2 carries the shift register's bits in its shift-out modes,
     # mode 4's free-running square wave under timer 2 for the bell and most
     # PET music, and the PCR's CB2 output otherwise, held high or low by
-    # hand or floating high as an input.
-    #
-    # The machine calls #cycle! once a cycle while #recording?, from #record
-    # on, so a sound nobody records costs only that check. Each sample is
-    # the share of its cycles CB2 spent high, through the output stage: a
-    # one-pole low-pass at 5 kHz and a one-pole high-pass at 100 Hz, so a
-    # line left high or low settles to silence.
+    # hand or floating high as an input. Machine::LineSound turns it into
+    # samples.
     class Sound
-      LOW_PASS_HZ = 5_000
-      HIGH_PASS_HZ = 100
-
-      # A swing from CB2 low to CB2 high, as a signed 16-bit sample.
-      SCALE = 24_000.0
+      include Machine::LineSound
 
       def initialize(via)
         @via = via
-        @recording = false
-        @high = true
-        @run = 0
-        @rate = 0
-        @clock_hz = 0
-        @remainder = 0
-        @window = 0
-        @left = 0
-        @sum = 0
-        @low = 0.0
-        @drift = 0.0
-        @low_pass = 0.0
-        @high_pass = 0.0
-        @samples = []
+        init_line_sound
       end
 
       def model = :cb2
 
-      attr_reader :recording
-      alias recording? recording
-
-      # Starts collecting the output, averaged down to `rate` samples a
-      # second at `clock_hz` cycles a second, for #drain_samples. The
-      # output stage takes CB2's level now as settled.
-      def record(rate:, clock_hz: 1_000_000)
-        @rate = rate
-        @clock_hz = clock_hz
-        @remainder = 0
-        @window = next_window
-        @left = @window
-        @sum = 0
-        @high = @via.cb2_output
-        @run = 0
-        @low = @drift = @high ? 1.0 : 0.0
-        @low_pass = 1.0 - Math.exp(-2.0 * Math::PI * LOW_PASS_HZ / rate)
-        @high_pass = 1.0 - Math.exp(-2.0 * Math::PI * HIGH_PASS_HZ / rate)
-        @samples = []
-        @recording = true
-      end
-
-      # Takes CB2's level for this cycle, while recording.
-      def cycle!
-        high = @via.cb2_output
-        if high == @high
-          @run += 1
-        else
-          hold(@high, @run)
-          @high = high
-          @run = 1
-        end
-      end
-
-      # The samples closed since the last drain.
-      def drain_samples
-        return [] unless @recording
-
-        hold(@high, @run)
-        @run = 0
-        samples = @samples
-        @samples = []
-        samples
-      end
-
       private
 
-      # Adds `cycles` cycles with CB2 high or low, closing every sample
-      # they finish.
-      def hold(high, cycles)
-        left = @left
-        while cycles >= left
-          @sum += left if high
-          cycles -= left
-          close
-          left = @left
-        end
-        @sum += cycles if high
-        @left = left - cycles
-      end
-
-      def close
-        @low += @low_pass * (@sum.fdiv(@window) - @low)
-        @drift += @high_pass * (@low - @drift)
-        sample = ((@low - @drift) * SCALE).round
-        sample = 32_767 if sample > 32_767
-        sample = -32_768 if sample < -32_768
-        @samples << sample
-        @sum = 0
-        @window = next_window
-        @left = @window
-      end
-
-      # Each window is a whole number of cycles, and they add up to the
-      # clock's cycles over a second.
-      def next_window
-        @remainder += @clock_hz
-        cycles = @remainder / @rate
-        @remainder -= cycles * @rate
-        cycles
-      end
+      def line_high? = @via.cb2_output
     end
   end
 end

data/lib/badline/pet/superpet/acia.rb

@@ -0,0 +1,12 @@
+# frozen_string_literal: true
+
+module Badline
+  class PET
+    class SuperPET < PET
+      # The board's 6551 at $EFF0, the RS-232 port's, on a 1.8432 MHz
+      # crystal, whose IRQ joins the PET's.
+      class ACIA < Chips::ACIA
+      end
+    end
+  end
+end

data/lib/badline/pet/superpet/board.rb

@@ -0,0 +1,221 @@
+# frozen_string_literal: true
+
+module Badline
+  class PET
+    class SuperPET < PET
+      # The Waterloo board, after Levak's PET-Interfaces.txt, André
+      # Fachat's SuperPET page and Commodore's 324037 schematic: 64K of
+      # RAM in 16 banks of 4K, one at a time at $9000-$9FFF, and the I/O
+      # page at $EF00 (IOPage), which both CPUs reach.
+      #
+      # The bank latch at $EFFC-$EFFD picks the bank with bits 0-3, and its
+      # bit 7 lets writes reach the system latch at $EFF8-$EFFB:
+      #
+      #   bit 0  the CPU while SW2 is at PROG: 1 the 6502, 0 the 6809
+      #   bit 1  the bank RAM while SW1 is at PROG: 1 read/write, 0 read only
+      #   bit 3  pulls the user port's diagnostic sense, PIA 1's PA7, low
+      #
+      # Bit 0 of $EFFE-$EFFF puts the board's own ROM socket at $9000 in
+      # place of the RAM, which badline leaves empty, while the 6502 runs.
+      # All three are write-only, and the RES line clears them, so the
+      # board starts at bank 0, and with SW2 at PROG with the 6809.
+      #
+      # SW1 is READ, R/W or PROG, the bank RAM's write protect, and SW2
+      # PROG, 6502 or 6809, the CPU. A write to the bank RAM while it is
+      # protected goes nowhere.
+      #
+      # While the 6809 runs, the 8032's ROMs step aside through its NO ROM
+      # line, and the Waterloo ROMs answer at $A000-$E7FF and $F000-$FFFF,
+      # the $E000 one with the CRTC table for the frame rate.
+      class Board
+        CPU_SWITCH = %w[6502 6809 prog].freeze
+
+        RAM_SWITCH = %w[rw read prog].freeze
+
+        # $EF00-$EFFF: the 6702 at $EFE0-$EFE3, the ACIA at $EFF0-$EFF3
+        # and the latches above. A read of a latch finds the last byte on
+        # the bus, and below $EFF0, where neither chip answers, $FF.
+        class IOPage
+          def initialize(board, bus, dongle, acia)
+            @board = board
+            @bus = bus
+            @dongle = dongle
+            @acia = acia
+          end
+
+          def peek(addr)
+            low = addr & 0xff
+            return @bus.data if low >= 0xf4
+            return @acia.peek(addr) if low >= 0xf0
+            return @dongle.peek(addr) if low >= 0xe0 && low < 0xe4
+
+            0xff
+          end
+
+          def poke(addr, value)
+            low = addr & 0xff
+            if low >= 0xfe
+              @board.socket = value
+            elsif low >= 0xfc
+              @board.bank_latch = value
+            elsif low >= 0xf8
+              @board.system_latch = value
+            elsif low >= 0xf0
+              @acia.poke(addr, value) if low < 0xf4
+            elsif low >= 0xe0
+              @dongle.poke(addr, value) if low < 0xe4
+            end
+          end
+        end
+
+        attr_reader :cells, :bank_latch, :system_latch, :cpu_switch, :ram_switch
+
+        # Bit 0 of $EFFE: 1 for the ROM socket at $9000.
+        attr_reader :socket
+
+        # +bus+ is the PET's, whose pages the board maps, and
+        # +keyboard_ports+ PIA 1's, whose PA7 the diagnostic sense is.
+        # +cpu_switch+ and +ram_switch+ are SW2's and SW1's positions, one
+        # of CPU_SWITCH's and RAM_SWITCH's, and +refresh_hz+ picks the
+        # Waterloo $E000 ROM, 50 or 60.
+        def initialize(bus, dongle:, acia:, keyboard_ports:, cpu_switch: "6502", ram_switch: "rw",
+                       refresh_hz: 50)
+          raise ArgumentError, "the CPU switch has no position #{cpu_switch}" unless CPU_SWITCH.include?(cpu_switch)
+          raise ArgumentError, "the RAM switch has no position #{ram_switch}" unless RAM_SWITCH.include?(ram_switch)
+
+          @bus = bus
+          @dongle = dongle
+          @keyboard_ports = keyboard_ports
+          @cpu_switch = cpu_switch
+          @ram_switch = ram_switch
+          @cells = Array.new(0x10000, 0)
+          @banks = Array.new(16) { |bank| Bus::Expansion::Window.new(@cells, bank << 12, 0x9000) }
+          @io = IOPage.new(self, bus, dongle, acia)
+          @bank_latch = 0
+          @system_latch = 0
+          @socket = 0
+          @rom_a = ROM.load("pet/superpet-a000.rom", 0xa000)
+          @rom_c = ROM.load("pet/superpet-c000.rom", 0xc000)
+          @rom_e = ROM.load(refresh_hz == 50 ? "pet/superpet-e000-50hz.rom" : "pet/superpet-e000.rom", 0xe000)
+          @m6809 = m6809_selected?
+          @select_handler = nil
+        end
+
+        # Calls the block when the CPU the switch and the system latch pick
+        # changes.
+        def on_select(&handler)
+          @select_handler = handler
+        end
+
+        # Whether the 6809 has the bus.
+        def m6809? = @m6809
+
+        def bank = @bank_latch & 0x0f
+
+        def bank_latch=(value)
+          @bank_latch = value
+          @bus.map_pages
+        end
+
+        def system_latch=(value)
+          return if @bank_latch.nobits?(0x80)
+
+          @system_latch = value
+          @keyboard_ports.diagnostic_low = value.anybits?(0x08)
+          select
+        end
+
+        def socket=(value)
+          @socket = @m6809 ? 0 : value & 0x01
+          @bus.map_pages
+        end
+
+        # Moves SW2, which picks the CPU at the next RES.
+        def cpu_switch=(position)
+          raise ArgumentError, "the CPU switch has no position #{position}" unless CPU_SWITCH.include?(position)
+
+          @cpu_switch = position
+        end
+
+        # Moves SW1, which protects the bank RAM from the next write on.
+        def ram_switch=(position)
+          raise ArgumentError, "the RAM switch has no position #{position}" unless RAM_SWITCH.include?(position)
+
+          @ram_switch = position
+          @bus.map_pages
+        end
+
+        # Whether writes to the bank RAM go nowhere.
+        def write_protected?
+          case @ram_switch
+          when "read" then true
+          when "rw" then false
+          else @system_latch.nobits?(0x02)
+          end
+        end
+
+        # Whether the CPU switch, or the system latch with it at PROG,
+        # picks the 6809.
+        def m6809_selected?
+          case @cpu_switch
+          when "6502" then false
+          when "6809" then true
+          else @system_latch.nobits?(0x01)
+          end
+        end
+
+        # The RES line clears the latches, and the 6702.
+        def reset!
+          @bank_latch = 0
+          @system_latch = 0
+          @socket = 0
+          @keyboard_ports.diagnostic_low = false
+          @dongle.reset!
+          select
+        end
+
+        def power_on!
+          @cells.fill(0)
+        end
+
+        # Lays the bank, or the empty socket, over $9000-$9FFF, the I/O
+        # page over $EF00, and the Waterloo ROMs over the 8032's while the
+        # 6809 runs.
+        def map(reads, writes)
+          if @socket.zero?
+            window = @banks[bank]
+            window.read_only = write_protected?
+            reads.fill(window, 0x90, 0x10)
+            writes.fill(window, 0x90, 0x10)
+          else
+            reads.fill(@bus.open_bus, 0x90, 0x10)
+            writes.fill(@bus.open_bus, 0x90, 0x10)
+          end
+          reads[0xef] = @io
+          writes[0xef] = @io
+          map_waterloo(reads) if @m6809
+        end
+
+        private
+
+        # Picks the CPU again, and hands the bus over if that changed it.
+        # The 6809 taking over clears the socket bit.
+        def select
+          m6809 = m6809_selected?
+          changed = m6809 != @m6809
+          @m6809 = m6809
+          @socket = 0 if m6809
+          @bus.map_pages
+          @select_handler&.call if changed
+        end
+
+        def map_waterloo(reads)
+          reads.fill(@rom_a, 0xa0, 0x20)
+          reads.fill(@rom_c, 0xc0, 0x20)
+          reads.fill(@rom_e, 0xe0, 0x08)
+          reads.fill(@rom_e, 0xf0, 0x10)
+        end
+      end
+    end
+  end
+end

data/lib/badline/pet/superpet/dongle.rb

@@ -0,0 +1,92 @@
+# frozen_string_literal: true
+
+module Badline
+  class PET
+    class SuperPET < PET
+      # The 6702 at $EFE0-$EFE3, the protection chip the Waterloo languages
+      # check for. Its behaviour comes from David Roberts' Visual 6702, a
+      # switch-level simulation of the decapped chip's netlist, driven a
+      # bus cycle at a time.
+      #
+      # Each data line has a shift register of its own, LENGTHS long, whose
+      # first stage the line reads, inverted where INVERTED has the bit
+      # set. A latch keeps the last byte written, all ones from the RES
+      # line. A write that sets D0 where the last one left it clear shifts
+      # every register one stage at the end of the next cycle, whichever
+      # cycle that is, so a read in it still finds the old byte. Each
+      # register takes in its first stage XORed with the latch's bit,
+      # inverted where FEEDBACK has the bit clear, the latch as that cycle
+      # leaves it. The RES line clears the registers.
+      class Dongle
+        LENGTHS = [6, 3, 7, 8, 1, 3, 5, 2].freeze
+
+        INVERTED = 0xd6
+
+        FEEDBACK = 0x29
+
+        # No shift waiting.
+        NONE = -1
+
+        # The registers, bit 0 of each the stage its line reads, the latch,
+        # and the cycle at whose end the registers shift, or NONE.
+        attr_reader :registers, :latch, :shift_at
+
+        # +clock+ answers #cycles, the cycle the CPU's access falls in.
+        def initialize(clock)
+          @clock = clock
+          @registers = Array.new(8, 0)
+          reset!
+        end
+
+        def reset!
+          @registers.fill(0)
+          @latch = 0xff
+          @shift_at = NONE
+        end
+
+        def peek(_addr)
+          now = @clock.cycles
+          shift if @shift_at != NONE && @shift_at < now
+          value = 0
+          8.times { |bit| value |= (@registers[bit] & 1) << bit }
+          value ^ INVERTED
+        end
+
+        def poke(_addr, value)
+          now = @clock.cycles
+          shift if @shift_at != NONE && @shift_at < now
+          raising = value.anybits?(0x01) && @latch.nobits?(0x01)
+          @latch = value
+          if @shift_at == now
+            shift
+          elsif raising
+            @shift_at = now + 1
+          end
+        end
+
+        # The registers as they stand once a shift waiting has happened.
+        def settled_registers
+          registers = @registers.dup
+          shift_registers(registers) if @shift_at != NONE
+          registers
+        end
+
+        private
+
+        def shift
+          @shift_at = NONE
+          shift_registers(@registers)
+        end
+
+        def shift_registers(registers)
+          incoming = @latch ^ FEEDBACK ^ 0xff
+          8.times do |bit|
+            register = registers[bit]
+            stage = (register ^ (incoming >> bit)) & 1
+            registers[bit] = (register >> 1) | (stage << (LENGTHS[bit] - 1))
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/pet/superpet/keyed_modules.rb

@@ -0,0 +1,63 @@
+# frozen_string_literal: true
+
+module Badline
+  class PET
+    class SuperPET < PET
+      # The SuperPET as keyed snapshot modules: the 8032's (PET::KeyedModules),
+      # then BL-SUPERPET with the board and the 6702 under dongle.*, BL-ACIA
+      # and BL-M6809. The traps on the Waterloo ROM's routines go in
+      # BL-TRAPDOS under waterloo.*, beside the KERNAL's. Without BL-ACIA or
+      # BL-M6809, as from xpet, the unit stays as it is. The CPU switch and
+      # the latches say which CPU has the bus, and the CPU that has it
+      # settles on its instruction boundary, or in SYNC or CWAI.
+      module KeyedModules
+        def settled_for_snapshot?
+          return super unless @m6809_running
+
+          @m6809.boundary? || @m6809.waiting?
+        end
+
+        def save_modules
+          sections = super
+          board = @board
+          dongle = @dongle
+          sections << Snapshot::Keyed.section("BL-SUPERPET") do |out|
+            board.save_fields(out)
+            dongle.save_fields(out, "dongle.")
+          end
+          sections << Snapshot::Keyed.section("BL-ACIA") { |out| @acia.save_fields(out) }
+          sections << Snapshot::Keyed.section("BL-M6809") { |out| @m6809.save_fields(out) }
+          sections
+        end
+
+        def load_modules(modules)
+          super
+          board = modules.required("BL-SUPERPET")
+          @board.load_fields(board)
+          @dongle.load_fields(board, "dongle.")
+          acia = modules.optional("BL-ACIA")
+          @acia.load_fields(acia) if acia
+          m6809 = modules.optional("BL-M6809")
+          @m6809.load_fields(m6809) if m6809
+          @m6809_running = @board.m6809?
+          @board.restored!
+          @acia.restored!
+          @m6809.restored!
+          self
+        end
+
+        def save_trap_dos_fields(out)
+          super
+          @waterloo_traps&.save_fields(out, "waterloo.")
+        end
+
+        def load_trap_dos_fields(input, detached: false)
+          super
+          @waterloo_traps&.load_fields(input, "waterloo.")
+        end
+      end
+
+      include KeyedModules
+    end
+  end
+end

data/lib/badline/pet/superpet/keyed_parts.rb

@@ -0,0 +1,76 @@
+# frozen_string_literal: true
+
+module Badline
+  class PET
+    class SuperPET < PET
+      class Board
+        # The latches, the socket bit and the 64K of bank RAM, in a keyed
+        # snapshot module (BL-SUPERPET). The switches come with the setup
+        # (Snapshot::PETSetup). Which CPU has the bus, and the diagnostic
+        # sense line, follow from the latches once loaded, and the pages
+        # are laid out again (#restored!).
+        module KeyedState
+          def save_fields(out)
+            out.int("bank_latch", @bank_latch).int("system_latch", @system_latch).int("socket", @socket)
+            out.bytes("ram", @cells)
+          end
+
+          def load_fields(input)
+            @bank_latch = input.byte("bank_latch", 0)
+            @system_latch = input.byte("system_latch", 0)
+            @socket = input.int("socket", 0) & 0x01
+            input.bytes_into("ram", @cells)
+            @m6809 = m6809_selected?
+            @keyboard_ports.diagnostic_low = @system_latch.anybits?(0x08)
+          end
+
+          def restored! = @bus.map_pages
+        end
+
+        include KeyedState
+      end
+
+      class Dongle
+        # The shift registers, the latch and a shift waiting, as the cycles
+        # from now to the one it ends, under `prefix`.
+        module KeyedState
+          def save_fields(out, prefix)
+            out.ints("#{prefix}registers", @registers).int("#{prefix}latch", @latch)
+            out.optional_int("#{prefix}shift_in", @shift_at == NONE ? nil : @shift_at - @clock.cycles)
+          end
+
+          def load_fields(input, prefix)
+            input.ints_into("#{prefix}registers", @registers)
+            @latch = input.byte("#{prefix}latch", 0xff)
+            shift_in = input.optional_int("#{prefix}shift_in")
+            @shift_at = shift_in.nil? ? NONE : @clock.cycles + shift_in
+          end
+        end
+
+        include KeyedState
+      end
+
+      class WaterlooTraps
+        # Whether a served device listens or talks, the channel and the
+        # command it was addressed with, and the bytes sent it so far,
+        # under `prefix`.
+        module KeyedState
+          def save_fields(out, prefix)
+            out.bool("#{prefix}listening", @listening).bool("#{prefix}talking", @talking)
+            out.int("#{prefix}channel", @channel).int("#{prefix}frame", @frame).ints("#{prefix}buffer", @buffer)
+          end
+
+          def load_fields(input, prefix)
+            @listening = input.bool("#{prefix}listening", false)
+            @talking = input.bool("#{prefix}talking", false)
+            @channel = input.int("#{prefix}channel", 0) & 0x0f
+            @frame = input.byte("#{prefix}frame", 0)
+            @buffer = input.ints("#{prefix}buffer", []).map { |byte| byte & 0xff }
+          end
+        end
+
+        include KeyedState
+      end
+    end
+  end
+end

data/lib/badline/pet/superpet/m6809.rb

@@ -0,0 +1,32 @@
+# frozen_string_literal: true
+
+module Badline
+  class PET
+    class SuperPET < PET
+      # The board's 6809E, on the PET's bus, as the 6502 is. A trap
+      # installed on an address runs as the 6809 is about to fetch an
+      # opcode there, and may move the PC on.
+      class M6809
+        include Chips::M6809::Core
+
+        def initialize(bus)
+          super
+          @traps = nil
+        end
+
+        def install_trap(addr, &handler)
+          (@traps ||= {})[addr] = handler
+        end
+
+        def remove_trap(addr)
+          @traps&.delete(addr)
+        end
+
+        def cycle!
+          @traps[@pc]&.call if @traps && boundary?
+          super
+        end
+      end
+    end
+  end
+end