badline 0.17.0 → 0.19.0

data/lib/badline/drives/model8050/fdc_bus.rb

@@ -31,6 +31,10 @@ module Badline
         # last cleared (Model8050::Idle).
         attr_accessor :volatile
 
+        # The bytes of the 6530's RAM read or written since it was last
+        # cleared, a bit for each pair of them (Model8050::Idle).
+        attr_accessor :ram_touched
+
         def initialize(common:, via:, rriot:)
           addressable_at(0, length: 2**16)
           @common = common
@@ -38,6 +42,7 @@ module Badline
           @rriot = rriot
           @data = 0
           @volatile = false
+          @ram_touched = 0
           @common_changes = 0
         end
 
@@ -78,6 +83,7 @@ module Badline
           end
           return peek_via(addr & 0x0f) if addr.anybits?(0x40)
 
+          @ram_touched |= 1 << ((addr & 0x3f) >> 1)
           @rriot.read_ram(addr)
         end
 
@@ -93,6 +99,7 @@ module Badline
           elsif addr.anybits?(0x40)
             @via.poke(0x40 | (addr & 0x0f), value)
           else
+            @ram_touched |= 1 << ((addr & 0x3f) >> 1)
             @rriot.write_ram(addr, value)
           end
         end

data/lib/badline/drives/model8050/idle.rb

@@ -5,10 +5,11 @@ module Badline
     class Model8050
       # Sleeping through the two processors' idle loops, exactly.
       #
-      # With nothing to do, the IP goes round DOS 2.7's idle loop from
-      # IP_LOOP, and the FDC round its job loop from FDC_LOOP, each pass
-      # finding the job queue empty, until ATN interrupts the IP or the
-      # 6530's timer the FDC, every 5 ms. A pass puts back what it found,
+      # With nothing to do, the IP goes round its DOS's idle loop from
+      # @ip_loop, and the FDC round its job loop from @fdc_loop (IP_LOOP and
+      # FDC_LOOP on the 8050), each pass finding the job queue empty, until
+      # ATN interrupts the IP or the 6530's timer the FDC, every 5 ms on the
+      # 8050. A pass puts back what it found,
       # so each processor comes back to its loop's start as it left it, and
       # only the chips' counters and the cycle counts move.
       #
@@ -20,10 +21,10 @@ module Badline
       # volatile), makes the pass repeatable. Once both processors have a
       # repeatable pass, with the motors off, no head stepping, no disk
       # going in or out and no interrupt pulled, the unit sleeps:
-      # host_cycle! only counts the cycles it owes, until one of the chips'
-      # counters is due to pull IRQ (quiet_cycles), the controller moves a
-      # line of the bus, or something outside reads or changes the unit
-      # (settle!).
+      # host_cycle! only counts host cycles, until the one in which a chip's
+      # counter is due to pull IRQ (quiet_cycles), until the controller
+      # moves a line of the bus (host_written!), or until something outside
+      # reads or changes the unit (settle!).
       #
       # Waking runs the counters on in bulk, counts off each processor's
       # whole passes, and runs the rest of a pass on that processor alone.
@@ -31,8 +32,21 @@ module Badline
       # order the two run in doesn't matter. Then the unit runs cycle by
       # cycle again. Woken by a counter, it keeps the passes it found, and
       # sleeps again as soon as both repeat: the IP's, which the timer's
-      # interrupt doesn't reach, at once, and the FDC's a pass after its
-      # interrupt. Woken from outside, it finds both afresh.
+      # interrupt doesn't reach, at once, and the FDC's once it is back at
+      # its loop's start where its last pass proved to repeat but for the
+      # bytes the interrupt changed (fdc_pass_found). Woken from outside, it
+      # finds both afresh.
+      #
+      # Woken by a counter on the FDC's side, as the 6530's timer wakes the
+      # controller every 5 ms, the unit wakes only the FDC's side, as the
+      # board does: the FDC with its VIA, its 6530 and the drives run cycle
+      # by cycle (fdc_step) through the interrupt, and the IP owes its
+      # cycles. The two sides meet only in the common RAM, and the IP's
+      # pass reads none of the FDC's chips, so while no write changes the
+      # common RAM, the IP's pass runs on as it did. The IP catches up on its
+      # passes as the unit falls asleep again, as soon as a write changes
+      # the common RAM, before a counter on its side is due to pull its IRQ,
+      # and when something outside reads or changes the unit.
       module Idle
         IP_LOOP = 0xc5a1
         FDC_LOOP = 0xfc17
@@ -47,20 +61,37 @@ module Badline
 
         def asleep? = @asleep
 
+        # Whether the unit, or the IP's side of it, owes cycles.
+        def dozing? = @asleep || @fdc_alone
+
         # Brings the unit up to the present, cycle for cycle, and drops the
         # passes it found, since whoever called may change it.
         def settle!
-          wake! if @asleep
+          if @asleep
+            wake!
+            @asleep = false
+          end
+          join_ip if @fdc_alone
           forget_passes
         end
 
         private
 
-        def init_idle
+        # The unit's loops start at +ip_loop+ and +fdc_loop+.
+        def init_idle(ip_loop, fdc_loop)
+          @ip_loop = ip_loop
+          @fdc_loop = fdc_loop
           @idle_skip = true
           @asleep = false
           @owed = 0
           @budget = 0
+          @fdc_alone = false
+          @ip_owed = 0
+          @ip_budget = 0
+          @alone_changes = 0
+          @planned = false
+          @slept = 0
+          @wake_at = 0
           forget_passes
         end
 
@@ -69,13 +100,53 @@ module Badline
           @fdc_mark = nil
           @ip_pass = nil
           @fdc_pass = nil
+          @fdc_proof = nil
         end
 
         # A cycle owed while asleep, which wakes the unit once the budget
-        # is spent.
+        # is spent: the FDC's side alone if the IP's counters leave it
+        # room.
         def owe_cycle
           @owed += 1
-          wake! if @owed >= @budget
+          return if @owed < @budget
+
+          wake!
+          wake_fdc unless @asleep
+        end
+
+        # The FDC's side runs on alone while the IP owes its cycles.
+        def wake_fdc
+          budget = [@data_riot.quiet_cycles, @control_riot.quiet_cycles].min
+          return if budget < 2 || @ip_pass.nil? || @fdc_alone
+
+          @fdc_alone = true
+          @ip_owed = 0
+          @ip_budget = budget
+          @alone_changes = common_changes
+        end
+
+        # A cycle of the FDC's side alone, the IP owing it. A write that
+        # changed the common RAM, or the IP's counters coming due, has the
+        # IP catch up and the unit run whole again.
+        def fdc_alone_cycle
+          fdc_step
+          @ip_owed += 1
+          return join_ip if common_changes != @alone_changes || @ip_owed >= @ip_budget
+
+          fdc = @fdc_cpu
+          @fdc_pass = nil if fdc.irq
+          fdc_pass_found if fdc.program_counter == @fdc_loop && fdc.boundary?
+        end
+
+        # Runs the IP's side over the cycles it owes, its counters in bulk
+        # and its passes, and the unit whole from then on.
+        def join_ip
+          owed = @ip_owed
+          @fdc_alone = false
+          @ip_owed = 0
+          @data_riot.fast_forward(owed)
+          @control_riot.fast_forward(owed)
+          skip(@ip_cpu, @ip_pass, @ip_mark, owed)
         end
 
         # Looks for the loops' starts after a cycle run awake. An interrupt
@@ -84,9 +155,9 @@ module Badline
           ip = @ip_cpu
           @ip_pass = nil if ip.irq
           @fdc_pass = nil if @fdc_cpu.irq
-          ip_pass_found if ip.program_counter == IP_LOOP && ip.boundary?
+          ip_pass_found if ip.program_counter == @ip_loop && ip.boundary?
           fdc = @fdc_cpu
-          fdc_pass_found if fdc.program_counter == FDC_LOOP && fdc.boundary?
+          fdc_pass_found if fdc.program_counter == @fdc_loop && fdc.boundary?
         end
 
         def ip_pass_found
@@ -97,12 +168,44 @@ module Badline
           fall_asleep if @ip_pass && @fdc_pass
         end
 
+        # The FDC is at its loop's start. A pass that repeated is kept as a
+        # proof with the bytes of the 6530's RAM it touched: from a state
+        # that differs from the proof's only in other bytes, as the timer's
+        # interrupt leaves it, the pass runs the same way and repeats too.
         def fdc_pass_found
-          state = fdc_state
-          @fdc_pass = repeated(@fdc_mark, state, @fdc_cpu, @fdc_bus.volatile)
+          registers = fdc_state
+          ram = @rriot.ram.dup
+          state = [registers, ram]
+          bus = @fdc_bus
+          touched = bus.ram_touched
+          pass = repeated(@fdc_mark, state, @fdc_cpu, bus.volatile)
+          if pass
+            @fdc_proof = [registers, ram, touched, pass]
+          elsif proven?(registers, ram)
+            pass = @fdc_proof[3]
+          end
+          @fdc_pass = pass
           @fdc_mark = [state, @fdc_cpu.cycles, @fdc_cpu.instructions]
-          @fdc_bus.volatile = false
-          fall_asleep if @ip_pass && @fdc_pass
+          bus.volatile = false
+          bus.ram_touched = 0
+          fall_asleep if @ip_pass && pass
+        end
+
+        # Whether the FDC stands where the proof's pass started, but for
+        # bytes of the 6530's RAM the pass didn't touch.
+        def proven?(registers, ram)
+          proof = @fdc_proof
+          return false if proof.nil? || proof[0] != registers
+
+          start = proof[1]
+          touched = proof[2]
+          index = 0
+          while index < 64
+            return false if touched.anybits?(1 << (index >> 1)) && start[index] != ram[index]
+
+            index += 1
+          end
+          true
         end
 
         # The pass since +mark+ as [cycles, instructions] if it left the
@@ -114,6 +217,7 @@ module Badline
         end
 
         def fall_asleep
+          join_ip if @fdc_alone
           return unless @mechanism.quiet? && !@ip_cpu.irq && !@fdc_cpu.irq
 
           budget = quiet_cycles
@@ -132,18 +236,30 @@ module Badline
         # Runs the cycles owed: the counters in bulk, then each processor's
         # whole passes and the rest of a pass.
         def wake!
+          owe_slept
           owed = @owed
           @asleep = false
           @owed = 0
-          return if owed.zero?
+          quiet = [owed, @budget].min
+          skip_passes(quiet) if quiet.positive?
+          (owed - quiet).times { @asleep ? owe_cycle : run_cycle }
+        end
 
-          @data_riot.fast_forward(owed)
-          @control_riot.fast_forward(owed)
-          @rriot.fast_forward(owed)
-          @via.fast_forward(owed)
-          skip(@ip_cpu, @ip_pass, @ip_mark, owed)
-          skip(@fdc_cpu, @fdc_pass, @fdc_mark, owed)
-          @cycles += owed
+        def skip_passes(cycles)
+          @data_riot.fast_forward(cycles)
+          @control_riot.fast_forward(cycles)
+          @rriot.fast_forward(cycles)
+          @via.fast_forward(cycles)
+          skip(@ip_cpu, @ip_pass, @ip_mark, cycles)
+          skip(@fdc_cpu, @fdc_pass, @fdc_mark, cycles)
+          @cycles += cycles
+        end
+
+        # The budget is spent: the unit wakes, its FDC's side alone if it
+        # can.
+        def doze
+          wake!
+          wake_fdc unless @asleep
         end
 
         # Counts off the processor's whole passes, moving its mark on with
@@ -163,10 +279,11 @@ module Badline
           [*@ip_cpu.idle_state, *@data_riot.idle_state, *@control_riot.idle_state, @ip_bus.data, common_changes]
         end
 
-        # What the FDC sees: its CPU, the VIA and the 6530 but for their
-        # counters, its bus's last byte, the drives and the common RAM.
+        # What the FDC sees but the 6530's RAM: its CPU, the VIA and the
+        # 6530's ports and timer but for their counters, its bus's last
+        # byte, the drives and the common RAM.
         def fdc_state
-          [*@fdc_cpu.idle_state, *@via.idle_state, *@rriot.idle_state, @fdc_bus.data, *@mechanism.idle_state,
+          [*@fdc_cpu.idle_state, *@via.idle_state, *@rriot.port_state, @fdc_bus.data, *@mechanism.idle_state,
            common_changes]
         end
 

data/lib/badline/drives/model8050/keyed_state.rb

@@ -16,7 +16,7 @@ module Badline
           def save_fields(out)
             image = @image
             out.text("path", image.path.to_s).bool("read_only", image.read_only?)
-            out.text("image.format", image.is_a?(Storage::D82Image) ? "d82" : "d80")
+            out.text("image.format", image_format)
             out.bytes("image", image.contents)
             @tracks.each do |number, cells|
               out.ints("track#{number}", cells) unless cells == build(number)
@@ -37,6 +37,9 @@ module Badline
 
         include KeyedState
 
+        # The kind of image the disk lays out, as image.format names it.
+        def image_format = @image.is_a?(Storage::D82Image) ? "d82" : "d80"
+
         # The disk a BL-D8-DISK module holds. A detached reader gets the
         # image write-protected, and it and a host file that is gone leave
         # it no path to write back to.
@@ -141,7 +144,7 @@ module Badline
           @rriot.load_fields(modules.required("#{name}-RRIOT"))
           disks = [0, 1].map do |drive|
             disk = modules.optional(disk_module(name, drive))
-            disk.nil? ? nil : Disk.from_fields(disk, detached: modules.detached?)
+            disk.nil? ? nil : disk_from_fields(disk, modules.detached?)
           end
           @mechanism.load_fields(modules.required("#{name}-MECH"), disks)
           @via.restored!

data/lib/badline/drives/model8050.rb

@@ -10,6 +10,8 @@ require "badline/drives/model8050/parts"
 require "badline/drives/model8050/ieee_port"
 require "badline/drives/model8050/disk"
 require "badline/drives/model8050/mechanism"
+require "badline/drives/model8050/dos_board"
+require "badline/drives/model8050/board"
 require "badline/drives/model8050/idle"
 require "badline/drives/model8050/keyed_state"
 
@@ -18,25 +20,21 @@ module Badline
     # The 8050 dual disk drive of the PET and CBM-II, two drives on one
     # IEEE-488 unit (schematic 8050001; the 8050/8250 service manual).
     #
-    # Two 6502s share the board, clocked at 1 MHz from one 12 MHz crystal
-    # on opposite phases. The interface processor (IP) runs DOS 2.7 from
-    # 16 KB of ROM at $C000, with two 6532s (IPBus): their RAM is its zero
-    # page and stack, and their ports face the IEEE-488 bus (IEEEPort). The
-    # floppy controller (FDC) runs the 1 KB program in its 6530's ROM, with
-    # a VIA and the 6530 facing the drives (FDCBus, Mechanism). The two
-    # meet in 4 KB of common RAM, which each reaches in its own half of
-    # the cycle: the IP leaves jobs there, and the FDC runs them.
+    # Two 6502s share the board (Board), clocked at 1 MHz from one 12 MHz
+    # crystal on opposite phases. The interface processor (IP) runs DOS 2.7
+    # from 16 KB of ROM at $C000, with two 6532s (IPBus): their RAM is its
+    # zero page and stack, and their ports face the IEEE-488 bus
+    # (IEEEPort). The floppy controller (FDC) runs the 1 KB program in its
+    # 6530's ROM, with a VIA and the 6530 facing the drives (FDCBus,
+    # Mechanism). The two meet in 4 KB of common RAM, which each reaches in
+    # its own half of the cycle: the IP leaves jobs there, and the FDC runs
+    # them.
     #
     # Reset starts both. The FDC waits on the common RAM for the IP, which
     # tests it, copies the FDC's start-up code into it ($C370) and waits for
     # the FDC to answer, before both settle into their idle loops.
-    #
-    # The drive clocks against the host through a phase accumulator, as
-    # Drives::Engine::Core does: each host cycle adds 1 MHz of phase, and
-    # every whole host period in it runs a cycle of both processors. While
-    # both processors idle, it sleeps instead (Idle), and the readers of its
-    # parts catch it up first.
     class Model8050
+      include Board
       include Idle
 
       CLOCK_HZ = 1_000_000
@@ -45,37 +43,10 @@ module Badline
       # run the IP's RAM test and the FDC's start-up and reads its jumpers.
       BOOT_CYCLES = 1_500_000
 
-      attr_reader :device, :ieee_bus
-
-      def ip_cpu = settled(@ip_cpu)
-
-      def fdc_cpu = settled(@fdc_cpu)
-
-      def ip_bus = settled(@ip_bus)
-
-      def fdc_bus = settled(@fdc_bus)
-
-      def common = settled(@common)
-
-      def data_riot = settled(@data_riot)
-
-      def control_riot = settled(@control_riot)
-
-      def via = settled(@via)
-
-      def rriot = settled(@rriot)
-
-      def mechanism = settled(@mechanism)
-
-      def cycles
-        settle!
-        @cycles
-      end
-
-      attr_writer :host_clock_hz
-
       def model_name = "8050"
 
+      def boot_cycles = BOOT_CYCLES
+
       # The sides each drive's disk has.
       def sides = 1
 
@@ -90,40 +61,13 @@ module Badline
         build_ip(dos_rom || ROM.load("8050/dos-2.7.rom", 0xc000))
         build_fdc(fdc_rom || ROM.read("8050/fdc-901869-01.rom"))
         @ip_cpu = IPCPU.new(@ip_bus)
+        @ip_cpu.power_on!
         @fdc_cpu = FDCCPU.new(@fdc_bus)
-        init_idle
+        @fdc_cpu.power_on!
+        init_idle(Idle::IP_LOOP, Idle::FDC_LOOP)
         @ieee_bus.attach(self)
       end
 
-      # Plugs the unit into an IEEE-488 bus, leaving the one it was on.
-      def connect(ieee_bus)
-        settle!
-        @ieee_bus.detach(self)
-        @ieee_bus = ieee_bus
-        @ieee_port.bus = ieee_bus
-        ieee_bus.attach(self)
-      end
-
-      # The lines the unit pulls on the bus while ATN is low or not
-      # (IEEEPort).
-      def ieee_low_lines(atn) = @ieee_port.ieee_low_lines(atn)
-
-      # The controller pushed its lines into the bus.
-      def host_written! = nil
-
-      # Which LEDs are lit: bit 0 drive 1's, bit 1 drive 0's, bit 2 the
-      # error LED. They hold still while the unit sleeps, so reading them
-      # leaves it asleep.
-      def leds = @ieee_port.leds
-
-      def led_on? = leds.anybits?(0x03)
-
-      # Puts a Disk in +drive+, 0 or 1. Nil takes the disk out.
-      def insert(disk, drive: 0)
-        settle!
-        @mechanism.insert(disk, drive)
-      end
-
       # Puts in the .d80 or .d82 image at +path+, write-protected with
       # `read_only`.
       def insert_image(path, drive: 0, read_only: false)
@@ -131,65 +75,8 @@ module Badline
         insert(Disk.new(image_class.new(path, read_only:)), drive:)
       end
 
-      # The Disk in +drive+, or nil.
-      def disk(drive = 0) = @mechanism.disk(drive)
-
-      # Stores what the heads wrote in the disks' images, as the motors
-      # stopping do.
-      def flush
-        settle!
-        @mechanism.flush
-      end
-
-      def power_led_on? = true
-
-      # Runs the drive cycles that fall in one host cycle, then takes the
-      # controller's lines for the next. Asleep, the unit owes the cycles
-      # instead, and wakes once the controller has moved a line.
-      def host_cycle!
-        phase = @phase + CLOCK_HZ
-        while phase >= @host_clock_hz
-          @asleep ? owe_cycle : run_cycle
-          phase -= @host_clock_hz
-        end
-        @phase = phase
-        settle! if @asleep && @ieee_port.lines_moved?
-        @ieee_port.latch_host
-      end
-
-      def cycle!
-        settle!
-        run_cycle
-      end
-
-      # The bus's IFC line resets both processors and every chip. RAM keeps
-      # its contents.
-      def reset!
-        settle!
-        @data_riot.reset!
-        @control_riot.reset!
-        @via.reset!
-        @rriot.reset!
-        @ip_cpu.reset!
-        @fdc_cpu.reset!
-      end
-
-      def inspect
-        "#<#{self.class.name} cycles=#{@cycles} ip=(#{@ip_cpu.inspect}) fdc=(#{@fdc_cpu.inspect})>"
-      end
-
       private
 
-      def settled(part)
-        settle!
-        part
-      end
-
-      def run_cycle
-        step
-        watch_loops if @idle_skip
-      end
-
       def build_ip(rom)
         @common = Memory.new([], length: 0x1000)
         @ieee_bus = IEEEBus.new
@@ -210,6 +97,9 @@ module Badline
         @mechanism.rriot = @rriot
       end
 
+      # The disk a BL-D8-DISK module holds (KeyedState).
+      def disk_from_fields(input, detached) = Disk.from_fields(input, detached:)
+
       # One cycle of the board: the drives, then the chips, then the IP and
       # the FDC, each in its own half of the cycle. ATN reaches UE1's PA7 as
       # the port latched it. UE1 pulls the IP's IRQ, and the VIA and the
@@ -230,6 +120,18 @@ module Badline
         @fdc_cpu.cycle!
         @cycles += 1
       end
+
+      # One cycle of the FDC's side alone, as step runs it (Idle).
+      def fdc_step
+        so = @mechanism.take_so
+        @mechanism.cycle!
+        @via.cycle!
+        @rriot.cycle!
+        @fdc_cpu.irq = @via.irq? || @rriot.irq?
+        @fdc_cpu.so! if so
+        @fdc_cpu.cycle!
+        @cycles += 1
+      end
     end
 
     # The 8250: the 8050's board driving double-sided mechanisms, 154 tracks