badline 0.17.0 → 0.19.0

data/lib/badline/c128/keyed_state.rb

@@ -39,6 +39,7 @@ module Badline
         pending = @pending_keys
         out.ints("host.pending_keys", pending) if pending
         out.bool("host.typing", !pending.nil?)
+        save_init_keys(out)
         out.int("host.init_pending", @cycles <= init_threshold ? @init_handlers.length : 0)
         out.bool("host.holding_commodore", @holding_commodore)
         @typist.save_fields(out, "host.typist.")
@@ -55,6 +56,7 @@ module Badline
         @cpu_reset_pending = input.bool("cpu_reset_pending", @cpu_reset_pending)
         pending = input.ints("host.pending_keys", [])
         @pending_keys = input.bool("host.typing", !pending.empty?) ? pending.dup : nil
+        load_init_keys(input)
         @init_handlers_lost = [input.int("host.init_pending", 0) - @init_handlers.length, 0].max
         load_holding_fields(input)
         @typist.load_fields(input, "host.typist.")

data/lib/badline/c128.rb

@@ -74,6 +74,8 @@ module Badline
 
     def family = :c128
 
+    def portless_board = nil
+
     def address_bus = @bus
 
     def region = @bus.region
@@ -124,6 +126,7 @@ module Badline
       @holding_commodore = false
       @bus = Bus.new(@model, sid_model: sid_model || @model.sid_model, mode:)
       @cpu = CPU.new(@bus, debug:)
+      @cpu.power_on! if @c64_built
       build_z80
       @vic = @bus.vic
       @vic.open_bus = -> { @bus.ram.peek(@cpu.program_counter) }
@@ -139,6 +142,7 @@ module Badline
       @restore_pulse = false
       @init_handlers = []
       @pending_keys = nil
+      @init_keys = nil
       @typist = Input::MatrixTypist.new(@bus.keyboard)
       @capture_output = nil
       init_drives
@@ -203,6 +207,7 @@ module Badline
       @vdc.power_on!
       @bus.power_on!
       reset!
+      @cpu.power_on! if @c64_built
       enter_c64_mode if @c64_built
     end
 

data/lib/badline/c64/bus/fittings.rb

@@ -15,8 +15,14 @@ module Badline
         # alone at $DC00-$DFFF and the cartridge port in Ultimax mode.
         BOARDS = %i[c64 pet64 gs max].freeze
 
+        # The boards with no serial port for a disk drive: the C64GS's case
+        # covers its board's, and the MAX Machine has none.
+        NO_SERIAL_PORT = { gs: "the C64GS", max: "the MAX Machine" }.freeze
+
         attr_reader :board
 
+        def portless_board = NO_SERIAL_PORT[@board]
+
         # Fits the KERNAL ROM ROMs::KERNALS names, leaves the cassette port
         # empty unless `datasette`, and puts the chips in the board BOARDS
         # names.

data/lib/badline/c64/keyed_state.rb

@@ -39,6 +39,7 @@ module Badline
         out.bool("dma", @dma)
         pending = @pending_keys
         out.ints("host.pending_keys", pending) if pending
+        save_init_keys(out)
         out.int("host.init_pending", booting? ? @init_handlers.length : 0)
       end
 
@@ -52,6 +53,7 @@ module Badline
         @dma = input.bool("dma", @dma)
         pending = input.ints("host.pending_keys", [])
         @pending_keys = pending.empty? ? nil : pending.dup
+        load_init_keys(input)
         @init_handlers_lost = [input.int("host.init_pending", 0) - @init_handlers.length, 0].max
       end
 

data/lib/badline/c64.rb

@@ -48,6 +48,10 @@ module Badline
 
     def datasette = address_bus.datasette
 
+    # The board's name when it has no serial port for a disk drive, or nil.
+    # Every family answers it, nil on all but these C64 boards.
+    def portless_board = address_bus.portless_board
+
     def install_debug_register(&) = address_bus.install_debug_register(&)
 
     # The machine options (sid_model:, cia_model:, vic_model:, region: and
@@ -63,6 +67,7 @@ module Badline
       @address_bus = Bus.new(**machine.except(*Bus::Fittings::NAMES))
       @address_bus.fit(**machine.slice(*Bus::Fittings::NAMES))
       @cpu = Chips::CPU.new(@address_bus, debug:)
+      @cpu.power_on!
       @vic = @address_bus.vic
       @vic.open_bus = -> { @address_bus.ram.peek(@cpu.program_counter) }
       @cia1 = @address_bus.cia1
@@ -80,6 +85,7 @@ module Badline
       @freeze_writes = 0
       @init_handlers = []
       @pending_keys = nil
+      @init_keys = nil
       @dos = nil
       @serial_trap = nil
       @save_trap = nil
@@ -140,6 +146,7 @@ module Badline
       vic.power_on!
       address_bus.power_on!
       reset!
+      cpu.power_on!
     end
 
     # The RES line reaches the CPU and its port, both CIAs, the SID, the

data/lib/badline/cbm2/keyed_state.rb

@@ -71,7 +71,9 @@ module Badline
         out.int("refresh", @refresh)
         pending = @pending_keys
         out.ints("host.pending_keys", pending) if pending
+        save_init_keys(out)
         out.int("host.init_pending", @cycles <= @init_threshold ? @init_handlers.length : 0)
+        save_ieee_drive_fields(out)
       end
 
       def load_machine_fields(input)
@@ -82,7 +84,9 @@ module Badline
         @refresh = input.int("refresh", 0).clamp(0, REFRESH_COUNT)
         pending = input.ints("host.pending_keys", [])
         @pending_keys = pending.empty? ? nil : pending.dup
+        load_init_keys(input)
         @init_handlers_lost = [input.int("host.init_pending", 0) - @init_handlers.length, 0].max
+        load_ieee_drive_fields(input)
       end
     end
 

data/lib/badline/cbm2/p500.rb

@@ -55,6 +55,8 @@ module Badline
 
       def family = :cbm2
 
+      def portless_board = nil
+
       def peek(addr) = @bus.peek(addr)
 
       def poke(addr, value) = @bus.poke(addr, value)
@@ -71,8 +73,9 @@ module Badline
       def region = @model.region
 
       # +model+ names one of Model::ALL, and +mains_hz+ the mains, 50 or
-      # 60, the model's region's unless given.
-      def initialize(model: Model::DEFAULT, mains_hz: nil, debug: false)
+      # 60, the model's region's unless given. +true_drive_model+ names the
+      # drive plug_true_drive plugs in (Drives::IEEEModels).
+      def initialize(model: Model::DEFAULT, mains_hz: nil, debug: false, true_drive_model: Drives::IEEEModels::DEFAULT)
         @model = Model.named(model)
         @mains_hz = mains_hz || @model.region.mains_hz
         raise ArgumentError, "the mains is 50 or 60 Hz, not #{@mains_hz}" unless [50, 60].include?(@mains_hz)
@@ -101,6 +104,7 @@ module Badline
         keyboard_ports.connect(@tpi2)
         map_io
         @cpu = CPU.new(@bus, debug:)
+        @cpu.power_on!
         @cycles = 0
         @mains_half_period = clock_hz / (2 * @mains_hz)
         @mains_countdown = @mains_half_period
@@ -112,10 +116,11 @@ module Badline
         @acia_due = Chips::ACIA::NEVER
         @init_handlers = []
         @pending_keys = nil
+        @init_keys = nil
         @dos = nil
         @ieee_trap = nil
         @capture_output = nil
-        init_ieee_drives
+        init_ieee_drives(true_drive_model)
         @init_threshold = INIT_THRESHOLD
         update_video_bus
       end
@@ -209,6 +214,7 @@ module Badline
         @color_ram.clear!
         @vic.power_on!
         reset!
+        @cpu.power_on!
       end
 
       # The cycle by which the KERNAL has tested segments 0 and 1 and BASIC

data/lib/badline/cbm2.rb

@@ -74,6 +74,8 @@ module Badline
 
     def family = :cbm2
 
+    def portless_board = nil
+
     # Reads and writes memory as the CPU sees it, in its execution segment.
     def peek(addr) = @bus.peek(addr)
 
@@ -94,8 +96,10 @@ module Badline
     # +model+ names one of Model::ALL, +kernal+ one of Model::KERNALS, and
     # +mains_hz+ the mains, 50 or 60, which also sets a 600's jumper for
     # the editor's 60 Hz CRTC table. +refresh+ false leaves out the DRAM
-    # refresh's stolen cycles.
-    def initialize(model: Model::DEFAULT, kernal: "04a", mains_hz: 50, refresh: true, debug: false)
+    # refresh's stolen cycles. +true_drive_model+ names the drive
+    # plug_true_drive plugs in (Drives::IEEEModels).
+    def initialize(model: Model::DEFAULT, kernal: "04a", mains_hz: 50, refresh: true, debug: false,
+                   true_drive_model: Drives::IEEEModels::DEFAULT)
       @model = Model.named(model)
       raise ArgumentError, "no CBM-II KERNAL named #{kernal}" unless Model::KERNALS.key?(kernal)
       raise ArgumentError, "the mains is 50 or 60 Hz, not #{mains_hz}" unless [50, 60].include?(mains_hz)
@@ -121,6 +125,7 @@ module Badline
       keyboard_ports.connect(@tpi2)
       map_io
       @cpu = CPU.new(@bus, debug:)
+      @cpu.power_on!
       @cycles = 0
       @mains_half_period = CLOCK_HZ / (2 * mains_hz)
       @mains_countdown = @mains_half_period
@@ -131,10 +136,11 @@ module Badline
       @acia_due = Chips::ACIA::NEVER
       @init_handlers = []
       @pending_keys = nil
+      @init_keys = nil
       @dos = nil
       @ieee_trap = nil
       @capture_output = nil
-      init_ieee_drives
+      init_ieee_drives(true_drive_model)
       @init_threshold = boot_cycles
     end
 
@@ -221,6 +227,7 @@ module Badline
     def power_cycle!
       @bus.power_on!
       reset!
+      @cpu.power_on!
     end
 
     private

data/lib/badline/chips/cia/timer.rb

@@ -52,7 +52,7 @@ module Badline
         end
 
         def cycle!(feed)
-          feed &&= @control.value & 0x01 != 0
+          feed &&= @control.value.anybits?(0x01)
           if @settled
             return @counter -= 1 if feed && @counter > 1
           elsif @empty
@@ -102,7 +102,7 @@ module Badline
         private
 
         def started?
-          @control.value & 0x01 != 0
+          @control.value.anybits?(0x01)
         end
 
         # Where fast_forward lands +cycles+ after an underflow, with

data/lib/badline/chips/cpu/core.rb

@@ -25,8 +25,8 @@ module Badline
         include Boundary
         include KeyedState
 
-        attr_reader :memory, :instructions, :boundary_crossed, :cycles, :pending_write
-        attr_accessor :program_counter, :stack_pointer, :status, :a, :x, :y, :nmi, :irq
+        attr_reader :memory, :instructions, :boundary_crossed, :cycles, :pending_write, :program_counter
+        attr_accessor :stack_pointer, :status, :a, :x, :y, :nmi, :irq
 
         alias pending_write? pending_write
 
@@ -56,15 +56,32 @@ module Badline
           end_sequence
         end
 
+        # Clears the registers and runs the reset sequence from its first
+        # stack read, the two reads at the program counter having run while
+        # the reset circuit held RES. The first opcode fetch comes 5 cycles
+        # after power-on, where x64sc's does.
+        def power_on!
+          @program_counter = @stack_pointer = 0
+          @a = @x = @y = 0
+          reset!
+          @index = 2
+        end
+
+        # Starts the reset sequence, RESET_PLAN, which reads the program
+        # counter from $FFFC and fetches the first opcode 7 cycles later. A,
+        # X and Y keep their values, and S ends 3 lower.
         def reset!
           status.interrupt = true
-          reset_registers
           @nmi = false
           @irq_sample = @irq_pending = false
           @nmi_sample = @nmi_pending = false
           @skip_poll = false
           @pending_write = false
-          end_sequence
+          @interrupt = 0xfffc
+          @brk = false
+          @plan = RESET_PLAN
+          @writes = RESET_WRITES
+          @index = 0
         end
 
         # Drops the instruction or interrupt sequence in flight and the
@@ -83,6 +100,14 @@ module Badline
           @pending_write = false
         end
 
+        # Sets the program counter. A CPU in its reset sequence leaves it,
+        # so the next cycle fetches an opcode at +address+ and not at the
+        # reset vector's.
+        def program_counter=(address)
+          @program_counter = address
+          end_sequence if @plan.equal?(RESET_PLAN)
+        end
+
         def p
           status.value
         end

data/lib/badline/chips/cpu/instruction_set.rb

@@ -40,7 +40,7 @@ module Badline
 
         def update_number_flags(value)
           status.zero = value.zero?
-          status.negative = value & 0x80 != 0
+          status.negative = value.anybits?(0x80)
           value
         end
 

data/lib/badline/chips/cpu/interrupts.rb

@@ -82,6 +82,15 @@ module Badline
           @nmi = false if @interrupt == 0xfffa
         end
 
+        def op_reset_dummy
+          @memory.peek(@program_counter)
+        end
+
+        def op_reset_stack
+          @memory.peek(stack_address)
+          @stack_pointer = (@stack_pointer - 1) & 0xff
+        end
+
         def op_int_vector_low
           @address = @memory.peek(@interrupt)
         end

data/lib/badline/chips/cpu/keyed_state.rb

@@ -4,14 +4,17 @@ module Badline
   module Chips
     class CPU
       # Where a CPU caught inside an instruction is, as a snapshot names it:
-      # an opcode's instruction, an IRQ or NMI sequence, or jammed.
-      POSITIONS = %w[boundary op interrupt jam].freeze
+      # an opcode's instruction, an IRQ or NMI sequence, jammed, or the
+      # reset sequence.
+      POSITIONS = %w[boundary op interrupt jam reset].freeze
 
       # The CPU's fields in a keyed snapshot module (Snapshot::Keyed): the
       # registers, the interrupt lines' pipeline, the counts and, inside an
       # instruction, where it is in hardware terms (pos.*), rather than as
       # the microcode lays it out.
       module KeyedState
+        SEQUENCE_NAMES = { INTERRUPT => "interrupt", RESET => "reset" }.freeze
+
         def save_fields(out)
           out.int("pc", @program_counter).int("sp", @stack_pointer).int("a", @a).int("x", @x).int("y", @y)
           out.int("p", @status.value).bool("nmi", @nmi).bool("so_high", @so_high)
@@ -75,8 +78,8 @@ module Badline
             return
           end
 
-          out.text("pos.seq", source == INTERRUPT ? "interrupt" : "op")
-          out.int("pos.op", source) unless source == INTERRUPT
+          out.text("pos.seq", SEQUENCE_NAMES.fetch(source, "op"))
+          out.int("pos.op", source) unless SEQUENCE_NAMES.key?(source)
           out.int("pos.t", position_t(source)).bool("pos.crossed", @boundary_crossed)
           out.bool("pos.branch_taken", @branch_taken == true).bool("pos.brk", @brk)
           out.optional_int("pos.vector", @interrupt)
@@ -88,7 +91,7 @@ module Badline
         # The cycles of the instruction or sequence run so far, counting the
         # opcode fetch as 1 and leaving out stalled cycles.
         def position_t(source)
-          return @index if source == INTERRUPT
+          return @index if SEQUENCE_NAMES.key?(source)
 
           MICROCODE.fetch(source).t_at(@index, @boundary_crossed)
         end
@@ -96,7 +99,8 @@ module Badline
         def load_position(input)
           case input.choice("pos.seq", POSITIONS, "boundary")
           when "op" then load_instruction(input)
-          when "interrupt" then load_interrupt(input)
+          when "interrupt" then load_sequence(input, INTERRUPT_PLAN, INTERRUPT_WRITES, 1)
+          when "reset" then load_sequence(input, RESET_PLAN, RESET_WRITES, 0)
           when "jam" then load_jam
           else load_boundary
           end
@@ -112,10 +116,11 @@ module Badline
           load_latches(input)
         end
 
-        def load_interrupt(input)
-          use_plan(INTERRUPT_PLAN, INTERRUPT_WRITES)
+        # An interrupt or reset sequence, whose plan starts at step +first+.
+        def load_sequence(input, plan, writes, first)
+          use_plan(plan, writes)
           @boundary_crossed = input.bool("pos.crossed", false)
-          @index = input.int("pos.t", 1).clamp(1, INTERRUPT_PLAN.length - 1)
+          @index = input.int("pos.t", first).clamp(first, plan.length - 1)
           load_latches(input)
         end
 
@@ -162,6 +167,7 @@ module Badline
           return FETCH if @plan.equal?(FETCH_PLAN)
           return INTERRUPT if @plan.equal?(INTERRUPT_PLAN)
           return JAMMED if @plan.equal?(JAMMED_PLAN)
+          return RESET if @plan.equal?(RESET_PLAN)
 
           MICROCODE.index { |micro| micro.plan.equal?(@plan) && micro.operation == @operation } ||
             MICROCODE.index { |micro| micro.plan.equal?(@plan) }

data/lib/badline/chips/cpu/microcode.rb

@@ -95,6 +95,14 @@ module Badline
         op_int_vector_low op_int_vector_high
       ].freeze
 
+      # RES runs BRK's sequence with its three stack writes turned into
+      # reads, which still count S down, and reads the vector at $FFFC. Its
+      # first two cycles read the program counter and leave it where it was.
+      RESET_PLAN = %i[
+        op_reset_dummy op_reset_dummy op_reset_stack op_reset_stack op_reset_stack
+        op_int_vector_low op_int_vector_high
+      ].freeze
+
       SPECIAL_PLANS = {
         brk: BRK_PLAN, jam: JAM_PLAN, jsr: JSR_PLAN, rts: RTS_PLAN,
         rti: RTI_PLAN, pha: PUSH_PLAN, php: PUSH_PLAN,
@@ -181,6 +189,7 @@ module Badline
       FETCH_WRITES = Microcode.write_mask(FETCH_PLAN)
       INTERRUPT_WRITES = Microcode.write_mask(INTERRUPT_PLAN)
       JAMMED_WRITES = Microcode.write_mask(JAMMED_PLAN)
+      RESET_WRITES = Microcode.write_mask(RESET_PLAN)
       MICROCODE = Microcode.table
 
       # The instruction methods, in a fixed order a snapshot names them by.
@@ -190,6 +199,7 @@ module Badline
       FETCH = -1
       INTERRUPT = -2
       JAMMED = -3
+      RESET = -4
     end
   end
 end

data/lib/badline/chips/m6809/arithmetic.rb

@@ -0,0 +1,140 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class M6809
+      # The ALU: each method returns its result and sets the flags it
+      # changes.
+      module Arithmetic
+        private
+
+        def flags(clear, set)
+          @cc = (@cc & ~clear & 0xff) | set
+        end
+
+        def nz8(result) = (result.nobits?(0x80) ? 0 : NEGATIVE) | (result.zero? ? ZERO : 0)
+
+        def nz16(result) = (result.nobits?(0x8000) ? 0 : NEGATIVE) | (result.zero? ? ZERO : 0)
+
+        # Loads, stores, AND, OR, EOR and TST: N and Z, V cleared.
+        def logic8(result)
+          flags(NEGATIVE | ZERO | OVERFLOW, nz8(result))
+          result
+        end
+
+        def logic16(result)
+          flags(NEGATIVE | ZERO | OVERFLOW, nz16(result))
+          result
+        end
+
+        def add8(left, right, carry)
+          sum = left + right + carry
+          result = sum & 0xff
+          overflow = ((left ^ result) & (right ^ result)).nobits?(0x80) ? 0 : OVERFLOW
+          half = (left ^ right ^ sum).nobits?(0x10) ? 0 : HALF_CARRY
+          flags(HALF_CARRY | NEGATIVE | ZERO | OVERFLOW | CARRY,
+                half | nz8(result) | overflow | (sum > 0xff ? CARRY : 0))
+          result
+        end
+
+        def sub8(left, right, borrow)
+          difference = left - right - borrow
+          result = difference & 0xff
+          overflow = ((left ^ right) & (left ^ result)).nobits?(0x80) ? 0 : OVERFLOW
+          flags(NEGATIVE | ZERO | OVERFLOW | CARRY, nz8(result) | overflow | (difference.negative? ? CARRY : 0))
+          result
+        end
+
+        def add16(left, right)
+          sum = left + right
+          result = sum & 0xffff
+          @alu_word = result
+          overflow = ((left ^ result) & (right ^ result)).nobits?(0x8000) ? 0 : OVERFLOW
+          flags(NEGATIVE | ZERO | OVERFLOW | CARRY, nz16(result) | overflow | (sum > 0xffff ? CARRY : 0))
+          result
+        end
+
+        def sub16(left, right)
+          difference = left - right
+          result = difference & 0xffff
+          @alu_word = result
+          overflow = ((left ^ right) & (left ^ result)).nobits?(0x8000) ? 0 : OVERFLOW
+          flags(NEGATIVE | ZERO | OVERFLOW | CARRY, nz16(result) | overflow | (difference.negative? ? CARRY : 0))
+          result
+        end
+
+        def carry = @cc & CARRY
+
+        def neg8(value) = sub8(0, value, 0)
+
+        def com8(value)
+          result = ~value & 0xff
+          flags(NEGATIVE | ZERO | OVERFLOW | CARRY, nz8(result) | CARRY)
+          result
+        end
+
+        # The undocumented XNC: NEG with C clear, COM with C set.
+        def xnc8(value) = carry.zero? ? neg8(value) : com8(value)
+
+        def lsr8(value)
+          result = value >> 1
+          flags(NEGATIVE | ZERO | CARRY, nz8(result) | (value & 1))
+          result
+        end
+
+        def ror8(value)
+          result = (value >> 1) | (carry << 7)
+          flags(NEGATIVE | ZERO | CARRY, nz8(result) | (value & 1))
+          result
+        end
+
+        def asr8(value)
+          result = (value >> 1) | (value & 0x80)
+          flags(NEGATIVE | ZERO | CARRY, nz8(result) | (value & 1))
+          result
+        end
+
+        def asl8(value) = rotate_left8(value, 0)
+
+        def rol8(value) = rotate_left8(value, carry)
+
+        def rotate_left8(value, low)
+          result = ((value << 1) | low) & 0xff
+          overflow = (value ^ (value << 1)).nobits?(0x80) ? 0 : OVERFLOW
+          flags(NEGATIVE | ZERO | OVERFLOW | CARRY, nz8(result) | overflow | (value >> 7))
+          result
+        end
+
+        def dec8(value)
+          result = (value - 1) & 0xff
+          flags(NEGATIVE | ZERO | OVERFLOW, nz8(result) | (value == 0x80 ? OVERFLOW : 0))
+          result
+        end
+
+        # The undocumented XDEC: DEC, with C set unless the operand was 0.
+        def xdec8(value)
+          result = dec8(value)
+          flags(CARRY, value.zero? ? 0 : CARRY)
+          result
+        end
+
+        def inc8(value)
+          result = (value + 1) & 0xff
+          flags(NEGATIVE | ZERO | OVERFLOW, nz8(result) | (value == 0x7f ? OVERFLOW : 0))
+          result
+        end
+
+        def clr8
+          flags(NEGATIVE | ZERO | OVERFLOW | CARRY, ZERO)
+          0
+        end
+
+        # The undocumented XCLRA and XCLRB: CLR, but C stays.
+        def xclr8
+          flags(NEGATIVE | ZERO | OVERFLOW, ZERO)
+          0
+        end
+      end
+    end
+  end
+end