badline 0.17.0 → 0.19.0

data/lib/badline/chips/m6809/keyed_state.rb

@@ -0,0 +1,147 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class M6809
+      # Every plan the CPU runs and every tail it keeps, by the name a
+      # snapshot gives it: the plans of their own by name, an indexed
+      # postbyte's, a PSH's and a PUL's by postbyte, and an opcode's by its
+      # page and opcode. A plan that has several names goes by the first.
+      module PlanNames
+        OWN = { "fetch" => FETCH_PLAN, "reset" => RESET_PLAN, "prefix" => PREFIX_PLAN, "none" => NO_TAIL,
+                "jump" => JUMP_TAIL, "interrupt" => INTERRUPT_PLAN, "fast_interrupt" => FAST_INTERRUPT_PLAN,
+                "waited_interrupt" => WAITED_INTERRUPT_PLAN, "return_entire" => RETURN_ENTIRE_PLAN,
+                "return_fast" => RETURN_FAST_PLAN, "long_branch_taken" => LONG_BRANCH_TAKEN_PLAN,
+                "sync_end" => SYNC_END_PLAN }.freeze
+
+        PAGES = [PAGE1, PAGE2, PAGE3].freeze
+
+        TABLE = (OWN.to_a +
+                 { "indexed" => INDEXED_PLANS, "push" => PUSH_PLANS, "pull" => PULL_PLANS }.flat_map do |kind, plans|
+                   Array.new(256) { |post| ["#{kind}.#{post}", plans[post]] }
+                 end +
+                 Array.new(PAGES.length * 256) do |slot|
+                   entry = PAGES[slot >> 8][slot & 0xff]
+                   name = "op.#{(slot >> 8) + 1}.#{slot & 0xff}"
+                   [["#{name}.plan", entry.plan], ["#{name}.tail", entry.tail]]
+                 end.flatten(1)).freeze
+
+        NAMES = TABLE.map(&:first).freeze
+        PLANS = TABLE.map(&:last).freeze
+
+        # What the opcodes and the interrupts run, by name.
+        OPERATIONS = (%w[none enter_nmi enter_firq enter_irq] +
+                      PAGES.flat_map { |page| page.map { |entry| entry.operation.to_s } }).uniq.freeze
+
+        module_function
+
+        def name_of(plan)
+          index = PLANS.index { |each_plan| each_plan.equal?(plan) }
+          index.nil? ? "fetch" : NAMES[index]
+        end
+
+        def named(name)
+          index = NAMES.index(name)
+          index.nil? ? nil : PLANS[index]
+        end
+      end
+
+      # The CPU's fields in a keyed snapshot module (Snapshot::Keyed): the
+      # registers, the interrupt lines and what the CPU has sampled of
+      # them, the cycle count, the working registers the steps share, and
+      # off an instruction boundary the plan running, the step in it and
+      # the tail to follow, by PlanNames. A plan it doesn't know puts the
+      # CPU on a boundary.
+      module KeyedState
+        def save_fields(out)
+          out.int("a", @a).int("b", @b).int("x", @x).int("y", @y).int("u", @u).int("s", @s).int("pc", @pc)
+          out.int("dp", @dp).int("cc", @cc).int("cycles", @cycles)
+          out.bool("irq", @irq).bool("firq", @firq).bool("nmi", @nmi).bool("halt", @halt)
+          out.bool("irq.latched", @irq_latched).bool("irq.seen", @irq_seen)
+          out.bool("firq.latched", @firq_latched).bool("firq.seen", @firq_seen)
+          out.bool("nmi.edge", @nmi_edge).bool("nmi.latched", @nmi_latched).bool("nmi.seen", @nmi_seen)
+          out.bool("nmi.armed", @nmi_armed).bool("halt.latched", @halt_latched).bool("halt.seen", @halt_seen)
+          save_working_fields(out)
+          out
+        end
+
+        def load_fields(input)
+          load_registers(input)
+          load_lines(input)
+          load_working_fields(input)
+        end
+
+        def restored! = nil
+
+        private
+
+        def save_working_fields(out)
+          out.int("ea", @ea).int("value", @value).int("post", @post).int("opcode", @opcode)
+          out.text("operation", @operation.to_s).int("page", PlanNames::PAGES.index { |page| page.equal?(@page) } + 1)
+          out.int("group", @group).int("previous_group", @previous_group).int("alu_word", @alu_word)
+          out.int("vector", @vector).int("interrupt_mask", @interrupt_mask).bool("stack_u", @stack_u)
+          return if boundary?
+
+          out.text("pos.plan", PlanNames.name_of(@plan)).int("pos.index", @index)
+          out.text("pos.tail", PlanNames.name_of(@tail))
+        end
+
+        def load_registers(input)
+          @a = input.byte("a", @a)
+          @b = input.byte("b", @b)
+          @x = input.word("x", @x)
+          @y = input.word("y", @y)
+          @u = input.word("u", @u)
+          @s = input.word("s", @s)
+          @pc = input.word("pc", @pc)
+          @dp = input.byte("dp", @dp)
+          @cc = input.byte("cc", @cc)
+          @cycles = input.int("cycles", @cycles)
+        end
+
+        def load_lines(input)
+          @irq = input.bool("irq", false)
+          @firq = input.bool("firq", false)
+          @nmi = input.bool("nmi", false)
+          @halt = input.bool("halt", false)
+          @irq_latched = input.bool("irq.latched", false)
+          @irq_seen = input.bool("irq.seen", false)
+          @firq_latched = input.bool("firq.latched", false)
+          @firq_seen = input.bool("firq.seen", false)
+          @nmi_edge = input.bool("nmi.edge", false)
+          @nmi_latched = input.bool("nmi.latched", false)
+          @nmi_seen = input.bool("nmi.seen", false)
+          @nmi_armed = input.bool("nmi.armed", @nmi_armed)
+          @halt_latched = input.bool("halt.latched", false)
+          @halt_seen = input.bool("halt.seen", false)
+        end
+
+        def load_working_fields(input)
+          @ea = input.word("ea", 0)
+          @value = input.word("value", 0)
+          @post = input.byte("post", 0)
+          @opcode = input.byte("opcode", 0)
+          @operation = input.choice("operation", PlanNames::OPERATIONS, "none").to_sym
+          @page = PlanNames::PAGES.fetch(input.int("page", 1).clamp(1, 3) - 1)
+          @group = input.int("group", GROUP_OTHER)
+          @previous_group = input.int("previous_group", GROUP_OTHER)
+          @alu_word = input.int("alu_word", 0)
+          @vector = input.word("vector", 0xfffe)
+          @interrupt_mask = input.byte("interrupt_mask", 0)
+          @stack_u = input.bool("stack_u", false)
+          load_position(input)
+        end
+
+        def load_position(input)
+          plan = PlanNames.named(input.text("pos.plan", "fetch"))
+          tail = PlanNames.named(input.text("pos.tail", "none"))
+          return boundary if plan.nil? || tail.nil? || plan.empty?
+
+          @plan = plan
+          @index = input.int("pos.index", 0).clamp(0, plan.length - 1)
+          @tail = tail
+        end
+      end
+    end
+  end
+end

data/lib/badline/chips/m6809/opcodes.rb

@@ -0,0 +1,159 @@
+# frozen_string_literal: true
+
+require "badline/chips/m6809/plans"
+
+module Badline
+  module Chips
+    class M6809
+      # The read-modify-write group: $00-$0F direct, $60-$6F indexed and
+      # $70-$7F extended, and $40-$4F and $50-$5F on A and B.
+      MEMORY_GROUP = %i[neg neg xnc com lsr lsr ror asr asl rol dec xdec inc tst jmp clr].freeze
+      A_GROUP = %i[nega nega xnca coma lsra lsra rora asra asla rola deca xdeca inca tsta xclra clra].freeze
+      B_GROUP = %i[negb negb xncb comb lsrb lsrb rorb asrb aslb rolb decb xdecb incb tstb xclrb clrb].freeze
+
+      # $80-$BF and $C0-$FF by low nibble: the instruction and its kind.
+      A_COLUMN = [%i[suba read8], %i[cmpa read8], %i[sbca read8], %i[subd read16_dead], %i[anda read8],
+                  %i[bita read8], %i[lda read8], %i[sta write8], %i[eora read8], %i[adca read8], %i[ora read8],
+                  %i[adda read8], %i[cmpx read16_dead], %i[jsr subroutine], %i[ldx read16], %i[stx write16]].freeze
+      B_COLUMN = [%i[subb read8], %i[cmpb read8], %i[sbcb read8], %i[addd read16_dead], %i[andb read8],
+                  %i[bitb read8], %i[ldb read8], %i[stb write8], %i[eorb read8], %i[adcb read8], %i[orb read8],
+                  %i[addb read8], %i[ldd read16], %i[std write16], %i[ldu read16], %i[stu write16]].freeze
+      PAGE2_COLUMN = { 0x3 => %i[cmpd read16_dead], 0xc => %i[cmpy read16_dead], 0xe => %i[ldy read16],
+                       0xf => %i[sty write16] }.freeze
+      PAGE2_B_COLUMN = { 0x3 => %i[xaddd read16_dead], 0xe => %i[lds read16], 0xf => %i[sts write16] }.freeze
+      PAGE3_COLUMN = { 0x3 => %i[cmpu read16_dead], 0xc => %i[cmps read16_dead] }.freeze
+      PAGE3_B_COLUMN = { 0x3 => %i[xaddu read16_dead] }.freeze
+
+      # Opcodes with a plan of their own, after the opcode fetch.
+      INHERENT = {
+        0x12 => [:nop, %i[dead_pc_exec]],
+        0x13 => [:sync, %i[dead_pc sync_wait]],
+        0x14 => [:none, %i[free_run]],
+        0x15 => [:none, %i[free_run]],
+        0x16 => [:jmp, %i[offset_hi offset_lo_pc dead_v dead_v_exec]],
+        0x17 => [:jsr, %i[offset_hi offset_lo_pc dead_v dead_v dead_ea dead_v push_pcl push_pch_exec]],
+        0x18 => [:x18, %i[next_byte_exec dead_v]],
+        0x19 => [:daa, %i[dead_pc_exec]],
+        0x1a => [:orcc, %i[immediate_exec dead_pc]],
+        0x1b => [:nop, %i[dead_pc_exec]],
+        0x1c => [:andcc, %i[immediate_exec dead_pc]],
+        0x1d => [:sex, %i[dead_pc_exec]],
+        0x1e => [:exg, %i[read_post dead_v dead_v dead_v dead_v dead_v dead_v_exec]],
+        0x1f => [:tfr, %i[read_post dead_v dead_v dead_v dead_v_exec]],
+        0x34 => [:none, %i[push_s_post]],
+        0x35 => [:none, %i[pull_s_post]],
+        0x36 => [:none, %i[push_u_post]],
+        0x37 => [:none, %i[pull_u_post]],
+        0x38 => [:andcc, %i[idle immediate_exec dead_pc]],
+        0x39 => [:none, %i[dead_pc pull_pch pull_pcl dead_v]],
+        0x3a => [:abx, %i[dead_pc dead_v_exec]],
+        0x3b => [:none, %i[dead_pc return_cc]],
+        0x3c => [:none, [:cwai_mask, :dead_pc, :dead_v, *PUSH_ALL, :cwai_wait]],
+        0x3d => [:mul, %i[dead_pc dead_v dead_v dead_v dead_v dead_v dead_v dead_v dead_v dead_v_exec]],
+        0x3e => [:xres, SOFTWARE_INTERRUPT_TAIL],
+        0x3f => [:swi, SOFTWARE_INTERRUPT_TAIL],
+        0x87 => [:xsta, %i[immediate_exec]],
+        0x8d => [:jsr, %i[offset8_branch dead_v dead_ea dead_v push_pcl push_pch_exec]],
+        0x8f => [:xstx, %i[immediate_discard store_immediate]],
+        0xc7 => [:xstb, %i[immediate_exec]],
+        0xcd => [:none, %i[free_run]],
+        0xcf => [:xstu, %i[immediate_discard store_immediate]]
+      }.freeze
+
+      PAGE2_INHERENT = {
+        0x3e => [:xswi2, SOFTWARE_INTERRUPT_TAIL],
+        0x3f => [:swi2, SOFTWARE_INTERRUPT_TAIL],
+        0x87 => [:xsta2, %i[immediate_exec]],
+        0x8f => [:xsty, %i[immediate_discard store_immediate]],
+        0xc7 => [:xstb2, %i[immediate_exec]],
+        0xcf => [:xsts, %i[immediate_discard store_immediate]]
+      }.freeze
+
+      PAGE3_INHERENT = {
+        0x3e => [:xfirq, SOFTWARE_INTERRUPT_TAIL],
+        0x3f => [:swi3, SOFTWARE_INTERRUPT_TAIL],
+        0x87 => [:xsta2, %i[immediate_exec]],
+        0x8f => [:xstx2, %i[immediate_discard store_immediate]],
+        0xc7 => [:xstb2, %i[immediate_exec]],
+        0xcf => [:xstu2, %i[immediate_discard store_immediate]]
+      }.freeze
+
+      SHORT_BRANCH_TAIL = %i[offset8_branch dead_v_branch].freeze
+      LONG_BRANCH_TAIL = %i[offset_hi offset_lo_pc dead_v_long_branch].freeze
+      LEA = { 0x30 => :leax, 0x31 => :leay, 0x32 => :leas, 0x33 => :leau }.freeze
+
+      # Builds the opcode tables.
+      module Opcodes
+        MODES = [nil, DIRECT_PLAN, INDEXED_PLAN, EXTENDED_PLAN].freeze
+
+        module_function
+
+        def entry(operation, plan, tail)
+          Entry.new(operation, plan.freeze, tail.freeze, GROUPS.fetch(operation, GROUP_OTHER))
+        end
+
+        def tail(kind, mode)
+          return IMMEDIATE_TAILS.fetch(kind) if mode.zero?
+
+          TAILS.fetch(kind)
+        end
+
+        def memory(opcode)
+          mode = if opcode < 0x10 then DIRECT_PLAN
+                 elsif opcode < 0x70 then INDEXED_PLAN
+                 else EXTENDED_PLAN
+                 end
+          name = MEMORY_GROUP[opcode & 0x0f]
+          entry(name, mode, TAILS.fetch({ tst: :test, jmp: :jump }.fetch(name, :rmw)))
+        end
+
+        # $80-$FF: immediate, direct, indexed and extended by bits 4 and 5.
+        def column(opcode, column)
+          name, kind = column.fetch(opcode & 0x0f)
+          mode = (opcode >> 4) & 0x3
+          return entry(:none, [], NO_TAIL) if mode.zero? && !IMMEDIATE_TAILS.key?(kind)
+
+          entry(name, mode.zero? ? [] : MODES.fetch(mode), tail(kind, mode))
+        end
+
+        def page1(opcode)
+          if (inherent = INHERENT[opcode]) then entry(inherent[0], [], inherent[1])
+          elsif opcode < 0x10 || (0x60..0x7f).cover?(opcode) then memory(opcode)
+          elsif (0x40..0x5f).cover?(opcode) then inherent_register(opcode)
+          elsif (0x20..0x2f).cover?(opcode) then entry(:none, [], SHORT_BRANCH_TAIL)
+          elsif LEA.key?(opcode) then entry(LEA[opcode], INDEXED_PLAN, TAILS[:load_address])
+          elsif opcode >= 0x80 then column(opcode, opcode >= 0xc0 ? B_COLUMN : A_COLUMN)
+          else entry(:none, [], NO_TAIL)
+          end
+        end
+
+        def inherent_register(opcode)
+          name = (opcode < 0x50 ? A_GROUP : B_GROUP)[opcode & 0x0f]
+          entry(name, [], %i[dead_pc_exec])
+        end
+
+        # Pages 2 and 3. An opcode a page doesn't define runs as on page 1,
+        # after the prefix's cycle.
+        def paged(opcode, page1, inherent, columns)
+          return entry(inherent[opcode][0], [], inherent[opcode][1]) if inherent.key?(opcode)
+          return entry(:none, [], LONG_BRANCH_TAIL) if columns.first == PAGE2_COLUMN && (0x20..0x2f).cover?(opcode)
+
+          column = opcode >= 0xc0 ? columns[1] : columns[0]
+          return page1[opcode] if opcode < 0x80 || !column.key?(opcode & 0x0f)
+
+          name, kind = column[opcode & 0x0f]
+          mode = (opcode >> 4) & 0x3
+          entry(name, mode.zero? ? [] : MODES.fetch(mode), tail(kind, mode))
+        end
+      end
+
+      PAGE1 = Array.new(256) { |opcode| Opcodes.page1(opcode) }.freeze
+      PAGE2 = Array.new(256) do |opcode|
+        Opcodes.paged(opcode, PAGE1, PAGE2_INHERENT, [PAGE2_COLUMN, PAGE2_B_COLUMN])
+      end.freeze
+      PAGE3 = Array.new(256) do |opcode|
+        Opcodes.paged(opcode, PAGE1, PAGE3_INHERENT, [PAGE3_COLUMN, PAGE3_B_COLUMN])
+      end.freeze
+    end
+  end
+end

data/lib/badline/chips/m6809/operations.rb

@@ -0,0 +1,258 @@
+# frozen_string_literal: true
+
+module Badline
+  module Chips
+    class M6809
+      # The instruction methods the plans' *_exec steps call. A read takes
+      # its operand from @value; a write and a read-modify-write leave the
+      # byte or word to write there.
+      module Operations
+        private
+
+        def none; end
+        def nop; end
+        def sync; end
+
+        def neg = @value = neg8(@value)
+        def xnc = @value = xnc8(@value)
+        def com = @value = com8(@value)
+        def lsr = @value = lsr8(@value)
+        def ror = @value = ror8(@value)
+        def asr = @value = asr8(@value)
+        def asl = @value = asl8(@value)
+        def rol = @value = rol8(@value)
+        def dec = @value = dec8(@value)
+        def xdec = @value = xdec8(@value)
+        def inc = @value = inc8(@value)
+        def tst = logic8(@value)
+        def clr = @value = clr8
+
+        def jmp
+          @pc = @ea
+        end
+
+        def nega = @a = neg8(@a)
+        def xnca = @a = xnc8(@a)
+        def coma = @a = com8(@a)
+        def lsra = @a = lsr8(@a)
+        def rora = @a = ror8(@a)
+        def asra = @a = asr8(@a)
+        def asla = @a = asl8(@a)
+        def rola = @a = rol8(@a)
+        def deca = @a = dec8(@a)
+        def xdeca = @a = xdec8(@a)
+        def inca = @a = inc8(@a)
+        def tsta = logic8(@a)
+        def xclra = @a = xclr8
+        def clra = @a = clr8
+
+        def negb = @b = neg8(@b)
+        def xncb = @b = xnc8(@b)
+        def comb = @b = com8(@b)
+        def lsrb = @b = lsr8(@b)
+        def rorb = @b = ror8(@b)
+        def asrb = @b = asr8(@b)
+        def aslb = @b = asl8(@b)
+        def rolb = @b = rol8(@b)
+        def decb = @b = dec8(@b)
+        def xdecb = @b = xdec8(@b)
+        def incb = @b = inc8(@b)
+        def tstb = logic8(@b)
+        def xclrb = @b = xclr8
+        def clrb = @b = clr8
+
+        def suba = @a = sub8(@a, @value, 0)
+        def cmpa = sub8(@a, @value, 0)
+        def sbca = @a = sub8(@a, @value, carry)
+        def anda = @a = logic8(@a & @value)
+        def bita = logic8(@a & @value)
+        def lda = @a = logic8(@value)
+        def sta = @value = logic8(@a)
+        def eora = @a = logic8(@a ^ @value)
+        def adca = @a = add8(@a, @value, carry)
+        def ora = @a = logic8(@a | @value)
+        def adda = @a = add8(@a, @value, 0)
+
+        def subb = @b = sub8(@b, @value, 0)
+        def cmpb = sub8(@b, @value, 0)
+        def sbcb = @b = sub8(@b, @value, carry)
+        def andb = @b = logic8(@b & @value)
+        def bitb = logic8(@b & @value)
+        def ldb = @b = logic8(@value)
+        def stb = @value = logic8(@b)
+        def eorb = @b = logic8(@b ^ @value)
+        def adcb = @b = add8(@b, @value, carry)
+        def orb = @b = logic8(@b | @value)
+        def addb = @b = add8(@b, @value, 0)
+
+        def subd = self.d = sub16(d, @value)
+        def addd = self.d = add16(d, @value)
+        def cmpd = sub16(d, @value)
+        def cmpx = sub16(@x, @value)
+        def cmpy = sub16(@y, @value)
+        def cmpu = sub16(@u, @value)
+        def cmps = sub16(@s, @value)
+        def xaddd = add16(d, @value)
+        def xaddu = add16(@u | 0xff00, @value)
+
+        def ldd = self.d = logic16(@value)
+        def ldx = @x = logic16(@value)
+        def ldy = @y = logic16(@value)
+        def ldu = @u = logic16(@value)
+        def lds = load_s(logic16(@value))
+        def std = @value = logic16(d)
+        def stx = @value = logic16(@x)
+        def sty = @value = logic16(@y)
+        def stu = @value = logic16(@u)
+        def sts = @value = logic16(@s)
+
+        # The undocumented stores immediate. Prefixed, they set N and clear
+        # Z and V. Unprefixed, their flags hang on the instruction before
+        # (Banks' "Flags for unprefixed Store Immediate"), and the 16-bit
+        # ones also clear Z unless the register's low byte is 0.
+        def xsta = flags(NEGATIVE | ZERO | OVERFLOW, previous_group_flags)
+        def xstb = flags(NEGATIVE | ZERO | OVERFLOW, previous_group_flags)
+        def xsta2 = flags(NEGATIVE | ZERO | OVERFLOW, NEGATIVE)
+        def xstb2 = flags(NEGATIVE | ZERO | OVERFLOW, NEGATIVE)
+        def xstx = @value = store_word_low(@x)
+        def xstu = @value = store_word_low(@u)
+
+        def xsty = @value = store_word_low_prefixed(@y)
+        def xsts = @value = store_word_low_prefixed(@s)
+        def xstx2 = @value = store_word_low_prefixed(@x)
+        def xstu2 = @value = store_word_low_prefixed(@u)
+
+        def store_word_low(word)
+          low = word & 0xff
+          set = previous_group_flags & (NEGATIVE | ZERO)
+          set &= ~ZERO unless low.zero?
+          flags(NEGATIVE | ZERO | OVERFLOW, set)
+          low
+        end
+
+        def store_word_low_prefixed(word)
+          flags(NEGATIVE | ZERO | OVERFLOW, NEGATIVE)
+          word & 0xff
+        end
+
+        def previous_group_flags
+          case @previous_group
+          when GROUP_N0_Z1 then ZERO
+          when GROUP_A_00 then nz8(@a)
+          when GROUP_A_FF then (@a == 0xff ? ZERO : 0) | (@a.anybits?(0x80) ? 0 : NEGATIVE)
+          when GROUP_A_01 then decremented_flags(@a)
+          when GROUP_B_01 then decremented_flags(@b)
+          when GROUP_WORD_01 then decremented_flags(@alu_word >> 8)
+          when GROUP_LEA then decremented_flags((@alu_word >> 8) | (@alu_word & 0xff))
+          else NEGATIVE
+          end
+        end
+
+        # Z for 1, N for a negative value less one, V for $80.
+        def decremented_flags(value)
+          (value == 1 ? ZERO : 0) | ((value - 1).nobits?(0x80) ? 0 : NEGATIVE) | (value == 0x80 ? OVERFLOW : 0)
+        end
+
+        # JSR, BSR and LBSR, once the return address is stacked.
+        def jsr
+          @pc = @ea
+        end
+
+        def leax
+          @alu_word = @ea
+          @x = @ea
+          flags(ZERO, @ea.zero? ? ZERO : 0)
+        end
+
+        def leay
+          @alu_word = @ea
+          @y = @ea
+          flags(ZERO, @ea.zero? ? ZERO : 0)
+        end
+
+        def leas
+          @alu_word = @ea
+          load_s(@ea)
+        end
+
+        def leau
+          @alu_word = @ea
+          @u = @ea
+        end
+
+        def orcc = @cc |= @value
+        def andcc = @cc &= @value
+
+        def abx = @x = (@x + @b) & 0xffff
+
+        def mul
+          self.d = @a * @b
+          flags(ZERO | CARRY, (d.zero? ? ZERO : 0) | (@b >> 7))
+        end
+
+        def sex
+          @a = @b.nobits?(0x80) ? 0 : 0xff
+          flags(NEGATIVE | ZERO, nz16(d))
+        end
+
+        # DAA. V is C xor bit 7 of the result, as Banks found, where the
+        # datasheet clears it.
+        def daa
+          correction = 0
+          correction |= 0x06 if @cc.anybits?(HALF_CARRY) || (@a & 0x0f) > 0x09
+          high = @a & 0xf0
+          correction |= 0x60 if @cc.anybits?(CARRY) || high > 0x90 || (high > 0x80 && (@a & 0x0f) > 0x09)
+          result = (@a + correction) & 0xff
+          carry = correction >= 0x60 ? CARRY : 0
+          overflow = (carry == 1) == result.anybits?(0x80) ? 0 : OVERFLOW
+          flags(NEGATIVE | ZERO | OVERFLOW | CARRY, nz8(result) | overflow | carry)
+          @a = result
+        end
+
+        # The undocumented $18: each flag, ANDed with its bit of the byte
+        # after the opcode, moves one bit up, and V also takes Z ANDed with
+        # bit 2.
+        def x18
+          masked = @cc & @value
+          @cc = ((masked << 1) & 0xff) | (masked.nobits?(ZERO) ? 0 : OVERFLOW)
+        end
+
+        def exg
+          first = @post >> 4
+          second = @post & 0x0f
+          value = transfer_register(second)
+          set_transfer_register(second, sized(transfer_register(first), first, second))
+          set_transfer_register(first, sized(value, second, first))
+        end
+
+        def tfr
+          source = @post >> 4
+          destination = @post & 0x0f
+          set_transfer_register(destination, sized(transfer_register(source), source, destination))
+        end
+
+        # A value moved from register code +from+ to +to+: an 8-bit register
+        # fills a 16-bit one's high byte with $FF, and a 16-bit one gives an
+        # 8-bit one its low byte.
+        def sized(value, from, to)
+          return value & 0xff if to >= 8
+          return value | 0xff00 if from >= 8
+
+          value
+        end
+
+        def swi = software_interrupt(0xfffa, IRQ_MASK | FIRQ_MASK, ENTIRE)
+        def swi2 = software_interrupt(0xfff4, 0, ENTIRE)
+        def swi3 = software_interrupt(0xfff2, 0, ENTIRE)
+        def xres = software_interrupt(0xfffe, 0, 0)
+        def xswi2 = software_interrupt(0xfff4, 0, 0)
+        def xfirq = software_interrupt(0xfff6, 0, 0)
+
+        def software_interrupt(vector, mask, entire)
+          @cc |= entire
+          interrupt_vector(vector, mask)
+        end
+      end
+    end
+  end
+end