badline 0.17.0 → 0.19.0

data/lib/badline/drives/model9060/idle.rb

@@ -0,0 +1,169 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model9060
+      # Sleeping through the two processors' idle loops, exactly, as
+      # Model8050::Idle does.
+      #
+      # With nothing to do, the IP goes round DOS 3.0's idle loop from
+      # IP_LOOP, and the SASI host round its job loop from SASI_LOOP, each
+      # pass finding the job queue empty, until ATN interrupts the IP. The
+      # host has no interrupt of its own. A pass puts back what it found, so
+      # each processor comes back to its loop's start as it left it.
+      #
+      # Each time a processor comes to its loop's start, the unit compares
+      # what that processor sees with what it saw last time round: the CPU,
+      # its chips but for their counters, its RAM and the common RAM. The
+      # same, with no read of a counter or an interrupt flag between, makes
+      # the pass repeatable. Once both are, with the hard disk's controller
+      # idle and no interrupt pulled, the unit sleeps until a counter is due
+      # to pull IRQ, the IEEE-488 controller moves a line, or something
+      # outside reads or changes the unit (settle!). Asleep, a host cycle
+      # only counts towards the one planned for the counter
+      # (DOSBoard#plan_sleep), and a moved line wakes the unit as the
+      # controller pushes it (DOSBoard#host_written!).
+      module Idle
+        IP_LOOP = 0xc131
+        SASI_LOOP = 0xf8f1
+
+        # Whether the unit may sleep through its idle loops.
+        attr_reader :idle_skip
+
+        def idle_skip=(on)
+          settle!
+          @idle_skip = on
+        end
+
+        def asleep? = @asleep
+
+        # Whether the unit owes cycles.
+        def dozing? = @asleep
+
+        # Brings the unit up to the present, cycle for cycle, and drops the
+        # passes it found, since whoever called may change it.
+        def settle!
+          wake! if @asleep
+          forget_passes
+        end
+
+        private
+
+        def init_idle
+          @idle_skip = true
+          @asleep = false
+          @owed = 0
+          @budget = 0
+          @planned = false
+          @slept = 0
+          @wake_at = 0
+          forget_passes
+        end
+
+        def forget_passes
+          @ip_mark = nil
+          @sasi_mark = nil
+          @ip_pass = nil
+          @sasi_pass = nil
+        end
+
+        def owe_cycle
+          @owed += 1
+          wake! if @owed >= @budget
+        end
+
+        def watch_loops
+          ip = @ip_cpu
+          @ip_pass = nil if ip.irq
+          @sasi_pass = nil if @sasi_cpu.irq
+          ip_pass_found if ip.program_counter == IP_LOOP && ip.boundary?
+          host = @sasi_cpu
+          sasi_pass_found if host.program_counter == SASI_LOOP && host.boundary?
+        end
+
+        def ip_pass_found
+          state = ip_state
+          @ip_pass = repeated(@ip_mark, state, @ip_cpu, @ip_bus.volatile)
+          @ip_mark = [state, @ip_cpu.cycles, @ip_cpu.instructions]
+          @ip_bus.volatile = false
+          fall_asleep if @ip_pass && @sasi_pass
+        end
+
+        def sasi_pass_found
+          state = sasi_state
+          @sasi_pass = repeated(@sasi_mark, state, @sasi_cpu, @sasi_bus.volatile)
+          @sasi_mark = [state, @sasi_cpu.cycles, @sasi_cpu.instructions]
+          @sasi_bus.volatile = false
+          fall_asleep if @ip_pass && @sasi_pass
+        end
+
+        def repeated(mark, state, cpu, volatile)
+          return nil if mark.nil? || volatile || mark[0] != state
+
+          [cpu.cycles - mark[1], cpu.instructions - mark[2]]
+        end
+
+        def fall_asleep
+          target = @target
+          return unless target.quiet? && !target.busy? && !@ip_cpu.irq && !@sasi_cpu.irq
+
+          budget = quiet_cycles
+          return if budget < 2
+
+          @asleep = true
+          @owed = 0
+          @budget = budget
+        end
+
+        def quiet_cycles
+          [@data_riot.quiet_cycles, @control_riot.quiet_cycles, @via.quiet_cycles].min
+        end
+
+        # The budget is spent (DOSBoard#slept_through?).
+        def doze = wake!
+
+        # Runs the cycles owed: the counters in bulk, then each processor's
+        # whole passes and the rest of a pass, and on a host cycle that ran
+        # past the budget, the rest cycle by cycle.
+        def wake!
+          owe_slept
+          owed = @owed
+          @asleep = false
+          @owed = 0
+          quiet = [owed, @budget].min
+          skip_passes(quiet) if quiet.positive?
+          (owed - quiet).times { @asleep ? owe_cycle : run_cycle }
+        end
+
+        def skip_passes(cycles)
+          @data_riot.fast_forward(cycles)
+          @control_riot.fast_forward(cycles)
+          @via.fast_forward(cycles)
+          @target.fast_forward(cycles)
+          skip(@ip_cpu, @ip_pass, @ip_mark, cycles)
+          skip(@sasi_cpu, @sasi_pass, @sasi_mark, cycles)
+          @cycles += cycles
+        end
+
+        def skip(cpu, pass, mark, owed)
+          passes = owed / pass[0]
+          cpu.fast_forward(passes * pass[0], passes * pass[1])
+          mark[1] += passes * pass[0]
+          mark[2] += passes * pass[1]
+          (owed - (passes * pass[0])).times { cpu.cycle! }
+        end
+
+        def ip_state
+          [*@ip_cpu.idle_state, *@data_riot.idle_state, *@control_riot.idle_state, @ip_bus.data, common_changes]
+        end
+
+        def sasi_state
+          [*@sasi_cpu.idle_state, *@via.idle_state, *@lines.state, *@sasi_bus.ram.read(0, 0x80), @sasi_bus.data,
+           common_changes]
+        end
+
+        def common_changes = @ip_bus.common_changes + @sasi_bus.common_changes
+      end
+    end
+  end
+end

data/lib/badline/drives/model9060/keyed_state.rb

@@ -0,0 +1,123 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model9060
+      class SASITarget
+        # The controller's fields in a keyed snapshot module (BL-D8-SASI):
+        # the bus phase, REQ, the cycles left to the next, the command, the
+        # bytes of the phase and the place in them, the write under way,
+        # the sense bytes, the fast mode, its clock, the heads' cylinder, the
+        # geometry and the block buffer, then the image's path and how it
+        # was opened. The image itself stays in its file, which each write
+        # reached as it ended.
+        module KeyedState
+          def save_fields(out)
+            out.int("phase", @phase).bool("request", @request).int("delay", @delay)
+            out.ints("command", @command).ints("buffer", @buffer).int("index", @index)
+            out.bool("writing", @writing).ints("sense", @sense).ints("last_sense", @last_sense)
+            out.bool("fast", @fast).int("cycle", @cycle).int("cylinder", @cylinder)
+            out.int("heads", @heads).int("sectors", @sectors).ints("block_buffer", @block_buffer)
+            disk = @disk
+            out.text("path", disk.nil? ? "" : disk.path.to_s).bool("read_only", disk.nil? || disk.read_only?)
+            out.int("disk_heads", disk.nil? ? 0 : disk.heads)
+          end
+
+          # A detached reader, or a host file that is gone, leaves the drive
+          # empty.
+          def load_fields(input, detached: false)
+            load_bus_fields(input)
+            path = input.text("path", "")
+            read_only = input.bool("read_only", false)
+            heads = input.int("disk_heads", 4)
+            @disk = detached || !File.file?(path) ? nil : Storage::D90Image.new(path, read_only:, heads:)
+          end
+
+          private
+
+          def load_bus_fields(input)
+            @phase = input.int("phase", @phase)
+            @request = input.bool("request", @request)
+            @delay = input.int("delay", @delay)
+            @command = input.ints("command", @command).dup
+            @buffer = input.ints("buffer", @buffer).dup
+            @index = input.int("index", @index)
+            @writing = input.bool("writing", @writing)
+            @sense = input.ints("sense", @sense).dup
+            @last_sense = input.ints("last_sense", @last_sense).dup
+            @fast = input.bool("fast", @fast)
+            @cycle = input.int("cycle", @cycle)
+            @cylinder = input.int("cylinder", @cylinder)
+            @heads = input.int("heads", @heads)
+            @sectors = input.int("sectors", @sectors)
+            @block_buffer = input.ints("block_buffer", @block_buffer).dup
+          end
+        end
+
+        include KeyedState
+      end
+
+      # The unit's own fields in a keyed snapshot module (BL-D8): its model,
+      # its clock phase and cycle count, each bus's last byte, the
+      # controller's lines as the port latched them, under ieee.*, and the
+      # SASI lines' ACK and RST levels. A save settles the unit first, so it
+      # is awake; a load finds its passes afresh.
+      module KeyedState
+        def save_fields(out)
+          settle!
+          out.text("model", model_name).int("phase", @phase).int("cycles", @cycles)
+          out.int("ip_data", @ip_bus.data).int("sasi_data", @sasi_bus.data)
+          out.int("ieee.host", @ieee_port.host)
+          ack_high, reset_high = @lines.state
+          out.bool("sasi.ack_high", ack_high).bool("sasi.reset_high", reset_high)
+          out
+        end
+
+        def load_fields(input)
+          settle!
+          input.choice("model", [model_name], model_name)
+          @phase = input.int("phase", @phase)
+          @cycles = input.int("cycles", @cycles)
+          @ip_bus.data = input.byte("ip_data", @ip_bus.data)
+          @sasi_bus.data = input.byte("sasi_data", @sasi_bus.data)
+          @ieee_port.host = input.int("ieee.host", @ieee_port.host)
+          @lines.state = [input.bool("sasi.ack_high", true), input.bool("sasi.reset_high", false)]
+        end
+
+        # The unit as modules of its own, named from `name` (BL-D8 for
+        # device 8): its own fields, the common RAM, UC1 and UE1 with their
+        # RAM, each processor, the host's RAM and VIA, and the hard disk's
+        # controller.
+        def save_modules(sections, name)
+          sections << Snapshot::Keyed.section(name) { |out| save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-COMMON") { |out| @common.save_fields(out, "ram") }
+          sections << Snapshot::Keyed.section("#{name}-RIOT1") { |out| @data_riot.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-RIOT2") { |out| @control_riot.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-IPCPU") { |out| @ip_cpu.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-SASICPU") { |out| @sasi_cpu.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-SASIRAM") { |out| @sasi_bus.ram.save_fields(out, "ram") }
+          sections << Snapshot::Keyed.section("#{name}-VIA") { |out| @via.save_fields(out) }
+          sections << Snapshot::Keyed.section("#{name}-SASI") { |out| @target.save_fields(out) }
+        end
+
+        # The unit from its modules, `input` being its own.
+        def load_modules(modules, input, name)
+          load_fields(input)
+          @common.load_fields(modules.required("#{name}-COMMON"), "ram")
+          @data_riot.load_fields(modules.required("#{name}-RIOT1"))
+          @control_riot.load_fields(modules.required("#{name}-RIOT2"))
+          @ip_cpu.load_fields(modules.required("#{name}-IPCPU"))
+          @sasi_cpu.load_fields(modules.required("#{name}-SASICPU"))
+          @sasi_bus.ram.load_fields(modules.required("#{name}-SASIRAM"), "ram")
+          @via.load_fields(modules.required("#{name}-VIA"))
+          @target.load_fields(modules.required("#{name}-SASI"), detached: modules.detached?)
+          @via.restored!
+          @ip_cpu.restored!
+          @sasi_cpu.restored!
+        end
+      end
+
+      include KeyedState
+    end
+  end
+end

data/lib/badline/drives/model9060/parts.rb

@@ -0,0 +1,98 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model9060
+      # The SASI host's VIA, at $0080, a class of its own so it keeps one
+      # type of peripheral.
+      class SASIVIA < Chips::VIA
+      end
+
+      # The SASI host's 6502, on the SASIBus.
+      class SASICPU
+        include Badline::Chips::CPU::Core
+        include Engine::IdleCPU
+      end
+
+      # The VIA's lines to the controller (SASITarget), on the board's
+      # transceivers:
+      #
+      #   PA0-7  the data bus             PB0  SEL out
+      #   CA1    REQ, rising as it rises  PB1  RST out
+      #   CA2    ACK, pulsed on each      PB2  C/D in
+      #          read or write of ORA     PB3  BSY in
+      #   CB2    the transceivers'        PB4  jumper J14: high for four
+      #          direction                     heads (D9060), low for six
+      #                                   PB6  I/O in
+      #                                   PB7  MSG in
+      #
+      # The ports read and drive each line high while it is asserted, SEL
+      # and RST only while PB0 and PB1 are outputs.
+      # SEL raised selects the controller with the data bus as the host
+      # drives it, and RST raised resets it. ACK falling hands it the byte
+      # on the data bus.
+      class SASILines
+        SEL = 0x01
+        RST = 0x02
+        CD = 0x04
+        BSY = 0x08
+        J14 = 0x10
+        IO = 0x40
+        MSG = 0x80
+
+        attr_reader :target
+        attr_writer :via
+
+        # `four_heads` is J14.
+        def initialize(target, four_heads:)
+          @target = target
+          @four_heads = four_heads
+          @via = nil
+          @ack_high = true
+          @reset_high = false
+        end
+
+        # The data bus: the controller's byte while it drives it.
+        def read_a(_lines)
+          target = @target
+          target.input? ? target.data : 0xff
+        end
+
+        def read_b(_lines)
+          target = @target
+          value = 0x23
+          value |= CD if target.control?
+          value |= BSY if target.busy?
+          value |= J14 if @four_heads
+          value |= IO if target.input?
+          value |= MSG if target.message?
+          value
+        end
+
+        # One cycle of the controller, then the host's ACK, RST and SEL to
+        # the controller, and REQ to CA1.
+        def cycle!
+          target = @target
+          via = @via
+          target.clock
+          ack_high = via.ca2_output
+          target.acknowledge(via.port_a_output) if @ack_high && !ack_high
+          @ack_high = ack_high
+          host = via.port_b_output & via.peek(0x82)
+          reset_high = host.anybits?(RST)
+          target.reset if reset_high && !@reset_high
+          @reset_high = reset_high
+          target.select(via.port_a_output) if host.anybits?(SEL)
+          via.ca1 = target.request?
+        end
+
+        # Everything the lines hold between cycles.
+        def state = [@ack_high, @reset_high]
+
+        def state=(values)
+          @ack_high, @reset_high = values
+        end
+      end
+    end
+  end
+end

data/lib/badline/drives/model9060/sasi_bus.rb

@@ -0,0 +1,88 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model9060
+      # The SASI host processor's bus on the DOS board (300010), where the
+      # 8050's floppy controller sits, with its decode and common RAM:
+      #
+      # $0000-$007F - the 6810's 128 bytes, mirrored at $0100 for the stack
+      # $0080-$008F - the VIA (SASILines)
+      # $0400-$13FF - the common RAM, 1 KB in each of the 8050's windows
+      # $F800-$FFFF - 300515, the host's program
+      #
+      # Writes to the ROM and to open bus go nowhere, and a read from open
+      # bus finds the last byte on the data bus.
+      class SASIBus
+        include Addressable
+
+        attr_reader :common, :ram, :via
+        attr_accessor :data
+
+        # How many writes have changed a byte of the common RAM
+        # (Model9060::Idle).
+        attr_reader :common_changes
+
+        # Whether a counter or an interrupt flag has been read since it was
+        # last cleared (Model9060::Idle).
+        attr_accessor :volatile
+
+        def initialize(rom:, common:, via:)
+          addressable_at(0, length: 2**16)
+          @rom = rom
+          @common = common
+          @via = via
+          @ram = Memory.new([], length: 0x80)
+          @data = 0
+          @volatile = false
+          @common_changes = 0
+        end
+
+        def peek(addr)
+          @data = if addr >= 0xf800
+                    @rom.peek(addr & 0x07ff)
+                  elsif addr < 0x0200
+                    peek_low(addr)
+                  elsif addr.between?(0x0400, 0x13ff)
+                    @common.peek(addr - 0x0400)
+                  else
+                    @data
+                  end
+        end
+
+        def poke(addr, value)
+          @data = value
+          if addr < 0x0200
+            poke_low(addr, value)
+          elsif addr.between?(0x0400, 0x13ff)
+            poke_common(addr - 0x0400, value)
+          end
+        end
+
+        private
+
+        def peek_low(addr)
+          return @ram.peek(addr & 0x7f) if addr.nobits?(0x80)
+          return @data if addr.anybits?(0x70)
+
+          register = addr & 0x0f
+          @volatile = true if register.between?(0x04, 0x0a) || register == 0x0d
+          @via.peek(0x80 | register)
+        end
+
+        def poke_low(addr, value)
+          if addr.nobits?(0x80)
+            @ram.poke(addr & 0x7f, value)
+          elsif addr.nobits?(0x70)
+            @via.poke(0x80 | (addr & 0x0f), value)
+          end
+        end
+
+        def poke_common(index, value)
+          @common_changes += 1 if @common.peek(index) != value
+          @common.poke(index, value)
+        end
+      end
+    end
+  end
+end

data/lib/badline/drives/model9060/sasi_commands.rb

@@ -0,0 +1,168 @@
+# frozen_string_literal: true
+
+module Badline
+  module Drives
+    class Model9060
+      # The commands the DOS board's SASI ROM (300515) sends, against the
+      # disk's blocks. A command's second to fourth bytes hold the drive
+      # (bits 5-7) and the block's LBA, its fifth the blocks to move.
+      #
+      # | Op | Command | Data |
+      # | --- | --- | --- |
+      # | $00 | Test Unit Ready | |
+      # | $01 | Recalibrate: seek to cylinder 0 | |
+      # | $03 | Request Sense: the last command's error and its LBA | 4 in |
+      # | $04 | Format Unit | |
+      # | $08 | Read | 256 a block in |
+      # | $0A | Write | 256 a block out |
+      # | $0B | Seek | |
+      # | $0C | Vendor: read the controller's block buffer (unverified) | 256 in |
+      # | $0E | Vendor: write the controller's block buffer (unverified) | 256 out |
+      # | $E3 | Vendor: four zero bytes from a drive that is there (unverified) | 4 in |
+      # | $C0 | Vendor: set the geometry (unverified) | |
+      #
+      # DOS 3.0 sends $E3 before it first reads a drive, and leaves a drive
+      # alone that fails it as DRIVE NOT READY, as drive 1 does here.
+      #
+      # $C0's fifth and sixth bytes are taken as the last head and the last
+      # sector of a head, as the ROM sends them (5 and 31 on a D9090 at
+      # boot). Its other bytes aren't used.
+      #
+      # An error's sense byte has its class in bits 4-5 and its code in bits
+      # 0-3, with bit 7 set when the LBA after it names the block. The ROM
+      # reads that byte from the message phase after a check condition,
+      # and the controller sends it there.
+      #
+      # Format Unit erases the disk at once and puts the controller in a
+      # fast mode, where Read, Write and Seek take no seek or rotation time,
+      # for the DOS's passes over the whole disk. Any other command ends
+      # it. Outside it a seek takes 3 ms a cylinder and 15 ms to settle, and
+      # the disk turns 32 blocks in 16.7 ms.
+      module SASICommands
+        DRIVE_NOT_READY = 0x04
+        WRITE_FAULT = 0x03
+        INVALID_COMMAND = 0x20
+        ILLEGAL_ADDRESS = 0xa1
+
+        BLOCK = 256
+        SECTOR_CYCLES = 521
+        STEP_CYCLES = 3_000
+        SETTLE_CYCLES = 15_000
+
+        DISK_COMMANDS = [0x00, 0x01, 0x04, 0x08, 0x0a, 0x0b, 0xe3].freeze
+        FAST_COMMANDS = [0x08, 0x0a, 0x0b].freeze
+
+        attr_reader :heads, :sectors, :cylinder
+
+        def fast? = @fast
+
+        private
+
+        def reset_geometry
+          @heads = 4
+          @sectors = 32
+          @block_buffer = Array.new(BLOCK, 0)
+        end
+
+        def execute
+          @fast = false unless FAST_COMMANDS.include?(@command[0])
+          case @command[0]
+          when 0x03 then enter(SASITarget::DATA_IN, @last_sense.dup, 1)
+          when 0x0c then enter(SASITarget::DATA_IN, @block_buffer.dup, 1)
+          when 0x0e then enter(SASITarget::DATA_OUT, Array.new(BLOCK, 0), 1)
+          when 0xc0 then set_geometry
+          else disk_command
+          end
+        end
+
+        def disk_command
+          return refuse(INVALID_COMMAND) unless DISK_COMMANDS.include?(@command[0])
+          return refuse(DRIVE_NOT_READY) unless @disk && (@command[1] >> 5).zero?
+
+          case @command[0]
+          when 0x00 then report
+          when 0x01 then report(travel(0))
+          when 0x04 then format_unit
+          when 0xe3 then enter(SASITarget::DATA_IN, [0, 0, 0, 0], 1)
+          else block_command
+          end
+        end
+
+        def block_command
+          return refuse(ILLEGAL_ADDRESS) unless @disk.blocks?(lba, @command[0] == 0x0b ? 1 : count)
+
+          case @command[0]
+          when 0x08 then read
+          when 0x0a then enter(SASITarget::DATA_OUT, Array.new(count * BLOCK, 0), 1)
+          else report(travel(cylinder_of(lba)))
+          end
+        end
+
+        def lba = ((@command[1] & 0x1f) << 16) | (@command[2] << 8) | @command[3]
+
+        def count = @command[4].zero? ? 256 : @command[4]
+
+        def cylinder_of(block) = block / (@heads * @sectors)
+
+        def set_geometry
+          @heads = @command[4] + 1
+          @sectors = @command[5] + 1
+          report
+        end
+
+        def read
+          bytes = @disk.read_blocks(lba, count)
+          @block_buffer = bytes.last(BLOCK)
+          enter(SASITarget::DATA_IN, bytes, access_cycles)
+        end
+
+        def data_received
+          if @command[0] == 0x0e
+            @block_buffer = @buffer.dup
+            report
+          else
+            @writing = true
+            @delay = access_cycles
+          end
+        end
+
+        def store_buffer
+          @disk.write_blocks(lba, @buffer)
+          @block_buffer = @buffer.last(BLOCK)
+          report
+        rescue Storage::WriteError
+          refuse(WRITE_FAULT)
+        end
+
+        def format_unit
+          blocks = @heads * @sectors
+          (0...@disk.block_count).step(blocks) do |first|
+            @disk.write_blocks(first, Array.new([blocks, @disk.block_count - first].min * BLOCK, 0))
+          end
+          @fast = true
+          report
+        rescue Storage::WriteError
+          refuse(WRITE_FAULT)
+        end
+
+        # The seek to the block's cylinder, the turn until the block comes
+        # under the head, and the blocks passing under it.
+        def access_cycles
+          return 1 if @fast
+
+          seek = travel(cylinder_of(lba))
+          slot = ((@cycle + seek) / SECTOR_CYCLES) % @sectors
+          seek + ((((lba % @sectors) - slot) % @sectors) * SECTOR_CYCLES) + (count * SECTOR_CYCLES)
+        end
+
+        def travel(target)
+          steps = (target - @cylinder).abs
+          @cylinder = target
+          return 1 if @fast || steps.zero?
+
+          (steps * STEP_CYCLES) + SETTLE_CYCLES
+        end
+      end
+    end
+  end
+end