axi_tdl 0.1.0 → 0.1.8
Sign up to get free protection for your applications and to get access to all the features.
- checksums.yaml +4 -4
- data/Rakefile +7 -0
- data/lib/axi/AXI4/axi4_direct_A1.sv +1 -1
- data/lib/axi/AXI4/axi4_direct_verc.sv +54 -54
- data/lib/axi/AXI4/axi4_dpram_cache.rb +1 -0
- data/lib/axi/AXI4/axi4_dpram_cache.sv +10 -10
- data/lib/axi/AXI4/axi4_rd_burst_track.sv +2 -1
- data/lib/axi/AXI4/axi4_wr_burst_track.sv +2 -1
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +9 -9
- data/lib/axi/AXI4/odata_pool_axi4_A3.sv +7 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +5 -5
- data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +8 -4
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +6 -6
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +12 -12
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +154 -0
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +242 -0
- data/lib/axi/AXI_stream/axis_insert_copy.sv +79 -0
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +48 -0
- data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +113 -0
- data/lib/axi/AXI_stream/axis_sim_master_model.rb +2 -0
- data/lib/axi/AXI_stream/axis_sim_master_model.sv +46 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
- data/lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv +50 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +2 -0
- data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +5 -3
- data/lib/axi/common/common_ram_sim_wrapper.sv +1 -1
- data/lib/axi/common/common_ram_wrapper.sv +1 -1
- data/lib/axi/common/test_write_mem.sv +1 -1
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +13 -13
- data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +14 -11
- data/lib/axi/platform_ip/fifo_36kb_long.sv +1 -1
- data/lib/axi/platform_ip/long_fifo_verb.sv +1 -1
- data/lib/axi/platform_ip/wide_fifo.sv +1 -1
- data/lib/axi/platform_ip/xilinx_fifo_verb.sv +1 -1
- data/lib/axi/platform_ip/xilinx_fifo_verc.sv +2 -1
- data/lib/axi/techbench/tb_axi_stream_split_channel.rb +2 -1
- data/lib/axi/techbench/tb_axi_stream_split_channel.sv +46 -45
- data/lib/axi_tdl.rb +31 -1
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/public_atom_module/CheckPClock.sv +53 -0
- data/lib/public_atom_module/LICENSE.md +674 -0
- data/lib/public_atom_module/altera_xilinx_always_block_sw.rb +57 -0
- data/lib/public_atom_module/bits_decode.sv +71 -0
- data/lib/public_atom_module/bits_decode_verb.sv +71 -0
- data/lib/public_atom_module/bits_decode_verb_sdl.rb +24 -0
- data/lib/public_atom_module/broaden.v +43 -0
- data/lib/public_atom_module/broaden_and_cross_clk.v +47 -0
- data/lib/public_atom_module/ceiling.v +39 -0
- data/lib/public_atom_module/ceiling_A1.v +42 -0
- data/lib/public_atom_module/clock_rst.sv +64 -0
- data/lib/public_atom_module/cross_clk_sync.v +37 -0
- data/lib/public_atom_module/edge_generator.v +50 -0
- data/lib/public_atom_module/flooring.v +36 -0
- data/lib/public_atom_module/latch_data.v +30 -0
- data/lib/public_atom_module/latency.v +48 -0
- data/lib/public_atom_module/latency_dynamic.v +83 -0
- data/lib/public_atom_module/latency_long.v +84 -0
- data/lib/public_atom_module/latency_verb.v +52 -0
- data/lib/public_atom_module/once_event.sv +65 -0
- data/lib/public_atom_module/pipe_reg.v +93 -0
- data/lib/public_atom_module/pipe_reg_2write_ports.v +84 -0
- data/lib/public_atom_module/sim/clock_rst_verb.sv +54 -0
- data/lib/public_atom_module/sim/clock_rst_verc.sv +69 -0
- data/lib/public_atom_module/sim/latency_long_tb.sv +49 -0
- data/lib/public_atom_module/sim/latency_long_tb.sv.bak +49 -0
- data/lib/public_atom_module/sim_system_pkg.sv +4 -0
- data/lib/public_atom_module/synth_system_pkg.sv +4 -0
- data/lib/tdl/Logic/logic_edge.rb +1 -1
- data/lib/tdl/auto_script/autogensdl.rb +2 -3
- data/lib/tdl/auto_script/import_hdl.rb +40 -5
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +47 -10
- data/lib/tdl/class_hdl/hdl_always_comb.rb +4 -1
- data/lib/tdl/class_hdl/hdl_always_ff.rb +3 -3
- data/lib/tdl/class_hdl/hdl_assign.rb +7 -1
- data/lib/tdl/class_hdl/hdl_block_ifelse.rb +7 -7
- data/lib/tdl/class_hdl/hdl_foreach.rb +2 -2
- data/lib/tdl/class_hdl/hdl_function.rb +4 -4
- data/lib/tdl/class_hdl/hdl_generate.rb +5 -2
- data/lib/tdl/class_hdl/hdl_initial.rb +25 -3
- data/lib/tdl/class_hdl/hdl_module_def.rb +9 -6
- data/lib/tdl/class_hdl/hdl_package.rb +45 -0
- data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +99 -27
- data/lib/tdl/class_hdl/hdl_struct.rb +2 -2
- data/lib/tdl/elements/Reset.rb +5 -9
- data/lib/tdl/elements/clock.rb +5 -9
- data/lib/tdl/elements/data_inf.rb +0 -17
- data/lib/tdl/elements/logic.rb +9 -31
- data/lib/tdl/elements/mail_box.rb +6 -1
- data/lib/tdl/elements/originclass.rb +17 -47
- data/lib/tdl/elements/parameter.rb +5 -6
- data/lib/tdl/examples/11_test_unit/dve.tcl +6 -153
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +2 -2
- data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +9 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +2 -2
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +2 -2
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -1
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +41 -0
- data/lib/tdl/examples/11_test_unit/tu0.sv +2 -1
- data/lib/tdl/examples/1_define_module/exmple_md.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +7 -7
- data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +4 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +2 -2
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +1 -1
- data/lib/tdl/examples/6_module_with_interface/example_interface.sv +8 -8
- data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +9 -9
- data/lib/tdl/examples/7_module_with_package/body_package.sv +4 -3
- data/lib/tdl/examples/7_module_with_package/example_pkg.sv +1 -1
- data/lib/tdl/examples/7_module_with_package/head_package.sv +4 -3
- data/lib/tdl/examples/8_top_module/dve.tcl +6 -0
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -1
- data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +29 -0
- data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
- data/lib/tdl/examples/8_top_module/test_top_sim.sv +9 -0
- data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +2 -1
- data/lib/tdl/examples/9_itegration/dve.tcl +155 -2
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +1 -1
- data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +1 -1
- data/lib/tdl/examples/9_itegration/test_tttop.sv +7 -38
- data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +38 -7
- data/lib/tdl/exlib/axis_verify.rb +4 -3
- data/lib/tdl/exlib/constraints_verb.rb +1 -0
- data/lib/tdl/exlib/itegration_verb.rb +47 -41
- data/lib/tdl/rebuild_ele/ele_base.rb +15 -10
- data/lib/tdl/sdlmodule/sdlmodule.rb +117 -51
- data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +1 -1
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +2 -2
- data/lib/tdl/sdlmodule/sdlmodule_instance.rb +3 -0
- data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +6 -6
- data/lib/tdl/sdlmodule/sdlmodule_varible.rb +6 -6
- data/lib/tdl/sdlmodule/test_unit_module.rb +6 -0
- data/lib/tdl/sdlmodule/top_module.rb +4 -0
- data/lib/tdl/tdl.rb +1 -11
- data/lib/tdl/tdlerror/tdlerror.rb +1 -1
- metadata +43 -5
- data/CODE_OF_CONDUCT.md +0 -74
- data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +0 -87
@@ -47,6 +47,20 @@ module ClassHDL
|
|
47
47
|
@tree << arg
|
48
48
|
end
|
49
49
|
@belong_to_module = belong_to_module
|
50
|
+
unless @belong_to_module
|
51
|
+
raise TdlError.new("OpertorChain must have belong_to_module")
|
52
|
+
end
|
53
|
+
end
|
54
|
+
|
55
|
+
def instance_inspect
|
56
|
+
str = ["self belong_to_module:#{belong_to_module.module_name}"]
|
57
|
+
index = 0
|
58
|
+
@tree.each do |node|
|
59
|
+
bl = "#{node[0].respond_to?(:belong_to_module) ? "belong_to_module:#{node[0].belong_to_module.module_name }" : '' }"
|
60
|
+
str << "{{ tree[#{index}][1]node[1]SYMB{#{node[1].to_s}} tree[#{index}][0]node[0]#{node[0].to_s} #{node[0].class} #{bl}}}"
|
61
|
+
index += 1
|
62
|
+
end
|
63
|
+
str.join(" ")
|
50
64
|
end
|
51
65
|
|
52
66
|
ClassHDL::OP_SYMBOLS.each do |os|
|
@@ -103,17 +117,20 @@ module ClassHDL
|
|
103
117
|
# self.nege = true
|
104
118
|
# return self
|
105
119
|
self.slaver = true
|
106
|
-
|
120
|
+
bel = belong_to_module || ( @tree[0][0].respond_to?(:belong_to_module) && @tree[0][0].belong_to_module )
|
121
|
+
new_op = OpertorChain.new(["~(#{self.instance(:assign, bel)})".to_nq])
|
107
122
|
end
|
108
123
|
|
109
124
|
def brackets
|
110
125
|
self.slaver = true
|
111
|
-
|
126
|
+
bel = ( @tree[0][0].respond_to?(:belong_to_module) && @tree[0][0].belong_to_module )
|
127
|
+
new_op = OpertorChain.new(["(#{self.instance(:assign, belong_to_module || bel)})".to_nq], belong_to_module)
|
112
128
|
end
|
113
129
|
|
114
130
|
def clog2
|
115
131
|
self.slaver = true
|
116
|
-
|
132
|
+
bel = belong_to_module || ( @tree[0][0].respond_to?(:belong_to_module) && @tree[0][0].belong_to_module )
|
133
|
+
new_op = OpertorChain.new(["$clog2(#{self.instance(:aasign, bel)})".to_nq],belong_to_module)
|
117
134
|
end
|
118
135
|
|
119
136
|
def self.define_op_flag(ruby_op,hdl_op)
|
@@ -143,10 +160,13 @@ module ClassHDL
|
|
143
160
|
|
144
161
|
|
145
162
|
def to_s
|
146
|
-
instance(type=:cond)
|
163
|
+
instance(type=:cond,belong_to_module || ( @tree[0][0].respond_to?(:belong_to_module) && @tree[0][0].belong_to_module ) )
|
147
164
|
end
|
148
165
|
|
149
|
-
def instance(type=:assign)
|
166
|
+
def instance(type=:assign,block_belong_to_module=nil,show=nil)
|
167
|
+
unless block_belong_to_module
|
168
|
+
raise TdlError.new("OpertorChain must has block_belong_to_module")
|
169
|
+
end
|
150
170
|
AssignDefOpertor.with_rollback_opertors(:old) do
|
151
171
|
str = ''
|
152
172
|
# both_symb_used = false
|
@@ -160,39 +180,75 @@ module ClassHDL
|
|
160
180
|
sb = " = "
|
161
181
|
end
|
162
182
|
else
|
163
|
-
|
164
|
-
|
165
|
-
# else
|
166
|
-
sb = "#{node[1].to_s}"
|
167
|
-
# end
|
183
|
+
|
184
|
+
sb = "#{node[1].to_s}"
|
168
185
|
end
|
169
186
|
else
|
170
|
-
|
171
|
-
|
172
|
-
|
173
|
-
|
174
|
-
#
|
187
|
+
sb = "#{node[1].to_s}"
|
188
|
+
end
|
189
|
+
|
190
|
+
if cnt==1 && show
|
191
|
+
puts "tree[1][1]<#{node[1]}> 使用 #{sb}"
|
175
192
|
end
|
176
193
|
|
177
194
|
unless node[0].is_a? OpertorChain
|
178
195
|
## 判断是不是属于 Var <= "String" 形式
|
179
196
|
if (@tree.length == 2) && node[0].instance_of?(String) && !@slaver
|
180
197
|
str += (sb + '"' + node[0].to_s + '"')
|
198
|
+
if show
|
199
|
+
puts "tree 长度等于2; tree[#{cnt}][0] is string; op is not slaver"
|
200
|
+
end
|
181
201
|
elsif node[0].instance_of?(String)
|
182
202
|
# "如果是字符串 则原始输出"
|
183
203
|
str += (sb + '"' + node[0].to_s + '"')
|
204
|
+
if show
|
205
|
+
puts "tree[#{cnt}][0] is string"
|
206
|
+
end
|
184
207
|
else
|
185
208
|
# str += (sb + node[0].to_s)
|
186
|
-
if
|
209
|
+
if block_belong_to_module
|
210
|
+
if (node[0].respond_to?(:root_ref) && node[0].respond_to?(:belong_to_module) && node[0].belong_to_module && (node[0].belong_to_module != block_belong_to_module) && node[0].belong_to_module.top_tb_ref? )
|
211
|
+
|
212
|
+
str += (sb + node[0].root_ref)
|
213
|
+
|
214
|
+
if show
|
215
|
+
puts "tree[#{cnt}][0].belong_to_module<#{node[0].belong_to_module.module_name}> != block_belong_to_module<#{block_belong_to_module.module_name}>"
|
216
|
+
end
|
217
|
+
## 反向添加到 TestUnitModule
|
218
|
+
if block_belong_to_module.is_a?(TestUnitModule)
|
219
|
+
block_belong_to_module.add_root_ref_ele(node[0])
|
220
|
+
if show
|
221
|
+
puts "block_belong_to_module<#{block_belong_to_module.module_name}> is TestUnitModule"
|
222
|
+
end
|
223
|
+
end
|
224
|
+
else
|
225
|
+
str += (sb + node[0].to_s)
|
226
|
+
if show
|
227
|
+
mmm = node[0].respond_to?(:belong_to_module) && node[0].belong_to_module.module_name
|
228
|
+
puts "tree[#{cnt}][0]<#{node[0].class}>: ref_root<#{node[0].respond_to?(:root_ref).to_s}> belong_to_module<#{mmm}> block_belong_to_module<#{block_belong_to_module.module_name}> ...."
|
229
|
+
end
|
230
|
+
end
|
231
|
+
elsif(node[0].respond_to?(:root_ref) && node[0].respond_to?(:belong_to_module) && node[0].belong_to_module && (node[0].belong_to_module != belong_to_module) && node[0].belong_to_module.top_tb_ref? )
|
187
232
|
# sb = "#{node[1].root_ref.to_s}"
|
188
233
|
str += (sb + node[0].root_ref)
|
234
|
+
|
235
|
+
if show
|
236
|
+
puts "tree[#{cnt}][0].belong_to_module<#{node[0].belong_to_module.module_name}> != op.belong_to_module<#{belong_to_module.module_name}>"
|
237
|
+
end
|
238
|
+
|
189
239
|
## 反向添加到 TestUnitModule
|
190
240
|
if belong_to_module.is_a?(TestUnitModule)
|
191
241
|
belong_to_module.add_root_ref_ele(node[0])
|
242
|
+
if show
|
243
|
+
puts "tree[#{cnt}][0]: op.belong_to_module<#{belong_to_module.module_name}> is TestUnitModule"
|
244
|
+
end
|
192
245
|
end
|
193
246
|
else
|
194
247
|
# sb = "#{node[1].to_s}"
|
195
248
|
str += (sb + node[0].to_s)
|
249
|
+
if show
|
250
|
+
puts "tree[#{cnt}][0]: op.belong_to_module<#{belong_to_module.module_name}> ..."
|
251
|
+
end
|
196
252
|
end
|
197
253
|
end
|
198
254
|
else
|
@@ -203,13 +259,17 @@ module ClassHDL
|
|
203
259
|
# if node[0].tree.length>2 && ["&","|","<",">"].include?(node[0].tree[1][1])
|
204
260
|
|
205
261
|
# else
|
262
|
+
|
206
263
|
if sb =~/(\||&){2,2}/
|
207
|
-
str += " #{sb}#{node[0].instance(:slaver).to_s}"
|
264
|
+
str += " #{sb}#{node[0].instance(:slaver,block_belong_to_module || belong_to_module).to_s}"
|
208
265
|
else
|
209
|
-
str += "#{sb}(#{node[0].instance(:slaver).to_s})"
|
266
|
+
str += "#{sb}(#{node[0].instance(:slaver,block_belong_to_module || belong_to_module).to_s})"
|
210
267
|
end
|
211
|
-
|
212
|
-
|
268
|
+
|
269
|
+
if show
|
270
|
+
puts "tree[#{cnt}][0] is op, block_belong_to_module<#{block_belong_to_module.to_s}> op.belong_to_module<#{belong_to_module.to_s}>"
|
271
|
+
end
|
272
|
+
|
213
273
|
end
|
214
274
|
cnt += 1
|
215
275
|
end
|
@@ -235,8 +295,10 @@ module ClassHDL
|
|
235
295
|
|
236
296
|
module AssignDefOpertor
|
237
297
|
@@included_class = []
|
238
|
-
@@curr_assign_block = HDLAssignBlock.new(
|
239
|
-
@@
|
298
|
+
@@curr_assign_block = HDLAssignBlock.new(true) ##HDLAssignBlock ##HDLAlwaysCombBlock
|
299
|
+
# @@curr_assign_block = nil
|
300
|
+
@@curr_assign_block_stack = [HDLAssignBlock.new(true) ]
|
301
|
+
# @@curr_assign_block_stack = []
|
240
302
|
@@curr_opertor_stack = [:old]
|
241
303
|
|
242
304
|
def self.curr_opertor_stack
|
@@ -296,7 +358,18 @@ module ClassHDL
|
|
296
358
|
b.slaver = true
|
297
359
|
end
|
298
360
|
## 当 进行 X < Y 等运算时OpertorChain 需要获取 assign block的 belong_to_module
|
299
|
-
|
361
|
+
if @@curr_assign_block
|
362
|
+
bblm = @@curr_assign_block.belong_to_module
|
363
|
+
elsif self.respond_to?(:belong_to_module)
|
364
|
+
bblm = self.belong_to_module
|
365
|
+
elsif b.respond_to?(:belong_to_module)
|
366
|
+
bblm = b.belong_to_module
|
367
|
+
|
368
|
+
else
|
369
|
+
bblm = nil
|
370
|
+
end
|
371
|
+
|
372
|
+
new_op = OpertorChain.new(nil, bblm)
|
300
373
|
new_op.tree.push([self])
|
301
374
|
new_op.tree.push([b,symb])
|
302
375
|
if @@curr_assign_block
|
@@ -511,7 +584,7 @@ class BaseElm
|
|
511
584
|
|
512
585
|
@_array_chain_hash_[name.to_s] = rel
|
513
586
|
end
|
514
|
-
TdlSpace::ArrayChain.
|
587
|
+
TdlSpace::ArrayChain.create(obj: @_array_chain_hash_[name.to_s], lchain:[], belong_to_module: self.belong_to_module)
|
515
588
|
end
|
516
589
|
end
|
517
590
|
end
|
@@ -576,9 +649,8 @@ module TdlSpace
|
|
576
649
|
end
|
577
650
|
ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
|
578
651
|
unless b
|
579
|
-
ArrayChain.
|
652
|
+
ArrayChain.create(obj: obj,lchain: chain+[a],belong_to_module: belong_to_module)
|
580
653
|
else
|
581
|
-
# ArrayChain.new(&obj,chain,[a,b])
|
582
654
|
@end_slice = [a,b]
|
583
655
|
self
|
584
656
|
end
|
@@ -610,7 +682,7 @@ module TdlSpace
|
|
610
682
|
end
|
611
683
|
|
612
684
|
def ~
|
613
|
-
ArrayChain.
|
685
|
+
ArrayChain.create(obj: "~#{self.to_s}", belong_to_module: belong_to_module)
|
614
686
|
end
|
615
687
|
end
|
616
688
|
end
|
@@ -158,7 +158,7 @@ module ClassHDL
|
|
158
158
|
|
159
159
|
def [](a)
|
160
160
|
if dimension
|
161
|
-
return TdlSpace::ArrayChain.
|
161
|
+
return TdlSpace::ArrayChain.create(obj:self,lchain:[a],belong_to_module: belong_to_module)
|
162
162
|
else
|
163
163
|
raise TdlError.new "#{@name} dimenson is nil "
|
164
164
|
end
|
@@ -171,7 +171,7 @@ module ClassHDL
|
|
171
171
|
self.define_singleton_method(e.name) do
|
172
172
|
# RedefOpertor.with_normal_operators do
|
173
173
|
ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
|
174
|
-
TdlSpace::ArrayChain.
|
174
|
+
TdlSpace::ArrayChain.create(obj:"#{@name}.#{e.to_s}".to_nq, belong_to_module: self.belong_to_module)
|
175
175
|
end
|
176
176
|
end
|
177
177
|
end
|
data/lib/tdl/elements/Reset.rb
CHANGED
@@ -5,7 +5,7 @@ class Reset < SignalElm
|
|
5
5
|
attr_reader :name,:active
|
6
6
|
attr_accessor :id,:ghost,:port,:dsize
|
7
7
|
|
8
|
-
def initialize(name:"system_rst",active:"LOW",port:false,dsize:1)
|
8
|
+
def initialize(name:"system_rst",active:"LOW",port:false,dsize:1, belong_to_module: nil)
|
9
9
|
name_legal?(name)
|
10
10
|
# @id = GlobalParam.CurrTdlModule.BindEleClassVars.Reset.id
|
11
11
|
@dsize = dsize
|
@@ -15,14 +15,10 @@ class Reset < SignalElm
|
|
15
15
|
if @active.eql?("low") && @active.eql?("high")
|
16
16
|
raise TdlError.new("RESET ACTIVE PARA #{@active} ERROR")
|
17
17
|
end
|
18
|
-
|
19
|
-
|
20
|
-
|
21
|
-
|
22
|
-
# end
|
23
|
-
# if @id == 2
|
24
|
-
# raise TdlError.new("____________")
|
25
|
-
# end
|
18
|
+
@belong_to_module = belong_to_module
|
19
|
+
unless @belong_to_module
|
20
|
+
raise TdlError.new("Reset<#{name}> dnot have belong_to_module")
|
21
|
+
end
|
26
22
|
end
|
27
23
|
|
28
24
|
# def signal
|
data/lib/tdl/elements/clock.rb
CHANGED
@@ -5,7 +5,7 @@ class Clock < SignalElm
|
|
5
5
|
attr_reader :name
|
6
6
|
attr_accessor :id,:ghost,:port,:dsize,:freqM,:jitter
|
7
7
|
|
8
|
-
def initialize(name:"system_clock",freqM:100.0,port:false,dsize:1,jitter: 0.01)
|
8
|
+
def initialize(name:"system_clock",freqM:100.0,port:false,dsize:1,jitter: 0.01, belong_to_module: nil)
|
9
9
|
name_legal?(name)
|
10
10
|
# @id = GlobalParam.CurrTdlModule.BindEleClassVars.Clock.id
|
11
11
|
@name = name
|
@@ -13,14 +13,10 @@ class Clock < SignalElm
|
|
13
13
|
@port = port
|
14
14
|
@dsize = dsize
|
15
15
|
@jitter = jitter
|
16
|
-
|
17
|
-
|
18
|
-
|
19
|
-
|
20
|
-
# end
|
21
|
-
# if @id == 0
|
22
|
-
# raise TdlError.new(" ID ")
|
23
|
-
# end
|
16
|
+
@belong_to_module = belong_to_module
|
17
|
+
unless @belong_to_module
|
18
|
+
raise TdlError.new("Clock<#{name}> dnot have belong_to_module")
|
19
|
+
end
|
24
20
|
end
|
25
21
|
|
26
22
|
# def port_length
|
@@ -567,23 +567,6 @@ end
|
|
567
567
|
|
568
568
|
class DataInf_C ## signals in interface
|
569
569
|
|
570
|
-
# def valid
|
571
|
-
# RedefOpertor.with_normal_operators do
|
572
|
-
# # raise TdlError.new("\nARRAY Don't have 'valid'") unless @dimension.empty?
|
573
|
-
# # NqString.new(signal.concat ".valid")
|
574
|
-
# if @dimension.empty?
|
575
|
-
# NqString.new(signal.concat ".valid")
|
576
|
-
# else
|
577
|
-
# unless @_array_chain_hash_
|
578
|
-
# rel = generate_inf_to_signals('valid',width=1)
|
579
|
-
# @_array_chain_hash_ = {}
|
580
|
-
# @_array_chain_hash_['valid'] = rel
|
581
|
-
# end
|
582
|
-
# TdlSpace::ArrayChain.new(@_array_chain_hash_['valid'],[])
|
583
|
-
# end
|
584
|
-
# end
|
585
|
-
# end
|
586
|
-
|
587
570
|
define_arraychain_tail_method('valid')
|
588
571
|
define_arraychain_tail_method('ready',width=1,rv=true)
|
589
572
|
define_arraychain_tail_method('vld_rdy')
|
data/lib/tdl/elements/logic.rb
CHANGED
@@ -21,7 +21,7 @@ class Logic < SignalElm
|
|
21
21
|
# attr_reader :dsize
|
22
22
|
attr_accessor :name,:dsize,:id,:ghost,:type
|
23
23
|
attr_reader :dimension,:port
|
24
|
-
def initialize(name:"tmp",dsize:1,port: false,default: nil,msb_high: true,dimension: [],type: "logic")
|
24
|
+
def initialize(name:"tmp",dsize:1,port: false,default: nil,msb_high: true,dimension: [],type: "logic",belong_to_module: nil)
|
25
25
|
@name = name
|
26
26
|
# @id = GlobalParam.CurrTdlModule.BindEleClassVars.Logic.id
|
27
27
|
@dsize = dsize
|
@@ -37,31 +37,12 @@ class Logic < SignalElm
|
|
37
37
|
yield
|
38
38
|
end
|
39
39
|
|
40
|
-
|
41
|
-
|
42
|
-
|
43
|
-
|
44
|
-
|
45
|
-
|
46
|
-
# define_method(:signal) do |h,l|
|
47
|
-
# if h
|
48
|
-
# hh = h
|
49
|
-
# else
|
50
|
-
# hh = dsize-1
|
51
|
-
# end
|
52
|
-
#
|
53
|
-
# if l
|
54
|
-
# ll = l
|
55
|
-
# else
|
56
|
-
# l = 0
|
57
|
-
# end
|
58
|
-
#
|
59
|
-
# if dsize == 1
|
60
|
-
# "#{name}_id#{@id}"
|
61
|
-
# else
|
62
|
-
# "#{name}_id#{@id}[#{hh}:#{ll}]"
|
63
|
-
# end
|
64
|
-
# end
|
40
|
+
@belong_to_module = belong_to_module
|
41
|
+
|
42
|
+
unless @belong_to_module
|
43
|
+
raise TdlError.new("Logic<#{@name}> be not belong_to_module")
|
44
|
+
end
|
45
|
+
|
65
46
|
end
|
66
47
|
|
67
48
|
def copy(name:@name.to_s,dsize:@dsize,port:@port,default:@default,msb_high:@msb_high,dimension:@dimension,type:@type,belong_to_module:@belong_to_module)
|
@@ -98,12 +79,9 @@ class Logic < SignalElm
|
|
98
79
|
b.slaver = true
|
99
80
|
end
|
100
81
|
|
101
|
-
|
102
|
-
# TdlSpace::ArrayChain.new(self,a,b)
|
103
|
-
# end
|
104
|
-
# end
|
82
|
+
|
105
83
|
ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
|
106
|
-
TdlSpace::ArrayChain.
|
84
|
+
TdlSpace::ArrayChain.create(obj: self,lchain: a, end_slice: b, belong_to_module: belong_to_module)
|
107
85
|
end
|
108
86
|
end
|
109
87
|
|
@@ -4,11 +4,16 @@ class MailBox < BaseElm
|
|
4
4
|
# include AlwaysBlock
|
5
5
|
# include RedefOpertor
|
6
6
|
attr_accessor :ghost
|
7
|
-
def initialize(name:'mbox',depth:100)
|
7
|
+
def initialize(name:'mbox',depth:100, belong_to_module: nil )
|
8
8
|
@name = name
|
9
9
|
|
10
10
|
@depth = depth
|
11
11
|
|
12
|
+
@belong_to_module = belong_to_module
|
13
|
+
unless @belong_to_module
|
14
|
+
raise TdlError.new("Clock<#{name}> dnot have belong_to_module")
|
15
|
+
end
|
16
|
+
|
12
17
|
end
|
13
18
|
|
14
19
|
def signal
|
@@ -8,8 +8,9 @@ module TdlSpace
|
|
8
8
|
end
|
9
9
|
|
10
10
|
class ArrayChain
|
11
|
-
attr_reader :obj,:chain,:end_slice
|
12
|
-
def initialize(obj="tmp",lchain=[],end_slice=false)
|
11
|
+
attr_reader :obj,:chain,:end_slice,:belong_to_module
|
12
|
+
def initialize(obj="tmp",lchain=[],end_slice=false,belong_to_module=nil)
|
13
|
+
@belong_to_module=belong_to_module
|
13
14
|
@obj = obj
|
14
15
|
if !end_slice
|
15
16
|
if lchain.is_a? Array
|
@@ -25,48 +26,19 @@ module TdlSpace
|
|
25
26
|
else
|
26
27
|
raise TdlError.new("数组下标类型出错")
|
27
28
|
end
|
29
|
+
|
30
|
+
unless @belong_to_module
|
31
|
+
raise TdlError.new "ArrayChain<#{obj.to_s}> 必须添加 belong_to_module"
|
32
|
+
end
|
28
33
|
end
|
29
34
|
|
30
|
-
|
31
|
-
|
32
|
-
|
33
|
-
|
34
|
-
|
35
|
-
|
36
|
-
|
37
|
-
# end
|
38
|
-
|
39
|
-
# if @end_slice
|
40
|
-
# raise TdlError.new("数组下标已经被用片选[#{@end_slice[0]},#{@end_slice[1]}]终结")
|
41
|
-
# end
|
42
|
-
# RedefOpertor.with_normal_operators do
|
43
|
-
# unless b
|
44
|
-
# ArrayChain.new(obj,chain+[a])
|
45
|
-
# else
|
46
|
-
# # ArrayChain.new(&obj,chain,[a,b])
|
47
|
-
# @end_slice = [a,b]
|
48
|
-
# self
|
49
|
-
# end
|
50
|
-
# end
|
51
|
-
# end
|
52
|
-
|
53
|
-
# def to_s
|
54
|
-
# RedefOpertor.with_normal_operators do
|
55
|
-
# str = ""
|
56
|
-
# chain.each do |e|
|
57
|
-
# unless e.is_a? ArrayChainSignalMethod
|
58
|
-
# str += "[#{e.to_s}]"
|
59
|
-
# else
|
60
|
-
# str += ".#{e.name.to_s}"
|
61
|
-
# end
|
62
|
-
# end
|
63
|
-
# if @end_slice
|
64
|
-
# str += "[#{@end_slice[0]}:#{@end_slice[1]}]"
|
65
|
-
# end
|
66
|
-
|
67
|
-
# "#{obj.to_s}#{str}".to_nq
|
68
|
-
# end
|
69
|
-
# end
|
35
|
+
def self.create(obj: "tmp",lchain: [],end_slice: false,belong_to_module: nil)
|
36
|
+
ArrayChain.new(obj, lchain, end_slice, belong_to_module)
|
37
|
+
end
|
38
|
+
|
39
|
+
def root_ref(&block)
|
40
|
+
"#{belong_to_module.root_ref(&block)}.#{to_s}".to_nq
|
41
|
+
end
|
70
42
|
|
71
43
|
def inspect
|
72
44
|
self.to_s
|
@@ -86,9 +58,7 @@ module TdlSpace
|
|
86
58
|
end
|
87
59
|
## 判断 obj是否响应方法
|
88
60
|
if @obj.respond_to?(method) && !method.to_s.eql?("inst_name")
|
89
|
-
|
90
|
-
# ArrayChain.new(@obj.to_s,lchain=@chain.dup.concat([ArrayChainSignalMethod.new(method)]))
|
91
|
-
ArrayChain.new(@obj,lchain=@chain.dup.concat([ArrayChainSignalMethod.new(method)]))
|
61
|
+
ArrayChain.create(obj: @obj,lchain:@chain.dup.concat([ArrayChainSignalMethod.new(method)]) ,belong_to_module: belong_to_module)
|
92
62
|
else
|
93
63
|
|
94
64
|
# raise TdlError.new("ArrayChain 没有末尾方法 #{method} #{arg}")
|
@@ -212,7 +182,7 @@ class BaseElm < AxiTdl::SdlModuleActiveBaseElm
|
|
212
182
|
|
213
183
|
@_array_chain_hash_[name.to_s] = rel
|
214
184
|
end
|
215
|
-
TdlSpace::ArrayChain.
|
185
|
+
TdlSpace::ArrayChain.create(obj: @_array_chain_hash_[name.to_s],lchain:[],belong_to_module: self.belong_to_module)
|
216
186
|
end
|
217
187
|
end
|
218
188
|
end
|
@@ -484,7 +454,7 @@ class InfElm
|
|
484
454
|
|
485
455
|
return signal if @dimension.empty?
|
486
456
|
|
487
|
-
TdlSpace::ArrayChain.
|
457
|
+
TdlSpace::ArrayChain.create(obj: self,lchain: a, end_slice: b, belong_to_module: belong_to_module)
|
488
458
|
end
|
489
459
|
|
490
460
|
def self.same_name_socket(way,mix,inf_array,base_new_inf=nil,belong_to_module=nil)
|