axi_tdl 0.1.0 → 0.1.8

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Files changed (146) hide show
  1. checksums.yaml +4 -4
  2. data/Rakefile +7 -0
  3. data/lib/axi/AXI4/axi4_direct_A1.sv +1 -1
  4. data/lib/axi/AXI4/axi4_direct_verc.sv +54 -54
  5. data/lib/axi/AXI4/axi4_dpram_cache.rb +1 -0
  6. data/lib/axi/AXI4/axi4_dpram_cache.sv +10 -10
  7. data/lib/axi/AXI4/axi4_rd_burst_track.sv +2 -1
  8. data/lib/axi/AXI4/axi4_wr_burst_track.sv +2 -1
  9. data/lib/axi/AXI4/axis_to_axi4_wr.sv +9 -9
  10. data/lib/axi/AXI4/odata_pool_axi4_A3.sv +7 -0
  11. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +5 -5
  12. data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +8 -4
  13. data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +6 -6
  14. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +12 -12
  15. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +154 -0
  16. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +242 -0
  17. data/lib/axi/AXI_stream/axis_insert_copy.sv +79 -0
  18. data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +48 -0
  19. data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +113 -0
  20. data/lib/axi/AXI_stream/axis_sim_master_model.rb +2 -0
  21. data/lib/axi/AXI_stream/axis_sim_master_model.sv +46 -0
  22. data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
  23. data/lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv +50 -0
  24. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +2 -0
  25. data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +5 -3
  26. data/lib/axi/common/common_ram_sim_wrapper.sv +1 -1
  27. data/lib/axi/common/common_ram_wrapper.sv +1 -1
  28. data/lib/axi/common/test_write_mem.sv +1 -1
  29. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +13 -13
  30. data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +14 -11
  31. data/lib/axi/platform_ip/fifo_36kb_long.sv +1 -1
  32. data/lib/axi/platform_ip/long_fifo_verb.sv +1 -1
  33. data/lib/axi/platform_ip/wide_fifo.sv +1 -1
  34. data/lib/axi/platform_ip/xilinx_fifo_verb.sv +1 -1
  35. data/lib/axi/platform_ip/xilinx_fifo_verc.sv +2 -1
  36. data/lib/axi/techbench/tb_axi_stream_split_channel.rb +2 -1
  37. data/lib/axi/techbench/tb_axi_stream_split_channel.sv +46 -45
  38. data/lib/axi_tdl.rb +31 -1
  39. data/lib/axi_tdl/version.rb +1 -1
  40. data/lib/public_atom_module/CheckPClock.sv +53 -0
  41. data/lib/public_atom_module/LICENSE.md +674 -0
  42. data/lib/public_atom_module/altera_xilinx_always_block_sw.rb +57 -0
  43. data/lib/public_atom_module/bits_decode.sv +71 -0
  44. data/lib/public_atom_module/bits_decode_verb.sv +71 -0
  45. data/lib/public_atom_module/bits_decode_verb_sdl.rb +24 -0
  46. data/lib/public_atom_module/broaden.v +43 -0
  47. data/lib/public_atom_module/broaden_and_cross_clk.v +47 -0
  48. data/lib/public_atom_module/ceiling.v +39 -0
  49. data/lib/public_atom_module/ceiling_A1.v +42 -0
  50. data/lib/public_atom_module/clock_rst.sv +64 -0
  51. data/lib/public_atom_module/cross_clk_sync.v +37 -0
  52. data/lib/public_atom_module/edge_generator.v +50 -0
  53. data/lib/public_atom_module/flooring.v +36 -0
  54. data/lib/public_atom_module/latch_data.v +30 -0
  55. data/lib/public_atom_module/latency.v +48 -0
  56. data/lib/public_atom_module/latency_dynamic.v +83 -0
  57. data/lib/public_atom_module/latency_long.v +84 -0
  58. data/lib/public_atom_module/latency_verb.v +52 -0
  59. data/lib/public_atom_module/once_event.sv +65 -0
  60. data/lib/public_atom_module/pipe_reg.v +93 -0
  61. data/lib/public_atom_module/pipe_reg_2write_ports.v +84 -0
  62. data/lib/public_atom_module/sim/clock_rst_verb.sv +54 -0
  63. data/lib/public_atom_module/sim/clock_rst_verc.sv +69 -0
  64. data/lib/public_atom_module/sim/latency_long_tb.sv +49 -0
  65. data/lib/public_atom_module/sim/latency_long_tb.sv.bak +49 -0
  66. data/lib/public_atom_module/sim_system_pkg.sv +4 -0
  67. data/lib/public_atom_module/synth_system_pkg.sv +4 -0
  68. data/lib/tdl/Logic/logic_edge.rb +1 -1
  69. data/lib/tdl/auto_script/autogensdl.rb +2 -3
  70. data/lib/tdl/auto_script/import_hdl.rb +40 -5
  71. data/lib/tdl/axi4/axi4_interconnect_verb.rb +47 -10
  72. data/lib/tdl/class_hdl/hdl_always_comb.rb +4 -1
  73. data/lib/tdl/class_hdl/hdl_always_ff.rb +3 -3
  74. data/lib/tdl/class_hdl/hdl_assign.rb +7 -1
  75. data/lib/tdl/class_hdl/hdl_block_ifelse.rb +7 -7
  76. data/lib/tdl/class_hdl/hdl_foreach.rb +2 -2
  77. data/lib/tdl/class_hdl/hdl_function.rb +4 -4
  78. data/lib/tdl/class_hdl/hdl_generate.rb +5 -2
  79. data/lib/tdl/class_hdl/hdl_initial.rb +25 -3
  80. data/lib/tdl/class_hdl/hdl_module_def.rb +9 -6
  81. data/lib/tdl/class_hdl/hdl_package.rb +45 -0
  82. data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +99 -27
  83. data/lib/tdl/class_hdl/hdl_struct.rb +2 -2
  84. data/lib/tdl/elements/Reset.rb +5 -9
  85. data/lib/tdl/elements/clock.rb +5 -9
  86. data/lib/tdl/elements/data_inf.rb +0 -17
  87. data/lib/tdl/elements/logic.rb +9 -31
  88. data/lib/tdl/elements/mail_box.rb +6 -1
  89. data/lib/tdl/elements/originclass.rb +17 -47
  90. data/lib/tdl/elements/parameter.rb +5 -6
  91. data/lib/tdl/examples/11_test_unit/dve.tcl +6 -153
  92. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +2 -2
  93. data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +9 -0
  94. data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +2 -2
  95. data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +2 -2
  96. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -1
  97. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +41 -0
  98. data/lib/tdl/examples/11_test_unit/tu0.sv +2 -1
  99. data/lib/tdl/examples/1_define_module/exmple_md.sv +1 -1
  100. data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +3 -3
  101. data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +3 -3
  102. data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +3 -3
  103. data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +1 -1
  104. data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +3 -3
  105. data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +3 -3
  106. data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +1 -1
  107. data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +3 -3
  108. data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +2 -2
  109. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +7 -7
  110. data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +4 -3
  111. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
  112. data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +2 -2
  113. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +1 -1
  114. data/lib/tdl/examples/6_module_with_interface/example_interface.sv +8 -8
  115. data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +9 -9
  116. data/lib/tdl/examples/7_module_with_package/body_package.sv +4 -3
  117. data/lib/tdl/examples/7_module_with_package/example_pkg.sv +1 -1
  118. data/lib/tdl/examples/7_module_with_package/head_package.sv +4 -3
  119. data/lib/tdl/examples/8_top_module/dve.tcl +6 -0
  120. data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -1
  121. data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +29 -0
  122. data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
  123. data/lib/tdl/examples/8_top_module/test_top_sim.sv +9 -0
  124. data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +2 -1
  125. data/lib/tdl/examples/9_itegration/dve.tcl +155 -2
  126. data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +1 -1
  127. data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +1 -1
  128. data/lib/tdl/examples/9_itegration/test_tttop.sv +7 -38
  129. data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +38 -7
  130. data/lib/tdl/exlib/axis_verify.rb +4 -3
  131. data/lib/tdl/exlib/constraints_verb.rb +1 -0
  132. data/lib/tdl/exlib/itegration_verb.rb +47 -41
  133. data/lib/tdl/rebuild_ele/ele_base.rb +15 -10
  134. data/lib/tdl/sdlmodule/sdlmodule.rb +117 -51
  135. data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +1 -1
  136. data/lib/tdl/sdlmodule/sdlmodule_draw.rb +2 -2
  137. data/lib/tdl/sdlmodule/sdlmodule_instance.rb +3 -0
  138. data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +6 -6
  139. data/lib/tdl/sdlmodule/sdlmodule_varible.rb +6 -6
  140. data/lib/tdl/sdlmodule/test_unit_module.rb +6 -0
  141. data/lib/tdl/sdlmodule/top_module.rb +4 -0
  142. data/lib/tdl/tdl.rb +1 -11
  143. data/lib/tdl/tdlerror/tdlerror.rb +1 -1
  144. metadata +43 -5
  145. data/CODE_OF_CONDUCT.md +0 -74
  146. data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +0 -87
data/lib/tdl/elements/parameter.rb CHANGED
@@ -6,7 +6,7 @@ class Parameter < BaseElm
6
6
  include BaseModule
7
7
  attr_accessor :name,:value,:id,:ghost,:type,:vcs_string
8
8
 
9
- def initialize(name: "P",value:100,local:false,port:false,show:true,type:nil)
9
+ def initialize(name: "P",value:100,local:false,port:false,show:true,type:nil,belong_to_module: nil)
10
10
  @name = name
11
11
  @local = local
12
12
  # @id = GlobalParam.CurrTdlModule.BindEleClassVars.Parameter.id
@@ -14,11 +14,10 @@ class Parameter < BaseElm
14
14
  @show = show
15
15
  @value = value
16
16
  @type = type
17
- # if @port
18
- # GlobalParam.CurrTdlModule.BindEleClassVars.Parameter.ports << self
19
- # else
20
- # GlobalParam.CurrTdlModule.BindEleClassVars.Parameter.inst_stack << method(:inst)
21
- # end
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+ @belong_to_module = belong_to_module
18
+ unless @belong_to_module
19
+ raise TdlError.new("Parameter<#{name}> dnot have belong_to_module")
20
+ end
22
21
  end
23
22
 
24
23
  def inst
data/lib/tdl/examples/11_test_unit/dve.tcl CHANGED
@@ -12,128 +12,8 @@ gui_set_time_units 1ps
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12
  ## gui_sg_addsignal -group "$_wave_session_group" { {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.test_fpga_version_inst.ctrl_udp_rd_version} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.to_ctrl_tap_in_inf} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf} {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.tcp_udp_proto_workshop_1G_inst.genblk1[0].tcp_data_stack_top_inst.client_port} }
13
13
  ## ==== [add_signal] ===== ##
14
14
 
15
- ## -------------- sub_md0_logic -------------------------
16
- set _wave_session_group_sub_md0_logic sub_md0_logic
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- # set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name -seed sub_md0_logic]
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- if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_logic"]} {
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- set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name]
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- }
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- set Group2_sub_md0_logic "$_wave_session_group_sub_md0_logic"
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-
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- ## 添加信号到 group
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- gui_sg_addsignal -group "$_wave_session_group_sub_md0_logic" { {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.cnt} }
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- ## ============== sub_md0_logic =========================
26
-
27
-
28
- ## -------------- sub_md0_interface -------------------------
29
- set _wave_session_group_sub_md0_interface sub_md0_interface
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- # set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name -seed sub_md0_interface]
31
- if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_interface"]} {
32
- set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name]
33
- }
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- set Group2_sub_md0_interface "$_wave_session_group_sub_md0_interface"
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-
36
- ## 添加信号到 group
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- gui_sg_addsignal -group "$_wave_session_group_sub_md0_interface" { {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.axis_in} }
38
- ## ============== sub_md0_interface =========================
39
-
40
-
41
- ## -------------- sub_md0_default -------------------------
42
- set _wave_session_group_sub_md0_default sub_md0_default
43
- # set _wave_session_group_sub_md0_default [gui_sg_generate_new_name -seed sub_md0_default]
44
- if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_default"]} {
45
- set _wave_session_group_sub_md0_default [gui_sg_generate_new_name]
46
- }
47
- set Group2_sub_md0_default "$_wave_session_group_sub_md0_default"
48
-
49
- ## 添加信号到 group
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- gui_sg_addsignal -group "$_wave_session_group_sub_md0_default" { }
51
- ## ============== sub_md0_default =========================
52
-
53
-
54
- ## -------------- sub_md0_default.inter_tf -------------------------
55
- ## set _wave_session_group_sub_md0_default_inter_tf Group1
56
- ## set _wave_session_group_sub_md0_default_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md0_default ]
57
15
 
58
- set _wave_session_group_sub_md0_default_inter_tf $_wave_session_group_sub_md0_default|
59
- append _wave_session_group_sub_md0_default_inter_tf inter_tf
60
- set sub_md0_default|inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
61
-
62
- # set Group2_sub_md0_default_inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
63
-
64
- ## 添加信号到 group
65
- gui_sg_addsignal -group "$_wave_session_group_sub_md0_default_inter_tf" { {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.inter_tf} }
66
- ## ============== sub_md0_default.inter_tf =========================
67
-
68
-
69
- ## -------------- sub_md1_default -------------------------
70
- set _wave_session_group_sub_md1_default sub_md1_default
71
- # set _wave_session_group_sub_md1_default [gui_sg_generate_new_name -seed sub_md1_default]
72
- if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_default"]} {
73
- set _wave_session_group_sub_md1_default [gui_sg_generate_new_name]
74
- }
75
- set Group2_sub_md1_default "$_wave_session_group_sub_md1_default"
76
-
77
- ## 添加信号到 group
78
- gui_sg_addsignal -group "$_wave_session_group_sub_md1_default" { {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.cnt} {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.axis_out} {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.enable} }
79
- ## ============== sub_md1_default =========================
80
-
81
-
82
- ## -------------- sub_md1_inner -------------------------
83
- set _wave_session_group_sub_md1_inner sub_md1_inner
84
- # set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name -seed sub_md1_inner]
85
- if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_inner"]} {
86
- set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name]
87
- }
88
- set Group2_sub_md1_inner "$_wave_session_group_sub_md1_inner"
89
-
90
- ## 添加信号到 group
91
- gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner" { }
92
- ## ============== sub_md1_inner =========================
93
-
94
16
 
95
- ## -------------- sub_md1_inner.inter_tf -------------------------
96
- ## set _wave_session_group_sub_md1_inner_inter_tf Group1
97
- ## set _wave_session_group_sub_md1_inner_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md1_inner ]
98
-
99
- set _wave_session_group_sub_md1_inner_inter_tf $_wave_session_group_sub_md1_inner|
100
- append _wave_session_group_sub_md1_inner_inter_tf inter_tf
101
- set sub_md1_inner|inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
102
-
103
- # set Group2_sub_md1_inner_inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
104
-
105
- ## 添加信号到 group
106
- gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner_inter_tf" { {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.inter_tf} }
107
- ## ============== sub_md1_inner.inter_tf =========================
108
-
109
-
110
- ## -------------- exp_test_unit_default -------------------------
111
- set _wave_session_group_exp_test_unit_default exp_test_unit_default
112
- # set _wave_session_group_exp_test_unit_default [gui_sg_generate_new_name -seed exp_test_unit_default]
113
- if {[gui_sg_is_group -name "$_wave_session_group_exp_test_unit_default"]} {
114
- set _wave_session_group_exp_test_unit_default [gui_sg_generate_new_name]
115
- }
116
- set Group2_exp_test_unit_default "$_wave_session_group_exp_test_unit_default"
117
-
118
- ## 添加信号到 group
119
- gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_default" { }
120
- ## ============== exp_test_unit_default =========================
121
-
122
-
123
- ## -------------- exp_test_unit_default.axis_data_inf -------------------------
124
- ## set _wave_session_group_exp_test_unit_default_axis_data_inf Group1
125
- ## set _wave_session_group_exp_test_unit_default_axis_data_inf [gui_sg_generate_new_name -seed axis_data_inf -parent $_wave_session_group_exp_test_unit_default ]
126
-
127
- set _wave_session_group_exp_test_unit_default_axis_data_inf $_wave_session_group_exp_test_unit_default|
128
- append _wave_session_group_exp_test_unit_default_axis_data_inf axis_data_inf
129
- set exp_test_unit_default|axis_data_inf "$_wave_session_group_exp_test_unit_default_axis_data_inf"
130
-
131
- # set Group2_exp_test_unit_default_axis_data_inf "$_wave_session_group_exp_test_unit_default_axis_data_inf"
132
-
133
- ## 添加信号到 group
134
- gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_default_axis_data_inf" { {Sim:tb_exp_test_unit.rtl_top.axis_data_inf} }
135
- ## ============== exp_test_unit_default.axis_data_inf =========================
136
-
137
17
 
138
18
  ## 创建波形窗口
139
19
  if {![info exists useOldWindow]} {
@@ -162,33 +42,9 @@ gui_wv_zoom_timerange -id ${Wave.3} 0 1000000000
162
42
  ## gui_list_add_group -id ${Wave.3} -after ${Group2} [list ${Group2|tx_inf}]
163
43
  ## gui_list_expand -id ${Wave.3} tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf
164
44
  ## === [add_signal_wave] === ##
165
- ## -------------- Group2_sub_md0_logic -------------------------
166
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_logic}]
167
- ## ============== Group2_sub_md0_logic =========================
168
- ## -------------- Group2_sub_md0_interface -------------------------
169
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_interface}]
170
- ## ============== Group2_sub_md0_interface =========================
171
- ## -------------- Group2_sub_md0_default -------------------------
172
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_default}]
173
- ## ============== Group2_sub_md0_default =========================
174
- ## -------------- sub_md0_default|inter_tf -------------------------
175
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md0_default|inter_tf}]
176
- ## ============== sub_md0_default|inter_tf =========================
177
- ## -------------- Group2_sub_md1_default -------------------------
178
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_default}]
179
- ## ============== Group2_sub_md1_default =========================
180
- ## -------------- Group2_sub_md1_inner -------------------------
181
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_inner}]
182
- ## ============== Group2_sub_md1_inner =========================
183
- ## -------------- sub_md1_inner|inter_tf -------------------------
184
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md1_inner|inter_tf}]
185
- ## ============== sub_md1_inner|inter_tf =========================
186
- ## -------------- Group2_exp_test_unit_default -------------------------
187
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_exp_test_unit_default}]
188
- ## ============== Group2_exp_test_unit_default =========================
189
- ## -------------- exp_test_unit_default|axis_data_inf -------------------------
190
- gui_list_add_group -id ${Wave.3} -after {New Group} [list ${exp_test_unit_default|axis_data_inf}]
191
- ## ============== exp_test_unit_default|axis_data_inf =========================
45
+
46
+
47
+
192
48
 
193
49
  gui_seek_criteria -id ${Wave.3} {Any Edge}
194
50
 
@@ -205,12 +61,9 @@ gui_list_set_filter -id ${Wave.3} -list { {Buffer 1} {Input 1} {Others 1} {Linka
205
61
  gui_list_set_filter -id ${Wave.3} -text {*}
206
62
  ##gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2} -position in
207
63
  ## === [add_bar] === ##
208
- gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_logic} -position in
209
- gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_interface} -position in
210
- gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_default} -position in
211
- gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md1_default} -position in
212
- gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md1_inner} -position in
213
- gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_exp_test_unit_default} -position in
64
+
65
+
66
+
214
67
 
215
68
  gui_marker_move -id ${Wave.3} {C1} 560248001
216
69
  gui_view_scroll -id ${Wave.3} -vertical -set 35
data/lib/tdl/examples/11_test_unit/exp_test_unit.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: 2021-03-20 12:08:01 +0800
8
+ created: 2021-05-04 20:03:48 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -18,7 +18,7 @@ module exp_test_unit (
18
18
  //==========================================================================
19
19
  //-------- define ----------------------------------------------------------
20
20
  logic enable;
21
- axi_stream_inf #(.DSIZE(8),.USIZE(1)) axis_data_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
21
+ axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) axis_data_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
22
22
  //==========================================================================
23
23
  //-------- instance --------------------------------------------------------
24
24
  sub_md1 sub_md1_inst(
data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv ADDED
@@ -0,0 +1,9 @@
1
+
2
+ `timescale 1ns/1ps
3
+ module exp_test_unit_sim();
4
+ initial begin
5
+ #(1us);
6
+ $warning("Check TopModule.sim,please!!!");
7
+ $stop;
8
+ end
9
+ endmodule
data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: 2021-03-20 12:08:00 +0800
8
+ created: 2021-05-04 20:03:33 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -20,7 +20,7 @@ module sub_md0 (
20
20
  logic clock;
21
21
  logic rst_n;
22
22
  logic [10-1:0] cnt ;
23
- data_inf_c #(.DSIZE(8)) inter_tf (.clock(clock),.rst_n(rst_n)) ;
23
+ data_inf_c #(.DSIZE(8),.FreqM(axis_in.FreqM)) inter_tf (.clock(clock),.rst_n(rst_n)) ;
24
24
  //==========================================================================
25
25
  //-------- instance --------------------------------------------------------
26
26
 
data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: 2021-03-20 12:08:00 +0800
8
+ created: 2021-05-04 20:03:33 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -20,7 +20,7 @@ module sub_md1 (
20
20
  logic clock;
21
21
  logic rst_n;
22
22
  logic [10-1:0] cnt ;
23
- data_inf_c #(.DSIZE(8)) inter_tf (.clock(clock),.rst_n(rst_n)) ;
23
+ data_inf_c #(.DSIZE(8),.FreqM(axis_out.FreqM)) inter_tf (.clock(clock),.rst_n(rst_n)) ;
24
24
  //==========================================================================
25
25
  //-------- instance --------------------------------------------------------
26
26
 
data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: 2021-03-20 12:08:01 +0800
8
+ created: 2021-05-04 20:03:48 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv ADDED
@@ -0,0 +1,41 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ created: 2021-04-03 14:05:10 +0800
9
+ madified:
10
+ ***********************************************/
11
+ `timescale 1ns/1ps
12
+
13
+ module tb_exp_test_unit_sim();
14
+ //==========================================================================
15
+ //-------- define ----------------------------------------------------------
16
+ logic sys_clk;
17
+ string test_unit_region;
18
+ logic [2-1:0] unit_pass_u ;
19
+ logic [2-1:0] unit_pass_d ;
20
+
21
+ //==========================================================================
22
+ //-------- instance --------------------------------------------------------
23
+ exp_test_unit_sim rtl_top(
24
+ /* input clock */.clock (sys_clk ),
25
+ /* input reset */.rst_n (1'b1 )
26
+ );
27
+ tu0 test_unit_0(
28
+ /* input */.from_up_pass (unit_pass_u[0] ),
29
+ /* output */.to_down_pass (unit_pass_d[0] )
30
+ );
31
+ tu1 test_unit_1(
32
+ /* input */.from_up_pass (unit_pass_u[1] ),
33
+ /* output */.to_down_pass (unit_pass_d[1] )
34
+ );
35
+ //==========================================================================
36
+ //-------- expression ------------------------------------------------------
37
+ assign unit_pass_u[0] = 1'b1;
38
+
39
+ assign unit_pass_u[1] = unit_pass_d[0];
40
+
41
+ endmodule
data/lib/tdl/examples/11_test_unit/tu0.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: 2021-03-20 12:08:00 +0800
8
+ created: 2021-05-04 20:03:48 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -28,6 +28,7 @@ initial begin
28
28
  to_down_pass = 1'b0;
29
29
  wait(from_up_pass);
30
30
  $root.tb_exp_test_unit.test_unit_region = "tu0";
31
+ $display("--------------- Current test_unit <%0s> --------------------", "tu0");
31
32
  $root.tb_exp_test_unit.rtl_top.sub_md1_inst.enable = 1'b1;
32
33
  #(1us);
33
34
  $root.tb_exp_test_unit.rtl_top.sub_md1_inst.enable = 1'b0;
data/lib/tdl/examples/1_define_module/exmple_md.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-03-29 17:23:25 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-05-04 20:03:33 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -15,8 +15,8 @@ module always_comb_test ();
15
15
  //-------- define ----------------------------------------------------------
16
16
  logic [1-1:0] tmp0[9-1:0][2-1:0] ;
17
17
  logic tmp1;
18
- data_inf_c #(.DSIZE(8)) a_inf (.clock(dclk),.rst_n(drstn)) ;
19
- data_inf_c #(.DSIZE(18)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
18
+ data_inf_c #(.DSIZE(8),.FreqM(101)) a_inf (.clock(dclk),.rst_n(drstn)) ;
19
+ data_inf_c #(.DSIZE(18),.FreqM(101)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
20
20
  //==========================================================================
21
21
  //-------- instance --------------------------------------------------------
22
22
 
data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-05-04 20:03:32 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -21,8 +21,8 @@ module always_ff_test (
21
21
  //-------- define ----------------------------------------------------------
22
22
  logic [1-1:0] tmp0[9-1:0][2-1:0] ;
23
23
  logic tmp1;
24
- data_inf_c #(.DSIZE(8)) a_inf (.clock(dclk),.rst_n(drstn)) ;
25
- data_inf_c #(.DSIZE(8)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
24
+ data_inf_c #(.DSIZE(8),.FreqM(101)) a_inf (.clock(dclk),.rst_n(drstn)) ;
25
+ data_inf_c #(.DSIZE(8),.FreqM(101)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
26
26
  //==========================================================================
27
27
  //-------- instance --------------------------------------------------------
28
28
 
data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-05-04 20:03:33 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -21,8 +21,8 @@ module case_test (
21
21
  //-------- define ----------------------------------------------------------
22
22
  logic [1-1:0] tmp0[9-1:0][2-1:0] ;
23
23
  logic tmp1;
24
- data_inf_c #(.DSIZE(8)) a_inf (.clock(dclk),.rst_n(drstn)) ;
25
- data_inf_c #(.DSIZE(8)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
24
+ data_inf_c #(.DSIZE(8),.FreqM(101)) a_inf (.clock(dclk),.rst_n(drstn)) ;
25
+ data_inf_c #(.DSIZE(8),.FreqM(101)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
26
26
  //==========================================================================
27
27
  //-------- instance --------------------------------------------------------
28
28
 
data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-04-03 13:47:03 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-05-04 20:03:33 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -15,8 +15,8 @@ module simple_assign_test ();
15
15
  //-------- define ----------------------------------------------------------
16
16
  logic [1-1:0] tmp0[9-1:0][2-1:0] ;
17
17
  logic tmp1;
18
- data_inf_c #(.DSIZE(8)) a_inf (.clock(dclk),.rst_n(drstn)) ;
19
- data_inf_c #(.DSIZE(8)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
18
+ data_inf_c #(.DSIZE(8),.FreqM(101)) a_inf (.clock(dclk),.rst_n(drstn)) ;
19
+ data_inf_c #(.DSIZE(8),.FreqM(101)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
20
20
  //==========================================================================
21
21
  //-------- instance --------------------------------------------------------
22
22
 
data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-05-04 20:03:32 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -21,8 +21,8 @@ module state_case_test (
21
21
  //-------- define ----------------------------------------------------------
22
22
  logic [1-1:0] tmp0[9-1:0][2-1:0] ;
23
23
  logic tmp1;
24
- data_inf_c #(.DSIZE(8)) a_inf (.clock(dclk),.rst_n(drstn)) ;
25
- data_inf_c #(.DSIZE(8)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
24
+ data_inf_c #(.DSIZE(8),.FreqM(101)) a_inf (.clock(dclk),.rst_n(drstn)) ;
25
+ data_inf_c #(.DSIZE(8),.FreqM(101)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
26
26
  //==========================================================================
27
27
  //-------- instance --------------------------------------------------------
28
28