axi_tdl 0.1.0 → 0.1.8

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Files changed (146) hide show
  1. checksums.yaml +4 -4
  2. data/Rakefile +7 -0
  3. data/lib/axi/AXI4/axi4_direct_A1.sv +1 -1
  4. data/lib/axi/AXI4/axi4_direct_verc.sv +54 -54
  5. data/lib/axi/AXI4/axi4_dpram_cache.rb +1 -0
  6. data/lib/axi/AXI4/axi4_dpram_cache.sv +10 -10
  7. data/lib/axi/AXI4/axi4_rd_burst_track.sv +2 -1
  8. data/lib/axi/AXI4/axi4_wr_burst_track.sv +2 -1
  9. data/lib/axi/AXI4/axis_to_axi4_wr.sv +9 -9
  10. data/lib/axi/AXI4/odata_pool_axi4_A3.sv +7 -0
  11. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +5 -5
  12. data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +8 -4
  13. data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +6 -6
  14. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +12 -12
  15. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +154 -0
  16. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +242 -0
  17. data/lib/axi/AXI_stream/axis_insert_copy.sv +79 -0
  18. data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +48 -0
  19. data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +113 -0
  20. data/lib/axi/AXI_stream/axis_sim_master_model.rb +2 -0
  21. data/lib/axi/AXI_stream/axis_sim_master_model.sv +46 -0
  22. data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
  23. data/lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv +50 -0
  24. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +2 -0
  25. data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +5 -3
  26. data/lib/axi/common/common_ram_sim_wrapper.sv +1 -1
  27. data/lib/axi/common/common_ram_wrapper.sv +1 -1
  28. data/lib/axi/common/test_write_mem.sv +1 -1
  29. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +13 -13
  30. data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +14 -11
  31. data/lib/axi/platform_ip/fifo_36kb_long.sv +1 -1
  32. data/lib/axi/platform_ip/long_fifo_verb.sv +1 -1
  33. data/lib/axi/platform_ip/wide_fifo.sv +1 -1
  34. data/lib/axi/platform_ip/xilinx_fifo_verb.sv +1 -1
  35. data/lib/axi/platform_ip/xilinx_fifo_verc.sv +2 -1
  36. data/lib/axi/techbench/tb_axi_stream_split_channel.rb +2 -1
  37. data/lib/axi/techbench/tb_axi_stream_split_channel.sv +46 -45
  38. data/lib/axi_tdl.rb +31 -1
  39. data/lib/axi_tdl/version.rb +1 -1
  40. data/lib/public_atom_module/CheckPClock.sv +53 -0
  41. data/lib/public_atom_module/LICENSE.md +674 -0
  42. data/lib/public_atom_module/altera_xilinx_always_block_sw.rb +57 -0
  43. data/lib/public_atom_module/bits_decode.sv +71 -0
  44. data/lib/public_atom_module/bits_decode_verb.sv +71 -0
  45. data/lib/public_atom_module/bits_decode_verb_sdl.rb +24 -0
  46. data/lib/public_atom_module/broaden.v +43 -0
  47. data/lib/public_atom_module/broaden_and_cross_clk.v +47 -0
  48. data/lib/public_atom_module/ceiling.v +39 -0
  49. data/lib/public_atom_module/ceiling_A1.v +42 -0
  50. data/lib/public_atom_module/clock_rst.sv +64 -0
  51. data/lib/public_atom_module/cross_clk_sync.v +37 -0
  52. data/lib/public_atom_module/edge_generator.v +50 -0
  53. data/lib/public_atom_module/flooring.v +36 -0
  54. data/lib/public_atom_module/latch_data.v +30 -0
  55. data/lib/public_atom_module/latency.v +48 -0
  56. data/lib/public_atom_module/latency_dynamic.v +83 -0
  57. data/lib/public_atom_module/latency_long.v +84 -0
  58. data/lib/public_atom_module/latency_verb.v +52 -0
  59. data/lib/public_atom_module/once_event.sv +65 -0
  60. data/lib/public_atom_module/pipe_reg.v +93 -0
  61. data/lib/public_atom_module/pipe_reg_2write_ports.v +84 -0
  62. data/lib/public_atom_module/sim/clock_rst_verb.sv +54 -0
  63. data/lib/public_atom_module/sim/clock_rst_verc.sv +69 -0
  64. data/lib/public_atom_module/sim/latency_long_tb.sv +49 -0
  65. data/lib/public_atom_module/sim/latency_long_tb.sv.bak +49 -0
  66. data/lib/public_atom_module/sim_system_pkg.sv +4 -0
  67. data/lib/public_atom_module/synth_system_pkg.sv +4 -0
  68. data/lib/tdl/Logic/logic_edge.rb +1 -1
  69. data/lib/tdl/auto_script/autogensdl.rb +2 -3
  70. data/lib/tdl/auto_script/import_hdl.rb +40 -5
  71. data/lib/tdl/axi4/axi4_interconnect_verb.rb +47 -10
  72. data/lib/tdl/class_hdl/hdl_always_comb.rb +4 -1
  73. data/lib/tdl/class_hdl/hdl_always_ff.rb +3 -3
  74. data/lib/tdl/class_hdl/hdl_assign.rb +7 -1
  75. data/lib/tdl/class_hdl/hdl_block_ifelse.rb +7 -7
  76. data/lib/tdl/class_hdl/hdl_foreach.rb +2 -2
  77. data/lib/tdl/class_hdl/hdl_function.rb +4 -4
  78. data/lib/tdl/class_hdl/hdl_generate.rb +5 -2
  79. data/lib/tdl/class_hdl/hdl_initial.rb +25 -3
  80. data/lib/tdl/class_hdl/hdl_module_def.rb +9 -6
  81. data/lib/tdl/class_hdl/hdl_package.rb +45 -0
  82. data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +99 -27
  83. data/lib/tdl/class_hdl/hdl_struct.rb +2 -2
  84. data/lib/tdl/elements/Reset.rb +5 -9
  85. data/lib/tdl/elements/clock.rb +5 -9
  86. data/lib/tdl/elements/data_inf.rb +0 -17
  87. data/lib/tdl/elements/logic.rb +9 -31
  88. data/lib/tdl/elements/mail_box.rb +6 -1
  89. data/lib/tdl/elements/originclass.rb +17 -47
  90. data/lib/tdl/elements/parameter.rb +5 -6
  91. data/lib/tdl/examples/11_test_unit/dve.tcl +6 -153
  92. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +2 -2
  93. data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +9 -0
  94. data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +2 -2
  95. data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +2 -2
  96. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -1
  97. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +41 -0
  98. data/lib/tdl/examples/11_test_unit/tu0.sv +2 -1
  99. data/lib/tdl/examples/1_define_module/exmple_md.sv +1 -1
  100. data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +3 -3
  101. data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +3 -3
  102. data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +3 -3
  103. data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +1 -1
  104. data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +3 -3
  105. data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +3 -3
  106. data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +1 -1
  107. data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +3 -3
  108. data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +2 -2
  109. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +7 -7
  110. data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +4 -3
  111. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
  112. data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +2 -2
  113. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +1 -1
  114. data/lib/tdl/examples/6_module_with_interface/example_interface.sv +8 -8
  115. data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +9 -9
  116. data/lib/tdl/examples/7_module_with_package/body_package.sv +4 -3
  117. data/lib/tdl/examples/7_module_with_package/example_pkg.sv +1 -1
  118. data/lib/tdl/examples/7_module_with_package/head_package.sv +4 -3
  119. data/lib/tdl/examples/8_top_module/dve.tcl +6 -0
  120. data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -1
  121. data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +29 -0
  122. data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
  123. data/lib/tdl/examples/8_top_module/test_top_sim.sv +9 -0
  124. data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +2 -1
  125. data/lib/tdl/examples/9_itegration/dve.tcl +155 -2
  126. data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +1 -1
  127. data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +1 -1
  128. data/lib/tdl/examples/9_itegration/test_tttop.sv +7 -38
  129. data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +38 -7
  130. data/lib/tdl/exlib/axis_verify.rb +4 -3
  131. data/lib/tdl/exlib/constraints_verb.rb +1 -0
  132. data/lib/tdl/exlib/itegration_verb.rb +47 -41
  133. data/lib/tdl/rebuild_ele/ele_base.rb +15 -10
  134. data/lib/tdl/sdlmodule/sdlmodule.rb +117 -51
  135. data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +1 -1
  136. data/lib/tdl/sdlmodule/sdlmodule_draw.rb +2 -2
  137. data/lib/tdl/sdlmodule/sdlmodule_instance.rb +3 -0
  138. data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +6 -6
  139. data/lib/tdl/sdlmodule/sdlmodule_varible.rb +6 -6
  140. data/lib/tdl/sdlmodule/test_unit_module.rb +6 -0
  141. data/lib/tdl/sdlmodule/top_module.rb +4 -0
  142. data/lib/tdl/tdl.rb +1 -11
  143. data/lib/tdl/tdlerror/tdlerror.rb +1 -1
  144. metadata +43 -5
  145. data/CODE_OF_CONDUCT.md +0 -74
  146. data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +0 -87
data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv ADDED
@@ -0,0 +1,48 @@
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+ /**********************************************
2
+ _______________________________________
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+ ___________ Cook Darwin __________
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+ _______________________________________
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+ descript:
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+ author : Cook.Darwin
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+ Version: VERA.0.0
8
+ created: 2021-04-16 17:01:05 +0800
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+ madified:
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+ ***********************************************/
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+ `timescale 1ns/1ps
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+
13
+ module axis_pipe_sync_seam #(
14
+ parameter LAT = 4,
15
+ parameter DSIZE = 32
16
+ )(
17
+ input [DSIZE-1:0] in_datas [LAT-1:0],
18
+ output [DSIZE-1:0] out_datas [LAT-1:0],
19
+ axi_stream_inf.slaver in_inf,
20
+ axi_stream_inf.master out_inf
21
+ );
22
+
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+ //==========================================================================
24
+ //-------- define ----------------------------------------------------------
25
+
26
+ data_inf_c #(.DSIZE(in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE),.FreqM(1.0)) data_in_inf (.clock(in_inf.aclk),.rst_n(in_inf.aresetn)) ;
27
+ data_inf_c #(.DSIZE(in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE),.FreqM(data_in_inf.FreqM)) data_out_inf (.clock(in_inf.aclk),.rst_n(in_inf.aresetn)) ;
28
+ //==========================================================================
29
+ //-------- instance --------------------------------------------------------
30
+ data_c_pipe_sync_seam #(
31
+ .LAT (LAT ),
32
+ .DSIZE (DSIZE )
33
+ )data_c_pipe_sync_seam_inst(
34
+ /* input */.in_datas (in_datas ),
35
+ /* output */.out_datas (out_datas ),
36
+ /* data_inf_c.slaver */.in_inf (data_in_inf ),
37
+ /* data_inf_c.master */.out_inf (data_out_inf )
38
+ );
39
+ //==========================================================================
40
+ //-------- expression ------------------------------------------------------
41
+ assign data_in_inf.data = {>>{in_inf.axis_tuser,in_inf.axis_tkeep,in_inf.axis_tlast,in_inf.axis_tdata}};
42
+ assign data_in_inf.valid = in_inf.axis_tvalid;
43
+ assign in_inf.axis_tready = data_in_inf.ready;
44
+ assign {out_inf.axis_tuser,out_inf.axis_tkeep,out_inf.axis_tlast,out_inf.axis_tdata} = data_out_inf.data;
45
+ assign out_inf.axis_tvalid = data_out_inf.valid;
46
+ assign data_out_inf.ready = out_inf.axis_tready;
47
+
48
+ endmodule
data/lib/axi/AXI_stream/axis_rom_contect_sim.sv ADDED
@@ -0,0 +1,113 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ created: 2021-04-16 17:01:02 +0800
9
+ madified:
10
+ ***********************************************/
11
+ `timescale 1ns/1ps
12
+
13
+ module axis_rom_contect_sim #(
14
+ parameter FNUM = 8,
15
+ parameter STEP = 1
16
+ )(
17
+ input [FNUM-1:0] load_files,
18
+ input [4095:0] init_files [FNUM-1:0],
19
+ axi_stream_inf.slaver a_axis_zip,
20
+ axi_stream_inf.slaver b_axis_zip,
21
+ axi_stream_inf.master a_rom_contect_inf,
22
+ axi_stream_inf.master b_rom_contect_inf
23
+ );
24
+
25
+ //==========================================================================
26
+ //-------- define ----------------------------------------------------------
27
+
28
+ axi_stream_inf #(.DSIZE((a_axis_zip.DSIZE / 2)),.FreqM(a_axis_zip.FreqM),.USIZE(1)) a_axis_unzip (.aclk(a_axis_zip.aclk),.aresetn(a_axis_zip.aresetn),.aclken(1'b1)) ;
29
+ axi_stream_inf #(.DSIZE((b_axis_zip.DSIZE / 2)),.FreqM(b_axis_zip.FreqM),.USIZE(1)) b_axis_unzip (.aclk(b_axis_zip.aclk),.aresetn(b_axis_zip.aresetn),.aclken(1'b1)) ;
30
+ cm_ram_inf #(.DSIZE(a_rom_contect_inf.DSIZE),.RSIZE(a_axis_zip.DSIZE),.MSIZE(1)) xram_inf();
31
+ axi_stream_inf #(.DSIZE(a_rom_contect_inf.DSIZE+(a_axis_zip.DSIZE / 2)),.FreqM(a_rom_contect_inf.FreqM),.USIZE(1)) a_rom_contect_inf_pre (.aclk(a_rom_contect_inf.aclk),.aresetn(a_rom_contect_inf.aresetn),.aclken(1'b1)) ;
32
+ axi_stream_inf #(.DSIZE(b_rom_contect_inf.DSIZE+(b_axis_zip.DSIZE / 2)),.FreqM(b_rom_contect_inf.FreqM),.USIZE(1)) b_rom_contect_inf_pre (.aclk(b_rom_contect_inf.aclk),.aresetn(b_rom_contect_inf.aresetn),.aclken(1'b1)) ;
33
+ //==========================================================================
34
+ //-------- instance --------------------------------------------------------
35
+ axis_uncompress_A1 #(
36
+ .ASIZE ((a_axis_zip.DSIZE / 2) ),
37
+ .LSIZE ((a_axis_zip.DSIZE / 2) ),
38
+ .STEP (STEP )
39
+ )axis_uncompress_A1_ainst(
40
+ /* axi_stream_inf.slaver */.axis_zip (a_axis_zip ),
41
+ /* axi_stream_inf.master */.axis_unzip (a_axis_unzip )
42
+ );
43
+ axis_uncompress_A1 #(
44
+ .ASIZE ((a_axis_zip.DSIZE / 2) ),
45
+ .LSIZE ((a_axis_zip.DSIZE / 2) ),
46
+ .STEP (STEP )
47
+ )axis_uncompress_A1_binst(
48
+ /* axi_stream_inf.slaver */.axis_zip (b_axis_zip ),
49
+ /* axi_stream_inf.master */.axis_unzip (b_axis_unzip )
50
+ );
51
+ common_ram_sim_wrapper #(
52
+ .FNUM (FNUM )
53
+ )common_ram_wrapper_sim_inst(
54
+ /* input */.load_files (load_files ),
55
+ /* input */.init_files (init_files ),
56
+ /* cm_ram_inf.slaver */.ram_inf (xram_inf )
57
+ );
58
+ axi_stream_planer #(
59
+ .LAT (3 ),
60
+ .DSIZE (a_rom_contect_inf.DSIZE ),
61
+ .HEAD ("FALSE" )
62
+ )axi_stream_planer_ainst(
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+ /* input */.reset (~a_axis_zip.aresetn ),
64
+ /* input */.pack_data (xram_inf.doa ),
65
+ /* axi_stream_inf.slaver */.axis_in (a_axis_unzip ),
66
+ /* axi_stream_inf.master */.axis_out (a_rom_contect_inf_pre )
67
+ );
68
+ axi_stream_planer #(
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+ .LAT (3 ),
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+ .DSIZE (b_rom_contect_inf.DSIZE ),
71
+ .HEAD ("FALSE" )
72
+ )axi_stream_planer_binst(
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+ /* input */.reset (~b_axis_zip.aresetn ),
74
+ /* input */.pack_data (xram_inf.dob ),
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+ /* axi_stream_inf.slaver */.axis_in (b_axis_unzip ),
76
+ /* axi_stream_inf.master */.axis_out (b_rom_contect_inf_pre )
77
+ );
78
+ //==========================================================================
79
+ //-------- expression ------------------------------------------------------
80
+ initial begin
81
+ assert(a_axis_zip.DSIZE==b_axis_zip.DSIZE)else begin
82
+ $error("a_axis_zip.DSIZE<%0d> must equal b_axis_zip.DSIZE<%0d>",a_axis_zip.DSIZE,b_axis_zip.DSIZE);
83
+ $stop;
84
+ end
85
+ assert(a_rom_contect_inf.DSIZE==b_rom_contect_inf.DSIZE)else begin
86
+ $error("a_rom_contect_inf.DSIZE<%0d>==b_rom_contect_inf.DSIZE<%0d>",a_rom_contect_inf.DSIZE,b_rom_contect_inf.DSIZE);
87
+ $stop;
88
+ end
89
+ end
90
+
91
+ assign xram_inf.addra = a_axis_unzip.axis_tdata;
92
+ assign xram_inf.dia = '0;
93
+ assign xram_inf.wea = '0;
94
+ assign xram_inf.ena = 1'b1;
95
+ assign xram_inf.clka = a_axis_zip.aclk;
96
+ assign xram_inf.rsta = ~a_axis_zip.aresetn;
97
+ assign xram_inf.addrb = b_axis_unzip.axis_tdata;
98
+ assign xram_inf.dib = '0;
99
+ assign xram_inf.web = '0;
100
+ assign xram_inf.enb = 1'b1;
101
+ assign xram_inf.clkb = b_axis_zip.aclk;
102
+ assign xram_inf.rstb = ~b_axis_zip.aresetn;
103
+
104
+ assign a_rom_contect_inf.axis_tdata = a_rom_contect_inf_pre.axis_tdata[a_rom_contect_inf.DSIZE-1:0];
105
+ assign a_rom_contect_inf.axis_tvalid = a_rom_contect_inf_pre.axis_tvalid;
106
+ assign a_rom_contect_inf.axis_tlast = a_rom_contect_inf_pre.axis_tlast;
107
+ assign a_rom_contect_inf_pre.axis_tready = a_rom_contect_inf.axis_tready;
108
+ assign b_rom_contect_inf.axis_tdata = b_rom_contect_inf_pre.axis_tdata[b_rom_contect_inf.DSIZE-1:0];
109
+ assign b_rom_contect_inf.axis_tvalid = b_rom_contect_inf_pre.axis_tvalid;
110
+ assign b_rom_contect_inf.axis_tlast = b_rom_contect_inf_pre.axis_tlast;
111
+ assign b_rom_contect_inf_pre.axis_tready = b_rom_contect_inf.axis_tready;
112
+
113
+ endmodule
data/lib/axi/AXI_stream/axis_sim_master_model.rb CHANGED
@@ -3,6 +3,7 @@ require_hdl 'data_c_sim_master_model.sv'
3
3
  TdlBuild.axis_sim_master_model(__dir__) do
4
4
  parameter.LOOP "TRUE"
5
5
  parameter.RAM_DEPTH 10000
6
+ input - 'enable'
6
7
  input - 'load_trigger'
7
8
  input[32] - 'total_length'
8
9
  input[512*8] - 'mem_file' # {axis_tvalid, axis_tuser, axis_tkeep, axis_tlast, axis_tdata}
@@ -13,6 +14,7 @@ TdlBuild.axis_sim_master_model(__dir__) do
13
14
  data_c_sim_master_model.data_c_sim_master_model_inst do |h| #(
14
15
  h.param.LOOP param.LOOP
15
16
  h.param.RAM_DEPTH param.RAM_DEPTH
17
+ h.input.enable enable
16
18
  h.input.load_trigger load_trigger
17
19
  h.input[32].total_length total_length
18
20
  h.input[512*8].mem_file mem_file
data/lib/axi/AXI_stream/axis_sim_master_model.sv ADDED
@@ -0,0 +1,46 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ created: 2021-04-16 17:01:07 +0800
9
+ madified:
10
+ ***********************************************/
11
+ `timescale 1ns/1ps
12
+
13
+ module axis_sim_master_model #(
14
+ parameter LOOP = "TRUE",
15
+ parameter RAM_DEPTH = 10000
16
+ )(
17
+ input enable,
18
+ input load_trigger,
19
+ input [31:0] total_length,
20
+ input [4095:0] mem_file,
21
+ axi_stream_inf.master out_inf
22
+ );
23
+
24
+ //==========================================================================
25
+ //-------- define ----------------------------------------------------------
26
+
27
+ data_inf_c #(.DSIZE(out_inf.DSIZE + out_inf.KSIZE + out_inf.USIZE + 1),.FreqM(1.0)) out_inf_dc (.clock(out_inf.aclk),.rst_n(out_inf.aresetn)) ;
28
+ //==========================================================================
29
+ //-------- instance --------------------------------------------------------
30
+ data_c_sim_master_model #(
31
+ .LOOP (LOOP ),
32
+ .RAM_DEPTH (RAM_DEPTH )
33
+ )data_c_sim_master_model_inst(
34
+ /* input */.enable (enable ),
35
+ /* input */.load_trigger (load_trigger ),
36
+ /* input */.total_length (total_length ),
37
+ /* input */.mem_file (mem_file ),
38
+ /* data_inf_c.master */.out_inf (out_inf_dc )
39
+ );
40
+ //==========================================================================
41
+ //-------- expression ------------------------------------------------------
42
+ assign out_inf.axis_tvalid = out_inf_dc.valid;
43
+ assign out_inf_dc.ready = out_inf.axis_tready;
44
+ assign {>>{out_inf.axis_tuser,out_inf.axis_tkeep,out_inf.axis_tlast,out_inf.axis_tdata}} = out_inf_dc.data;
45
+
46
+ endmodule
data/lib/axi/AXI_stream/axis_split_channel_verb.sv ADDED
@@ -0,0 +1,62 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ created: 2021-04-16 17:01:06 +0800
9
+ madified:
10
+ ***********************************************/
11
+ `timescale 1ns/1ps
12
+
13
+ module axis_split_channel_verb (
14
+ input [15:0] split_len,
15
+ axi_stream_inf.slaver origin_inf,
16
+ axi_stream_inf.master first_inf,
17
+ axi_stream_inf.master end_inf
18
+ );
19
+
20
+ //==========================================================================
21
+ //-------- define ----------------------------------------------------------
22
+ logic clock;
23
+ logic rst_n;
24
+ logic [16-1:0] insert_seed ;
25
+ logic [16-1:0] next_split_len ;
26
+ axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_insert (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
27
+ //==========================================================================
28
+ //-------- instance --------------------------------------------------------
29
+ axis_insert_copy axis_insert_copy_inst(
30
+ /* input */.insert_seed (insert_seed ),
31
+ /* input */.insert_len (8'd1 ),
32
+ /* axi_stream_inf.slaver */.in_inf (origin_inf ),
33
+ /* axi_stream_inf.master */.out_inf (origin_inf_insert )
34
+ );
35
+ common_fifo #(
36
+ .DEPTH (4 ),
37
+ .DSIZE (16 )
38
+ )common_fifo_head_bytesx_inst(
39
+ /* input */.clock (clock ),
40
+ /* input */.rst_n (rst_n ),
41
+ /* input */.wdata (split_len ),
42
+ /* input */.wr_en ((origin_inf.axis_tcnt == '0) && origin_inf.axis_tvalid && origin_inf.axis_tready ),
43
+ /* output */.rdata (next_split_len ),
44
+ /* input */.rd_en (origin_inf_insert.axis_tvalid && origin_inf_insert.axis_tready && origin_inf_insert.axis_tlast ),
45
+ /* output */.count (/*unused */ ),
46
+ /* output */.empty (/*unused */ ),
47
+ /* output */.full (/*unused */ )
48
+ );
49
+ axi_stream_split_channel axi_stream_split_channel_inst(
50
+ /* input */.split_len (next_split_len ),
51
+ /* axi_stream_inf.slaver */.origin_inf (origin_inf_insert ),
52
+ /* axi_stream_inf.master */.first_inf (first_inf ),
53
+ /* axi_stream_inf.master */.end_inf (end_inf )
54
+ );
55
+ //==========================================================================
56
+ //-------- expression ------------------------------------------------------
57
+ assign clock = origin_inf.aclk;
58
+ assign rst_n = origin_inf.aresetn;
59
+
60
+ assign insert_seed = split_len-1'b1;
61
+
62
+ endmodule
data/lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv ADDED
@@ -0,0 +1,50 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ creaded:
9
+ madified:
10
+ ***********************************************/
11
+ `timescale 1ns/1ps
12
+ (* axi_stream = "true" *)
13
+ module axis_width_convert_verb #(
14
+ parameter IDSIZE = 8,
15
+ parameter ODSIZE = 16
16
+ )(
17
+ axi_stream_inf.slaver in_axis,
18
+ axi_stream_inf.master out_axis
19
+ );
20
+
21
+ generate
22
+ if(IDSIZE == ODSIZE)
23
+ axis_direct_A1 #(
24
+ .IDSIZE (in_axis.DSIZE),
25
+ .ODSIZE (out_axis.DSIZE)
26
+ )axis_direct_A1_inst(
27
+ /* axi_stream_inf.slaver */ .slaver (in_axis ),
28
+ /* axi_stream_inf.master */ .master (out_axis )
29
+ );
30
+ else
31
+ width_convert_verb #(
32
+ .ISIZE (IDSIZE ),
33
+ .OSIZE (ODSIZE )
34
+ )width_convert_verb_inst(
35
+ /* input */ .clock (in_axis.aclk ),
36
+ /* input */ .rst_n (in_axis.aresetn ),
37
+ /* input [ISIZE-1:0] */ .wr_data (in_axis.axis_tdata ),
38
+ /* input */ .wr_vld (in_axis.axis_tvalid ),
39
+ /* output logic */ .wr_ready (in_axis.axis_tready ),
40
+ /* input */ .wr_last (in_axis.axis_tlast ),
41
+ /* input */ .wr_align_last (1'b0), //can be leave 1'b0
42
+ /* output logic[OSIZE-1:0] */ .rd_data (out_axis.axis_tdata ),
43
+ /* output logic */ .rd_vld (out_axis.axis_tvalid ),
44
+ /* input */ .rd_ready (out_axis.axis_tready ),
45
+ /* output */ .rd_last (out_axis.axis_tlast )
46
+ );
47
+
48
+ endgenerate
49
+
50
+ endmodule
data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv CHANGED
@@ -21,6 +21,8 @@ module axi_stream_packet_long_fifo #(
21
21
  axi_stream_inf.master axis_out
22
22
  );
23
23
 
24
+ assign axis_out.axis_tuser = '0;
25
+
24
26
  //--->> NATIVE FIFO IP <<------------------------------
25
27
  // (* dont_touch = "true" *)
26
28
  logic data_fifo_full;
data/lib/axi/AXI_stream/parse_big_field_table_verb.sv CHANGED
@@ -26,6 +26,8 @@ module parse_big_field_table_verb #(
26
26
  axi_stream_inf.mirror cm_mirror
27
27
  );
28
28
 
29
+ localparam VSIZE = $clog2(FIELD_LEN);
30
+
29
31
  import SystemPkg::*;
30
32
 
31
33
  initial begin
@@ -78,13 +80,13 @@ always_ff@(posedge clock,negedge rst_n)begin
78
80
  else begin
79
81
  if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tlast)
80
82
  region_valid <= 1'b1;
81
- else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt == (FIELD_LEN-1'b1))
83
+ else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt[VSIZE:0] == (FIELD_LEN-1'b1))
82
84
  region_valid <= 1'b0;
83
85
  else region_valid <= region_valid;
84
86
  end
85
87
  end
86
88
 
87
- localparam VSIZE = $clog2(FIELD_LEN);
89
+
88
90
  logic[DSIZE-1:0] value_array [0:FIELD_LEN-1];
89
91
 
90
92
  always_ff@(posedge clock,negedge rst_n)begin
@@ -107,7 +109,7 @@ always_ff@(posedge clock,negedge rst_n)begin
107
109
  if(out_valid)
108
110
  out_valid <= 1'b0;
109
111
  else out_valid <= 1'b1;
110
- else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt == (FIELD_LEN-1'b1))
112
+ else if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.axis_tcnt[VSIZE:0] == (FIELD_LEN-1'b1))
111
113
  out_valid <= 1'b1;
112
114
  else if(region_valid)
113
115
  out_valid <= 1'b0;
data/lib/axi/common/common_ram_sim_wrapper.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ creaded: XXXX.XX.XX
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
data/lib/axi/common/common_ram_wrapper.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ creaded:
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
data/lib/axi/common/test_write_mem.sv CHANGED
@@ -15,7 +15,7 @@ initial begin
15
15
  BRAM[0][2][3] = 14;
16
16
  BRAM[0][2][4] = 15;
17
17
 
18
- $writememh("/home/myw357/work/FPGA/acce_20201211/git_repo/wmy/axi/common/mem_format.coe",BRAM);
18
+ $writememh("./mem_format.coe",BRAM);
19
19
 
20
20
  end
21
21
 
data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ creaded:
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -23,8 +23,8 @@ module data_c_pipe_sync_seam #(
23
23
  //==========================================================================
24
24
  //-------- define ----------------------------------------------------------
25
25
 
26
- data_inf_c #(.DSIZE(in_inf.DSIZE)) in_inf_array[LAT-1:0] (.clock(in_inf.clock),.rst_n(in_inf.rst_n)) ;
27
- data_inf_c #(.DSIZE(out_inf.DSIZE)) out_inf_array[LAT-1:0] (.clock(out_inf.clock),.rst_n(out_inf.rst_n)) ;
26
+ data_inf_c #(.DSIZE(in_inf.DSIZE),.FreqM(in_inf.FreqM)) in_inf_array[LAT-1:0] (.clock(in_inf.clock),.rst_n(in_inf.rst_n)) ;
27
+ data_inf_c #(.DSIZE(out_inf.DSIZE),.FreqM(out_inf.FreqM)) out_inf_array[LAT-1:0] (.clock(out_inf.clock),.rst_n(out_inf.rst_n)) ;
28
28
  //==========================================================================
29
29
  //-------- instance --------------------------------------------------------
30
30
 
@@ -48,22 +48,22 @@ for(genvar KK0=0;KK0 < LAT;KK0++)begin
48
48
  endgenerate
49
49
  //-------- CLOCKs Total 2 ----------------------
50
50
  //--->> CheckClock <<----------------
51
- logic cc_done_7,cc_same_7;
52
- integer cc_afreq_7,cc_bfreq_7;
53
- ClockSameDomain CheckPClock_inst_7(
51
+ logic cc_done_8,cc_same_8;
52
+ integer cc_afreq_8,cc_bfreq_8;
53
+ ClockSameDomain CheckPClock_inst_8(
54
54
  /* input */ .aclk (in_inf.clock ),
55
55
  /* input */ .bclk (out_inf.clock ),
56
- /* output logic */ .done (cc_done_7),
57
- /* output logic */ .same (cc_same_7),
58
- /* output integer */ .aFreqK (cc_afreq_7),
59
- /* output integer */ .bFreqK (cc_bfreq_7)
56
+ /* output logic */ .done (cc_done_8),
57
+ /* output logic */ .same (cc_same_8),
58
+ /* output integer */ .aFreqK (cc_afreq_8),
59
+ /* output integer */ .bFreqK (cc_bfreq_8)
60
60
  );
61
61
 
62
62
  initial begin
63
- wait(cc_done_7);
64
- assert(cc_same_7)
63
+ wait(cc_done_8);
64
+ assert(cc_same_8)
65
65
  else begin
66
- $error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_7, 1000000.0/cc_bfreq_7);
66
+ $error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_8, 1000000.0/cc_bfreq_8);
67
67
  repeat(10)begin
68
68
  @(posedge in_inf.clock);
69
69
  end