axi_tdl 0.1.0 → 0.1.8

data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb

@@ -88,7 +88,7 @@ module TdlSpace
                 dimension = []
             end
             name = to_inp(name)
-            belong_to_module.Def.logic(name: name,dsize: @chain.last || 1,dimension: dimension,type: @type || 'logic')
+            rel = belong_to_module.Def.logic(name: name,dsize: @chain.last || 1,dimension: dimension,type: @type || 'logic')
         end
 
         def wire 

data/lib/tdl/sdlmodule/sdlmodule_draw.rb

@@ -52,12 +52,12 @@ class SdlModule
         pre_inst_stack_call
         @out_sv_path ||= '..\..\tdl\test_sdlmodule'
         if File.exist?(File.join(@out_sv_path,"#{module_name}.sv")) 
-            old_str = File.open(File.join(@out_sv_path,"#{module_name}.sv")).read.gsub(/\/\*.*?\*\//m,"").gsub(/\/\/.*/,"").sub(/^`timescale .*/,"").strip
+            old_str = File.open(File.join(@out_sv_path,"#{module_name}.sv")).read.sub(/\/\*.*?\*\//m,"").gsub(/\/\/.*/,"").sub(/^`timescale .*/,"").strip
         
 
             head_str,body_str = build_module_verb(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code)
             new_str = head_str+body_str
-            if body_str.gsub(/\/\*.*?\*\//m,"").gsub(/\/\/.*/,"").strip != old_str
+            if body_str.gsub(/\/\/.*/,"").strip != old_str
                 File.open(File.join(@out_sv_path,"#{module_name}.sv"),"w") do |f|
                     f.print new_str
                 end

data/lib/tdl/sdlmodule/sdlmodule_instance.rb

@@ -448,6 +448,9 @@ class SdlModule
         # @ports = (@port_clocks + @port_resets + @port_logics + @port_datainfs + @port_datainf_c_s + @port_videoinfs + @port_axisinfs + @port_axi4infs + @port_axilinfs)
         @instance_cnt ||= 0
         inst_p = SdlInst.new(origin:self,name:name)
+     
+        @instances ||= []
+        @instances << inst_p
 
         @port_params.each do |k,v|
             inst_p.inst_param_hash[k.to_s] = nil

data/lib/tdl/sdlmodule/sdlmodule_port_define.rb

@@ -65,7 +65,7 @@ class SdlModule
         if value.is_a? Float
             type = :real
         end
-        tmp = Parameter.new(name:name.to_s,value:value,port:true,type:type,show:show)
+        tmp = Parameter.new(name:name.to_s,value:value,port:true,type:type,show:show, belong_to_module: self)
         add_to_new_module("@port_params",tmp)
         add_method_to_itgt(name,tmp)
         tmp
@@ -87,7 +87,7 @@ class SdlModule
         #     tmp
         # end
         ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
-            tmp = Logic.new(name:name,dsize:dsize,port:"input",dimension:dimension)
+            tmp = Logic.new(name:name,dsize:dsize,port:"input",dimension:dimension, belong_to_module: self)
             add_to_new_module("@port_logics",tmp)
             add_method_to_itgt(name,tmp)
             tmp
@@ -109,7 +109,7 @@ class SdlModule
         #     tmp
         # end
         ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
-            tmp = Logic.new(name:name,dsize:dsize,port:"output",dimension:dimension,type: 'logic')
+            tmp = Logic.new(name:name,dsize:dsize,port:"output",dimension:dimension,type: 'logic', belong_to_module: self)
             add_to_new_module("@port_logics",tmp)
 
             if block_given?
@@ -136,7 +136,7 @@ class SdlModule
         #     tmp
         # end
         ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
-            tmp = Logic.new(name:name,dsize:dsize,port:"inout",dimension:dimension,type: '' )
+            tmp = Logic.new(name:name,dsize:dsize,port:"inout",dimension:dimension,type: '' , belong_to_module: self)
             add_to_new_module("@port_logics",tmp)
 
             if block_given?
@@ -150,7 +150,7 @@ class SdlModule
     def Clock(name,freqM:100,port: :input,pin:[],iostd:[],dsize:1,pin_prop:nil)
         port_name_chk(name)
         pin,iostd = parse_pin_prop(pin_prop) if pin_prop
-        a = Clock.new(name:name,freqM:freqM,port:port,dsize:dsize)
+        a = Clock.new(name:name,freqM:freqM,port:port,dsize:dsize, belong_to_module: self)
         add_to_new_module("@port_clocks",a)
 
         if block_given?
@@ -164,7 +164,7 @@ class SdlModule
     def Reset(name,port: :input,active:"low",pin:[],iostd:[],dsize:1,pin_prop:nil)
         port_name_chk(name)
         pin,iostd = parse_pin_prop(pin_prop) if pin_prop
-        a = Reset.new(name:name,active:active.to_s.downcase,port:port,dsize:dsize)
+        a = Reset.new(name:name,active:active.to_s.downcase,port:port,dsize:dsize, belong_to_module: self)
         add_to_new_module("@port_resets",a)
         # define_method(name){ a }
         add_method_to_itgt(name,a)

data/lib/tdl/sdlmodule/sdlmodule_varible.rb

@@ -13,25 +13,25 @@ class DefXp
     end
 
     def logic(name:"tmp",dsize:1,port:false,default:nil,msb_high:true,dimension:[],type:"logic",&block)
-        lg = Logic.new(name:name,dsize:dsize,port:port,default:default,msb_high:msb_high,dimension:dimension,type:type)
+        lg = Logic.new(name:name,dsize:dsize,port:port,default:default,msb_high:msb_high,dimension:dimension,type:type, belong_to_module: @sdlmodule)
         var_common(lg,&block)
         add_method_to_itgt(name,lg)
     end
 
     def clock(name:"",freqM:100,dsize:1,&block)
-        a = Clock.new(name:name,freqM:freqM,dsize:dsize)
+        a = Clock.new(name:name,freqM:freqM,dsize:dsize, belong_to_module: @sdlmodule)
         var_common(a,&block)
         add_method_to_itgt(name,a)
     end
 
     def reset(name:"",active:"low",dsize:1,&block)
-        a = Reset.new(name:name,active:active,dsize:dsize)
+        a = Reset.new(name:name,active:active,dsize:dsize, belong_to_module: @sdlmodule)
         var_common(a,&block)
         add_method_to_itgt(name,a)
     end
 
     def parameter(name:"P",value:100,local:false,type:nil,&block)
-        a = Parameter.new(name:name,value:value,local:local,port:false,show:true,type:type)
+        a = Parameter.new(name:name,value:value,local:local,port:false,show:true,type:type, belong_to_module: @sdlmodule)
         var_common(a,&block)
         add_method_to_itgt(name,a)
     end
@@ -77,12 +77,12 @@ class DefXp
     # end
 
     def mailbox(name:'mbox',depth:100,&block)
-        a = MailBox.new(name:name,depth:depth)
+        a = MailBox.new(name:name,depth:depth, belong_to_module: @sdlmodule)
         var_common(a,&block)
     end
 
     def debuglogic(name:"tmp",dsize:1,port:false,default:nil,msb_high:true,dimension:[],type:"logic",&block)
-        lg = DebugLogic.new(name:name,dsize:dsize,port:port,default:default,msb_high:msb_high,dimension:dimension,type:type)
+        lg = DebugLogic.new(name:name,dsize:dsize,port:port,default:default,msb_high:msb_high,dimension:dimension,type:type, belong_to_module: @sdlmodule)
         var_common(lg,&block)
         add_method_to_itgt(name,lg)
     end

data/lib/tdl/sdlmodule/test_unit_module.rb

@@ -43,6 +43,8 @@ class SdlModule
     end
 
     def gen_dev_wave_tcl ## 返回一个[]
+        return ['','',''] unless TopModule.sim
+
         dve_tcl_hash = {}
         track_signals_hash.each do |flag, base_ele_bhash|
             base_elms = []
@@ -50,6 +52,7 @@ class SdlModule
             intf_elms_name = []
             base_ele_bhash.each do |ele, sub_filter_block|
                 _ref_paths = ele.path_refs(&@__track_filter_block__)
+                _ref_paths.uniq!
 
                 if sub_filter_block
                     _ref_paths = _ref_paths.select do |e| 
@@ -143,6 +146,8 @@ class SdlModule
 
                 sub_hash.each do |ele, sub_filter_block|
                     _root_refs = ele.path_refs(&filter_block)
+                    _root_refs.uniq!
+                    
                     if sub_filter_block 
                         _root_refs.select! do |e| sub_filter_block.call(e) end
                     end    
@@ -210,6 +215,7 @@ class TestUnitModule < SdlModule ##TestUnitModule 是在编译完 TopModule TB
             to_down_pass    <= 1.b0
             initial_exec("wait(from_up_pass)")
             initial_exec("$root.#{TopModule.current.techbench.module_name}.test_unit_region = \"#{module_name}\"")
+            initial_exec("$display(\"--------------- Current test_unit <%0s> --------------------\", \"#{module_name}\")")
             block.call ## collect __root_ref_eles__ at here
             to_down_pass    <= 1.b1
         end

data/lib/tdl/sdlmodule/top_module.rb

@@ -340,6 +340,7 @@ endmodule\n"
     end
 
     define_global("sim",nil)
+    define_global("itgt_implicit_reject",nil)
 
 end
 ## 添加 itegration verb
@@ -437,6 +438,9 @@ class TopModule
                 SdlModule.gen_dev_wave_tcl File.join(sdlm.vcs_path,"dve.tcl")
             end
             sdlm.create_xdc
+
+            ## 全局contain_hdl 引入到 TopModule
+            sdlm.contain_hdl(*$__contain_hdl__)
         else 
             sdlm.origin_sv = true 
         end

data/lib/tdl/tdl.rb

@@ -138,7 +138,7 @@ require_relative "./exlib/logic_verify.rb"
 $argvs_hash = {}
 $argvs_hash = Parser.parse($TdlARGV || ARGV) 
 TopModule.sim = $argvs_hash[:sim]
-
+TopModule.itgt_implicit_reject = $argvs_hash[:itgt_implicit_reject]
 class Tdl
 
     def self.comment(c="-",info="_____")
@@ -271,16 +271,6 @@ class Tdl
         puts(pagination("SUMMARY"))
         puts "#{TopModule.sim ? 'SIM' : 'SYNTH'} RUN SPEND #{Time.now - $__start_time__} sec @ TIME : #{Time.now}"
 
-        ## ----------- 
-        # TopModule.current.ref_modules.uniq.each do |e| 
-        #     unless  e.is_a? ClassHDL::ClearSdlModule
-        #         puts "#{e.real_sv_path}: #{e.module_name}"
-        #     end
-        # end
-        ## ===========
-        # File.open("/home/myw357/work/FPGA/mammo_tcp_20210315/tmp.tcl", "w") do |f|
-        #     f.puts SdlModule.call_module('test_mac_1g_verb').gen_dev_wave_tcl
-        # end
     end
 
 end

data/lib/tdl/tdlerror/tdlerror.rb

@@ -4,6 +4,6 @@ class TdlError < ScriptError
         head_str0 = String.new("\n+_____________________________________________+\n")
         head_str1 = "\n|----------------TDL ERROR--------------------|\n"
         end_str0  = "\n+================TDL ERROR====================+\n"
-        super(head_str0.concat(head_str1).concat(arge.to_s[0,255]+end_str0))
+        super(head_str0.concat(head_str1).concat(arge.to_s[0,255]).concat(end_str0))
     end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: axi_tdl
 version: !ruby/object:Gem::Version
-  version: 0.1.0
+  version: 0.1.8
 platform: ruby
 authors:
 - Cook.Darwin
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2021-03-21 00:00:00.000000000 Z
+date: 2021-05-30 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rake
@@ -64,7 +64,6 @@ files:
 - ".github/workflows/ruby.yml"
 - ".gitignore"
 - ".travis.yml"
-- CODE_OF_CONDUCT.md
 - Gemfile
 - LICENSE
 - README.EN.md
@@ -209,6 +208,7 @@ files:
 - lib/axi/AXI_stream/axi_stream_partition_A1.sv
 - lib/axi/AXI_stream/axi_stream_planer.sv
 - lib/axi/AXI_stream/axi_stream_split_channel.rb
+- lib/axi/AXI_stream/axi_stream_split_channel.sv
 - lib/axi/AXI_stream/axi_streams_combin.sv
 - lib/axi/AXI_stream/axi_streams_combin_A1.sv
 - lib/axi/AXI_stream/axi_streams_scaler.sv
@@ -230,8 +230,10 @@ files:
 - lib/axi/AXI_stream/axis_head_cut.sv
 - lib/axi/AXI_stream/axis_head_cut_verb.sv
 - lib/axi/AXI_stream/axis_head_cut_verc.rb
+- lib/axi/AXI_stream/axis_head_cut_verc.sv
 - lib/axi/AXI_stream/axis_inct_s2m_with_flag.sv
 - lib/axi/AXI_stream/axis_insert_copy.rb
+- lib/axi/AXI_stream/axis_insert_copy.sv
 - lib/axi/AXI_stream/axis_intc_M2S_with_addr_inf.sv
 - lib/axi/AXI_stream/axis_intc_S2M_with_addr_inf.sv
 - lib/axi/AXI_stream/axis_interconnect_S2M_pipe.sv
@@ -240,18 +242,20 @@ files:
 - lib/axi/AXI_stream/axis_length_split.sv
 - lib/axi/AXI_stream/axis_length_split_with_addr.sv
 - lib/axi/AXI_stream/axis_length_split_with_user.sv
-- lib/axi/AXI_stream/axis_length_split_writh_user.sv
 - lib/axi/AXI_stream/axis_link_trigger.sv
 - lib/axi/AXI_stream/axis_master_empty.sv
 - lib/axi/AXI_stream/axis_mirror_to_master.sv
 - lib/axi/AXI_stream/axis_mirrors.sv
 - lib/axi/AXI_stream/axis_orthogonal.sv
 - lib/axi/AXI_stream/axis_pipe_sync_seam.rb
+- lib/axi/AXI_stream/axis_pipe_sync_seam.sv
 - lib/axi/AXI_stream/axis_ram_buffer.sv
 - lib/axi/AXI_stream/axis_rom_contect.rb
 - lib/axi/AXI_stream/axis_rom_contect.sv
 - lib/axi/AXI_stream/axis_rom_contect_sim.rb
+- lib/axi/AXI_stream/axis_rom_contect_sim.sv
 - lib/axi/AXI_stream/axis_sim_master_model.rb
+- lib/axi/AXI_stream/axis_sim_master_model.sv
 - lib/axi/AXI_stream/axis_sim_slaver_model.rb
 - lib/axi/AXI_stream/axis_sim_verify_by_coe.sv
 - lib/axi/AXI_stream/axis_slaver_empty.sv
@@ -259,6 +263,7 @@ files:
 - lib/axi/AXI_stream/axis_slaver_pipe_A1.sv
 - lib/axi/AXI_stream/axis_slaver_vector_empty.sv
 - lib/axi/AXI_stream/axis_split_channel_verb.rb
+- lib/axi/AXI_stream/axis_split_channel_verb.sv
 - lib/axi/AXI_stream/axis_to_axi4_or_lite.rb
 - lib/axi/AXI_stream/axis_to_axi4_or_lite.sv
 - lib/axi/AXI_stream/axis_to_data_inf.sv
@@ -281,6 +286,7 @@ files:
 - lib/axi/AXI_stream/data_width/axis_width_combin.sv
 - lib/axi/AXI_stream/data_width/axis_width_combin_A1.sv
 - lib/axi/AXI_stream/data_width/axis_width_convert.sv
+- lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv
 - lib/axi/AXI_stream/data_width/axis_width_destruct.sv
 - lib/axi/AXI_stream/data_width/axis_width_destruct_A1.sv
 - lib/axi/AXI_stream/ex_status/axis_ex_status.sv
@@ -547,6 +553,34 @@ files:
 - lib/axi/video_interface/video_interface.sv
 - lib/axi_tdl.rb
 - lib/axi_tdl/version.rb
+- lib/public_atom_module/CheckPClock.sv
+- lib/public_atom_module/LICENSE.md
+- lib/public_atom_module/altera_xilinx_always_block_sw.rb
+- lib/public_atom_module/bits_decode.sv
+- lib/public_atom_module/bits_decode_verb.sv
+- lib/public_atom_module/bits_decode_verb_sdl.rb
+- lib/public_atom_module/broaden.v
+- lib/public_atom_module/broaden_and_cross_clk.v
+- lib/public_atom_module/ceiling.v
+- lib/public_atom_module/ceiling_A1.v
+- lib/public_atom_module/clock_rst.sv
+- lib/public_atom_module/cross_clk_sync.v
+- lib/public_atom_module/edge_generator.v
+- lib/public_atom_module/flooring.v
+- lib/public_atom_module/latch_data.v
+- lib/public_atom_module/latency.v
+- lib/public_atom_module/latency_dynamic.v
+- lib/public_atom_module/latency_long.v
+- lib/public_atom_module/latency_verb.v
+- lib/public_atom_module/once_event.sv
+- lib/public_atom_module/pipe_reg.v
+- lib/public_atom_module/pipe_reg_2write_ports.v
+- lib/public_atom_module/sim/clock_rst_verb.sv
+- lib/public_atom_module/sim/clock_rst_verc.sv
+- lib/public_atom_module/sim/latency_long_tb.sv
+- lib/public_atom_module/sim/latency_long_tb.sv.bak
+- lib/public_atom_module/sim_system_pkg.sv
+- lib/public_atom_module/synth_system_pkg.sv
 - lib/spec/spec_helper.rb
 - lib/tdl/LICENSE
 - lib/tdl/Logic/Logic.tar.gz
@@ -1120,11 +1154,13 @@ files:
 - lib/tdl/examples/11_test_unit/exp_test_unit.rb
 - lib/tdl/examples/11_test_unit/exp_test_unit.sv
 - lib/tdl/examples/11_test_unit/exp_test_unit_constraints.xdc
+- lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv
 - lib/tdl/examples/11_test_unit/modules/sub_md0.rb
 - lib/tdl/examples/11_test_unit/modules/sub_md0.sv
 - lib/tdl/examples/11_test_unit/modules/sub_md1.rb
 - lib/tdl/examples/11_test_unit/modules/sub_md1.sv
 - lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv
+- lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv
 - lib/tdl/examples/11_test_unit/tu0.sv
 - lib/tdl/examples/11_test_unit/tu1.sv
 - lib/tdl/examples/1_define_module/example1.rb
@@ -1196,8 +1232,10 @@ files:
 - lib/tdl/examples/8_top_module/example.rb
 - lib/tdl/examples/8_top_module/pins.yml
 - lib/tdl/examples/8_top_module/tb_test_top.sv
+- lib/tdl/examples/8_top_module/tb_test_top_sim.sv
 - lib/tdl/examples/8_top_module/test_top.sv
 - lib/tdl/examples/8_top_module/test_top_constraints.xdc
+- lib/tdl/examples/8_top_module/test_top_sim.sv
 - lib/tdl/examples/9_itegration/A_itgt/a_test_md.sv
 - lib/tdl/examples/9_itegration/A_itgt/a_test_module.rb
 - lib/tdl/examples/9_itegration/A_itgt/itgt_module_a_block.rb
@@ -1293,7 +1331,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.0.3
+rubygems_version: 3.0.3.1
 signing_key: 
 specification_version: 4
 summary: Axi 是一个轻量级的AXI4库. Tdl 是一种硬件构造语言

data/CODE_OF_CONDUCT.md

@@ -1,74 +0,0 @@
-# Contributor Covenant Code of Conduct
-
-## Our Pledge
-
-In the interest of fostering an open and welcoming environment, we as
-contributors and maintainers pledge to making participation in our project and
-our community a harassment-free experience for everyone, regardless of age, body
-size, disability, ethnicity, gender identity and expression, level of experience,
-nationality, personal appearance, race, religion, or sexual identity and
-orientation.
-
-## Our Standards
-
-Examples of behavior that contributes to creating a positive environment
-include:
-
-* Using welcoming and inclusive language
-* Being respectful of differing viewpoints and experiences
-* Gracefully accepting constructive criticism
-* Focusing on what is best for the community
-* Showing empathy towards other community members
-
-Examples of unacceptable behavior by participants include:
-
-* The use of sexualized language or imagery and unwelcome sexual attention or
-advances
-* Trolling, insulting/derogatory comments, and personal or political attacks
-* Public or private harassment
-* Publishing others' private information, such as a physical or electronic
-  address, without explicit permission
-* Other conduct which could reasonably be considered inappropriate in a
-  professional setting
-
-## Our Responsibilities
-
-Project maintainers are responsible for clarifying the standards of acceptable
-behavior and are expected to take appropriate and fair corrective action in
-response to any instances of unacceptable behavior.
-
-Project maintainers have the right and responsibility to remove, edit, or
-reject comments, commits, code, wiki edits, issues, and other contributions
-that are not aligned to this Code of Conduct, or to ban temporarily or
-permanently any contributor for other behaviors that they deem inappropriate,
-threatening, offensive, or harmful.
-
-## Scope
-
-This Code of Conduct applies both within project spaces and in public spaces
-when an individual is representing the project or its community. Examples of
-representing a project or community include using an official project e-mail
-address, posting via an official social media account, or acting as an appointed
-representative at an online or offline event. Representation of a project may be
-further defined and clarified by project maintainers.
-
-## Enforcement
-
-Instances of abusive, harassing, or otherwise unacceptable behavior may be
-reported by contacting the project team at cook_darwin@hotmail.com. All
-complaints will be reviewed and investigated and will result in a response that
-is deemed necessary and appropriate to the circumstances. The project team is
-obligated to maintain confidentiality with regard to the reporter of an incident.
-Further details of specific enforcement policies may be posted separately.
-
-Project maintainers who do not follow or enforce the Code of Conduct in good
-faith may face temporary or permanent repercussions as determined by other
-members of the project's leadership.
-
-## Attribution
-
-This Code of Conduct is adapted from the [Contributor Covenant][homepage], version 1.4,
-available at [http://contributor-covenant.org/version/1/4][version]
-
-[homepage]: http://contributor-covenant.org
-[version]: http://contributor-covenant.org/version/1/4/

data/lib/axi/AXI_stream/axis_length_split_writh_user.sv

@@ -1,87 +0,0 @@
-/**********************************************
-______________   ______________
-______________ X ______________
-______________  ______________
-
-descript:
-author : Cook.Darwin
-Version: VERA.0.X 2018/1/25 
-    use axis_user to detect last
-creaded: 2017/5/19 
-madified:
-***********************************************/
-`timescale 1ns/1ps
-(* axi_stream = "true" *)
-module axis_length_split_with_user (
-    input [31:0]           length,      ////[0] mean 0 len
-    (* up_stream = "true" *)
-    axi_stream_inf.slaver  axis_in,
-    (* down_stream = "true" *)
-    axi_stream_inf.master  axis_out
-);
-
-wire    clock,rst_n,clken;
-
-assign  clock   = axis_in.aclk;
-assign  rst_n   = axis_in.aresetn;
-assign  clken   = axis_in.aclken;
-
-axi_stream_inf #(.DSIZE(axis_in.DSIZE)) axis_pre (.aclk(clock),.aresetn(rst_n),.aclken(clken));
-
-
-logic [31:0]        cnt;
-
-always@(posedge clock,negedge rst_n)
-    if(~rst_n)  cnt     <= '0;
-    else begin
-        if(axis_in.axis_tvalid  && axis_in.axis_tready && axis_in.axis_tlast)
-                cnt     <= '0;
-        else if(axis_in.axis_tvalid  && axis_in.axis_tready && (cnt >= (length-1)))
-                cnt     <= '0;
-        else if(axis_in.axis_tvalid  && axis_in.axis_tready)
-                cnt     <= cnt + 1'b1;
-        else    cnt     <= cnt;
-    end
-
-logic   new_last;
-
-always@(posedge clock,negedge rst_n)
-    if(~rst_n)  new_last    <= 1'b0;
-    else begin
-        if(axis_in.axis_tvalid  && axis_in.axis_tready && (new_last||axis_in.axis_tlast))
-                new_last    <= 1'b0;
-        else if(axis_in.axis_tvalid  && axis_in.axis_tready && cnt==(length-2))
-                new_last    <= 1'b1;
-        else    new_last    <= new_last;
-    end
-
-// logic   mark_tail;
-//
-// always@(posedge clock,negedge rst_n)
-//     if(~rst_n)  mark_tail   <= 1'b0;
-//     else begin
-//         if(axis_in.axis_tvalid  && axis_in.axis_tready && axis_in.axis_tlast)
-//                 mark_tail   <= 1'b0;
-//         else if(axis_in.axis_tvalid  && axis_in.axis_tready && axis_in.axis_tcnt==(length-1))
-//                 mark_tail   <= 1'b1;
-//         else    mark_tail   <= mark_tail;
-//     end
-
-assign axis_pre.axis_tvalid = axis_in.axis_tvalid;
-assign axis_pre.axis_tdata  = axis_in.axis_tdata;
-assign axis_pre.axis_tlast  = new_last || axis_in.axis_tlast;
-assign axis_pre.axis_tkeep  = axis_in.axis_tkeep;
-// assign axis_pre.axis_tuser  = axis_in.axis_tuser;
-assign axis_pre.axis_tuser  = axis_in.axis_tlast;
-assign axis_in.axis_tready  = axis_pre.axis_tready;
-
-axis_connect_pipe axis_connect_pipe_inst(
-/*  axi_stream_inf.slaver  */  .axis_in     (axis_pre   ),
-/*  axi_stream_inf.master  */  .axis_out    (axis_out   )
-);
-
-int out_cnt;
-
-assign out_cnt = axis_out.axis_tcnt;
-
-endmodule