axi_tdl 0.1.0 → 0.1.8
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- checksums.yaml +4 -4
- data/Rakefile +7 -0
- data/lib/axi/AXI4/axi4_direct_A1.sv +1 -1
- data/lib/axi/AXI4/axi4_direct_verc.sv +54 -54
- data/lib/axi/AXI4/axi4_dpram_cache.rb +1 -0
- data/lib/axi/AXI4/axi4_dpram_cache.sv +10 -10
- data/lib/axi/AXI4/axi4_rd_burst_track.sv +2 -1
- data/lib/axi/AXI4/axi4_wr_burst_track.sv +2 -1
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +9 -9
- data/lib/axi/AXI4/odata_pool_axi4_A3.sv +7 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +5 -5
- data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +8 -4
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +6 -6
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +12 -12
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +154 -0
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +242 -0
- data/lib/axi/AXI_stream/axis_insert_copy.sv +79 -0
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +48 -0
- data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +113 -0
- data/lib/axi/AXI_stream/axis_sim_master_model.rb +2 -0
- data/lib/axi/AXI_stream/axis_sim_master_model.sv +46 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
- data/lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv +50 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +2 -0
- data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +5 -3
- data/lib/axi/common/common_ram_sim_wrapper.sv +1 -1
- data/lib/axi/common/common_ram_wrapper.sv +1 -1
- data/lib/axi/common/test_write_mem.sv +1 -1
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +13 -13
- data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +14 -11
- data/lib/axi/platform_ip/fifo_36kb_long.sv +1 -1
- data/lib/axi/platform_ip/long_fifo_verb.sv +1 -1
- data/lib/axi/platform_ip/wide_fifo.sv +1 -1
- data/lib/axi/platform_ip/xilinx_fifo_verb.sv +1 -1
- data/lib/axi/platform_ip/xilinx_fifo_verc.sv +2 -1
- data/lib/axi/techbench/tb_axi_stream_split_channel.rb +2 -1
- data/lib/axi/techbench/tb_axi_stream_split_channel.sv +46 -45
- data/lib/axi_tdl.rb +31 -1
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/public_atom_module/CheckPClock.sv +53 -0
- data/lib/public_atom_module/LICENSE.md +674 -0
- data/lib/public_atom_module/altera_xilinx_always_block_sw.rb +57 -0
- data/lib/public_atom_module/bits_decode.sv +71 -0
- data/lib/public_atom_module/bits_decode_verb.sv +71 -0
- data/lib/public_atom_module/bits_decode_verb_sdl.rb +24 -0
- data/lib/public_atom_module/broaden.v +43 -0
- data/lib/public_atom_module/broaden_and_cross_clk.v +47 -0
- data/lib/public_atom_module/ceiling.v +39 -0
- data/lib/public_atom_module/ceiling_A1.v +42 -0
- data/lib/public_atom_module/clock_rst.sv +64 -0
- data/lib/public_atom_module/cross_clk_sync.v +37 -0
- data/lib/public_atom_module/edge_generator.v +50 -0
- data/lib/public_atom_module/flooring.v +36 -0
- data/lib/public_atom_module/latch_data.v +30 -0
- data/lib/public_atom_module/latency.v +48 -0
- data/lib/public_atom_module/latency_dynamic.v +83 -0
- data/lib/public_atom_module/latency_long.v +84 -0
- data/lib/public_atom_module/latency_verb.v +52 -0
- data/lib/public_atom_module/once_event.sv +65 -0
- data/lib/public_atom_module/pipe_reg.v +93 -0
- data/lib/public_atom_module/pipe_reg_2write_ports.v +84 -0
- data/lib/public_atom_module/sim/clock_rst_verb.sv +54 -0
- data/lib/public_atom_module/sim/clock_rst_verc.sv +69 -0
- data/lib/public_atom_module/sim/latency_long_tb.sv +49 -0
- data/lib/public_atom_module/sim/latency_long_tb.sv.bak +49 -0
- data/lib/public_atom_module/sim_system_pkg.sv +4 -0
- data/lib/public_atom_module/synth_system_pkg.sv +4 -0
- data/lib/tdl/Logic/logic_edge.rb +1 -1
- data/lib/tdl/auto_script/autogensdl.rb +2 -3
- data/lib/tdl/auto_script/import_hdl.rb +40 -5
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +47 -10
- data/lib/tdl/class_hdl/hdl_always_comb.rb +4 -1
- data/lib/tdl/class_hdl/hdl_always_ff.rb +3 -3
- data/lib/tdl/class_hdl/hdl_assign.rb +7 -1
- data/lib/tdl/class_hdl/hdl_block_ifelse.rb +7 -7
- data/lib/tdl/class_hdl/hdl_foreach.rb +2 -2
- data/lib/tdl/class_hdl/hdl_function.rb +4 -4
- data/lib/tdl/class_hdl/hdl_generate.rb +5 -2
- data/lib/tdl/class_hdl/hdl_initial.rb +25 -3
- data/lib/tdl/class_hdl/hdl_module_def.rb +9 -6
- data/lib/tdl/class_hdl/hdl_package.rb +45 -0
- data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +99 -27
- data/lib/tdl/class_hdl/hdl_struct.rb +2 -2
- data/lib/tdl/elements/Reset.rb +5 -9
- data/lib/tdl/elements/clock.rb +5 -9
- data/lib/tdl/elements/data_inf.rb +0 -17
- data/lib/tdl/elements/logic.rb +9 -31
- data/lib/tdl/elements/mail_box.rb +6 -1
- data/lib/tdl/elements/originclass.rb +17 -47
- data/lib/tdl/elements/parameter.rb +5 -6
- data/lib/tdl/examples/11_test_unit/dve.tcl +6 -153
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +2 -2
- data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +9 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +2 -2
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +2 -2
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -1
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +41 -0
- data/lib/tdl/examples/11_test_unit/tu0.sv +2 -1
- data/lib/tdl/examples/1_define_module/exmple_md.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +3 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +7 -7
- data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +4 -3
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +2 -2
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +1 -1
- data/lib/tdl/examples/6_module_with_interface/example_interface.sv +8 -8
- data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +9 -9
- data/lib/tdl/examples/7_module_with_package/body_package.sv +4 -3
- data/lib/tdl/examples/7_module_with_package/example_pkg.sv +1 -1
- data/lib/tdl/examples/7_module_with_package/head_package.sv +4 -3
- data/lib/tdl/examples/8_top_module/dve.tcl +6 -0
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -1
- data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +29 -0
- data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
- data/lib/tdl/examples/8_top_module/test_top_sim.sv +9 -0
- data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +2 -1
- data/lib/tdl/examples/9_itegration/dve.tcl +155 -2
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +1 -1
- data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +1 -1
- data/lib/tdl/examples/9_itegration/test_tttop.sv +7 -38
- data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +38 -7
- data/lib/tdl/exlib/axis_verify.rb +4 -3
- data/lib/tdl/exlib/constraints_verb.rb +1 -0
- data/lib/tdl/exlib/itegration_verb.rb +47 -41
- data/lib/tdl/rebuild_ele/ele_base.rb +15 -10
- data/lib/tdl/sdlmodule/sdlmodule.rb +117 -51
- data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +1 -1
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +2 -2
- data/lib/tdl/sdlmodule/sdlmodule_instance.rb +3 -0
- data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +6 -6
- data/lib/tdl/sdlmodule/sdlmodule_varible.rb +6 -6
- data/lib/tdl/sdlmodule/test_unit_module.rb +6 -0
- data/lib/tdl/sdlmodule/top_module.rb +4 -0
- data/lib/tdl/tdl.rb +1 -11
- data/lib/tdl/tdlerror/tdlerror.rb +1 -1
- metadata +43 -5
- data/CODE_OF_CONDUCT.md +0 -74
- data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +0 -87
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript:
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author : Cook.Darwin
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Version: VERA.0.0
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creaded:
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madified:
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***********************************************/
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`timescale 1ns/1ps
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module axi_stream_split_channel (
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input [15:0] split_len,
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axi_stream_inf.slaver origin_inf,
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axi_stream_inf.master first_inf,
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axi_stream_inf.master end_inf
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);
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//==========================================================================
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//-------- define ----------------------------------------------------------
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logic clock;
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logic rst_n;
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logic addr;
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logic new_last;
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axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_add_last (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) sub_origin_inf [1:0] (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
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//==========================================================================
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//-------- instance --------------------------------------------------------
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axi_stream_interconnect_S2M #(
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.NUM (2 )
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)axi_stream_interconnect_S2M_inst(
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/* input */.addr (addr ),
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/* axi_stream_inf.slaver */.s00 (origin_inf_add_last ),
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/* axi_stream_inf.master */.m00 (sub_origin_inf )
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);
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//==========================================================================
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//-------- expression ------------------------------------------------------
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axi_stream_inf #(.DSIZE(first_inf.DSIZE)) sub_first_inf[1-1:0](.aclk(first_inf.aclk),.aresetn(first_inf.aresetn),.aclken(1'b1));
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axis_direct axis_direct_first_inf_inst0 (
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/* axi_stream_inf.slaver*/ .slaver (sub_origin_inf[0]),
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/* axi_stream_inf.master*/ .master (sub_first_inf[0])
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);
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axi_stream_inf #(.DSIZE(end_inf.DSIZE)) sub_end_inf[1-1:0](.aclk(end_inf.aclk),.aresetn(end_inf.aresetn),.aclken(1'b1));
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axis_direct axis_direct_end_inf_inst0 (
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/* axi_stream_inf.slaver*/ .slaver (sub_origin_inf[1]),
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/* axi_stream_inf.master*/ .master (sub_end_inf[0])
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);
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//-------- CLOCKs Total 3 ----------------------
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//--->> CheckClock <<----------------
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logic cc_done_6,cc_same_6;
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integer cc_afreq_6,cc_bfreq_6;
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ClockSameDomain CheckPClock_inst_6(
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/* input */ .aclk (origin_inf.aclk ),
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/* input */ .bclk (first_inf.aclk ),
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/* output logic */ .done (cc_done_6),
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/* output logic */ .same (cc_same_6),
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/* output integer */ .aFreqK (cc_afreq_6),
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/* output integer */ .bFreqK (cc_bfreq_6)
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);
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initial begin
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wait(cc_done_6);
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assert(cc_same_6)
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else begin
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$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != first_inf.aclk<%0f M>",1000000.0/cc_afreq_6, 1000000.0/cc_bfreq_6);
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repeat(10)begin
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@(posedge origin_inf.aclk);
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end
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$stop;
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end
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end
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//---<< CheckClock >>----------------
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//--->> CheckClock <<----------------
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logic cc_done_7,cc_same_7;
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integer cc_afreq_7,cc_bfreq_7;
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ClockSameDomain CheckPClock_inst_7(
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/* input */ .aclk (origin_inf.aclk ),
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/* input */ .bclk (end_inf.aclk ),
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/* output logic */ .done (cc_done_7),
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/* output logic */ .same (cc_same_7),
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/* output integer */ .aFreqK (cc_afreq_7),
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/* output integer */ .bFreqK (cc_bfreq_7)
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);
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initial begin
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wait(cc_done_7);
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assert(cc_same_7)
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else begin
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$error("--- Error : `axi_stream_split_channel` clock is not same, origin_inf.aclk< %0f M> != end_inf.aclk<%0f M>",1000000.0/cc_afreq_7, 1000000.0/cc_bfreq_7);
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repeat(10)begin
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@(posedge origin_inf.aclk);
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end
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$stop;
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end
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end
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//---<< CheckClock >>----------------
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//======== CLOCKs Total 3 ======================
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assign clock = origin_inf.aclk;
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assign rst_n = origin_inf.aresetn;
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always_ff@(posedge clock,negedge rst_n) begin
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if(~rst_n)begin
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addr <= 1'b0;
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new_last <= 1'b0;
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end
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else begin
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if(origin_inf.axis_tvalid && origin_inf.axis_tready)begin
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new_last <= origin_inf.axis_tcnt==(split_len-2);
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end
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else begin
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new_last <= new_last;
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end
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if(origin_inf.axis_tvalid && origin_inf.axis_tready && origin_inf.axis_tlast)begin
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addr <= 1'b0;
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end
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else if(origin_inf.axis_tcnt==(split_len-1)&&origin_inf.axis_tvalid && origin_inf.axis_tready)begin
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addr <= 1'b1;
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end
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else begin
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addr <= addr;
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end
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end
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end
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assign origin_inf_add_last.axis_tdata = origin_inf.axis_tdata;
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assign origin_inf_add_last.axis_tvalid = origin_inf.axis_tvalid;
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assign origin_inf_add_last.axis_tuser = origin_inf.axis_tuser;
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assign origin_inf_add_last.axis_tkeep = origin_inf.axis_tkeep;
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assign origin_inf_add_last.axis_tlast = origin_inf.axis_tlast|new_last;
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assign origin_inf.axis_tready = origin_inf_add_last.axis_tready;
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axis_direct axis_direct_first_inf_instMM (
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/* axi_stream_inf.slaver*/ .slaver (sub_first_inf[0]),
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/* axi_stream_inf.master*/ .master (first_inf)
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);
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axis_direct axis_direct_end_inf_instMM (
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/* axi_stream_inf.slaver*/ .slaver (sub_end_inf[0]),
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/* axi_stream_inf.master*/ .master (end_inf)
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);
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endmodule
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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4
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_______________________________________
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descript:
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author : Cook.Darwin
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7
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Version: VERC.0.0
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8
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creaded:
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9
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madified:
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10
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***********************************************/
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11
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`timescale 1ns/1ps
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12
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+
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13
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module axis_head_cut_verc #(
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14
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parameter BYTE_BITS = 8,
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15
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parameter DX = (origin_inf.DSIZE / BYTE_BITS)
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16
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)(
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17
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input [9:0] bytes,
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18
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axi_stream_inf.slaver origin_inf,
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axi_stream_inf.master out_inf
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);
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//==========================================================================
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//-------- define ----------------------------------------------------------
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logic clock;
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logic rst_n;
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logic [18-1:0] origin_sync_info[3-1:0] ;
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logic [18-1:0] origin_sync_info_out[3-1:0] ;
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logic [10-1:0] bytes_Q ;
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logic [10-1:0] bytes_QQ ;
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logic [4-1:0] bytes_x ;
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logic [4-1:0] bytes_x_Q ;
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logic [4-1:0] bytes_x_tmp ;
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logic [4-1:0] bytes_x_sub_nDx ;
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logic [4-1:0] bytes_x_sub_nDx_tmp ;
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logic [2-1:0] route_addr ;
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logic [2-1:0] route_addr_tmp ;
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logic fifo_wr_en;
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logic [4-1:0] int_cut_len ;
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logic [4-1:0] shift_sel_pre ;
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logic fifo_wr_en_lat;
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logic [4-1:0] shift_sel ;
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axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_post (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
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43
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axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) sub_origin_inf [2:0] (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
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44
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axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_ss (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
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45
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axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_cut_mix (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_ss_E0 (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
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axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.FreqM(origin_inf.FreqM),.USIZE(1)) origin_inf_ss_E0_CH (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
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48
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axi_stream_inf #(.DSIZE(out_inf.DSIZE),.FreqM(out_inf.FreqM),.USIZE(1)) out_inf_branchR325 (.aclk(out_inf.aclk),.aresetn(out_inf.aresetn),.aclken(1'b1)) ;
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49
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+
//==========================================================================
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50
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//-------- instance --------------------------------------------------------
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axis_pipe_sync_seam #(
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52
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.LAT (3 ),
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53
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.DSIZE (18 )
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)axis_pipe_sync_seam_inst(
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/* input */.in_datas (origin_sync_info ),
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/* output */.out_datas (origin_sync_info_out ),
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/* axi_stream_inf.slaver */.in_inf (origin_inf ),
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/* axi_stream_inf.master */.out_inf (origin_inf_post )
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);
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axi_stream_interconnect_S2M #(
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.NUM (3 )
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)axi_stream_interconnect_S2M_inst(
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/* input */.addr (route_addr ),
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/* axi_stream_inf.slaver */.s00 (origin_inf_post ),
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/* axi_stream_inf.master */.m00 (sub_origin_inf )
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);
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67
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common_fifo #(
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68
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.DEPTH (4 ),
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69
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.DSIZE (4 )
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70
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)common_fifo_head_bytesx_inst(
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/* input */.clock (clock ),
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/* input */.rst_n (rst_n ),
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/* input */.wdata (bytes_x ),
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/* input */.wr_en (fifo_wr_en && (bytes_x!= '0) ),
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/* output */.rdata (int_cut_len ),
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/* input */.rd_en ((sub_origin_inf[1].axis_tvalid && sub_origin_inf[1].axis_tready && sub_origin_inf[1].axis_tlast) ),
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/* output */.count (/*unused */ ),
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/* output */.empty (/*unused */ ),
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/* output */.full (/*unused */ )
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);
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axis_head_cut_verb axis_head_cut_verb_inst(
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/* input */.length ({12'd0,int_cut_len} ),
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/* axi_stream_inf.slaver */.axis_in (sub_origin_inf[1] ),
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/* axi_stream_inf.master */.axis_out (origin_inf_ss )
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+
);
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86
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axis_append_A1 #(
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87
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.MODE ("END" ),
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88
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.DSIZE (out_inf.DSIZE ),
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.HEAD_FIELD_LEN (1 ),
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.HEAD_FIELD_NAME ("HEAD Filed" ),
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.END_FIELD_LEN (1 ),
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.END_FIELD_NAME ("END Filed" )
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93
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+
)axis_append_A1_inst(
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/* input */.enable (1'b1 ),
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95
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+
/* input */.head_value (/*unused */ ),
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96
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/* input */.end_value ('0 ),
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97
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/* axi_stream_inf.slaver */.origin_in (origin_inf_cut_mix ),
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98
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/* axi_stream_inf.master */.append_out (origin_inf_ss_E0 )
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99
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+
);
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100
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+
common_fifo #(
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101
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.DEPTH (4 ),
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102
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+
.DSIZE (4 )
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103
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+
)common_fifo_head_nDx_inst(
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104
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/* input */.clock (clock ),
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105
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+
/* input */.rst_n (rst_n ),
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106
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/* input */.wdata (shift_sel_pre ),
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107
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/* input */.wr_en (fifo_wr_en_lat ),
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108
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+
/* output */.rdata (shift_sel ),
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109
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+
/* input */.rd_en (origin_inf_ss_E0.axis_tvalid && origin_inf_ss_E0.axis_tready && origin_inf_ss_E0.axis_tlast ),
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110
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+
/* output */.count (/*unused */ ),
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111
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+
/* output */.empty (/*unused */ ),
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112
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+
/* output */.full (/*unused */ )
|
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113
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+
);
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114
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+
axis_connect_pipe_right_shift_verb #(
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115
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+
.SHIFT_BYTE_BIT (BYTE_BITS ),
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116
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+
.SNUM (DX )
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117
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+
)axis_connect_pipe_right_shift_verb_inst(
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118
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+
/* input */.shift_sel (shift_sel ),
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119
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+
/* axi_stream_inf.slaver */.axis_in (origin_inf_ss_E0 ),
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120
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+
/* axi_stream_inf.master */.axis_out (origin_inf_ss_E0_CH )
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121
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+
);
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122
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+
axis_head_cut_verb last_cut_inst(
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123
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+
/* input */.length (16'd1 ),
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124
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+
/* axi_stream_inf.slaver */.axis_in (origin_inf_ss_E0_CH ),
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125
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+
/* axi_stream_inf.master */.axis_out (out_inf_branchR325 )
|
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126
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+
);
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127
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+
//==========================================================================
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|
128
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+
//-------- expression ------------------------------------------------------
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129
|
+
|
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130
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+
axi_stream_inf #(.DSIZE(out_inf.DSIZE)) sub_out_inf[2-1:0](.aclk(out_inf.aclk),.aresetn(out_inf.aresetn),.aclken(1'b1));
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131
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+
|
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132
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+
|
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133
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+
axis_direct axis_direct_out_inf_inst0 (
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134
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+
/* axi_stream_inf.slaver*/ .slaver (sub_origin_inf[0]),
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135
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+
/* axi_stream_inf.master*/ .master (sub_out_inf[0])
|
|
136
|
+
);
|
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137
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+
|
|
138
|
+
axis_direct axis_direct_out_inf_inst1 (
|
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139
|
+
/* axi_stream_inf.slaver*/ .slaver (out_inf_branchR325),
|
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140
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+
/* axi_stream_inf.master*/ .master (sub_out_inf[1])
|
|
141
|
+
);
|
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142
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+
|
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143
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+
|
|
144
|
+
axi_stream_inf #(.DSIZE(origin_inf_cut_mix.DSIZE)) sub_origin_inf_cut_mix[2-1:0](.aclk(origin_inf_cut_mix.aclk),.aresetn(origin_inf_cut_mix.aresetn),.aclken(1'b1));
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|
145
|
+
|
|
146
|
+
|
|
147
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+
axis_direct axis_direct_origin_inf_cut_mix_inst0 (
|
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148
|
+
/* axi_stream_inf.slaver*/ .slaver (origin_inf_ss),
|
|
149
|
+
/* axi_stream_inf.master*/ .master (sub_origin_inf_cut_mix[0])
|
|
150
|
+
);
|
|
151
|
+
|
|
152
|
+
axis_direct axis_direct_origin_inf_cut_mix_inst1 (
|
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153
|
+
/* axi_stream_inf.slaver*/ .slaver (sub_origin_inf[2]),
|
|
154
|
+
/* axi_stream_inf.master*/ .master (sub_origin_inf_cut_mix[1])
|
|
155
|
+
);
|
|
156
|
+
initial begin
|
|
157
|
+
assert(DX<17)else begin
|
|
158
|
+
$error("param.DX<%0d> !< 17",DX);
|
|
159
|
+
$stop;
|
|
160
|
+
end
|
|
161
|
+
end
|
|
162
|
+
|
|
163
|
+
assign clock = origin_inf.aclk;
|
|
164
|
+
assign rst_n = origin_inf.aresetn;
|
|
165
|
+
|
|
166
|
+
always_comb begin
|
|
167
|
+
bytes_x_tmp = '0;
|
|
168
|
+
for(integer gvar_cc_1=0;gvar_cc_1<10;gvar_cc_1=gvar_cc_1+1)begin
|
|
169
|
+
if(bytes<DX*(10-gvar_cc_1))begin
|
|
170
|
+
bytes_x_tmp = (10-1)-gvar_cc_1;
|
|
171
|
+
end
|
|
172
|
+
end
|
|
173
|
+
end
|
|
174
|
+
|
|
175
|
+
assign origin_sync_info[0] = {bytes_x_tmp,bytes_x_tmp,bytes};
|
|
176
|
+
assign {bytes_x,bytes_Q} = {origin_sync_info_out[0][13:10],origin_sync_info_out[0][9:0]};
|
|
177
|
+
assign bytes_x_sub_nDx_tmp = bytes_Q-(bytes_x*DX);
|
|
178
|
+
assign origin_sync_info[1] = {bytes_x_sub_nDx_tmp,bytes_x,bytes_Q};
|
|
179
|
+
assign {bytes_x_sub_nDx,bytes_x_Q,bytes_QQ} = {origin_sync_info_out[1][17:14],origin_sync_info_out[1][13:10],origin_sync_info_out[1][9:0]};
|
|
180
|
+
assign origin_sync_info[2] = {10'd0,route_addr_tmp};
|
|
181
|
+
assign route_addr = origin_sync_info_out[2][1:0];
|
|
182
|
+
|
|
183
|
+
always_comb begin
|
|
184
|
+
if(bytes_QQ=='0)begin
|
|
185
|
+
route_addr_tmp = 2'd0;
|
|
186
|
+
end
|
|
187
|
+
else if(bytes_x_Q=='0)begin
|
|
188
|
+
route_addr_tmp = 2'd2;
|
|
189
|
+
end
|
|
190
|
+
else if(bytes_x_sub_nDx=='0)begin
|
|
191
|
+
route_addr_tmp = 2'd1;
|
|
192
|
+
end
|
|
193
|
+
else begin
|
|
194
|
+
route_addr_tmp = 2'd1;
|
|
195
|
+
end
|
|
196
|
+
end
|
|
197
|
+
|
|
198
|
+
always_ff@(posedge clock,negedge rst_n) begin
|
|
199
|
+
if(~rst_n)begin
|
|
200
|
+
fifo_wr_en <= 1'b0;
|
|
201
|
+
end
|
|
202
|
+
else begin
|
|
203
|
+
fifo_wr_en <= (origin_inf.axis_tcnt=='0&&origin_inf.axis_tvalid && origin_inf.axis_tready);
|
|
204
|
+
end
|
|
205
|
+
end
|
|
206
|
+
|
|
207
|
+
assign shift_sel_pre = DX-bytes_x_sub_nDx;
|
|
208
|
+
|
|
209
|
+
|
|
210
|
+
//----->> fifo_wr_en LAST DELAY <<------------------
|
|
211
|
+
latency #(
|
|
212
|
+
.LAT (2),
|
|
213
|
+
.DSIZE (1)
|
|
214
|
+
)fifo_wr_en_lat2_inst(
|
|
215
|
+
clock,
|
|
216
|
+
rst_n,
|
|
217
|
+
fifo_wr_en,
|
|
218
|
+
fifo_wr_en_lat
|
|
219
|
+
);
|
|
220
|
+
//-----<< fifo_wr_en LAST DELAY >>------------------
|
|
221
|
+
|
|
222
|
+
|
|
223
|
+
axi_stream_interconnect_M2S_A1 #(
|
|
224
|
+
//axi_stream_interconnect_M2S_noaddr #(
|
|
225
|
+
.NUM (2)
|
|
226
|
+
// .DSIZE (out_inf.DSIZE)
|
|
227
|
+
)out_inf_M2S_noaddr_inst(
|
|
228
|
+
/* axi_stream_inf.slaver */ .s00 (sub_out_inf ), //[NUM-1:0],
|
|
229
|
+
/* axi_stream_inf.master */ .m00 (out_inf) //
|
|
230
|
+
);
|
|
231
|
+
|
|
232
|
+
|
|
233
|
+
axi_stream_interconnect_M2S_A1 #(
|
|
234
|
+
//axi_stream_interconnect_M2S_noaddr #(
|
|
235
|
+
.NUM (2)
|
|
236
|
+
// .DSIZE (origin_inf.DSIZE)
|
|
237
|
+
)origin_inf_cut_mix_M2S_noaddr_inst(
|
|
238
|
+
/* axi_stream_inf.slaver */ .s00 (sub_origin_inf_cut_mix ), //[NUM-1:0],
|
|
239
|
+
/* axi_stream_inf.master */ .m00 (origin_inf_cut_mix) //
|
|
240
|
+
);
|
|
241
|
+
|
|
242
|
+
endmodule
|
|
@@ -0,0 +1,79 @@
|
|
|
1
|
+
/**********************************************
|
|
2
|
+
_______________________________________
|
|
3
|
+
___________ Cook Darwin __________
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
6
|
+
author : Cook.Darwin
|
|
7
|
+
Version: VERA.0.0
|
|
8
|
+
created: 2021-04-16 17:01:06 +0800
|
|
9
|
+
madified:
|
|
10
|
+
***********************************************/
|
|
11
|
+
`timescale 1ns/1ps
|
|
12
|
+
|
|
13
|
+
module axis_insert_copy (
|
|
14
|
+
input [15:0] insert_seed,
|
|
15
|
+
input [7:0] insert_len,
|
|
16
|
+
axi_stream_inf.slaver in_inf,
|
|
17
|
+
axi_stream_inf.master out_inf
|
|
18
|
+
);
|
|
19
|
+
|
|
20
|
+
//==========================================================================
|
|
21
|
+
//-------- define ----------------------------------------------------------
|
|
22
|
+
logic clock;
|
|
23
|
+
logic rst_n;
|
|
24
|
+
logic insert_tri;
|
|
25
|
+
axi_stream_inf #(.DSIZE(in_inf.DSIZE),.FreqM(in_inf.FreqM),.USIZE(1)) in_inf_valve (.aclk(in_inf.aclk),.aresetn(in_inf.aresetn),.aclken(1'b1)) ;
|
|
26
|
+
//==========================================================================
|
|
27
|
+
//-------- instance --------------------------------------------------------
|
|
28
|
+
axis_connect_pipe axis_connect_pipe_inst(
|
|
29
|
+
/* axi_stream_inf.slaver */.axis_in (in_inf_valve ),
|
|
30
|
+
/* axi_stream_inf.master */.axis_out (out_inf )
|
|
31
|
+
);
|
|
32
|
+
//==========================================================================
|
|
33
|
+
//-------- expression ------------------------------------------------------
|
|
34
|
+
assign clock = in_inf.aclk;
|
|
35
|
+
assign rst_n = in_inf.aresetn;
|
|
36
|
+
|
|
37
|
+
assign in_inf_valve.axis_tdata = in_inf.axis_tdata;
|
|
38
|
+
assign in_inf_valve.axis_tvalid = in_inf.axis_tvalid|insert_tri;
|
|
39
|
+
assign in_inf_valve.axis_tuser = in_inf.axis_tuser;
|
|
40
|
+
assign in_inf_valve.axis_tkeep = in_inf.axis_tkeep;
|
|
41
|
+
assign in_inf.axis_tready = in_inf_valve.axis_tready&~insert_tri;
|
|
42
|
+
assign in_inf_valve.axis_tlast = in_inf.axis_tlast&~insert_tri;
|
|
43
|
+
|
|
44
|
+
always_ff@(posedge clock,negedge rst_n) begin
|
|
45
|
+
if(~rst_n)begin
|
|
46
|
+
insert_tri <= 1'b0;
|
|
47
|
+
end
|
|
48
|
+
else begin
|
|
49
|
+
if(insert_seed=='0)begin
|
|
50
|
+
if(in_inf.axis_tvalid && in_inf.axis_tready && in_inf.axis_tlast)begin
|
|
51
|
+
insert_tri <= 1'b1;
|
|
52
|
+
end
|
|
53
|
+
else if(in_inf_valve.axis_tvalid && in_inf_valve.axis_tready)begin
|
|
54
|
+
insert_tri <= (in_inf_valve.axis_tcnt<(insert_len-1'b1));
|
|
55
|
+
end
|
|
56
|
+
else if(in_inf_valve.axis_tcnt=='0&&~(in_inf.axis_tvalid && in_inf.axis_tready))begin
|
|
57
|
+
insert_tri <= 1'b1;
|
|
58
|
+
end
|
|
59
|
+
else begin
|
|
60
|
+
insert_tri <= insert_tri;
|
|
61
|
+
end
|
|
62
|
+
end
|
|
63
|
+
else begin
|
|
64
|
+
if(in_inf_valve.axis_tvalid && in_inf_valve.axis_tready)begin
|
|
65
|
+
if(in_inf_valve.axis_tcnt>=(insert_seed-1'b1) &&(in_inf_valve.axis_tcnt<((insert_seed+insert_len)-1'b1))&&~in_inf.axis_tlast)begin
|
|
66
|
+
insert_tri <= 1'b1;
|
|
67
|
+
end
|
|
68
|
+
else begin
|
|
69
|
+
insert_tri <= 1'b0;
|
|
70
|
+
end
|
|
71
|
+
end
|
|
72
|
+
else begin
|
|
73
|
+
insert_tri <= insert_tri;
|
|
74
|
+
end
|
|
75
|
+
end
|
|
76
|
+
end
|
|
77
|
+
end
|
|
78
|
+
|
|
79
|
+
endmodule
|