axi_tdl 0.1.0 → 0.1.8

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Files changed (146) hide show
  1. checksums.yaml +4 -4
  2. data/Rakefile +7 -0
  3. data/lib/axi/AXI4/axi4_direct_A1.sv +1 -1
  4. data/lib/axi/AXI4/axi4_direct_verc.sv +54 -54
  5. data/lib/axi/AXI4/axi4_dpram_cache.rb +1 -0
  6. data/lib/axi/AXI4/axi4_dpram_cache.sv +10 -10
  7. data/lib/axi/AXI4/axi4_rd_burst_track.sv +2 -1
  8. data/lib/axi/AXI4/axi4_wr_burst_track.sv +2 -1
  9. data/lib/axi/AXI4/axis_to_axi4_wr.sv +9 -9
  10. data/lib/axi/AXI4/odata_pool_axi4_A3.sv +7 -0
  11. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +5 -5
  12. data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +8 -4
  13. data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +6 -6
  14. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +12 -12
  15. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +154 -0
  16. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +242 -0
  17. data/lib/axi/AXI_stream/axis_insert_copy.sv +79 -0
  18. data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +48 -0
  19. data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +113 -0
  20. data/lib/axi/AXI_stream/axis_sim_master_model.rb +2 -0
  21. data/lib/axi/AXI_stream/axis_sim_master_model.sv +46 -0
  22. data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
  23. data/lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv +50 -0
  24. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +2 -0
  25. data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +5 -3
  26. data/lib/axi/common/common_ram_sim_wrapper.sv +1 -1
  27. data/lib/axi/common/common_ram_wrapper.sv +1 -1
  28. data/lib/axi/common/test_write_mem.sv +1 -1
  29. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +13 -13
  30. data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +14 -11
  31. data/lib/axi/platform_ip/fifo_36kb_long.sv +1 -1
  32. data/lib/axi/platform_ip/long_fifo_verb.sv +1 -1
  33. data/lib/axi/platform_ip/wide_fifo.sv +1 -1
  34. data/lib/axi/platform_ip/xilinx_fifo_verb.sv +1 -1
  35. data/lib/axi/platform_ip/xilinx_fifo_verc.sv +2 -1
  36. data/lib/axi/techbench/tb_axi_stream_split_channel.rb +2 -1
  37. data/lib/axi/techbench/tb_axi_stream_split_channel.sv +46 -45
  38. data/lib/axi_tdl.rb +31 -1
  39. data/lib/axi_tdl/version.rb +1 -1
  40. data/lib/public_atom_module/CheckPClock.sv +53 -0
  41. data/lib/public_atom_module/LICENSE.md +674 -0
  42. data/lib/public_atom_module/altera_xilinx_always_block_sw.rb +57 -0
  43. data/lib/public_atom_module/bits_decode.sv +71 -0
  44. data/lib/public_atom_module/bits_decode_verb.sv +71 -0
  45. data/lib/public_atom_module/bits_decode_verb_sdl.rb +24 -0
  46. data/lib/public_atom_module/broaden.v +43 -0
  47. data/lib/public_atom_module/broaden_and_cross_clk.v +47 -0
  48. data/lib/public_atom_module/ceiling.v +39 -0
  49. data/lib/public_atom_module/ceiling_A1.v +42 -0
  50. data/lib/public_atom_module/clock_rst.sv +64 -0
  51. data/lib/public_atom_module/cross_clk_sync.v +37 -0
  52. data/lib/public_atom_module/edge_generator.v +50 -0
  53. data/lib/public_atom_module/flooring.v +36 -0
  54. data/lib/public_atom_module/latch_data.v +30 -0
  55. data/lib/public_atom_module/latency.v +48 -0
  56. data/lib/public_atom_module/latency_dynamic.v +83 -0
  57. data/lib/public_atom_module/latency_long.v +84 -0
  58. data/lib/public_atom_module/latency_verb.v +52 -0
  59. data/lib/public_atom_module/once_event.sv +65 -0
  60. data/lib/public_atom_module/pipe_reg.v +93 -0
  61. data/lib/public_atom_module/pipe_reg_2write_ports.v +84 -0
  62. data/lib/public_atom_module/sim/clock_rst_verb.sv +54 -0
  63. data/lib/public_atom_module/sim/clock_rst_verc.sv +69 -0
  64. data/lib/public_atom_module/sim/latency_long_tb.sv +49 -0
  65. data/lib/public_atom_module/sim/latency_long_tb.sv.bak +49 -0
  66. data/lib/public_atom_module/sim_system_pkg.sv +4 -0
  67. data/lib/public_atom_module/synth_system_pkg.sv +4 -0
  68. data/lib/tdl/Logic/logic_edge.rb +1 -1
  69. data/lib/tdl/auto_script/autogensdl.rb +2 -3
  70. data/lib/tdl/auto_script/import_hdl.rb +40 -5
  71. data/lib/tdl/axi4/axi4_interconnect_verb.rb +47 -10
  72. data/lib/tdl/class_hdl/hdl_always_comb.rb +4 -1
  73. data/lib/tdl/class_hdl/hdl_always_ff.rb +3 -3
  74. data/lib/tdl/class_hdl/hdl_assign.rb +7 -1
  75. data/lib/tdl/class_hdl/hdl_block_ifelse.rb +7 -7
  76. data/lib/tdl/class_hdl/hdl_foreach.rb +2 -2
  77. data/lib/tdl/class_hdl/hdl_function.rb +4 -4
  78. data/lib/tdl/class_hdl/hdl_generate.rb +5 -2
  79. data/lib/tdl/class_hdl/hdl_initial.rb +25 -3
  80. data/lib/tdl/class_hdl/hdl_module_def.rb +9 -6
  81. data/lib/tdl/class_hdl/hdl_package.rb +45 -0
  82. data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +99 -27
  83. data/lib/tdl/class_hdl/hdl_struct.rb +2 -2
  84. data/lib/tdl/elements/Reset.rb +5 -9
  85. data/lib/tdl/elements/clock.rb +5 -9
  86. data/lib/tdl/elements/data_inf.rb +0 -17
  87. data/lib/tdl/elements/logic.rb +9 -31
  88. data/lib/tdl/elements/mail_box.rb +6 -1
  89. data/lib/tdl/elements/originclass.rb +17 -47
  90. data/lib/tdl/elements/parameter.rb +5 -6
  91. data/lib/tdl/examples/11_test_unit/dve.tcl +6 -153
  92. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +2 -2
  93. data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +9 -0
  94. data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +2 -2
  95. data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +2 -2
  96. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -1
  97. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +41 -0
  98. data/lib/tdl/examples/11_test_unit/tu0.sv +2 -1
  99. data/lib/tdl/examples/1_define_module/exmple_md.sv +1 -1
  100. data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +3 -3
  101. data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +3 -3
  102. data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +3 -3
  103. data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +1 -1
  104. data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +3 -3
  105. data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +3 -3
  106. data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +1 -1
  107. data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +3 -3
  108. data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +2 -2
  109. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +7 -7
  110. data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +4 -3
  111. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
  112. data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +2 -2
  113. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +1 -1
  114. data/lib/tdl/examples/6_module_with_interface/example_interface.sv +8 -8
  115. data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +9 -9
  116. data/lib/tdl/examples/7_module_with_package/body_package.sv +4 -3
  117. data/lib/tdl/examples/7_module_with_package/example_pkg.sv +1 -1
  118. data/lib/tdl/examples/7_module_with_package/head_package.sv +4 -3
  119. data/lib/tdl/examples/8_top_module/dve.tcl +6 -0
  120. data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -1
  121. data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +29 -0
  122. data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
  123. data/lib/tdl/examples/8_top_module/test_top_sim.sv +9 -0
  124. data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +2 -1
  125. data/lib/tdl/examples/9_itegration/dve.tcl +155 -2
  126. data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +1 -1
  127. data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +1 -1
  128. data/lib/tdl/examples/9_itegration/test_tttop.sv +7 -38
  129. data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +38 -7
  130. data/lib/tdl/exlib/axis_verify.rb +4 -3
  131. data/lib/tdl/exlib/constraints_verb.rb +1 -0
  132. data/lib/tdl/exlib/itegration_verb.rb +47 -41
  133. data/lib/tdl/rebuild_ele/ele_base.rb +15 -10
  134. data/lib/tdl/sdlmodule/sdlmodule.rb +117 -51
  135. data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +1 -1
  136. data/lib/tdl/sdlmodule/sdlmodule_draw.rb +2 -2
  137. data/lib/tdl/sdlmodule/sdlmodule_instance.rb +3 -0
  138. data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +6 -6
  139. data/lib/tdl/sdlmodule/sdlmodule_varible.rb +6 -6
  140. data/lib/tdl/sdlmodule/test_unit_module.rb +6 -0
  141. data/lib/tdl/sdlmodule/top_module.rb +4 -0
  142. data/lib/tdl/tdl.rb +1 -11
  143. data/lib/tdl/tdlerror/tdlerror.rb +1 -1
  144. metadata +43 -5
  145. data/CODE_OF_CONDUCT.md +0 -74
  146. data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +0 -87
data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
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  descript:
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  author : Cook.Darwin
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  Version: VERA.0.0
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- created: xxxx.xx.xx
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+ created: 2021-04-03 13:47:04 +0800
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  madified:
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  ***********************************************/
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  `timescale 1ns/1ps
data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
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  descript:
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  author : Cook.Darwin
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  Version: VERA.0.0
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- created: xxxx.xx.xx
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+ created: 2021-05-04 20:03:33 +0800
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  madified:
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  ***********************************************/
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  `timescale 1ns/1ps
@@ -21,9 +21,9 @@ module test_module (
21
21
  //==========================================================================
22
22
  //-------- define ----------------------------------------------------------
23
23
  logic [axi_wr_inf.ASIZE-1:0] addr ;
24
- logic [axi_wr_inf.IDSIZE-4-1:0] id ;
24
+ logic [(axi_wr_inf.IDSIZE - 4)-1:0] id ;
25
25
  logic [24-1:0] length ;
26
- axi_inf #(.DSIZE(axi_wr_inf.DSIZE),.IDSIZE(axi_wr_inf.IDSIZE-4),.ASIZE(axi_wr_inf.ASIZE),.LSIZE(24),.MODE("ONLY_WRITE"),.ADDR_STEP(8192)) pre_axi_wr_inf (.axi_aclk(axi_wr_inf.axi_aclk),.axi_aresetn(axi_wr_inf.axi_aresetn)) ;
26
+ axi_inf #(.DSIZE(axi_wr_inf.DSIZE),.IDSIZE((axi_wr_inf.IDSIZE - 4)),.ASIZE(axi_wr_inf.ASIZE),.LSIZE(24),.MODE("ONLY_WRITE"),.ADDR_STEP(8192),.FreqM(1.0)) pre_axi_wr_inf (.axi_aclk(axi_wr_inf.axi_aclk),.axi_aresetn(axi_wr_inf.axi_aresetn)) ;
27
27
  //==========================================================================
28
28
  //-------- instance --------------------------------------------------------
29
29
  axi_stream_cache_35bit cache_inst(
data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
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  descript:
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  author : Cook.Darwin
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  Version: VERA.0.0
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- created: xxxx.xx.xx
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+ created: 2021-05-04 20:03:33 +0800
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  ***********************************************/
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  `timescale 1ns/1ps
@@ -21,7 +21,7 @@ module test_module_port (
21
21
  //==========================================================================
22
22
  //-------- define ----------------------------------------------------------
23
23
 
24
- data_inf_c #(.DSIZE(test_data_inf_c.DSIZE)) inherited_inf (.clock(test_data_inf_c.clock),.rst_n(test_data_inf_c.rst_n)) ;
24
+ data_inf_c #(.DSIZE(test_data_inf_c.DSIZE),.FreqM(test_data_inf_c.FreqM)) inherited_inf (.clock(test_data_inf_c.clock),.rst_n(test_data_inf_c.rst_n)) ;
25
25
  //==========================================================================
26
26
  //-------- instance --------------------------------------------------------
27
27
  test_module_port_sub test_module_port_sub_inst(
data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
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- created: 2021-03-20 20:34:51 +0800
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+ created: 2021-05-30 12:21:35 +0800
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  `timescale 1ns/1ps
@@ -19,13 +19,13 @@ module test_module_var #(
19
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20
20
  //==========================================================================
21
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  //-------- define ----------------------------------------------------------
22
- localparam ASIZE = 20;
23
- axi_stream_inf #(.DSIZE(8),.USIZE(1)) tmp_axis_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
24
- axi_stream_inf #(.DSIZE(8),.USIZE(1)) tmp_axis0_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
25
- axi_inf #(.DSIZE(32),.IDSIZE(2),.ASIZE(8),.LSIZE(9),.MODE("BOTH"),.ADDR_STEP(4294967295)) tmp_axi4_inf (.axi_aclk(clock),.axi_aresetn(rst_n)) ;
22
+ localparam ASIZE = 20 ;
23
+ axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) tmp_axis_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
24
+ axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) tmp_axis0_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
25
+ axi_inf #(.DSIZE(32),.IDSIZE(2),.ASIZE(8),.LSIZE(9),.MODE("BOTH"),.ADDR_STEP(4294967295),.FreqM(100)) tmp_axi4_inf (.axi_aclk(clock),.axi_aresetn(rst_n)) ;
26
26
  data_inf #(.DSIZE(5)) tmp_data_inf();
27
- data_inf_c #(.DSIZE(3)) tmp_data_inf_c (.clock(clock),.rst_n(rst_n)) ;
28
- data_inf_c #(.DSIZE(3)) opopopopo (.clock(clock),.rst_n(rst_n)) ;
27
+ data_inf_c #(.DSIZE(3),.FreqM(100)) tmp_data_inf_c (.clock(clock),.rst_n(rst_n)) ;
28
+ data_inf_c #(.DSIZE(3),.FreqM(100)) opopopopo (.clock(clock),.rst_n(rst_n)) ;
29
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  //==========================================================================
30
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  //-------- instance --------------------------------------------------------
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data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv CHANGED
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  descript:
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  author : Cook.Darwin
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  Version: VERA.0.0
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- created: 2021-03-20 12:10:27 +0800
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+ created: 2021-04-03 12:04:33 +0800
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- module test_packageparameter NUM = 6;();
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+ package test_package;
14
+ parameter NUM = 6;
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  //==========================================================================
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  //-------- define ----------------------------------------------------------
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  typedef struct {
@@ -34,4 +35,4 @@ s_ing s_ing_v1;
34
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  //-------- expression ------------------------------------------------------
35
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  assign zing_v0.op[9] = 0;
36
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37
- endmodule
38
+ endpackage:test_package
data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv CHANGED
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  descript:
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  author : Cook.Darwin
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  Version: VERA.0.0
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- created: 2021-03-21 10:19:17 +0800
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+ created: 2021-05-30 12:21:54 +0800
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  ***********************************************/
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  `timescale 1ns/1ps
data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
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  descript:
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  author : Cook.Darwin
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  Version: VERA.0.0
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- created: xxxx.xx.xx
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+ created: 2021-05-04 20:03:33 +0800
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@@ -19,7 +19,7 @@ module main_md (
19
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  //==========================================================================
20
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  //-------- define ----------------------------------------------------------
21
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22
- axi_stream_inf #(.DSIZE(8),.USIZE(1)) tmp_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
22
+ axi_stream_inf #(.DSIZE(8),.FreqM(100),.USIZE(1)) tmp_inf (.aclk(clock),.aresetn(rst_n),.aclken(1'b1)) ;
23
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  //==========================================================================
24
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  //-------- instance --------------------------------------------------------
25
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  sdl_md sdl_md_inst(
data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
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  descript:
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  author : Cook.Darwin
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  Version: VERA.0.0
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- created: xxxx.xx.xx
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+ created: 2021-04-03 13:14:02 +0800
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  madified:
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  ***********************************************/
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  `timescale 1ns/1ps
data/lib/tdl/examples/6_module_with_interface/example_interface.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
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  descript:
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  author : Cook.Darwin
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  Version: VERA.0.0
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- created: xxxx.xx.xx
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+ created: 2021-05-04 20:03:32 +0800
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@@ -24,13 +24,13 @@ module example_interface (
24
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  //==========================================================================
25
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  //-------- define ----------------------------------------------------------
26
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27
- data_inf_c #(.DSIZE(8)) a_inf (.clock(dim.clock),.rst_n(dim.clock)) ;
28
- data_inf_c #(.DSIZE(8)) c_inf [7:0] (.clock(dim.clock),.rst_n(dim.clock)) ;
29
- axi_stream_inf #(.DSIZE(8),.USIZE(1)) f_inf (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
30
- axi_stream_inf #(.DSIZE(8),.USIZE(1)) g_inf [1:0] (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
31
- axi_lite_inf #(.DSIZE(32),.ASIZE(32)) h_inf (.axi_aclk(alm.axi_aclk),.axi_aresetn(alm.axi_aresetn)) ;
32
- axi_inf #(.DSIZE(32),.IDSIZE(3),.ASIZE(32),.LSIZE(10),.MODE("BOTH"),.ADDR_STEP(4096)) i_inf (.axi_aclk(a4m.axi_aclk),.axi_aresetn(a4m.axi_aresetn)) ;
33
- axi_inf #(.DSIZE(31),.IDSIZE(3),.ASIZE(37),.LSIZE(12),.MODE("BOTH"),.ADDR_STEP(1024)) j_inf [8:0][4:0][2:0] (.axi_aclk(a4m.axi_aclk),.axi_aresetn(a4m.axi_aresetn)) ;
27
+ data_inf_c #(.DSIZE(8),.FreqM(101)) a_inf (.clock(dim.clock),.rst_n(dim.clock)) ;
28
+ data_inf_c #(.DSIZE(8),.FreqM(101)) c_inf [7:0] (.clock(dim.clock),.rst_n(dim.clock)) ;
29
+ axi_stream_inf #(.DSIZE(8),.FreqM(1.0),.USIZE(1)) f_inf (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
30
+ axi_stream_inf #(.DSIZE(8),.FreqM(1.0),.USIZE(1)) g_inf [1:0] (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
31
+ axi_lite_inf #(.DSIZE(32),.ASIZE(32),.FreqM(103)) h_inf (.axi_aclk(alm.axi_aclk),.axi_aresetn(alm.axi_aresetn)) ;
32
+ axi_inf #(.DSIZE(32),.IDSIZE(3),.ASIZE(32),.LSIZE(10),.MODE("BOTH"),.ADDR_STEP(4096),.FreqM(103)) i_inf (.axi_aclk(a4m.axi_aclk),.axi_aresetn(a4m.axi_aresetn)) ;
33
+ axi_inf #(.DSIZE(31),.IDSIZE(3),.ASIZE(37),.LSIZE(12),.MODE("BOTH"),.ADDR_STEP(1024),.FreqM(103)) j_inf [8:0][4:0][2:0] (.axi_aclk(a4m.axi_aclk),.axi_aresetn(a4m.axi_aresetn)) ;
34
34
  //==========================================================================
35
35
  //-------- instance --------------------------------------------------------
36
36
 
data/lib/tdl/examples/6_module_with_interface/inf_collect.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-05-04 20:03:32 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -24,14 +24,14 @@ module inf_collect (
24
24
  //==========================================================================
25
25
  //-------- define ----------------------------------------------------------
26
26
 
27
- data_inf_c #(.DSIZE(8)) a_inf (.clock(dim.clock),.rst_n(dim.clock)) ;
28
- data_inf_c #(.DSIZE(8)) c_inf [7:0] (.clock(dim.clock),.rst_n(dim.clock)) ;
29
- axi_stream_inf #(.DSIZE(8),.USIZE(1)) f_inf (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
30
- axi_stream_inf #(.DSIZE(8),.USIZE(1)) p_inf (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
31
- axi_stream_inf #(.DSIZE(8),.USIZE(1)) g_inf [1:0] (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
32
- axi_lite_inf #(.DSIZE(32),.ASIZE(32)) h_inf (.axi_aclk(alm.axi_aclk),.axi_aresetn(alm.axi_aresetn)) ;
33
- axi_inf #(.DSIZE(32),.IDSIZE(3),.ASIZE(32),.LSIZE(10),.MODE("BOTH"),.ADDR_STEP(4096)) i_inf (.axi_aclk(a4m.axi_aclk),.axi_aresetn(a4m.axi_aresetn)) ;
34
- axi_inf #(.DSIZE(31),.IDSIZE(3),.ASIZE(37),.LSIZE(12),.MODE("BOTH"),.ADDR_STEP(1024)) j_inf [8:0][4:0][2:0] (.axi_aclk(a4m.axi_aclk),.axi_aresetn(a4m.axi_aresetn)) ;
27
+ data_inf_c #(.DSIZE(8),.FreqM(101)) a_inf (.clock(dim.clock),.rst_n(dim.clock)) ;
28
+ data_inf_c #(.DSIZE(8),.FreqM(101)) c_inf [7:0] (.clock(dim.clock),.rst_n(dim.clock)) ;
29
+ axi_stream_inf #(.DSIZE(8),.FreqM(1.0),.USIZE(1)) f_inf (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
30
+ axi_stream_inf #(.DSIZE(8),.FreqM(1.0),.USIZE(1)) p_inf (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
31
+ axi_stream_inf #(.DSIZE(8),.FreqM(1.0),.USIZE(1)) g_inf [1:0] (.aclk(asis.aclk),.aresetn(asis.aresetn),.aclken(1'b1)) ;
32
+ axi_lite_inf #(.DSIZE(32),.ASIZE(32),.FreqM(103)) h_inf (.axi_aclk(alm.axi_aclk),.axi_aresetn(alm.axi_aresetn)) ;
33
+ axi_inf #(.DSIZE(32),.IDSIZE(3),.ASIZE(32),.LSIZE(10),.MODE("BOTH"),.ADDR_STEP(4096),.FreqM(103)) i_inf (.axi_aclk(a4m.axi_aclk),.axi_aresetn(a4m.axi_aresetn)) ;
34
+ axi_inf #(.DSIZE(31),.IDSIZE(3),.ASIZE(37),.LSIZE(12),.MODE("BOTH"),.ADDR_STEP(1024),.FreqM(103)) j_inf [8:0][4:0][2:0] (.axi_aclk(a4m.axi_aclk),.axi_aresetn(a4m.axi_aresetn)) ;
35
35
  //==========================================================================
36
36
  //-------- instance --------------------------------------------------------
37
37
 
data/lib/tdl/examples/7_module_with_package/body_package.sv CHANGED
@@ -5,12 +5,13 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: 2021-03-20 12:10:27 +0800
8
+ created: 2021-04-03 12:04:33 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
 
12
12
 
13
- module body_packageparameter BDSIZE = 10;();
13
+ package body_package;
14
+ parameter BDSIZE = 10;
14
15
  //==========================================================================
15
16
  //-------- define ----------------------------------------------------------
16
17
 
@@ -21,4 +22,4 @@ module body_packageparameter BDSIZE = 10;();
21
22
  //==========================================================================
22
23
  //-------- expression ------------------------------------------------------
23
24
 
24
- endmodule
25
+ endpackage:body_package
data/lib/tdl/examples/7_module_with_package/example_pkg.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-04-03 13:14:02 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
data/lib/tdl/examples/7_module_with_package/head_package.sv CHANGED
@@ -5,12 +5,13 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: 2021-03-20 12:10:27 +0800
8
+ created: 2021-04-03 12:04:33 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
 
12
12
 
13
- module head_packageparameter HDSIZE = 8;();
13
+ package head_package;
14
+ parameter HDSIZE = 8;
14
15
  //==========================================================================
15
16
  //-------- define ----------------------------------------------------------
16
17
  typedef struct {
@@ -25,4 +26,4 @@ logic valid;
25
26
  //==========================================================================
26
27
  //-------- expression ------------------------------------------------------
27
28
 
28
- endmodule
29
+ endpackage:head_package
data/lib/tdl/examples/8_top_module/dve.tcl CHANGED
@@ -13,6 +13,8 @@ gui_set_time_units 1ps
13
13
  ## ==== [add_signal] ===== ##
14
14
 
15
15
 
16
+
17
+
16
18
  ## 创建波形窗口
17
19
  if {![info exists useOldWindow]} {
18
20
  set useOldWindow true
@@ -42,6 +44,8 @@ gui_wv_zoom_timerange -id ${Wave.3} 0 1000000000
42
44
  ## === [add_signal_wave] === ##
43
45
 
44
46
 
47
+
48
+
45
49
  gui_seek_criteria -id ${Wave.3} {Any Edge}
46
50
 
47
51
 
@@ -59,6 +63,8 @@ gui_list_set_filter -id ${Wave.3} -text {*}
59
63
  ## === [add_bar] === ##
60
64
 
61
65
 
66
+
67
+
62
68
  gui_marker_move -id ${Wave.3} {C1} 560248001
63
69
  gui_view_scroll -id ${Wave.3} -vertical -set 35
64
70
  gui_show_grid -id ${Wave.3} -enable false
data/lib/tdl/examples/8_top_module/tb_test_top.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: 2021-03-20 12:10:27 +0800
8
+ created: 2021-04-03 14:05:10 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv ADDED
@@ -0,0 +1,29 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ created: 2021-04-03 13:35:39 +0800
9
+ madified:
10
+ ***********************************************/
11
+ `timescale 1ns/1ps
12
+
13
+ module tb_test_top_sim();
14
+ //==========================================================================
15
+ //-------- define ----------------------------------------------------------
16
+ string test_unit_region;
17
+ logic [0-1:0] unit_pass_u ;
18
+ logic [0-1:0] unit_pass_d ;
19
+
20
+ //==========================================================================
21
+ //-------- instance --------------------------------------------------------
22
+ test_top_sim rtl_top(
23
+ /* input clock */.sys_clock ( ),
24
+ /* output */.odata ( )
25
+ );
26
+ //==========================================================================
27
+ //-------- expression ------------------------------------------------------
28
+
29
+ endmodule
data/lib/tdl/examples/8_top_module/test_top.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-05-30 12:21:54 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
data/lib/tdl/examples/8_top_module/test_top_sim.sv ADDED
@@ -0,0 +1,9 @@
1
+
2
+ `timescale 1ns/1ps
3
+ module test_top_sim();
4
+ initial begin
5
+ #(1us);
6
+ $warning("Check TopModule.sim,please!!!");
7
+ $stop;
8
+ end
9
+ endmodule
data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: 2021-03-20 23:48:13 +0800
8
+ created: 2021-05-04 20:03:49 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -28,6 +28,7 @@ initial begin
28
28
  to_down_pass = 1'b0;
29
29
  wait(from_up_pass);
30
30
  $root.tb_test_tttop_sim.test_unit_region = "test_clock_bb";
31
+ $display("--------------- Current test_unit <%0s> --------------------", "test_clock_bb");
31
32
  to_down_pass = 1'b1;
32
33
  end
33
34
 
data/lib/tdl/examples/9_itegration/dve.tcl CHANGED
@@ -12,6 +12,128 @@ gui_set_time_units 1ps
12
12
  ## gui_sg_addsignal -group "$_wave_session_group" { {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.test_fpga_version_inst.ctrl_udp_rd_version} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.to_ctrl_tap_in_inf} {Sim:tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf} {Sim:tb_Mammo_TCP_sim.g1_test_mac_1g_inst.tcp_udp_proto_workshop_1G_inst.genblk1[0].tcp_data_stack_top_inst.client_port} }
13
13
  ## ==== [add_signal] ===== ##
14
14
 
15
+ ## -------------- sub_md0_logic -------------------------
16
+ set _wave_session_group_sub_md0_logic sub_md0_logic
17
+ # set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name -seed sub_md0_logic]
18
+ if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_logic"]} {
19
+ set _wave_session_group_sub_md0_logic [gui_sg_generate_new_name]
20
+ }
21
+ set Group2_sub_md0_logic "$_wave_session_group_sub_md0_logic"
22
+
23
+ ## 添加信号到 group
24
+ gui_sg_addsignal -group "$_wave_session_group_sub_md0_logic" { {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.cnt} }
25
+ ## ============== sub_md0_logic =========================
26
+
27
+
28
+ ## -------------- sub_md0_interface -------------------------
29
+ set _wave_session_group_sub_md0_interface sub_md0_interface
30
+ # set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name -seed sub_md0_interface]
31
+ if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_interface"]} {
32
+ set _wave_session_group_sub_md0_interface [gui_sg_generate_new_name]
33
+ }
34
+ set Group2_sub_md0_interface "$_wave_session_group_sub_md0_interface"
35
+
36
+ ## 添加信号到 group
37
+ gui_sg_addsignal -group "$_wave_session_group_sub_md0_interface" { {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.axis_in} }
38
+ ## ============== sub_md0_interface =========================
39
+
40
+
41
+ ## -------------- sub_md0_default -------------------------
42
+ set _wave_session_group_sub_md0_default sub_md0_default
43
+ # set _wave_session_group_sub_md0_default [gui_sg_generate_new_name -seed sub_md0_default]
44
+ if {[gui_sg_is_group -name "$_wave_session_group_sub_md0_default"]} {
45
+ set _wave_session_group_sub_md0_default [gui_sg_generate_new_name]
46
+ }
47
+ set Group2_sub_md0_default "$_wave_session_group_sub_md0_default"
48
+
49
+ ## 添加信号到 group
50
+ gui_sg_addsignal -group "$_wave_session_group_sub_md0_default" { }
51
+ ## ============== sub_md0_default =========================
52
+
53
+
54
+ ## -------------- sub_md0_default.inter_tf -------------------------
55
+ ## set _wave_session_group_sub_md0_default_inter_tf Group1
56
+ ## set _wave_session_group_sub_md0_default_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md0_default ]
57
+
58
+ set _wave_session_group_sub_md0_default_inter_tf $_wave_session_group_sub_md0_default|
59
+ append _wave_session_group_sub_md0_default_inter_tf inter_tf
60
+ set sub_md0_default|inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
61
+
62
+ # set Group2_sub_md0_default_inter_tf "$_wave_session_group_sub_md0_default_inter_tf"
63
+
64
+ ## 添加信号到 group
65
+ gui_sg_addsignal -group "$_wave_session_group_sub_md0_default_inter_tf" { {Sim:tb_exp_test_unit.rtl_top.sub_md0_inst.inter_tf} }
66
+ ## ============== sub_md0_default.inter_tf =========================
67
+
68
+
69
+ ## -------------- sub_md1_default -------------------------
70
+ set _wave_session_group_sub_md1_default sub_md1_default
71
+ # set _wave_session_group_sub_md1_default [gui_sg_generate_new_name -seed sub_md1_default]
72
+ if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_default"]} {
73
+ set _wave_session_group_sub_md1_default [gui_sg_generate_new_name]
74
+ }
75
+ set Group2_sub_md1_default "$_wave_session_group_sub_md1_default"
76
+
77
+ ## 添加信号到 group
78
+ gui_sg_addsignal -group "$_wave_session_group_sub_md1_default" { {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.cnt} {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.axis_out} {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.enable} }
79
+ ## ============== sub_md1_default =========================
80
+
81
+
82
+ ## -------------- sub_md1_inner -------------------------
83
+ set _wave_session_group_sub_md1_inner sub_md1_inner
84
+ # set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name -seed sub_md1_inner]
85
+ if {[gui_sg_is_group -name "$_wave_session_group_sub_md1_inner"]} {
86
+ set _wave_session_group_sub_md1_inner [gui_sg_generate_new_name]
87
+ }
88
+ set Group2_sub_md1_inner "$_wave_session_group_sub_md1_inner"
89
+
90
+ ## 添加信号到 group
91
+ gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner" { }
92
+ ## ============== sub_md1_inner =========================
93
+
94
+
95
+ ## -------------- sub_md1_inner.inter_tf -------------------------
96
+ ## set _wave_session_group_sub_md1_inner_inter_tf Group1
97
+ ## set _wave_session_group_sub_md1_inner_inter_tf [gui_sg_generate_new_name -seed inter_tf -parent $_wave_session_group_sub_md1_inner ]
98
+
99
+ set _wave_session_group_sub_md1_inner_inter_tf $_wave_session_group_sub_md1_inner|
100
+ append _wave_session_group_sub_md1_inner_inter_tf inter_tf
101
+ set sub_md1_inner|inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
102
+
103
+ # set Group2_sub_md1_inner_inter_tf "$_wave_session_group_sub_md1_inner_inter_tf"
104
+
105
+ ## 添加信号到 group
106
+ gui_sg_addsignal -group "$_wave_session_group_sub_md1_inner_inter_tf" { {Sim:tb_exp_test_unit.rtl_top.sub_md1_inst.inter_tf} }
107
+ ## ============== sub_md1_inner.inter_tf =========================
108
+
109
+
110
+ ## -------------- exp_test_unit_default -------------------------
111
+ set _wave_session_group_exp_test_unit_default exp_test_unit_default
112
+ # set _wave_session_group_exp_test_unit_default [gui_sg_generate_new_name -seed exp_test_unit_default]
113
+ if {[gui_sg_is_group -name "$_wave_session_group_exp_test_unit_default"]} {
114
+ set _wave_session_group_exp_test_unit_default [gui_sg_generate_new_name]
115
+ }
116
+ set Group2_exp_test_unit_default "$_wave_session_group_exp_test_unit_default"
117
+
118
+ ## 添加信号到 group
119
+ gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_default" { }
120
+ ## ============== exp_test_unit_default =========================
121
+
122
+
123
+ ## -------------- exp_test_unit_default.axis_data_inf -------------------------
124
+ ## set _wave_session_group_exp_test_unit_default_axis_data_inf Group1
125
+ ## set _wave_session_group_exp_test_unit_default_axis_data_inf [gui_sg_generate_new_name -seed axis_data_inf -parent $_wave_session_group_exp_test_unit_default ]
126
+
127
+ set _wave_session_group_exp_test_unit_default_axis_data_inf $_wave_session_group_exp_test_unit_default|
128
+ append _wave_session_group_exp_test_unit_default_axis_data_inf axis_data_inf
129
+ set exp_test_unit_default|axis_data_inf "$_wave_session_group_exp_test_unit_default_axis_data_inf"
130
+
131
+ # set Group2_exp_test_unit_default_axis_data_inf "$_wave_session_group_exp_test_unit_default_axis_data_inf"
132
+
133
+ ## 添加信号到 group
134
+ gui_sg_addsignal -group "$_wave_session_group_exp_test_unit_default_axis_data_inf" { {Sim:tb_exp_test_unit.rtl_top.axis_data_inf} }
135
+ ## ============== exp_test_unit_default.axis_data_inf =========================
136
+
15
137
 
16
138
  ## 创建波形窗口
17
139
  if {![info exists useOldWindow]} {
@@ -40,7 +162,33 @@ gui_wv_zoom_timerange -id ${Wave.3} 0 1000000000
40
162
  ## gui_list_add_group -id ${Wave.3} -after ${Group2} [list ${Group2|tx_inf}]
41
163
  ## gui_list_expand -id ${Wave.3} tb_Mammo_TCP_sim.rtl_top.fpga_version_verb.ctrl_tap_inf
42
164
  ## === [add_signal_wave] === ##
43
-
165
+ ## -------------- Group2_sub_md0_logic -------------------------
166
+ gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_logic}]
167
+ ## ============== Group2_sub_md0_logic =========================
168
+ ## -------------- Group2_sub_md0_interface -------------------------
169
+ gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_interface}]
170
+ ## ============== Group2_sub_md0_interface =========================
171
+ ## -------------- Group2_sub_md0_default -------------------------
172
+ gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md0_default}]
173
+ ## ============== Group2_sub_md0_default =========================
174
+ ## -------------- sub_md0_default|inter_tf -------------------------
175
+ gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md0_default|inter_tf}]
176
+ ## ============== sub_md0_default|inter_tf =========================
177
+ ## -------------- Group2_sub_md1_default -------------------------
178
+ gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_default}]
179
+ ## ============== Group2_sub_md1_default =========================
180
+ ## -------------- Group2_sub_md1_inner -------------------------
181
+ gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_sub_md1_inner}]
182
+ ## ============== Group2_sub_md1_inner =========================
183
+ ## -------------- sub_md1_inner|inter_tf -------------------------
184
+ gui_list_add_group -id ${Wave.3} -after {New Group} [list ${sub_md1_inner|inter_tf}]
185
+ ## ============== sub_md1_inner|inter_tf =========================
186
+ ## -------------- Group2_exp_test_unit_default -------------------------
187
+ gui_list_add_group -id ${Wave.3} -after {New Group} [list ${Group2_exp_test_unit_default}]
188
+ ## ============== Group2_exp_test_unit_default =========================
189
+ ## -------------- exp_test_unit_default|axis_data_inf -------------------------
190
+ gui_list_add_group -id ${Wave.3} -after {New Group} [list ${exp_test_unit_default|axis_data_inf}]
191
+ ## ============== exp_test_unit_default|axis_data_inf =========================
44
192
 
45
193
  gui_seek_criteria -id ${Wave.3} {Any Edge}
46
194
 
@@ -57,7 +205,12 @@ gui_list_set_filter -id ${Wave.3} -list { {Buffer 1} {Input 1} {Others 1} {Linka
57
205
  gui_list_set_filter -id ${Wave.3} -text {*}
58
206
  ##gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2} -position in
59
207
  ## === [add_bar] === ##
60
-
208
+ gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_logic} -position in
209
+ gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_interface} -position in
210
+ gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md0_default} -position in
211
+ gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md1_default} -position in
212
+ gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_sub_md1_inner} -position in
213
+ gui_list_set_insertion_bar -id ${Wave.3} -group ${Group2_exp_test_unit_default} -position in
61
214
 
62
215
  gui_marker_move -id ${Wave.3} {C1} 560248001
63
216
  gui_view_scroll -id ${Wave.3} -vertical -set 35