axi_tdl 0.1.0 → 0.1.8

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Files changed (146) hide show
  1. checksums.yaml +4 -4
  2. data/Rakefile +7 -0
  3. data/lib/axi/AXI4/axi4_direct_A1.sv +1 -1
  4. data/lib/axi/AXI4/axi4_direct_verc.sv +54 -54
  5. data/lib/axi/AXI4/axi4_dpram_cache.rb +1 -0
  6. data/lib/axi/AXI4/axi4_dpram_cache.sv +10 -10
  7. data/lib/axi/AXI4/axi4_rd_burst_track.sv +2 -1
  8. data/lib/axi/AXI4/axi4_wr_burst_track.sv +2 -1
  9. data/lib/axi/AXI4/axis_to_axi4_wr.sv +9 -9
  10. data/lib/axi/AXI4/odata_pool_axi4_A3.sv +7 -0
  11. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +5 -5
  12. data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +8 -4
  13. data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +6 -6
  14. data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +12 -12
  15. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +154 -0
  16. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +242 -0
  17. data/lib/axi/AXI_stream/axis_insert_copy.sv +79 -0
  18. data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +48 -0
  19. data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +113 -0
  20. data/lib/axi/AXI_stream/axis_sim_master_model.rb +2 -0
  21. data/lib/axi/AXI_stream/axis_sim_master_model.sv +46 -0
  22. data/lib/axi/AXI_stream/axis_split_channel_verb.sv +62 -0
  23. data/lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv +50 -0
  24. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +2 -0
  25. data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +5 -3
  26. data/lib/axi/common/common_ram_sim_wrapper.sv +1 -1
  27. data/lib/axi/common/common_ram_wrapper.sv +1 -1
  28. data/lib/axi/common/test_write_mem.sv +1 -1
  29. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +13 -13
  30. data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +14 -11
  31. data/lib/axi/platform_ip/fifo_36kb_long.sv +1 -1
  32. data/lib/axi/platform_ip/long_fifo_verb.sv +1 -1
  33. data/lib/axi/platform_ip/wide_fifo.sv +1 -1
  34. data/lib/axi/platform_ip/xilinx_fifo_verb.sv +1 -1
  35. data/lib/axi/platform_ip/xilinx_fifo_verc.sv +2 -1
  36. data/lib/axi/techbench/tb_axi_stream_split_channel.rb +2 -1
  37. data/lib/axi/techbench/tb_axi_stream_split_channel.sv +46 -45
  38. data/lib/axi_tdl.rb +31 -1
  39. data/lib/axi_tdl/version.rb +1 -1
  40. data/lib/public_atom_module/CheckPClock.sv +53 -0
  41. data/lib/public_atom_module/LICENSE.md +674 -0
  42. data/lib/public_atom_module/altera_xilinx_always_block_sw.rb +57 -0
  43. data/lib/public_atom_module/bits_decode.sv +71 -0
  44. data/lib/public_atom_module/bits_decode_verb.sv +71 -0
  45. data/lib/public_atom_module/bits_decode_verb_sdl.rb +24 -0
  46. data/lib/public_atom_module/broaden.v +43 -0
  47. data/lib/public_atom_module/broaden_and_cross_clk.v +47 -0
  48. data/lib/public_atom_module/ceiling.v +39 -0
  49. data/lib/public_atom_module/ceiling_A1.v +42 -0
  50. data/lib/public_atom_module/clock_rst.sv +64 -0
  51. data/lib/public_atom_module/cross_clk_sync.v +37 -0
  52. data/lib/public_atom_module/edge_generator.v +50 -0
  53. data/lib/public_atom_module/flooring.v +36 -0
  54. data/lib/public_atom_module/latch_data.v +30 -0
  55. data/lib/public_atom_module/latency.v +48 -0
  56. data/lib/public_atom_module/latency_dynamic.v +83 -0
  57. data/lib/public_atom_module/latency_long.v +84 -0
  58. data/lib/public_atom_module/latency_verb.v +52 -0
  59. data/lib/public_atom_module/once_event.sv +65 -0
  60. data/lib/public_atom_module/pipe_reg.v +93 -0
  61. data/lib/public_atom_module/pipe_reg_2write_ports.v +84 -0
  62. data/lib/public_atom_module/sim/clock_rst_verb.sv +54 -0
  63. data/lib/public_atom_module/sim/clock_rst_verc.sv +69 -0
  64. data/lib/public_atom_module/sim/latency_long_tb.sv +49 -0
  65. data/lib/public_atom_module/sim/latency_long_tb.sv.bak +49 -0
  66. data/lib/public_atom_module/sim_system_pkg.sv +4 -0
  67. data/lib/public_atom_module/synth_system_pkg.sv +4 -0
  68. data/lib/tdl/Logic/logic_edge.rb +1 -1
  69. data/lib/tdl/auto_script/autogensdl.rb +2 -3
  70. data/lib/tdl/auto_script/import_hdl.rb +40 -5
  71. data/lib/tdl/axi4/axi4_interconnect_verb.rb +47 -10
  72. data/lib/tdl/class_hdl/hdl_always_comb.rb +4 -1
  73. data/lib/tdl/class_hdl/hdl_always_ff.rb +3 -3
  74. data/lib/tdl/class_hdl/hdl_assign.rb +7 -1
  75. data/lib/tdl/class_hdl/hdl_block_ifelse.rb +7 -7
  76. data/lib/tdl/class_hdl/hdl_foreach.rb +2 -2
  77. data/lib/tdl/class_hdl/hdl_function.rb +4 -4
  78. data/lib/tdl/class_hdl/hdl_generate.rb +5 -2
  79. data/lib/tdl/class_hdl/hdl_initial.rb +25 -3
  80. data/lib/tdl/class_hdl/hdl_module_def.rb +9 -6
  81. data/lib/tdl/class_hdl/hdl_package.rb +45 -0
  82. data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +99 -27
  83. data/lib/tdl/class_hdl/hdl_struct.rb +2 -2
  84. data/lib/tdl/elements/Reset.rb +5 -9
  85. data/lib/tdl/elements/clock.rb +5 -9
  86. data/lib/tdl/elements/data_inf.rb +0 -17
  87. data/lib/tdl/elements/logic.rb +9 -31
  88. data/lib/tdl/elements/mail_box.rb +6 -1
  89. data/lib/tdl/elements/originclass.rb +17 -47
  90. data/lib/tdl/elements/parameter.rb +5 -6
  91. data/lib/tdl/examples/11_test_unit/dve.tcl +6 -153
  92. data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +2 -2
  93. data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +9 -0
  94. data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +2 -2
  95. data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +2 -2
  96. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +1 -1
  97. data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +41 -0
  98. data/lib/tdl/examples/11_test_unit/tu0.sv +2 -1
  99. data/lib/tdl/examples/1_define_module/exmple_md.sv +1 -1
  100. data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +3 -3
  101. data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +3 -3
  102. data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +3 -3
  103. data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +1 -1
  104. data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +3 -3
  105. data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +3 -3
  106. data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +1 -1
  107. data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +3 -3
  108. data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +2 -2
  109. data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +7 -7
  110. data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +4 -3
  111. data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
  112. data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +2 -2
  113. data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +1 -1
  114. data/lib/tdl/examples/6_module_with_interface/example_interface.sv +8 -8
  115. data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +9 -9
  116. data/lib/tdl/examples/7_module_with_package/body_package.sv +4 -3
  117. data/lib/tdl/examples/7_module_with_package/example_pkg.sv +1 -1
  118. data/lib/tdl/examples/7_module_with_package/head_package.sv +4 -3
  119. data/lib/tdl/examples/8_top_module/dve.tcl +6 -0
  120. data/lib/tdl/examples/8_top_module/tb_test_top.sv +1 -1
  121. data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +29 -0
  122. data/lib/tdl/examples/8_top_module/test_top.sv +1 -1
  123. data/lib/tdl/examples/8_top_module/test_top_sim.sv +9 -0
  124. data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +2 -1
  125. data/lib/tdl/examples/9_itegration/dve.tcl +155 -2
  126. data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +1 -1
  127. data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +1 -1
  128. data/lib/tdl/examples/9_itegration/test_tttop.sv +7 -38
  129. data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +38 -7
  130. data/lib/tdl/exlib/axis_verify.rb +4 -3
  131. data/lib/tdl/exlib/constraints_verb.rb +1 -0
  132. data/lib/tdl/exlib/itegration_verb.rb +47 -41
  133. data/lib/tdl/rebuild_ele/ele_base.rb +15 -10
  134. data/lib/tdl/sdlmodule/sdlmodule.rb +117 -51
  135. data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +1 -1
  136. data/lib/tdl/sdlmodule/sdlmodule_draw.rb +2 -2
  137. data/lib/tdl/sdlmodule/sdlmodule_instance.rb +3 -0
  138. data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +6 -6
  139. data/lib/tdl/sdlmodule/sdlmodule_varible.rb +6 -6
  140. data/lib/tdl/sdlmodule/test_unit_module.rb +6 -0
  141. data/lib/tdl/sdlmodule/top_module.rb +4 -0
  142. data/lib/tdl/tdl.rb +1 -11
  143. data/lib/tdl/tdlerror/tdlerror.rb +1 -1
  144. metadata +43 -5
  145. data/CODE_OF_CONDUCT.md +0 -74
  146. data/lib/axi/AXI_stream/axis_length_split_writh_user.sv +0 -87
checksums.yaml CHANGED
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data/Rakefile CHANGED
@@ -12,3 +12,10 @@ Rake::TestTask.new(:test) do |t|
12
12
  # t.ruby_opts = ["-c"]
13
13
  # t.verbose = true
14
14
  end
15
+
16
+ desc "编译TB"
17
+ task :tb do
18
+ require_relative "./lib/axi_tdl.rb"
19
+ puts AxiTdl::VERSION
20
+ require_relative "./lib/axi/techbench/tb_axi_stream_split_channel.rb"
21
+ end
data/lib/axi/AXI4/axi4_direct_A1.sv CHANGED
@@ -53,7 +53,7 @@ initial begin
53
53
  case(MODE)
54
54
  "BOTH_to_BOTH","BOTH_to_ONLY_READ","BOTH_to_ONLY_WRITE":
55
55
  assert(slaver.MODE =="BOTH")
56
- else $error("SLAVER AXIS MODE<%s> != BOTH",slaver.MODE);
56
+ else $error("SLAVER AXIS MODE<%0s> != BOTH",slaver.MODE);
57
57
  "ONLY_READ_to_BOTH":
58
58
  assert(slaver.MODE == "ONLY_READ")
59
59
  else $error("SLAVER AXIS MODE != ONLY_READ");
data/lib/axi/AXI4/axi4_direct_verc.sv CHANGED
@@ -25,9 +25,9 @@ module axi4_direct_verc #(
25
25
  `parameter_string IGNORE_LSIZE = "FALSE" //(* show = "false" *)
26
26
  )(
27
27
  (* axi4_up = "true" *)
28
- axi_inf.slaver slaver,
28
+ axi_inf.slaver slaver_inf,
29
29
  (* axi4_down = "true" *)
30
- axi_inf.master master
30
+ axi_inf.master master_inf
31
31
  );
32
32
 
33
33
 
@@ -36,60 +36,60 @@ import SystemPkg::*;
36
36
  initial begin
37
37
  #(1us);
38
38
  if(IGNORE_IDSIZE == "FALSE")begin
39
- assert(slaver.IDSIZE <= master.IDSIZE) //idsize of slaver can be smaller thane master's
39
+ assert(slaver_inf.IDSIZE <= master_inf.IDSIZE) //idsize of slaver_inf can be smaller thane master_inf's
40
40
  else begin
41
41
  $error("SLAVER AXIS IDSIZE != MASTER AXIS IDSIZE");
42
42
  $finish;
43
43
  end
44
44
  end
45
45
  if(IGNORE_DSIZE == "FALSE")begin
46
- assert(slaver.DSIZE == master.DSIZE)
46
+ assert(slaver_inf.DSIZE == master_inf.DSIZE)
47
47
  else $error("SLAVER AXIS DSIZE != MASTER AXIS DSIZE");
48
48
  end
49
49
  if(IGNORE_ASIZE == "FALSE")begin
50
- assert(slaver.ASIZE == master.ASIZE)
50
+ assert(slaver_inf.ASIZE == master_inf.ASIZE)
51
51
  else $error("SLAVER AXIS ASIZE != MASTER AXIS ASIZE");
52
52
  end
53
53
  if(IGNORE_LSIZE == "FALSE")begin
54
- assert(slaver.LSIZE == master.LSIZE)
54
+ assert(slaver_inf.LSIZE == master_inf.LSIZE)
55
55
  else $error("SLAVER AXIS LSIZE != MASTER AXIS LSIZE");
56
56
  end
57
57
  case(MODE)
58
58
  "BOTH_to_BOTH","BOTH_to_ONLY_READ","BOTH_to_ONLY_WRITE":
59
- assert(slaver.MODE =="BOTH" && SLAVER_MODE=="BOTH")
60
- else $error("SLAVER AXIS MODE<%s> != BOTH",slaver.MODE);
59
+ assert(slaver_inf.MODE =="BOTH" && SLAVER_MODE=="BOTH")
60
+ else $error("SLAVER AXIS MODE<%s> != BOTH",slaver_inf.MODE);
61
61
  "ONLY_READ_to_BOTH":
62
- assert(slaver.MODE == "ONLY_READ" && SLAVER_MODE=="ONLY_READ")
62
+ assert(slaver_inf.MODE == "ONLY_READ" && SLAVER_MODE=="ONLY_READ")
63
63
  else $error("SLAVER AXIS MODE != ONLY_READ");
64
64
  "ONLY_WRITE_to_BOTH","ONLY_WRITE_to_ONLY_WRITE":
65
- assert(slaver.MODE == "ONLY_WRITE" && SLAVER_MODE=="ONLY_WRITE")
65
+ assert(slaver_inf.MODE == "ONLY_WRITE" && SLAVER_MODE=="ONLY_WRITE")
66
66
  else begin
67
67
  $error("SLAVER AXIS MODE != ONLY_WRITE");
68
68
  $finish;
69
69
  end
70
70
  "ONLY_READ_to_ONLY_READ":
71
- assert(slaver.MODE == "ONLY_READ" && SLAVER_MODE=="ONLY_READ")
71
+ assert(slaver_inf.MODE == "ONLY_READ" && SLAVER_MODE=="ONLY_READ")
72
72
  else $error("SLAVER AXIS MODE != ONLY_READ");
73
73
  default:
74
- assert(slaver.MODE == "_____")
74
+ assert(slaver_inf.MODE == "_____")
75
75
  else $error("SLAVER AXIS MODE ERROR") ;
76
76
  endcase
77
77
 
78
78
  case(MODE)
79
79
  "ONLY_WRITE_to_BOTH","ONLY_READ_to_BOTH","BOTH_to_BOTH":
80
- assert(master.MODE == "BOTH" && MASTER_MODE=="BOTH")
80
+ assert(master_inf.MODE == "BOTH" && MASTER_MODE=="BOTH")
81
81
  else $error("MASTER AXIS MODE != BOTH");
82
82
  "BOTH_to_ONLY_READ":
83
- assert(master.MODE == "ONLY_READ" && MASTER_MODE=="ONLY_READY")
83
+ assert(master_inf.MODE == "ONLY_READ" && MASTER_MODE=="ONLY_READY")
84
84
  else $error("MASTER AXIS MODE != ONLY_READ");
85
85
  "BOTH_to_ONLY_WRITE","ONLY_WRITE_to_ONLY_WRITE":
86
- assert(master.MODE == "ONLY_WRITE" && MASTER_MODE=="ONLY_WRITE")
86
+ assert(master_inf.MODE == "ONLY_WRITE" && MASTER_MODE=="ONLY_WRITE")
87
87
  else $error("MASTER AXIS MODE != ONLY_WRITE");
88
88
  "ONLY_READ_to_ONLY_READ":
89
- assert(master.MODE == "ONLY_READ" && MASTER_MODE=="ONLY_READ")
89
+ assert(master_inf.MODE == "ONLY_READ" && MASTER_MODE=="ONLY_READ")
90
90
  else $error("MASTER AXIS MODE != ONLY_READ");
91
91
  default:
92
- assert(master.MODE == "_____")
92
+ assert(master_inf.MODE == "_____")
93
93
  else $error("MASTER AXIS MODE ERROR");
94
94
  endcase
95
95
 
@@ -97,49 +97,49 @@ end
97
97
 
98
98
  generate
99
99
  if(MASTER_MODE!="ONLY_READ")begin
100
- assign master.axi_awid = slaver.axi_awid ;
101
- assign master.axi_awaddr = slaver.axi_awaddr ;
102
- assign master.axi_awlen = slaver.axi_awlen ;
103
- assign master.axi_awsize = slaver.axi_awsize ;
104
- assign master.axi_awburst = slaver.axi_awburst;
105
- assign master.axi_awlock = slaver.axi_awlock ;
106
- assign master.axi_awcache = slaver.axi_awcache;
107
- assign master.axi_awprot = slaver.axi_awprot ;
108
- assign master.axi_awqos = slaver.axi_awqos ;
109
- assign master.axi_awvalid = slaver.axi_awvalid;
110
- assign slaver.axi_awready = master.axi_awready;
111
- assign master.axi_wdata = slaver.axi_wdata ;
112
- assign master.axi_wstrb = slaver.axi_wstrb ;
113
- assign master.axi_wlast = slaver.axi_wlast ;
114
- assign master.axi_wvalid = slaver.axi_wvalid ;
115
- assign slaver.axi_wready = master.axi_wready ;
116
- assign master.axi_bready = slaver.axi_bready ;
117
- assign slaver.axi_bid = master.axi_bid ;
118
- assign slaver.axi_bresp = master.axi_bresp ;
119
- assign slaver.axi_bvalid = master.axi_bvalid ;
100
+ assign master_inf.axi_awid = slaver_inf.axi_awid ;
101
+ assign master_inf.axi_awaddr = slaver_inf.axi_awaddr ;
102
+ assign master_inf.axi_awlen = slaver_inf.axi_awlen ;
103
+ assign master_inf.axi_awsize = slaver_inf.axi_awsize ;
104
+ assign master_inf.axi_awburst = slaver_inf.axi_awburst;
105
+ assign master_inf.axi_awlock = slaver_inf.axi_awlock ;
106
+ assign master_inf.axi_awcache = slaver_inf.axi_awcache;
107
+ assign master_inf.axi_awprot = slaver_inf.axi_awprot ;
108
+ assign master_inf.axi_awqos = slaver_inf.axi_awqos ;
109
+ assign master_inf.axi_awvalid = slaver_inf.axi_awvalid;
110
+ assign slaver_inf.axi_awready = master_inf.axi_awready;
111
+ assign master_inf.axi_wdata = slaver_inf.axi_wdata ;
112
+ assign master_inf.axi_wstrb = slaver_inf.axi_wstrb ;
113
+ assign master_inf.axi_wlast = slaver_inf.axi_wlast ;
114
+ assign master_inf.axi_wvalid = slaver_inf.axi_wvalid ;
115
+ assign slaver_inf.axi_wready = master_inf.axi_wready ;
116
+ assign master_inf.axi_bready = slaver_inf.axi_bready ;
117
+ assign slaver_inf.axi_bid = master_inf.axi_bid ;
118
+ assign slaver_inf.axi_bresp = master_inf.axi_bresp ;
119
+ assign slaver_inf.axi_bvalid = master_inf.axi_bvalid ;
120
120
  end
121
121
  endgenerate
122
122
 
123
123
 
124
124
  generate
125
125
  if(MASTER_MODE!="ONLY_WRITE")begin
126
- assign master.axi_arid = slaver.axi_arid ;
127
- assign master.axi_araddr = slaver.axi_araddr ;
128
- assign master.axi_arlen = slaver.axi_arlen ;
129
- assign master.axi_arsize = slaver.axi_arsize ;
130
- assign master.axi_arburst = slaver.axi_arburst;
131
- assign master.axi_arlock = slaver.axi_arlock ;
132
- assign master.axi_arcache = slaver.axi_arcache;
133
- assign master.axi_arprot = slaver.axi_arprot ;
134
- assign master.axi_arqos = slaver.axi_arqos ;
135
- assign master.axi_arvalid = slaver.axi_arvalid;
136
- assign slaver.axi_arready = master.axi_arready;
137
- assign master.axi_rready = slaver.axi_rready ;
138
- assign slaver.axi_rid = master.axi_rid ;
139
- assign slaver.axi_rdata = master.axi_rdata ;
140
- assign slaver.axi_rresp = master.axi_rresp ;
141
- assign slaver.axi_rlast = master.axi_rlast ;
142
- assign slaver.axi_rvalid = master.axi_rvalid ;
126
+ assign master_inf.axi_arid = slaver_inf.axi_arid ;
127
+ assign master_inf.axi_araddr = slaver_inf.axi_araddr ;
128
+ assign master_inf.axi_arlen = slaver_inf.axi_arlen ;
129
+ assign master_inf.axi_arsize = slaver_inf.axi_arsize ;
130
+ assign master_inf.axi_arburst = slaver_inf.axi_arburst;
131
+ assign master_inf.axi_arlock = slaver_inf.axi_arlock ;
132
+ assign master_inf.axi_arcache = slaver_inf.axi_arcache;
133
+ assign master_inf.axi_arprot = slaver_inf.axi_arprot ;
134
+ assign master_inf.axi_arqos = slaver_inf.axi_arqos ;
135
+ assign master_inf.axi_arvalid = slaver_inf.axi_arvalid;
136
+ assign slaver_inf.axi_arready = master_inf.axi_arready;
137
+ assign master_inf.axi_rready = slaver_inf.axi_rready ;
138
+ assign slaver_inf.axi_rid = master_inf.axi_rid ;
139
+ assign slaver_inf.axi_rdata = master_inf.axi_rdata ;
140
+ assign slaver_inf.axi_rresp = master_inf.axi_rresp ;
141
+ assign slaver_inf.axi_rlast = master_inf.axi_rlast ;
142
+ assign slaver_inf.axi_rvalid = master_inf.axi_rvalid ;
143
143
  end
144
144
  endgenerate
145
145
 
data/lib/axi/AXI4/axi4_dpram_cache.rb CHANGED
@@ -4,6 +4,7 @@ require_sdl 'common_ram_wrapper.rb'
4
4
 
5
5
  require_hdl File.join(__dir__,"./full_axi4_to_axis.sv")
6
6
  require_hdl 'data_inf_c_planer_A1.sv'
7
+ data_inf_c_planer_A1.contain_hdl 'data_inf_planer_A1.sv'
7
8
 
8
9
  TdlBuild.axi4_dpram_cache(__dir__) do
9
10
  parameter.INIT_FILE ''
data/lib/axi/AXI4/axi4_dpram_cache.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ created: 2021-04-16 17:01:03 +0800
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -20,15 +20,15 @@ module axi4_dpram_cache #(
20
20
  //==========================================================================
21
21
  //-------- define ----------------------------------------------------------
22
22
 
23
- cm_ram_inf #(.DSIZE(a_inf.DSIZE),.RSIZE(a_inf.ASIZE),.MSIZE(a_inf.DSIZE/8)) xram_inf();
24
- axi_stream_inf #(.DSIZE(a_inf.ASIZE+a_inf.DSIZE+1),.USIZE(1)) a_axis_inf (.aclk(a_inf.axi_aclk),.aresetn(a_inf.axi_aresetn),.aclken(1'b1)) ;
25
- axi_stream_inf #(.DSIZE(a_inf.DSIZE),.USIZE(1)) a_axis_rd_inf (.aclk(a_inf.axi_aclk),.aresetn(a_inf.axi_aresetn),.aclken(1'b1)) ;
26
- data_inf_c #(.DSIZE(a_inf.ASIZE+1)) a_datac_rd_inf (.clock(a_inf.axi_aclk),.rst_n(a_inf.axi_aresetn)) ;
27
- data_inf_c #(.DSIZE(a_inf.ASIZE+a_inf.DSIZE+1)) a_datac_rd_rel_inf (.clock(a_inf.axi_aclk),.rst_n(a_inf.axi_aresetn)) ;
28
- axi_stream_inf #(.DSIZE(b_inf.ASIZE+b_inf.DSIZE+1),.USIZE(1)) b_axis_inf (.aclk(b_inf.axi_aclk),.aresetn(b_inf.axi_aresetn),.aclken(1'b1)) ;
29
- axi_stream_inf #(.DSIZE(b_inf.DSIZE),.USIZE(1)) b_axis_rd_inf (.aclk(b_inf.axi_aclk),.aresetn(b_inf.axi_aresetn),.aclken(1'b1)) ;
30
- data_inf_c #(.DSIZE(b_inf.ASIZE+1)) b_datac_rd_inf (.clock(b_inf.axi_aclk),.rst_n(b_inf.axi_aresetn)) ;
31
- data_inf_c #(.DSIZE(b_inf.ASIZE+b_inf.DSIZE+1)) b_datac_rd_rel_inf (.clock(b_inf.axi_aclk),.rst_n(b_inf.axi_aresetn)) ;
23
+ cm_ram_inf #(.DSIZE(a_inf.DSIZE),.RSIZE(a_inf.ASIZE),.MSIZE((a_inf.DSIZE / 8))) xram_inf();
24
+ axi_stream_inf #(.DSIZE(a_inf.ASIZE+a_inf.DSIZE+1),.FreqM(1.0),.USIZE(1)) a_axis_inf (.aclk(a_inf.axi_aclk),.aresetn(a_inf.axi_aresetn),.aclken(1'b1)) ;
25
+ axi_stream_inf #(.DSIZE(a_inf.DSIZE),.FreqM(1.0),.USIZE(1)) a_axis_rd_inf (.aclk(a_inf.axi_aclk),.aresetn(a_inf.axi_aresetn),.aclken(1'b1)) ;
26
+ data_inf_c #(.DSIZE(a_inf.ASIZE+1),.FreqM(1.0)) a_datac_rd_inf (.clock(a_inf.axi_aclk),.rst_n(a_inf.axi_aresetn)) ;
27
+ data_inf_c #(.DSIZE(a_inf.ASIZE+a_inf.DSIZE+1),.FreqM(1.0)) a_datac_rd_rel_inf (.clock(a_inf.axi_aclk),.rst_n(a_inf.axi_aresetn)) ;
28
+ axi_stream_inf #(.DSIZE(b_inf.ASIZE+b_inf.DSIZE+1),.FreqM(1.0),.USIZE(1)) b_axis_inf (.aclk(b_inf.axi_aclk),.aresetn(b_inf.axi_aresetn),.aclken(1'b1)) ;
29
+ axi_stream_inf #(.DSIZE(b_inf.DSIZE),.FreqM(1.0),.USIZE(1)) b_axis_rd_inf (.aclk(b_inf.axi_aclk),.aresetn(b_inf.axi_aresetn),.aclken(1'b1)) ;
30
+ data_inf_c #(.DSIZE(b_inf.ASIZE+1),.FreqM(1.0)) b_datac_rd_inf (.clock(b_inf.axi_aclk),.rst_n(b_inf.axi_aresetn)) ;
31
+ data_inf_c #(.DSIZE(b_inf.ASIZE+b_inf.DSIZE+1),.FreqM(1.0)) b_datac_rd_rel_inf (.clock(b_inf.axi_aclk),.rst_n(b_inf.axi_aresetn)) ;
32
32
  //==========================================================================
33
33
  //-------- instance --------------------------------------------------------
34
34
  full_axi4_to_axis full_axi4_to_axis_ainst(
data/lib/axi/AXI4/axi4_rd_burst_track.sv CHANGED
@@ -16,7 +16,8 @@ module axi4_rd_burst_track #(
16
16
  )(
17
17
  axi_inf.mirror_rd axi4_mirror
18
18
  );
19
- import GlobalPkg::*;
19
+ // import GlobalPkg::*;
20
+ import SystemPkg::*;
20
21
 
21
22
  logic LSIZE =
22
23
  (axi4_mirror.IDSIZE>= 37 )? 9 : //
data/lib/axi/AXI4/axi4_wr_burst_track.sv CHANGED
@@ -16,7 +16,8 @@ module axi4_wr_burst_track #(
16
16
  axi_inf.mirror_wr axi4_mirror
17
17
  );
18
18
 
19
- import GlobalPkg::*;
19
+ // import GlobalPkg::*;
20
+ import SystemPkg::*;
20
21
 
21
22
  logic LSIZE =
22
23
  (axi4_mirror.IDSIZE>= 37 )? 9 : //
data/lib/axi/AXI4/axis_to_axi4_wr.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ creaded:
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -53,11 +53,11 @@ logic rd_en;
53
53
  logic fifo_empty;
54
54
  logic fifo_full;
55
55
  logic stream_en;
56
- axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
57
- axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) long_fifo_axis_out (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
58
- axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
59
- axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP)) axi_wr_vcs_cp_R1977 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
60
- axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
56
+ axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
57
+ axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) long_fifo_axis_out (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
58
+ axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.FreqM(1.0),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
59
+ axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP),.FreqM(axi_wr.FreqM)) axi_wr_vcs_cp_R1624 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
60
+ axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
61
61
  //==========================================================================
62
62
  //-------- instance --------------------------------------------------------
63
63
  axis_length_split_with_addr #(
@@ -94,13 +94,13 @@ independent_clock_fifo #(
94
94
  axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
95
95
  /* output */.stream_en (stream_en ),
96
96
  /* axi_stream_inf.slaver */.id_add_len_in (id_add_len_in ),
97
- /* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (axi_wr_vcs_cp_R1977 )
97
+ /* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (axi_wr_vcs_cp_R1624 )
98
98
  );
99
99
  vcs_axi4_comptable #(
100
100
  .ORIGIN ("master_wr_aux_no_resp" ),
101
101
  .TO ("master_wr" )
102
- )vcs_axi4_comptable_axi_wr_aux_R874_axi_wr_inst(
103
- /* input */.origin (axi_wr_vcs_cp_R1977 ),
102
+ )vcs_axi4_comptable_axi_wr_aux_R675_axi_wr_inst(
103
+ /* input */.origin (axi_wr_vcs_cp_R1624 ),
104
104
  /* output */.to (axi_wr )
105
105
  );
106
106
  axis_valve_with_pipe #(
data/lib/axi/AXI4/odata_pool_axi4_A3.sv CHANGED
@@ -26,6 +26,13 @@ module odata_pool_axi4_A3 #(
26
26
 
27
27
  `include "define_macro.sv"
28
28
 
29
+ initial begin
30
+ assert (addr_size_inf.DSIZE == 64)
31
+ else begin
32
+ $display("addr_size_inf.DSIZE<%0d> != 64",addr_size_inf.DSIZE);
33
+ end
34
+ end
35
+
29
36
  logic fifo_empty;
30
37
  logic fifo_full;
31
38
  logic [31:0] fifo_addr;
data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ creaded:
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -23,10 +23,10 @@ logic clock;
23
23
  logic rst_n;
24
24
  (* MARK_DEBUG="true" *)(* dont_touch="true" *)logic fifo_empty;
25
25
  (* MARK_DEBUG="true" *)(* dont_touch="true" *)logic fifo_full;
26
- data_inf_c #(.DSIZE(long_inf.IDSIZE+long_inf.LSIZE+long_inf.ASIZE)) pre_partition_data_inf (.clock(clock),.rst_n(rst_n)) ;
27
- data_inf_c #(.DSIZE(short_inf.IDSIZE+long_inf.LSIZE+long_inf.ASIZE)) post_partition_data_inf (.clock(clock),.rst_n(rst_n)) ;
28
- data_inf_c #(.DSIZE(1)) partition_pulse_inf (.clock(clock),.rst_n(rst_n)) ;
29
- data_inf_c #(.DSIZE(1)) wait_last_inf (.clock(clock),.rst_n(rst_n)) ;
26
+ data_inf_c #(.DSIZE(long_inf.IDSIZE+long_inf.LSIZE+long_inf.ASIZE),.FreqM(long_inf.FreqM)) pre_partition_data_inf (.clock(clock),.rst_n(rst_n)) ;
27
+ data_inf_c #(.DSIZE(short_inf.IDSIZE+long_inf.LSIZE+long_inf.ASIZE),.FreqM(long_inf.FreqM)) post_partition_data_inf (.clock(clock),.rst_n(rst_n)) ;
28
+ data_inf_c #(.DSIZE(1),.FreqM(long_inf.FreqM)) partition_pulse_inf (.clock(clock),.rst_n(rst_n)) ;
29
+ data_inf_c #(.DSIZE(1),.FreqM(long_inf.FreqM)) wait_last_inf (.clock(clock),.rst_n(rst_n)) ;
30
30
  //==========================================================================
31
31
  //-------- instance --------------------------------------------------------
32
32
  data_inf_partition #(
data/lib/axi/AXI4/packet_partition/data_inf_partition.rb CHANGED
@@ -31,8 +31,8 @@ TdlBuild.data_inf_partition(__dir__) do
31
31
  logic - 'tail_len'
32
32
  logic - 'one_long_stream'
33
33
  logic - 'fifo_wr'
34
- debugLogic - 'fifo_full'
35
- debugLogic - 'fifo_empty'
34
+ logic - 'fifo_full'
35
+ logic - 'fifo_empty'
36
36
 
37
37
  always_comb do
38
38
  CASE ps.C do
@@ -267,8 +267,12 @@ TdlBuild.data_inf_partition(__dir__) do
267
267
  end
268
268
 
269
269
  ### Track
270
- debugLogic[10] - 'st5_cnt'
271
- debugLogic - 'track_st5'
270
+ # debugLogic[10] - 'st5_cnt'
271
+ # debugLogic - 'track_st5'
272
+
273
+ logic[10] - 'st5_cnt'
274
+ logic - 'track_st5'
275
+
272
276
  always_ff(posedge.clock,negedge.rst_n) do
273
277
  IF ~rst_n do
274
278
  st5_cnt <= 0.A
data/lib/axi/AXI4/packet_partition/data_inf_partition.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ creaded:
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -29,14 +29,14 @@ logic rst_n;
29
29
  logic tail_len;
30
30
  logic one_long_stream;
31
31
  logic fifo_wr;
32
+ logic fifo_full;
33
+ logic fifo_empty;
32
34
  logic [IDSIZE+4-1:0] curr_id ;
33
35
  logic [LSIZE-1:0] curr_length ;
34
- logic [(data_in.DSIZE-IDSIZE)-LSIZE-1:0] curr_addr ;
36
+ logic [(data_in.DSIZE - IDSIZE)-LSIZE-1:0] curr_addr ;
35
37
  logic [LSIZE-1:0] wr_length ;
36
- (* MARK_DEBUG="true" *)(* dont_touch="true" *)logic fifo_full;
37
- (* MARK_DEBUG="true" *)(* dont_touch="true" *)logic fifo_empty;
38
- (* MARK_DEBUG="true" *)(* dont_touch="true" *)logic [9:0] st5_cnt ;
39
- (* MARK_DEBUG="true" *)(* dont_touch="true" *)logic track_st5;
38
+ logic [10-1:0] st5_cnt ;
39
+ logic track_st5;
40
40
 
41
41
  //==========================================================================
42
42
  //-------- instance --------------------------------------------------------
data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv CHANGED
@@ -5,7 +5,7 @@ _______________________________________
5
5
  descript:
6
6
  author : Cook.Darwin
7
7
  Version: VERA.0.0
8
- created: xxxx.xx.xx
8
+ creaded:
9
9
  madified:
10
10
  ***********************************************/
11
11
  `timescale 1ns/1ps
@@ -53,11 +53,11 @@ logic fifo_rd_en;
53
53
  logic fifo_empty;
54
54
  logic fifo_full;
55
55
  logic stream_en;
56
- axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
57
- axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) fifo_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
58
- axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
59
- axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP)) axi_wr_vcs_cp_R236 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
60
- axi_stream_inf #(.DSIZE(axis_in.DSIZE),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
56
+ axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) split_out (.aclk(axis_in.aclk),.aresetn(axis_in.aresetn),.aclken(1'b1)) ;
57
+ axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) fifo_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
58
+ axi_stream_inf #(.DSIZE(axi_wr.IDSIZE + axi_wr.ASIZE + axi_wr.LSIZE),.FreqM(1.0),.USIZE(1)) id_add_len_in (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
59
+ axi_inf #(.DSIZE(axi_wr.DSIZE),.IDSIZE(axi_wr.IDSIZE),.ASIZE(axi_wr.ASIZE),.LSIZE(axi_wr.LSIZE),.MODE(axi_wr.MODE),.ADDR_STEP(axi_wr.ADDR_STEP),.FreqM(axi_wr.FreqM)) axi_wr_vcs_cp_R1219 (.axi_aclk(axi_wr.axi_aclk),.axi_aresetn(axi_wr.axi_aresetn)) ;
60
+ axi_stream_inf #(.DSIZE(axis_in.DSIZE),.FreqM(axis_in.FreqM),.USIZE(1)) pipe_axis (.aclk(axi_wr.axi_aclk),.aresetn(axi_wr.axi_aresetn),.aclken(1'b1)) ;
61
61
  //==========================================================================
62
62
  //-------- instance --------------------------------------------------------
63
63
  axis_length_split_with_addr #(
@@ -91,16 +91,16 @@ independent_clock_fifo #(
91
91
  /* output */.full (fifo_full )
92
92
  );
93
93
  axi4_wr_auxiliary_gen_without_resp axi4_wr_auxiliary_gen_without_resp_inst(
94
- /* output */.stream_en (stream_en ),
95
- /* axi_stream_inf.slaver */.id_add_len_in (id_add_len_in ),
96
- /* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (axi_wr_vcs_cp_R236 )
94
+ /* output */.stream_en (stream_en ),
95
+ /* axi_stream_inf.slaver */.id_add_len_in (id_add_len_in ),
96
+ /* axi_inf.master_wr_aux_no_resp */.axi_wr_aux (axi_wr_vcs_cp_R1219 )
97
97
  );
98
98
  vcs_axi4_comptable #(
99
99
  .ORIGIN ("master_wr_aux_no_resp" ),
100
100
  .TO ("master_wr" )
101
- )vcs_axi4_comptable_axi_wr_aux_R372_axi_wr_inst(
102
- /* input */.origin (axi_wr_vcs_cp_R236 ),
103
- /* output */.to (axi_wr )
101
+ )vcs_axi4_comptable_axi_wr_aux_R827_axi_wr_inst(
102
+ /* input */.origin (axi_wr_vcs_cp_R1219 ),
103
+ /* output */.to (axi_wr )
104
104
  );
105
105
  axis_valve_with_pipe #(
106
106
  .MODE ("OUT" )