axi_tdl 0.1.0 → 0.1.8

data/lib/tdl/examples/9_itegration/tb_test_tttop.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-04-03 13:47:04 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps

data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv

@@ -5,7 +5,7 @@ _______________________________________
 descript:
 author : Cook.Darwin
 Version: VERA.0.0
-created: xxxx.xx.xx
+created: 2021-04-03 14:05:10 +0800
 madified:
 ***********************************************/
 `timescale 1ns/1ps

data/lib/tdl/examples/9_itegration/test_tttop.sv

@@ -1,40 +1,9 @@
-/**********************************************
-_______________________________________ 
-___________    Cook Darwin   __________    
-_______________________________________
-descript:
-author : Cook.Darwin
-Version: VERA.0.0
-created: 2021-03-21 10:19:00 +0800
-madified:
-***********************************************/
-`timescale 1ns/1ps
-
-module test_tttop (
-    input global_sys_clk
-);
-
-//==========================================================================
-//-------- define ----------------------------------------------------------
-logic  clock_100M;
-logic  rstn_100M;
-axi_stream_inf #(.DSIZE(16),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
-//==========================================================================
-//-------- instance --------------------------------------------------------
-simple_clock simple_clock_inst(
-/* input clock  */.sys_clk (global_sys_clk ),
-/* output clock */.clock   (clock_100M     ),
-/* output reset */.rst_n   (rstn_100M      )
-);
-a_test_md a_test_md_inst(
-/* input clock           */.clock      (clock_100M   ),
-/* input reset           */.rst        (~rstn_100M   ),
-/* axi_stream_inf.master */.origin_inf (x_origin_inf )
-);
-//==========================================================================
-//-------- expression ------------------------------------------------------
-assign x_origin_inf.axis_tvalid = 1'b0;
-assign x_origin_inf.axis_tdata = '0;
-assign x_origin_inf.axis_tlast = 1'b0;
 
+`timescale 1ns/1ps
+module test_tttop();
+initial begin
+    #(1us);
+    $warning("Check TopModule.sim,please!!!");
+    $stop;
+end
 endmodule

data/lib/tdl/examples/9_itegration/test_tttop_sim.sv

@@ -1,9 +1,40 @@
-
+/**********************************************
+_______________________________________ 
+___________    Cook Darwin   __________    
+_______________________________________
+descript:
+author : Cook.Darwin
+Version: VERA.0.0
+created: 2021-05-30 12:21:54 +0800
+madified:
+***********************************************/
 `timescale 1ns/1ps
-module test_tttop_sim();
-initial begin
-    #(1us);
-    $warning("Check TopModule.sim,please!!!");
-    $stop;
-end
+
+module test_tttop_sim (
+    input global_sys_clk
+);
+
+//==========================================================================
+//-------- define ----------------------------------------------------------
+logic  clock_100M;
+logic  rstn_100M;
+axi_stream_inf #(.DSIZE(16),.FreqM(100),.USIZE(1)) x_origin_inf (.aclk(clock_100M),.aresetn(rstn_100M),.aclken(1'b1)) ;
+//==========================================================================
+//-------- instance --------------------------------------------------------
+simple_clock simple_clock_inst(
+/* input clock  */.sys_clk (global_sys_clk ),
+/* output clock */.clock   (clock_100M     ),
+/* output reset */.rst_n   (rstn_100M      )
+);
+a_test_md a_test_md_inst(
+/* input clock           */.clock      (clock_100M   ),
+/* input reset           */.rst        (~rstn_100M   ),
+/* axi_stream_inf.master */.origin_inf (x_origin_inf )
+);
+//==========================================================================
+//-------- expression ------------------------------------------------------
+assign x_origin_inf.axis_tvalid = 1'b0;
+assign x_origin_inf.axis_tdata = '0;
+assign x_origin_inf.axis_tlast = 1'b0;
+
 endmodule

data/lib/tdl/exlib/axis_verify.rb

@@ -128,9 +128,9 @@ end
 
 class AxiStream
 
-    def to_simple_sim_master_coe(length: [10,200], gap_len: [0,10], data: [ (0...100) ] , vld_perc: [50, 100], loop_coe: true)
+    def to_simple_sim_master_coe(enable: 1.b1, length: [10,200], gap_len: [0,10], data: [ (0...100) ] , vld_perc: [50, 100], loop_coe: true)
         # raise TdlError.new "file cant be empty"  unless file
-        file = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","#{self.name}_#{globle_random_name_flag}.coe")
+        file = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","coe_#{self.name}_#{globle_random_name_flag}.coe")
         _sps = nil
         ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
             require_sdl 'axis_sim_master_model.rb'
@@ -144,11 +144,12 @@ class AxiStream
             _sps 
         end
 
-        @belong_to_module.instance_exec(self,file,loop_coe) do |_self,file,loop_coe| 
+        @belong_to_module.instance_exec(self,file,loop_coe,enable) do |_self,file,loop_coe,_enable| 
 
             Instance(:axis_sim_master_model,"sim_model_inst_#{_self.name}") do |h| 
                 h.param.LOOP                (loop_coe ? "TRUE" : "FALSE")
                 h.param.RAM_DEPTH           File.open(File.expand_path(file)).readlines.size
+                h.input.enable              _enable
                 h.input.load_trigger        1.b0
                 h.input[32].total_length    h.param.RAM_DEPTH
                 h.input[512*8].mem_file     File.expand_path(file) # {axis_tvalid, axis_tuser, axis_tkeep, axis_tlast, axis_tdata}

data/lib/tdl/exlib/constraints_verb.rb

@@ -41,6 +41,7 @@ class ConstraintsVerb
             pulltype = ([pulltype] * pin_name.size ) unless pulltype.is_a? Array
             drive = ([drive] * pin_name.size ) unless drive.is_a? Array
 
+            pin_name = ((pin_name.is_a?(Array) && pin_name) || [pin_name] )
             pin_name.each_index do |index|
                 @package_pin_and_IOSTANDARD << [port_name[index],pin_name[index].to_s.upcase,iostandard[index].to_s.upcase,pulltype[index].to_s,drive[index].to_s]
 

data/lib/tdl/exlib/itegration_verb.rb

@@ -493,7 +493,7 @@ class ItegrationVerb
     def self.test_unit_inst(&filter_block)
         # blocks = self.instance_variable_get("@_inst_test_unit_blocks_")
         # blocks = instance_variable_get("@_inst_test_unit_blocks_") || []
-        blocks = @@_inst_test_unit_blocks_
+        blocks = @@_inst_test_unit_blocks_ || []
         return unless blocks
         return if blocks.empty?
         return unless TopModule.sim
@@ -671,39 +671,42 @@ class ItegrationVerb
                 end
             end
             ## 先从 已经加入的隐性itgt搜索
-            @top_module.implicit_itgt_collect.each do |i|
-                explort_attrs = i.class.get_itgt_var('itegration_explort_collect')
-                if ((explort_attrs & container_attrs).sort == container_attrs.sort && i.flag_match(flag_attrs))
-                    # puts "Itgt Good"
-                    mark = true
-                    unless self.respond_to? e
-                        define_singleton_method(e) do
-                            ## 如果从其他模块调用则出发 dynac_active
-                            ItegrationVerbAgent.new(i)
+            ## 去除隐性引入
+            unless TopModule.itgt_implicit_reject
+                @top_module.implicit_itgt_collect.each do |i|
+                    explort_attrs = i.class.get_itgt_var('itegration_explort_collect')
+                    if ((explort_attrs & container_attrs).sort == container_attrs.sort && i.flag_match(flag_attrs))
+                        # puts "Itgt Good"
+                        mark = true
+                        unless self.respond_to? e
+                            define_singleton_method(e) do
+                                ## 如果从其他模块调用则出发 dynac_active
+                                ItegrationVerbAgent.new(i)
+                            end
+                            i.link_eval
+                            i.child_inst_itgt << self
                         end
-                        i.link_eval
-                        i.child_inst_itgt << self
+                        break
                     end
-                    break
                 end
-            end
-            next if mark    ## 找到了 就处理下一个Link
-            ## 如果没有找到 再从 ItegrationVerb children里面找到比加入
-            @@child.each do |c|
-                explort_attrs = c.get_itgt_var('itegration_explort_collect')
-                # puts explort_attrs
-                if ((explort_attrs & container_attrs).sort == container_attrs.sort && c.flag_match(flag_attrs))
-                    # puts "Child Good"
-                    isp = @top_module.add_itegration(c.to_s,nickname:'implicit',implicit:true)
-                    @top_module.implicit_itgt_collect << isp
-                    ## 如果是隐性添加，先不要加入pin_map
-                    define_singleton_method(e) do
-                        ItegrationVerbAgent.new(isp)
+                next if mark    ## 找到了 就处理下一个Link
+                ## 如果没有找到 再从 ItegrationVerb children里面找到比加入
+                @@child.each do |c|
+                    explort_attrs = c.get_itgt_var('itegration_explort_collect')
+                    # puts explort_attrs
+                    if ((explort_attrs & container_attrs).sort == container_attrs.sort && c.flag_match(flag_attrs))
+                        # puts "Child Good"
+                        isp = @top_module.add_itegration(c.to_s,nickname:'implicit',implicit:true)
+                        @top_module.implicit_itgt_collect << isp
+                        ## 如果是隐性添加，先不要加入pin_map
+                        define_singleton_method(e) do
+                            ItegrationVerbAgent.new(isp)
+                        end
+                        isp.link_eval
+                        isp.child_inst_itgt << self
+                        mark = true
+                        break
                     end
-                    isp.link_eval
-                    isp.child_inst_itgt << self
-                    mark = true
-                    break
                 end
             end
 
@@ -736,18 +739,21 @@ class ItegrationVerb
             next if mark    ## 找到了 就处理下一个Link
             ##
             ## 如果没有找到 再从 ItegrationVerb children里面找到比加入
-            @@child.each do |c|
-                explort_attrs = c.get_itgt_var('itegration_explort_collect')
-                if (explort_attrs & container_attrs).sort == container_attrs.sort
-                    isp = @top_module.add_itegration(c.to_s,nickname:'implicit',implicit:true)
-                    @top_module.implicit_itgt_collect << isp
-                    ## 如果是隐性添加，先不要加入pin_map
+            ## 去除隐性引入
+            unless TopModule.itgt_implicit_reject
+                @@child.each do |c|
+                    explort_attrs = c.get_itgt_var('itegration_explort_collect')
+                    if (explort_attrs & container_attrs).sort == container_attrs.sort
+                        isp = @top_module.add_itegration(c.to_s,nickname:'implicit',implicit:true)
+                        @top_module.implicit_itgt_collect << isp
+                        ## 如果是隐性添加，先不要加入pin_map
 
-                    define_singleton_method(e) do
-                        ItegrationVerbAgent.new(isp)
+                        define_singleton_method(e) do
+                            ItegrationVerbAgent.new(isp)
+                        end
+                        mark = true
+                        break
                     end
-                    mark = true
-                    break
                 end
             end
 
@@ -770,7 +776,7 @@ class ItegrationVerb
     end
 
     ## 添加测试用例
-
+    @@_inst_test_unit_blocks_ = []
     def self.def_test_unit(name,path,&block)
         # @@_inst_test_unit_blocks_ = instance_variable_get("@_inst_test_unit_blocks_")
         @@_inst_test_unit_blocks_ ||= []

data/lib/tdl/rebuild_ele/ele_base.rb

@@ -128,7 +128,7 @@ module TdlSpace
                 define_method(tdl_key) do 
                     rel = self.instance_variable_get("@_#{tdl_key}_")
                     unless rel 
-                        "#{inst_name}.#{hdl_key}".to_nq
+                        TdlSpace::ArrayChain.create(obj: "#{inst_name}.#{hdl_key}".to_nq, belong_to_module: belong_to_module)
                     else 
                         rel 
                     end
@@ -152,9 +152,9 @@ module TdlSpace
                 define_method('clock') do 
                     rel = self.instance_variable_get("@_#{tdl_key}_")
                     if !dimension || dimension.empty?
-                        rel || TdlSpace::ArrayChain.new("#{self.inst_name}.#{hdl_key}")
+                        rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{hdl_key}", belong_to_module: belong_to_module)
                     else  
-                        rel || TdlSpace::ArrayChain.new("#{self.inst_name}[0].#{hdl_key}")
+                        rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}[0].#{hdl_key}", belong_to_module: belong_to_module)
                     end
                 end
 
@@ -171,7 +171,7 @@ module TdlSpace
              self.class_exec(tdl_key) do |tdl_key|
                 define_method('reset') do 
                     rel = self.instance_variable_get("@_#{tdl_key}_")
-                    rel || TdlSpace::ArrayChain.new("#{self.inst_name}.#{hdl_key}")
+                    rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{hdl_key}", belong_to_module: belong_to_module)
                 end
 
                 define_method("reset=") do |arg|
@@ -200,7 +200,7 @@ module TdlSpace
             self.class_exec(tdl_key) do |tdl_key|
                 define_method(tdl_key) do 
                     rel = self.instance_variable_get("@_#{tdl_key}_") || default_value
-                    rel || TdlSpace::ArrayChain.new("#{self.inst_name}.#{hdl_key}")
+                    rel || TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{hdl_key}", belong_to_module: belong_to_module)
                 end
 
                 define_method("#{tdl_key}=") do |arg|
@@ -215,7 +215,7 @@ module TdlSpace
                 _io_map(e,e,nil,'sdata',nil)
                 self.class_exec(e) do |e|
                     define_method(e) do 
-                        TdlSpace::ArrayChain.new("#{self.inst_name}.#{e}")
+                        TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{e}", belong_to_module: belong_to_module)
                     end
                 end
             end
@@ -225,7 +225,7 @@ module TdlSpace
             _io_map(name,name,nil,'pdata',dimension)
             self.class_exec(name) do |e|
                 define_method(e) do 
-                    TdlSpace::ArrayChain.new("#{self.inst_name}.#{e}")
+                    TdlSpace::ArrayChain.create(obj:"#{self.inst_name}.#{e}", belong_to_module: belong_to_module)
                 end
             end
         end
@@ -374,7 +374,7 @@ module TdlSpace
                     e.slaver = true
                 end 
             end
-            TdlSpace::ArrayChain.new(self,a)
+            TdlSpace::ArrayChain.create(obj: self,lchain: a, belong_to_module: belong_to_module)
         end
 
         def instance(exp_len: nil)
@@ -432,11 +432,16 @@ module TdlSpace
                 vv = rel || v[1]
                 # vv = self.send(k) || v[1]
                 ## 不例化 FreqM，FreqM只是为了SDL兼容
-                if vv && k.to_s != 'freqM'
+                # if vv && k.to_s != 'freqM'
+                if vv 
                     if vv.instance_of?(String)
                         str << ".#{v[0]}(\"#{vv}\")"
                     else
-                        str << ".#{v[0]}(#{vv})"
+                        if k.to_s == 'freqM'
+                            str << ".#{v[0]}(#{(respond_to?(:clock) && self.clock.is_a?(Clock) && self.clock.freqM ) || vv})"
+                        else 
+                            str << ".#{v[0]}(#{vv})"
+                        end
                     end
                 end
             end

data/lib/tdl/sdlmodule/sdlmodule.rb

@@ -74,7 +74,7 @@ class SdlModule
             if e.is_a? String 
                 next 
             end
-            tmp = e.new(name:"#{head}_NC")
+            tmp = e.new(name:"#{head}_NC",belong_to_module: self)
             tmp.belong_to_module = self
             tmp.ghost = true
             instance_variable_set("@#{head}_NC",tmp)
@@ -127,16 +127,6 @@ class SdlModule
         @@allmodule << self
         @module_name = name
         @real_sv_path = File.join(@out_sv_path,"#{@module_name}.sv") if @out_sv_path
-        # @port_clocks = []
-        # @port_resets = []
-        # @port_params = []
-        # @port_logics = []
-        # @port_datainfs = []
-        # @port_datainf_c_s = []
-        # @port_videoinfs = []
-        # @port_axisinfs = []
-        # @port_axi4infs = []
-        # @port_axilinfs = []
 
         @port_clocks        = Hash.new
         @port_resets        = Hash.new
@@ -164,52 +154,16 @@ class SdlModule
             # self.instance_variable_set("#{head_str}_NC",tmp)
         end
         create_ghost
-        # @super_modules = []
-        # @Logic_collect = []
-        # @Logic_inst = []
-        # @Logic_draw = []
-        #
-        # @Clock_collect = []
-        # @Clock_inst = []
-        # @Clock_draw = []
-        #
-        # @Reset_collect = []
-        # @Reset_inst = []
-        # @Reset_draw = []
-        #
-        # @Parameter_collect = []
-        # @Parameter_inst = []
-        # @Parameter_draw = []
-        #
-        # @DataInf_collect = []
-        # @DataInf_inst = []
-        # @DataInf_draw = []
-        #
-        # @DataInf_C_collect = []
-        # @DataInf_C_inst = []
-        # @DataInf_C_draw = []
-        #
-        # @AxiStream_collect = []
-        # @AxiStream_inst = []
-        # @AxiStream_draw = []
-        #
-        # @AxiLite_collect = []
-        # @AxiLite_inst = []
-        # @AxiLite_draw = []
-        #
-        # @VideoInf_collect = []
-        # @VideoInf_inst = []
-        # @VideoInf_draw = []
-        #
-        # @Axi4_collect = []
-        # @Axi4_inst = []
-        # @Axi4_draw = []
+
         if block_given?
             yield(self)
         end
 
         @instanced_and_parent_module ||= Hash.new
         @instance_and_children_module ||= Hash.new
+
+        ## 记录当前模块被例化的 具体对象
+        @instances =[]
     end
 
     public
@@ -473,3 +427,115 @@ class SdlModule
         end
     end
 end
+
+class SdlModule 
+
+    ## 获取信号的绝对路径
+    def path_refs(&block)
+        collects = []
+        if self != TopModule.current.techbench
+            @instances.each do |it|
+                it.origin.parents_inst_tree do |tree|
+                    ll = ["$root"]
+                    rt = tree.reverse
+                    rt.each_index do |index|
+                        if rt[index].respond_to? :module_name
+                            ll << rt[index].module_name 
+                        else 
+                            ll << rt[index].inst_name
+                        end
+                    end
+                    # ll << it.inst_name
+                    new_name = ll.join('.').to_nq
+                    if block_given?
+                        if yield(new_name)
+                            collects << new_name
+                        end 
+                    else
+                        collects << new_name
+                    end
+                end
+            end
+        else
+            collects = ["$root.#{self.module_name}".to_nq]
+        end
+        collects
+    end
+
+    ## 定义获取 信号的绝对路径
+    def root_ref(&block)
+        ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
+            rels = path_refs(&block)
+            if block_given?
+                sst = "block given"
+            else
+                sst = "no block"
+            end
+
+            if rels.size == 1
+                rels[0]
+            elsif rels.size == 0
+                raise TdlError.new "#{module_name} Cant find root ref {#{sst}}"
+            else
+                raise TdlError.new "#{module_name} Find multi root refs {#{sst}} \n#{rels.join("\n")}\n"
+            end
+        end
+    end
+
+end
+
+## 迭代 本模块及本模块的子模块
+class SdlModule 
+
+    def all_ref_sdlmodules(&block) 
+        sdlms = instance_and_children_module.values.uniq
+        sdlms = sdlms.map do |e|
+            if e.instance_and_children_module.any? 
+                e.all_ref_sdlmodules(&block)
+            else 
+                e 
+            end
+        end
+        sdlms = sdlms.unshift(self)
+        sdlms = sdlms.flatten
+        sdlms.map(&block)
+    end
+
+end
+
+### 有时候 sdlmodule 引用的是 HDL文件，为了能够 正常引用到 需要特殊处理
+class SdlModule
+    def contain_hdl(*hdl_names)
+        __contain_hdl__(false,*hdl_names)
+    end
+
+    def __contain_hdl__(recreate,*hdl_names)
+        hdl_names = hdl_names.map do |e| 
+
+            if e.include?("/") || e.include?("\\")
+                e 
+            else  
+                
+                ee = find_first_hdl_path(e)
+                if recreate && !ee 
+                    raise TdlError.new("Cant find #{e} in tdl_paths")
+                end
+                ee || e
+            end
+        end 
+        unless recreate
+            @__contain_hdl__ ||= []
+            @__contain_hdl__ += hdl_names
+        else 
+            @__contain_hdl__ = hdl_names
+        end
+        @__contain_hdl__.uniq!
+        @__contain_hdl__
+    end
+
+    def require_hdl(*hdl_path)
+        hdl_path.each do |hp|
+            __require_hdl__(hp,self)
+        end
+    end
+end