axi_tdl 0.1.0 → 0.1.8

data/lib/tdl/axi4/axi4_interconnect_verb.rb

@@ -66,7 +66,34 @@ class Axi4
             # next unless e.is_a? Axi4
             if e.is_a? Axi4
                 e.band_params_from(self)
-                @interconnect_up_streams << e
+                
+                ## e is a Vector 
+                if e.dimension[0].is_a?(Integer) && e.dimension[0] > 1
+                    # require_hdl 'axi4_direct_B1.sv'
+                    require_hdl 'axi4_direct_verc.sv'
+
+                    e.dimension[0].times do |xi|
+                        _ne = e.copy(name: "#{e.inst_name}_toM_#{xi}")
+                        # _ne << e[xi]
+                        # belong_to_module.Instance('axi4_direct_B1',"axi4_direc_#{e.inst_name}_toM_#{xi}") do |h|
+                        #     # h.param.MODE    mode_str    #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
+                        #     h.slaver_inf        e[xi]
+                        #     h.master_inf        _ne
+                        # end
+
+                        belong_to_module.Instance('axi4_direct_verc',"axi4_direc_#{e.inst_name}_toM_#{xi}") do |h|
+                            h.param.MODE            "#{_ne.mode}_to_#{_ne.mode}"    # //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
+                            h.param.SLAVER_MODE     _ne.mode    #    //
+                            h.param.MASTER_MODE     _ne.mode    #    //
+                            h.slaver_inf        e[xi]
+                            h.master_inf        _ne
+                        end
+                
+                        @interconnect_up_streams << _ne 
+                    end    
+                else
+                    @interconnect_up_streams << e
+                end
             else
                 raise TdlError.new("When use `<<` for axi4's M2S ,argvs must be axi4 too.\nOtherwise use `naxi4_mix_interconnect_M2S` directly")
             end
@@ -218,11 +245,20 @@ class Axi4
                 else
                     mode_str = "ONLY_READ_to_BOTH"
                 end
-                require_hdl 'axi4_direct_B1.sv'
-                # Axi4.axi4_direct_a1(mode:mode_str,slaver:lo,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
-                belong_to_module.Instance('axi4_direct_B1',"axi4_direct_a1_long_to_wide_#{sub_name}_#{globle_random_name_flag()}") do |h|
-                    # h.param.MODE    mode_str    #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
-                    h.slaver_inf        lo
+                # require_hdl 'axi4_direct_B1.sv'
+                # # Axi4.axi4_direct_a1(mode:mode_str,slaver:lo,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
+                # belong_to_module.Instance('axi4_direct_B1',"axi4_direct_a1_long_to_wide_#{sub_name}_#{globle_random_name_flag()}") do |h|
+                #     # h.param.MODE    mode_str    #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
+                #     h.slaver_inf        lo
+                #     h.master_inf        "#{sub_name}[#{index}]".to_nq
+                # end
+
+                require_hdl 'axi4_direct_verc.sv'
+                belong_to_module.Instance('axi4_direct_verc',"axi4_direct_a1_long_to_wide_#{sub_name}_#{globle_random_name_flag()}") do |h|
+                    h.param.MODE            mode_str    # //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
+                    h.param.SLAVER_MODE     (wr_lg ? "ONLY_WRITE" : "ONLY_READ")    #    //
+                    h.param.MASTER_MODE     "BOTH"    #    //
+                    h.slaver_inf        (lo.respond_to?(:dimension) && lo.dimension[0]==1 && lo[0])  || lo
                     h.master_inf        "#{sub_name}[#{index}]".to_nq
                 end
 
@@ -252,10 +288,11 @@ class Axi4
         @_long_slim_to_wide.each do |e|
             mode_str = e.mode + "_to_BOTH"
             # Axi4.axi4_direct_a1(mode:mode_str,slaver:e,master:"#{sub_name}[#{index}]",belong_to_module:belong_to_module)
+            require_hdl 'axi4_direct_B1.sv'
             belong_to_module.Instance('axi4_direct_B1',"axi4_direct_a1_inst_long_to_wide_#{sub_name}") do |h|
                 # h.param.MODE    mode_str    #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
-                h.slaver        e
-                h.master        "#{sub_name}[#{index}]".to_nq
+                h.slaver_inf        e
+                h.master_inf        "#{sub_name}[#{index}]".to_nq
             end
             index = index + 1
         end
@@ -311,8 +348,8 @@ class Axi4
 "\naxi4_direct_B1 /* #(
     .MODE       (\"#{_str}\")    //ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
 )*/ iterconnect_direct_A1_#{name}_instMM(
-/* axi_inf.slaver */  .slaver   (sub_axi_#{name}_inf[0]),
-/* axi_inf.master */  .master   (#{name})
+/* axi_inf.slaver */  .slaver_inf   (sub_axi_#{name}_inf[0]),
+/* axi_inf.master */  .master_inf   (#{name})
 );\n"
         end
 

data/lib/tdl/class_hdl/hdl_always_comb.rb

@@ -7,6 +7,9 @@ module ClassHDL
         def initialize(belong_to_module)
             @opertor_chains = []
             @belong_to_module = belong_to_module
+            unless @belong_to_module
+                raise TdlError.new("HDLAlwaysCombBlock must have belong_to_module")
+            end
         end
 
         def instance
@@ -17,7 +20,7 @@ module ClassHDL
                     str.push op.instance(:assign).gsub(/^./){ |m| "    #{m}"}
                 else 
                     unless op.slaver
-                        rel_str = ClassHDL.compact_op_ch(op.instance(:assign))
+                        rel_str = ClassHDL.compact_op_ch(op.instance(:assign, @belong_to_module))
                         str.push "    #{rel_str};"
                     end
                 end

data/lib/tdl/class_hdl/hdl_always_ff.rb

@@ -63,7 +63,7 @@ module ClassHDL
                     str.push op.instance(:always_ff).gsub(/^./){ |m| "    #{m}"}
                 else 
                     unless op.slaver
-                        rel_str = ClassHDL.compact_op_ch(op.instance(:always_ff))
+                        rel_str = ClassHDL.compact_op_ch(op.instance(:always_ff, belong_to_module))
                         str.push "    #{rel_str};"
                     end
                 end
@@ -89,7 +89,7 @@ module ClassHDL
                     str.push op.instance(:always_ff).gsub(/^./){ |m| "    #{m}"}
                 else 
                     unless op.slaver
-                        rel_str = ClassHDL.compact_op_ch(op.instance(:always_ff))
+                        rel_str = ClassHDL.compact_op_ch(op.instance(:always_ff,belong_to_module))
                         str.push "    #{rel_str};"
                     end
                 end
@@ -143,7 +143,7 @@ module ClassHDL
                     str.push op.instance(:assign).gsub(/^./){ |m| "    #{m}"}
                 else 
                     unless op.slaver
-                        rel_str = ClassHDL.compact_op_ch(op.instance(:assign))
+                        rel_str = ClassHDL.compact_op_ch(op.instance(:assign, belong_to_module))
                         str.push "    #{rel_str};"
                     end
                 end

data/lib/tdl/class_hdl/hdl_assign.rb

@@ -8,14 +8,20 @@ module ClassHDL
         def initialize(belong_to_module)
             @opertor_chains = []
             @belong_to_module = belong_to_module
+            unless @belong_to_module 
+                raise TdlError.new("HDLAssignBlock must have belong_to_module")
+            end
         end
 
         def instance
+            unless @belong_to_module.is_a?(SdlModule) 
+                raise TdlError.new("HDLAssignBlock must have belong_to_module")
+            end
             str = []
             opertor_chains.each do |op|
                 
                 unless op.slaver
-                    sub_str = op.instance(:assign)
+                    sub_str = op.instance(:assign,belong_to_module)
                     # if sub_str =~ /^(?<head>[\w\.\[\]\:]+\s*)(?<eq><?=\s*)\((?<body>.+)\)$/
                     #     rel_str = $~[:head] + $~[:eq] + $~[:body]
                     # else 

data/lib/tdl/class_hdl/hdl_block_ifelse.rb

@@ -11,7 +11,7 @@ module ClassHDL
 
         def instance(as_type= :cond)
             if cond.is_a? ClassHDL::OpertorChain
-                head_str = "if(#{cond.instance(:cond)})begin"
+                head_str = "if(#{cond.instance(:cond, belong_to_module)})begin"
             else 
                 head_str = "if(#{cond.to_s})begin"
             end
@@ -20,7 +20,7 @@ module ClassHDL
             opertor_chains.each do |oc|
                 unless oc.is_a? BlockIF
                     unless oc.slaver
-                        rel_str = ClassHDL.compact_op_ch(oc.instance(as_type))
+                        rel_str = ClassHDL.compact_op_ch(oc.instance(as_type, belong_to_module))
                         sub_str.push "    #{rel_str};"
                     end
                 else 
@@ -36,7 +36,7 @@ module ClassHDL
     class BlockELSIF < BlockIF
         def instance(as_type= :cond)
             if cond.is_a? ClassHDL::OpertorChain
-                head_str = "else if(#{cond.instance(:cond)})begin"
+                head_str = "else if(#{cond.instance(:cond, belong_to_module)})begin"
             else 
                 head_str = "else if(#{cond.to_s})begin"
             end
@@ -45,7 +45,7 @@ module ClassHDL
             opertor_chains.each do |oc|
                 unless oc.is_a? BlockIF
                     unless oc.slaver
-                        sub_str.push "    #{oc.instance(as_type)};"
+                        sub_str.push "    #{oc.instance(as_type, belong_to_module)};"
                     end
                 else 
                     sub_str.push( oc.instance(as_type).gsub(/^./){ |m| "    #{m}"} )
@@ -66,7 +66,7 @@ module ClassHDL
             opertor_chains.each do |oc|
                 unless oc.is_a? BlockIF
                     unless oc.slaver
-                        sub_str.push "    #{oc.instance(as_type)};"
+                        sub_str.push "    #{oc.instance(as_type, belong_to_module)};"
                     end
                 else 
                     sub_str.push( oc.instance(as_type).gsub(/^./){ |m| "    #{m}"} )
@@ -135,7 +135,7 @@ module ClassHDL
             opertor_chains.each do |oc|
                 unless oc.is_a? BlockIF
                     unless oc.slaver
-                        sub_str.push "    #{oc.instance(as_type)};"
+                        sub_str.push "    #{oc.instance(as_type, belong_to_module)};"
                     end
                 else 
                     sub_str.push( oc.instance(as_type).gsub(/^./){ |m| "    #{m}"} )
@@ -168,7 +168,7 @@ module ClassHDL
             opertor_chains.each do |oc|
                 unless oc.is_a? BlockIF
                     unless oc.slaver
-                        sub_str.push "    #{oc.instance(as_type)};"
+                        sub_str.push "    #{oc.instance(as_type, belong_to_module)};"
                     end
                 else 
                     sub_str.push( oc.instance(as_type).gsub(/^./){ |m| "    #{m}"} )

data/lib/tdl/class_hdl/hdl_foreach.rb

@@ -10,7 +10,7 @@ module ClassHDL
             opertor_chains.each do |oc|
                 unless oc.is_a? BlockIF
                     unless oc.slaver
-                        sub_str.push "    #{oc.instance(as_type)};"
+                        sub_str.push "    #{oc.instance(as_type, belong_to_module)};"
                     end
                 else 
                     sub_str.push( oc.instance(as_type).gsub(/^./){ |m| "    #{m}"} )
@@ -36,7 +36,7 @@ module ClassHDL
             opertor_chains.each do |oc|
                 unless oc.is_a? BlockIF
                     unless oc.slaver
-                        sub_str.push "    #{oc.instance(as_type)};"
+                        sub_str.push "    #{oc.instance(as_type,belong_to_module)};"
                     end
                 else 
                     sub_str.push( oc.instance(as_type).gsub(/^./){ |m| "    #{m}"} )

data/lib/tdl/class_hdl/hdl_function.rb

@@ -13,7 +13,7 @@ module ClassHDL
             if @func_inst.return_type.is_a? StructMeta
                 @func_inst.return_type.struct_slots.each do |e|
                     self.define_singleton_method(e.name) do 
-                        TdlSpace::ArrayChain.new("#{@func_inst.name}.#{e.name}".to_nq)
+                        TdlSpace::ArrayChain.create(obj: "#{@func_inst.name}.#{e.name}".to_nq, belong_to_module: @func_inst.belong_to_module )
                     end
                 end
             end
@@ -90,7 +90,7 @@ module ClassHDL
                     str.push op.instance(:assign).gsub(/^./){ |m| "    #{m}"}
                 else 
                     unless op.slaver
-                        rel_str = ClassHDL.compact_op_ch(op.instance(:assign))
+                        rel_str = ClassHDL.compact_op_ch(op.instance(:assign,belong_to_module))
                         str.push "    #{rel_str};"
                     end
                 end
@@ -193,7 +193,7 @@ module ClassHDL
                 # pin,iostd = parse_pin_prop(pin_prop) if pin_prop
                 # RedefOpertor.with_normal_operators do
                 ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
-                    tmp = Logic.new(name:name,dsize:dsize,port:"input",dimension:dimension)
+                    tmp = Logic.new(name:name,dsize:dsize,port:"input",dimension:dimension, belong_to_module: self)
                     # add_to_new_module("@port_logics",tmp)
                     # add_method_to_itgt(name,tmp)
                     tmp
@@ -205,7 +205,7 @@ module ClassHDL
                 # pin,iostd = parse_pin_prop(pin_prop) if pin_prop
                 # RedefOpertor.with_normal_operators do
                 ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do
-                    tmp = Logic.new(name:name,dsize:dsize,port:"output logic",dimension:dimension)
+                    tmp = Logic.new(name:name,dsize:dsize,port:"output logic",dimension:dimension, belong_to_module: self)
                     # add_to_new_module("@port_logics",tmp)
         
                     if block_given?

data/lib/tdl/class_hdl/hdl_generate.rb

@@ -20,6 +20,9 @@ module ClassHDL
         def initialize(belong_to_module)
             @belong_to_module = belong_to_module
             super("genblk#{globle_random_name_flag()}")
+            unless @belong_to_module
+                raise TdlError.new("GenerateBlock must have belong_to_module")
+            end
         end
 
 
@@ -41,7 +44,7 @@ module ClassHDL
         def IF(cond,&block)
             if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? HDLAssignGenerateBlock
                 if cond.respond_to?(:instance)
-                    head_str = "\nif(#{cond.instance(:cond)})begin\n"
+                    head_str = "\nif(#{cond.instance(:cond, @belong_to_module)})begin\n"
                 else 
                     head_str = "\nif(#{cond})begin\n"
                 end
@@ -67,7 +70,7 @@ module ClassHDL
         def ELSIF(cond,&block)
             if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? HDLAssignGenerateBlock
                 if cond.respond_to?(:instance)
-                    head_str = "else if(#{cond.instance(:cond)})begin\n"
+                    head_str = "else if(#{cond.instance(:cond,@belong_to_module)})begin\n"
                 else 
                     head_str = "else if(#{cond})begin\n"
                 end

data/lib/tdl/class_hdl/hdl_initial.rb

@@ -7,6 +7,9 @@ module ClassHDL
         def initialize(belong_to_module)
             @opertor_chains = []
             @belong_to_module = belong_to_module
+            unless @belong_to_module 
+                raise TdlError.new("HDLInitialBlock must have belong_to_module")
+            end
         end
 
         def instance(block_name=nil)
@@ -17,7 +20,26 @@ module ClassHDL
                     str.push op.instance(:assign).gsub(/^./){ |m| "    #{m}"}
                 else 
                     unless op.slaver
-                        rel_str = ClassHDL.compact_op_ch(op.instance(:assign))
+                        rel_str = ClassHDL.compact_op_ch(op.instance(:assign, belong_to_module))
+                        str.push "    #{rel_str};"
+                    end
+                end
+                
+            end
+            str.push "end\n"
+            str.join("\n")
+        end
+
+        def instance_inspect()
+            str = []
+            block_name=nil
+            str.push "initial begin#{block_name ? ':'.concat(block_name.to_s) : ''}"
+            opertor_chains.each do |op|
+                unless op.is_a? OpertorChain
+                    str.push op.instance(:assign).gsub(/^./){ |m| "    #{m}"}
+                else 
+                    unless op.slaver
+                        rel_str = ClassHDL.compact_op_ch(op.instance(:assign,belong_to_module))
                         str.push "    #{rel_str};"
                     end
                 end
@@ -41,7 +63,7 @@ module ClassHDL
     class BlocAssertIF < BlockIF
         def instance(as_type= :cond)
             if cond.is_a? ClassHDL::OpertorChain
-                head_str = "assert(#{cond.instance(:cond)})else begin"
+                head_str = "assert(#{cond.instance(:cond, belong_to_module)})else begin"
             else 
                 head_str = "assert(#{cond.to_s})else begin"
             end
@@ -50,7 +72,7 @@ module ClassHDL
             opertor_chains.each do |oc|
                 unless oc.is_a? BlockIF
                     unless oc.slaver
-                        sub_str.push "    #{oc.instance(as_type)};"
+                        sub_str.push "    #{oc.instance(as_type,belong_to_module)};"
                     end
                 else 
                     sub_str.push( oc.instance(as_type).gsub(/^./){ |m| "    #{m}"} )

data/lib/tdl/class_hdl/hdl_module_def.rb

@@ -170,6 +170,9 @@ module ClassHDL
         def initialize(sdlm,args={})
             @chain = []
             @sdlm = sdlm
+            unless @sdlm 
+                raise TdlError.new("ImplicitPortBase<#{args.to_s}> dont have belong_to_module")
+            end
             @up_args = args
         end
 
@@ -298,7 +301,7 @@ module ClassHDL
             if sub_type.is_a? StructMeta
                 @sub_type.struct_slots.each do |e|
                     obj.define_singleton_method(e.name) do 
-                        TdlSpace::ArrayChain.new("#{obj.name}.#{e.name}".to_nq)
+                        TdlSpace::ArrayChain.create(obj: "#{obj.name}.#{e.name}".to_nq, belong_to_module: obj.belong_to_module)
                     end
                 end
             end
@@ -380,27 +383,27 @@ class SdlModule
 
     def >>(*args)
         str = "{>>{#{args.map{|e| e.to_s }.join(',')}}}"
-        TdlSpace::ArrayChain.new(str)
+        TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
     end
 
     def <<(*args)
         str = "{<<{#{args.map{|e| e.to_s }.join(',')}}}"
-        TdlSpace::ArrayChain.new(str)
+        TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
     end
 
     def logic_bind_(*args)
         str = "{#{args.map{|e| e.to_s }.join(',')}}"
-        TdlSpace::ArrayChain.new(str)
+        TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
     end
 
     def clog2(arg)
         str = "$clog2(#{arg.to_s})"
-        TdlSpace::ArrayChain.new(str)
+        TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
     end
 
     def bits(arg)
         str = "$bits(#{arg.to_s})"
-        TdlSpace::ArrayChain.new(str)
+        TdlSpace::ArrayChain.create(obj: str, belong_to_module: self)
     end
 
 end

data/lib/tdl/class_hdl/hdl_package.rb

@@ -90,6 +90,51 @@ module ClassHDL
             return str
         end
 
+        def build_module_verb(ex_param: "",ex_port: "",ex_up_code: "",ex_down_code: "")
+            # Tdl.Puts pagination(module_name)
+            Tdl.Build_SdlModule_Puts(module_name)
+    
+            ex_param        = ex_param.to_s     unless ex_param
+            ex_port         = ex_port.to_s      unless ex_port
+            ex_up_code      = ex_up_code.to_s   unless ex_up_code
+            ex_down_code    = ex_down_code.to_s unless ex_down_code
+    
+            # gen_auto_method     # auto generate class method for interface
+            # draw = Tdl.inst + Tdl.draw
+    
+            instance_draw_str = instance_draw       # It must run before vars_define_inst,because some signals define when inst
+            vars_exec_inst_str = vars_exec_inst     # It must run before vars_define_inst,because some signals define when vars exec
+    
+            post_str = post_inst_stack_call()
+    
+            unless post_str.strip.empty?
+                post_str = pagination("ROOT REF") + post_str
+            end
+    
+            draw = pagination("define") + vars_define_inst + pagination("instance") + instance_draw_str + pagination("expression") + vars_exec_inst_str + post_str
+    
+            unless ex_up_code.empty?
+                ex_up_code = "\n//------>> EX CODE <<-------------------\n" + ex_up_code + "//------<< EX CODE >>-------------------\n"
+            end
+    
+            unless ex_down_code.empty?
+                ex_down_code = "//------>> EX CODE <<-------------------\n" + ex_down_code + "//------<< EX CODE >>-------------------\n"
+            end
+    
+
+            module_name_str = @module_name
+    
+    
+            # str = module_head+"package #{module_name_str};\n"  + build_params(ex_param) + ex_up_code + draw + ex_down_code + "\nendpackage:#{module_name_str}\n" + add_sub_module_file_paths
+            str = "package #{module_name_str};\n"  + build_params(ex_param) + ex_up_code + draw + ex_down_code + "\nendpackage:#{module_name_str}\n" + add_sub_module_file_paths
+
+            create_vivado_tcl if @create_tcl
+            create_constraints_file if @create_sdc
+    
+            return [module_head_verb,str]
+        end
+
+
     end
 
     # class ReqPakcgeLine