smallworld-re 1.0.0__py3-none-any.whl

smallworld/state/cpus/mips64.py

@@ -0,0 +1,372 @@
+import typing
+
+from ... import platforms
+from .. import state
+from . import cpu
+
+
+class MIPS64(cpu.CPU):
+    """Abstract CPU state object for all MIPS64 targets"""
+
+    # Excluded registers:
+    # - zero: Hard-wired to zero
+    # - at: Reserved for assembler
+    # - kX: Reserved for kernel; used as general in some ABIs
+    # - fX: Floating-point registers
+    # - acX: Accumulator registers
+    _GENERAL_PURPOSE_REGS = [
+        "v0",
+        "v1",
+        "a0",
+        "a1",
+        "a2",
+        "a3",
+        "a4",
+        "a5",
+        "a6",
+        "a7",
+        "t0",
+        "t1",
+        "t2",
+        "t3",
+        "t4",
+        "t8",
+        "t9",
+        "s0",
+        "s1",
+        "s2",
+        "s3",
+        "s4",
+        "s5",
+        "s6",
+        "s7",
+        "s8",
+    ]
+
+    def get_general_purpose_registers(self) -> typing.List[str]:
+        return self._GENERAL_PURPOSE_REGS
+
+    def __init__(self):
+        super().__init__()
+        # NOTE: MIPS registers have both a name and a number.
+        # NOTE: This follows the n64 ABI.
+        # According to n64, there are only six temporary registers;
+        # t0 - t3, t8 and t9.
+
+        # *** General-Purpose Registers ***
+        # Assembler-Temporary Register
+        self.at = state.Register("at", size=8)
+        self.add(self.at)
+        self._1 = state.RegisterAlias("1", self.at, size=8, offset=0)
+        self.add(self._1)
+        # Return Value Registers
+        self.v0 = state.Register("v0", size=8)
+        self.add(self.v0)
+        self._2 = state.RegisterAlias("2", self.v0, size=8, offset=0)
+        self.add(self._2)
+        self.v1 = state.Register("v1", size=8)
+        self.add(self.v1)
+        self._3 = state.RegisterAlias("3", self.v1, size=8, offset=0)
+        self.add(self._3)
+        # Argument Registers
+        self.a0 = state.Register("a0", size=8)
+        self.add(self.a0)
+        self._4 = state.RegisterAlias("4", self.a0, size=8, offset=0)
+        self.add(self._4)
+        self.a1 = state.Register("a1", size=8)
+        self.add(self.a1)
+        self._5 = state.RegisterAlias("5", self.a1, size=8, offset=0)
+        self.add(self._5)
+        self.a2 = state.Register("a2", size=8)
+        self.add(self.a2)
+        self._6 = state.RegisterAlias("6", self.a2, size=8, offset=0)
+        self.add(self._6)
+        self.a3 = state.Register("a3", size=8)
+        self.add(self.a3)
+        self._7 = state.RegisterAlias("7", self.a3, size=8, offset=0)
+        self.add(self._7)
+        self.a4 = state.Register("a4", size=8)
+        self.add(self.a4)
+        self._8 = state.RegisterAlias("8", self.a4, size=8, offset=0)
+        self.add(self._8)
+        self.a5 = state.Register("a5", size=8)
+        self.add(self.a5)
+        self._9 = state.RegisterAlias("9", self.a5, size=8, offset=0)
+        self.add(self._9)
+        self.a6 = state.Register("a6", size=8)
+        self.add(self.a6)
+        self._10 = state.RegisterAlias("10", self.a6, size=8, offset=0)
+        self.add(self._10)
+        self.a7 = state.Register("a7", size=8)
+        self.add(self.a7)
+        self._11 = state.RegisterAlias("11", self.a7, size=8, offset=0)
+        self.add(self._11)
+        # Temporary Registers
+        self.t0 = state.Register("t0", size=8)
+        self.add(self.t0)
+        self._12 = state.RegisterAlias("12", self.t0, size=8, offset=0)
+        self.add(self._12)
+        self.t1 = state.Register("t1", size=8)
+        self.add(self.t1)
+        self._13 = state.RegisterAlias("13", self.t1, size=8, offset=0)
+        self.add(self._13)
+        self.t2 = state.Register("t2", size=8)
+        self.add(self.t2)
+        self._14 = state.RegisterAlias("14", self.t2, size=8, offset=0)
+        self.add(self._14)
+        self.t3 = state.Register("t3", size=8)
+        self.add(self.t3)
+        self._15 = state.RegisterAlias("15", self.t3, size=8, offset=0)
+        self.add(self._15)
+        # NOTE: These numbers aren't out of order.
+        # t8 and t9 are later in the register file than t0 - t3.
+        # The gap is also intentional; t4 - t7 were sacrificed
+        # to make room for a4 - a7
+        self.t8 = state.Register("t8", size=8)
+        self.add(self.t8)
+        self._24 = state.RegisterAlias("24", self.t8, size=8, offset=0)
+        self.add(self._24)
+        self.t9 = state.Register("t9", size=8)
+        self.add(self.t9)
+        self._25 = state.RegisterAlias("25", self.t9, size=8, offset=0)
+        self.add(self._25)
+        # Saved Registers
+        self.s0 = state.Register("s0", size=8)
+        self.add(self.s0)
+        self._16 = state.RegisterAlias("16", self.s0, size=8, offset=0)
+        self.add(self._16)
+        self.s1 = state.Register("s1", size=8)
+        self.add(self.s1)
+        self._17 = state.RegisterAlias("17", self.s1, size=8, offset=0)
+        self.add(self._17)
+        self.s2 = state.Register("s2", size=8)
+        self.add(self.s2)
+        self._18 = state.RegisterAlias("18", self.s2, size=8, offset=0)
+        self.add(self._18)
+        self.s3 = state.Register("s3", size=8)
+        self.add(self.s3)
+        self._19 = state.RegisterAlias("19", self.s3, size=8, offset=0)
+        self.add(self._19)
+        self.s4 = state.Register("s4", size=8)
+        self.add(self.s4)
+        self._20 = state.RegisterAlias("20", self.s4, size=8, offset=0)
+        self.add(self._20)
+        self.s5 = state.Register("s5", size=8)
+        self.add(self.s5)
+        self._21 = state.RegisterAlias("21", self.s5, size=8, offset=0)
+        self.add(self._21)
+        self.s6 = state.Register("s6", size=8)
+        self.add(self.s6)
+        self._22 = state.RegisterAlias("22", self.s6, size=8, offset=0)
+        self.add(self._22)
+        self.s7 = state.Register("s7", size=8)
+        self.add(self.s7)
+        self._23 = state.RegisterAlias("23", self.s7, size=8, offset=0)
+        self.add(self._23)
+        # NOTE: Register #30 was originally the Frame Pointer.
+        # It's been re-aliased as s8, since many ABIs don't use the frame pointer.
+        # Unicorn and Sleigh prefer to use the alias s8,
+        # so it should be the base register.
+        self.s8 = state.Register("s8", size=8)
+        self.add(self.s8)
+        self.fp = state.RegisterAlias("fp", self.s8, size=8, offset=0)
+        self.add(self.fp)
+        self._30 = state.RegisterAlias("30", self.s8, size=8, offset=0)
+        self.add(self._30)
+        # Kernel-reserved Registers
+        self.k0 = state.Register("k0", size=8)
+        self.add(self.k0)
+        self._26 = state.RegisterAlias("26", self.k0, size=8, offset=0)
+        self.add(self._26)
+        self.k1 = state.Register("k1", size=8)
+        self.add(self.k1)
+        self._27 = state.RegisterAlias("27", self.k1, size=8, offset=0)
+        self.add(self._27)
+        # *** Pointer Registers ***
+        # Zero register
+        self.zero = state.FixedRegister("zero", size=8, value=0)
+        self.add(self.zero)
+        self._0 = state.RegisterAlias("0", self.zero, size=8, offset=0)
+        self.add(self._0)
+        # Global Offset Pointer
+        self.gp = state.Register("gp", size=8)
+        self.add(self.gp)
+        self._28 = state.RegisterAlias("28", self.gp, size=8, offset=0)
+        self.add(self._28)
+        # Stack Pointer
+        self.sp = state.Register("sp", size=8)
+        self.add(self.sp)
+        self._29 = state.RegisterAlias("29", self.sp, size=8, offset=0)
+        self.add(self._29)
+        # Return Address
+        self.ra = state.Register("ra", size=8)
+        self.add(self.ra)
+        self._31 = state.RegisterAlias("31", self.ra, size=8, offset=0)
+        self.add(self._31)
+        # Program Counter
+        self.pc = state.Register("pc", size=8)
+        self.add(self.pc)
+        # *** Floating Point Registers ***
+        self.f1 = state.Register("f1", size=8)
+        self.add(self.f1)
+        self.f0 = state.Register("f0", size=8)
+        self.add(self.f0)
+        self.f3 = state.Register("f3", size=8)
+        self.add(self.f3)
+        self.f2 = state.Register("f2", size=8)
+        self.add(self.f2)
+        self.f5 = state.Register("f5", size=8)
+        self.add(self.f5)
+        self.f4 = state.Register("f4", size=8)
+        self.add(self.f4)
+        self.f7 = state.Register("f7", size=8)
+        self.add(self.f7)
+        self.f6 = state.Register("f6", size=8)
+        self.add(self.f6)
+        self.f9 = state.Register("f9", size=8)
+        self.add(self.f9)
+        self.f8 = state.Register("f8", size=8)
+        self.add(self.f8)
+        self.f11 = state.Register("f11", size=8)
+        self.add(self.f11)
+        self.f10 = state.Register("f10", size=8)
+        self.add(self.f10)
+        self.f13 = state.Register("f13", size=8)
+        self.add(self.f13)
+        self.f12 = state.Register("f12", size=8)
+        self.add(self.f12)
+        self.f15 = state.Register("f15", size=8)
+        self.add(self.f15)
+        self.f14 = state.Register("f14", size=8)
+        self.add(self.f14)
+        self.f17 = state.Register("f17", size=8)
+        self.add(self.f17)
+        self.f16 = state.Register("f16", size=8)
+        self.add(self.f16)
+        self.f19 = state.Register("f19", size=8)
+        self.add(self.f19)
+        self.f18 = state.Register("f18", size=8)
+        self.add(self.f18)
+        self.f21 = state.Register("f21", size=8)
+        self.add(self.f21)
+        self.f20 = state.Register("f20", size=8)
+        self.add(self.f20)
+        self.f23 = state.Register("f23", size=8)
+        self.add(self.f23)
+        self.f22 = state.Register("f22", size=8)
+        self.add(self.f22)
+        self.f25 = state.Register("f25", size=8)
+        self.add(self.f25)
+        self.f24 = state.Register("f24", size=8)
+        self.add(self.f24)
+        self.f27 = state.Register("f27", size=8)
+        self.add(self.f27)
+        self.f26 = state.Register("f26", size=8)
+        self.add(self.f26)
+        self.f29 = state.Register("f29", size=8)
+        self.add(self.f29)
+        self.f28 = state.Register("f28", size=8)
+        self.add(self.f28)
+        self.f31 = state.Register("f31", size=8)
+        self.add(self.f31)
+        self.f30 = state.Register("f30", size=8)
+        self.add(self.f30)
+        # *** Floating Point Control Registers ***
+        # NOTE: These are taken from Sleigh, and the MIPS docs.
+        # Unicorn doesn't use these names, and has a different number of registers.
+        self.fir = state.Register("fir", size=4)
+        self.add(self.fir)
+        self.fcsr = state.Register("fcsr", size=4)
+        self.add(self.fcsr)
+        self.fexr = state.Register("fexr", size=4)
+        self.add(self.fexr)
+        self.fenr = state.Register("fenr", size=4)
+        self.add(self.fenr)
+        self.fccr = state.Register("fccr", size=4)
+        self.add(self.fccr)
+
+
+class MIPS64EL(MIPS64):
+    """Auto-generated CPU state for mips:mips32:little.
+
+    Generated from Pcode language MIPS:LE:32:default, and Unicorn package
+    unicorn.mips_const.
+    """
+
+    platform = platforms.Platform(
+        platforms.Architecture.MIPS64, platforms.Byteorder.LITTLE
+    )
+
+    def __init__(self):
+        super().__init__()
+        # *** Accumulator Registers ***
+        # MIPS uses these to implement 128-bit results
+        # from 64-bit multiplication, amongst others.
+        self.ac0 = state.Register("ac0", size=16)
+        self.add(self.ac0)
+        self.lo = state.RegisterAlias("lo0", self.ac0, size=8, offset=0)
+        self.add(self.lo)
+        self.hi = state.RegisterAlias("hi0", self.ac0, size=8, offset=4)
+        self.add(self.hi)
+        self.ac1 = state.Register("ac1", size=16)
+        self.add(self.ac1)
+        self.lo1 = state.RegisterAlias("lo1", self.ac1, size=8, offset=0)
+        self.add(self.lo1)
+        self.hi1 = state.RegisterAlias("hi1", self.ac1, size=8, offset=4)
+        self.add(self.hi1)
+        self.ac2 = state.Register("ac2", size=16)
+        self.add(self.ac2)
+        self.lo2 = state.RegisterAlias("lo2", self.ac2, size=8, offset=0)
+        self.add(self.lo2)
+        self.hi2 = state.RegisterAlias("hi2", self.ac2, size=8, offset=4)
+        self.add(self.hi2)
+        self.ac3 = state.Register("ac3", size=16)
+        self.add(self.ac3)
+        self.lo3 = state.RegisterAlias("lo3", self.ac3, size=8, offset=0)
+        self.add(self.lo3)
+        self.hi3 = state.RegisterAlias("hi3", self.ac3, size=8, offset=4)
+        self.add(self.hi3)
+        # TODO: MIPS has a boatload of extensions with their own registers.
+        # There isn't a clean join between Sleigh, Unicorn, and MIPS docs.
+
+
+class MIPS64BE(MIPS64):
+    """Auto-generated CPU state for mips:mips32:big.
+
+    Generated from Pcode language MIPS:BE:32:default, and Unicorn package
+    unicorn.mips_const.
+    """
+
+    platform = platforms.Platform(
+        platforms.Architecture.MIPS64, platforms.Byteorder.BIG
+    )
+
+    def __init__(self):
+        super().__init__()
+        # *** Accumulator Registers ***
+        # MIPS uses these to implement 64-bit results
+        # from 32-bit multiplication, amongst others.
+        self.ac0 = state.Register("ac0", size=8)
+        self.add(self.ac0)
+        self.hi = state.RegisterAlias("hi0", self.ac0, size=8, offset=0)
+        self.add(self.hi)
+        self.lo = state.RegisterAlias("lo0", self.ac0, size=8, offset=4)
+        self.add(self.lo)
+        self.ac1 = state.Register("ac1", size=8)
+        self.add(self.ac1)
+        self.hi1 = state.RegisterAlias("hi1", self.ac1, size=8, offset=0)
+        self.add(self.hi1)
+        self.lo1 = state.RegisterAlias("lo1", self.ac1, size=8, offset=4)
+        self.add(self.lo1)
+        self.ac2 = state.Register("ac2", size=8)
+        self.add(self.ac2)
+        self.hi2 = state.RegisterAlias("hi2", self.ac2, size=8, offset=0)
+        self.add(self.hi2)
+        self.lo2 = state.RegisterAlias("lo2", self.ac2, size=8, offset=4)
+        self.add(self.lo2)
+        self.ac3 = state.Register("ac3", size=8)
+        self.add(self.ac3)
+        self.hi3 = state.RegisterAlias("hi3", self.ac3, size=8, offset=0)
+        self.add(self.hi3)
+        self.lo3 = state.RegisterAlias("lo3", self.ac3, size=8, offset=4)
+        self.add(self.lo3)

smallworld/state/cpus/powerpc.py

@@ -0,0 +1,229 @@
+import typing
+
+from ... import platforms
+from .. import state
+from . import cpu
+
+
+class PowerPC(cpu.CPU):
+    """CPU state for 32-bit PowerPC."""
+
+    _GENERAL_PURPOSE_REGS = [f"r{i}" for i in range(0, 32)]
+
+    def get_general_purpose_registers(self) -> typing.List[str]:
+        return self._GENERAL_PURPOSE_REGS
+
+    def __init__(self, wordsize):
+        super().__init__()
+        # *** General Purpose Registers ***
+        # NOTE: Used expressive names for GPRs and FPRs.
+        # gasm just refers to GPRs and FPRS by number.
+        # They use the same numbers; it's very annoying.
+        self.r0 = state.Register("r0", size=wordsize)
+        self.add(self.r0)
+        # NOTE: GPR 1 is also the stack pointer.
+        self.r1 = state.Register("r1", size=wordsize)
+        self.add(self.r1)
+        self.sp = state.RegisterAlias("sp", self.r1, size=wordsize, offset=0)
+        self.add(self.sp)
+        self.r2 = state.Register("r2", size=wordsize)
+        self.add(self.r2)
+        self.r3 = state.Register("r3", size=wordsize)
+        self.add(self.r3)
+        self.r4 = state.Register("r4", size=wordsize)
+        self.add(self.r4)
+        self.r5 = state.Register("r5", size=wordsize)
+        self.add(self.r5)
+        self.r6 = state.Register("r6", size=wordsize)
+        self.add(self.r6)
+        self.r7 = state.Register("r7", size=wordsize)
+        self.add(self.r7)
+        self.r8 = state.Register("r8", size=wordsize)
+        self.add(self.r8)
+        self.r9 = state.Register("r9", size=wordsize)
+        self.add(self.r9)
+        self.r10 = state.Register("r10", size=wordsize)
+        self.add(self.r10)
+        self.r11 = state.Register("r11", size=wordsize)
+        self.add(self.r11)
+        self.r12 = state.Register("r12", size=wordsize)
+        self.add(self.r12)
+        self.r13 = state.Register("r13", size=wordsize)
+        self.add(self.r13)
+        self.r14 = state.Register("r14", size=wordsize)
+        self.add(self.r14)
+        self.r15 = state.Register("r15", size=wordsize)
+        self.add(self.r15)
+        self.r16 = state.Register("r16", size=wordsize)
+        self.add(self.r16)
+        self.r17 = state.Register("r17", size=wordsize)
+        self.add(self.r17)
+        self.r18 = state.Register("r18", size=wordsize)
+        self.add(self.r18)
+        self.r19 = state.Register("r19", size=wordsize)
+        self.add(self.r19)
+        self.r20 = state.Register("r20", size=wordsize)
+        self.add(self.r20)
+        self.r21 = state.Register("r21", size=wordsize)
+        self.add(self.r21)
+        self.r22 = state.Register("r22", size=wordsize)
+        self.add(self.r22)
+        self.r23 = state.Register("r23", size=wordsize)
+        self.add(self.r23)
+        self.r24 = state.Register("r24", size=wordsize)
+        self.add(self.r24)
+        self.r25 = state.Register("r25", size=wordsize)
+        self.add(self.r25)
+        self.r26 = state.Register("r26", size=wordsize)
+        self.add(self.r26)
+        self.r27 = state.Register("r27", size=wordsize)
+        self.add(self.r27)
+        self.r28 = state.Register("r28", size=wordsize)
+        self.add(self.r28)
+        self.r29 = state.Register("r29", size=wordsize)
+        self.add(self.r29)
+        self.r30 = state.Register("r30", size=wordsize)
+        self.add(self.r30)
+        # NOTE: GPR 31 is also the base pointer
+        self.r31 = state.Register("r31", size=wordsize)
+        self.add(self.r31)
+        self.bp = state.RegisterAlias("bp", self.r31, size=wordsize, offset=0)
+        self.add(self.bp)
+
+        # Floating Point Registers
+        # Always 8 bytes, regardless of wordsize.
+        self.f0 = state.Register("f0", size=8)
+        self.add(self.f0)
+        self.f1 = state.Register("f1", size=8)
+        self.add(self.f1)
+        self.f2 = state.Register("f2", size=8)
+        self.add(self.f2)
+        self.f3 = state.Register("f3", size=8)
+        self.add(self.f3)
+        self.f4 = state.Register("f4", size=8)
+        self.add(self.f4)
+        self.f5 = state.Register("f5", size=8)
+        self.add(self.f5)
+        self.f6 = state.Register("f6", size=8)
+        self.add(self.f6)
+        self.f7 = state.Register("f7", size=8)
+        self.add(self.f7)
+        self.f8 = state.Register("f8", size=8)
+        self.add(self.f8)
+        self.f9 = state.Register("f9", size=8)
+        self.add(self.f9)
+        self.f10 = state.Register("f10", size=8)
+        self.add(self.f10)
+        self.f11 = state.Register("f11", size=8)
+        self.add(self.f11)
+        self.f12 = state.Register("f12", size=8)
+        self.add(self.f12)
+        self.f13 = state.Register("f13", size=8)
+        self.add(self.f13)
+        self.f14 = state.Register("f14", size=8)
+        self.add(self.f14)
+        self.f15 = state.Register("f15", size=8)
+        self.add(self.f15)
+        self.f16 = state.Register("f16", size=8)
+        self.add(self.f16)
+        self.f17 = state.Register("f17", size=8)
+        self.add(self.f17)
+        self.f18 = state.Register("f18", size=8)
+        self.add(self.f18)
+        self.f19 = state.Register("f19", size=8)
+        self.add(self.f19)
+        self.f20 = state.Register("f20", size=8)
+        self.add(self.f20)
+        self.f21 = state.Register("f21", size=8)
+        self.add(self.f21)
+        self.f22 = state.Register("f22", size=8)
+        self.add(self.f22)
+        self.f23 = state.Register("f23", size=8)
+        self.add(self.f23)
+        self.f24 = state.Register("f24", size=8)
+        self.add(self.f24)
+        self.f25 = state.Register("f25", size=8)
+        self.add(self.f25)
+        self.f26 = state.Register("f26", size=8)
+        self.add(self.f26)
+        self.f27 = state.Register("f27", size=8)
+        self.add(self.f27)
+        self.f28 = state.Register("f28", size=8)
+        self.add(self.f28)
+        self.f29 = state.Register("f29", size=8)
+        self.add(self.f29)
+        self.f30 = state.Register("f30", size=8)
+        self.add(self.f30)
+        self.f31 = state.Register("f31", size=8)
+        self.add(self.f31)
+
+        # *** Pointer Registers ***
+        # Program Counter.
+        # Not really a register; nothing can access it directly
+        self.pc = state.Register("pc", size=wordsize)
+        self.add(self.pc)
+
+        # Link Register
+        self.lr = state.Register("lr", size=wordsize)
+        self.add(self.lr)
+
+        # Counter Register
+        # Acts either as a loop index, or a branch target register
+        # Only `ctr` and `lr` can act as branch targets.
+        self.ctr = state.Register("ctr", size=wordsize)
+        self.add(self.ctr)
+
+        # *** Condition Registers ***
+        # Condition Register
+        # The actual condition register `cr` is a single 32-bit register,
+        # but it's broken into eight 4-bit fields which are accessed separately.
+        self.cr0 = state.Register("cr0", size=1)  # Integer condition bits
+        self.add(self.cr0)
+        self.cr1 = state.Register("cr1", size=1)  # Floatibg point condition bits
+        self.add(self.cr1)
+        self.cr2 = state.Register("cr2", size=1)
+        self.add(self.cr2)
+        self.cr3 = state.Register("cr3", size=1)
+        self.add(self.cr3)
+        self.cr4 = state.Register("cr4", size=1)
+        self.add(self.cr4)
+        self.cr5 = state.Register("cr5", size=1)
+        self.add(self.cr5)
+        self.cr6 = state.Register("cr6", size=1)
+        self.add(self.cr6)
+        self.cr7 = state.Register("cr7", size=1)
+        self.add(self.cr7)
+
+        # Integer Exception Register
+        self.xer = state.Register("xer", size=4)
+        self.add(self.xer)
+
+        # Floating Point Status and Control Register
+        self.fpsrc = state.Register("fpscr", size=4)
+        self.add(self.fpsrc)
+
+        # TODO: This only focuses on the user-facing registrers.
+        # ppc has a huge number of privileged registers.
+        # Extend this as needed.
+
+
+class PowerPC32(PowerPC):
+    """CPU state for 32-bit PowerPC."""
+
+    platform = platforms.Platform(
+        platforms.Architecture.POWERPC32, platforms.Byteorder.BIG
+    )
+
+    def __init__(self):
+        super().__init__(4)
+
+
+class PowerPC64(PowerPC):
+    """CPU state for 64-bit PowerPC."""
+
+    platform = platforms.Platform(
+        platforms.Architecture.POWERPC64, platforms.Byteorder.BIG
+    )
+
+    def __init__(self):
+        super().__init__(8)