smallworld-re 1.0.0__py3-none-any.whl

smallworld/emulators/unicorn/machdefs/arm.py

@@ -0,0 +1,321 @@
+import capstone
+import unicorn
+
+from ....platforms import Architecture, Byteorder
+from .machdef import UnicornMachineDef
+
+
+class ARMMachineDef(UnicornMachineDef):
+    """Base Unicorn machine definition for 32-bit ARM"""
+
+    uc_arch = unicorn.UC_ARCH_ARM
+    uc_mode = unicorn.UC_MODE_ARM
+
+    cs_arch = capstone.CS_ARCH_ARM
+    cs_mode = capstone.CS_MODE_ARM
+
+    pc_reg = "pc"
+
+    def __init__(self):
+        self._registers = {
+            "r0": (unicorn.arm_const.UC_ARM_REG_R0, "r0", 0, 4),
+            "r1": (unicorn.arm_const.UC_ARM_REG_R1, "r1", 0, 4),
+            "r2": (unicorn.arm_const.UC_ARM_REG_R2, "r2", 0, 4),
+            "r3": (unicorn.arm_const.UC_ARM_REG_R3, "r3", 0, 4),
+            "r4": (unicorn.arm_const.UC_ARM_REG_R4, "r4", 0, 4),
+            "r5": (unicorn.arm_const.UC_ARM_REG_R5, "r5", 0, 4),
+            "r6": (unicorn.arm_const.UC_ARM_REG_R6, "r6", 0, 4),
+            "r7": (unicorn.arm_const.UC_ARM_REG_R7, "r7", 0, 4),
+            "r8": (unicorn.arm_const.UC_ARM_REG_R8, "r8", 0, 4),
+            # r9 doubles as the Static base pointer
+            "r9": (unicorn.arm_const.UC_ARM_REG_R9, "r9", 0, 4),
+            "sb": (unicorn.arm_const.UC_ARM_REG_SB, "r9", 0, 4),
+            # r10 doubles as the Stack Limit pointer
+            "r10": (unicorn.arm_const.UC_ARM_REG_R10, "r10", 0, 4),
+            "sl": (unicorn.arm_const.UC_ARM_REG_SL, "r10", 0, 4),
+            # r11 doubles as the Frame Pointer, if desired.
+            "r11": (unicorn.arm_const.UC_ARM_REG_R11, "r11", 0, 4),
+            "fp": (unicorn.arm_const.UC_ARM_REG_FP, "r11", 0, 4),
+            # r12 doubles as the Intra-call scratch register
+            "r12": (unicorn.arm_const.UC_ARM_REG_R12, "r12", 0, 4),
+            "ip": (unicorn.arm_const.UC_ARM_REG_IP, "r12", 0, 4),
+            "sp": (unicorn.arm_const.UC_ARM_REG_SP, "sp", 0, 4),
+            "lr": (unicorn.arm_const.UC_ARM_REG_LR, "lr", 0, 4),
+            "pc": (unicorn.arm_const.UC_ARM_REG_PC, "pc", 0, 4),
+        }
+
+
+class ARMMachineMixinM:
+    """Mixin for ARM M-series machine models"""
+
+    def __init__(self):
+        super().__init__()
+        self._registers.update(
+            {
+                # NOTE: PSR is aliased to CPSR
+                # This is an artifact of the fact that Unicorn
+                # seems to emulate a mash-up of M- and A-series arm.
+                "psr": (unicorn.arm_const.UC_ARM_REG_CPSR, "psr", 0, 4),
+                "primask": (unicorn.arm_const.UC_ARM_REG_PRIMASK, "primask", 0, 4),
+                "basepri": (unicorn.arm_const.UC_ARM_REG_BASEPRI, "basepri", 0, 4),
+                "faultmask": (
+                    unicorn.arm_const.UC_ARM_REG_FAULTMASK,
+                    "faultmask",
+                    0,
+                    4,
+                ),
+                "control": (unicorn.arm_const.UC_ARM_REG_CONTROL, "control", 0, 4),
+                "msp": (unicorn.arm_const.UC_ARM_REG_MSP, "msp", 0, 4),
+                "psp": (unicorn.arm_const.UC_ARM_REG_PSP, "psp", 0, 4),
+            }
+        )
+
+
+class ARMMachineMixinRA:
+    """Mixin for ARM R- or A- series machine models"""
+
+    def __init__(self):
+        super().__init__()
+        self._registers.update(
+            {
+                "cpsr": (unicorn.arm_const.UC_ARM_REG_CPSR, "cpsr", 0, 4),
+                "spsr": (unicorn.arm_const.UC_ARM_REG_SPSR, "spsr", 0, 4),
+                # NOTE: None of the banked registers have Unicorn IDs
+                "sp_usr": (unicorn.arm_const.UC_ARM_REG_INVALID, "sp_usr", 0, 4),
+                "lr_usr": (unicorn.arm_const.UC_ARM_REG_INVALID, "lr_usr", 0, 4),
+                "r8_usr": (unicorn.arm_const.UC_ARM_REG_INVALID, "r8_usr", 0, 4),
+                "r9_usr": (unicorn.arm_const.UC_ARM_REG_INVALID, "r9_usr", 0, 4),
+                "r10_usr": (unicorn.arm_const.UC_ARM_REG_INVALID, "r10_usr", 0, 4),
+                "r11_usr": (unicorn.arm_const.UC_ARM_REG_INVALID, "r11_usr", 0, 4),
+                "r12_usr": (unicorn.arm_const.UC_ARM_REG_INVALID, "r12_usr", 0, 4),
+                "sp_hyp": (unicorn.arm_const.UC_ARM_REG_INVALID, "sp_hyp", 0, 4),
+                "spsr_hyp": (unicorn.arm_const.UC_ARM_REG_INVALID, "spsr_hyp", 0, 4),
+                "elr_hyp": (unicorn.arm_const.UC_ARM_REG_INVALID, "elr_hyp", 0, 4),
+                "sp_svc": (unicorn.arm_const.UC_ARM_REG_INVALID, "sp_svc", 0, 4),
+                "lr_svc": (unicorn.arm_const.UC_ARM_REG_INVALID, "lr_svc", 0, 4),
+                "spsr_svc": (unicorn.arm_const.UC_ARM_REG_INVALID, "spsr_svc", 0, 4),
+                "sp_abt": (unicorn.arm_const.UC_ARM_REG_INVALID, "sp_abt", 0, 4),
+                "lr_abt": (unicorn.arm_const.UC_ARM_REG_INVALID, "lr_abt", 0, 4),
+                "spsr_abt": (unicorn.arm_const.UC_ARM_REG_INVALID, "spsr_abt", 0, 4),
+                "sp_und": (unicorn.arm_const.UC_ARM_REG_INVALID, "sp_und", 0, 4),
+                "lr_und": (unicorn.arm_const.UC_ARM_REG_INVALID, "lr_und", 0, 4),
+                "spsr_und": (unicorn.arm_const.UC_ARM_REG_INVALID, "spsr_und", 0, 4),
+                "sp_mon": (unicorn.arm_const.UC_ARM_REG_INVALID, "sp_mon", 0, 4),
+                "lr_mon": (unicorn.arm_const.UC_ARM_REG_INVALID, "lr_mon", 0, 4),
+                "spsr_mon": (unicorn.arm_const.UC_ARM_REG_INVALID, "spsr_mon", 0, 4),
+                "sp_irq": (unicorn.arm_const.UC_ARM_REG_INVALID, "sp_irq", 0, 4),
+                "lr_irq": (unicorn.arm_const.UC_ARM_REG_INVALID, "lr_irq", 0, 4),
+                "spsr_irq": (unicorn.arm_const.UC_ARM_REG_INVALID, "spsr_irq", 0, 4),
+                "sp_fiq": (unicorn.arm_const.UC_ARM_REG_INVALID, "sp_fiq", 0, 4),
+                "lr_fiq": (unicorn.arm_const.UC_ARM_REG_INVALID, "lr_fiq", 0, 4),
+                "spsr_fiq": (unicorn.arm_const.UC_ARM_REG_INVALID, "spsr_fiq", 0, 4),
+                "r8_fiq": (unicorn.arm_const.UC_ARM_REG_INVALID, "r8_fiq", 0, 4),
+                "r9_fiq": (unicorn.arm_const.UC_ARM_REG_INVALID, "r9_fiq", 0, 4),
+                "r10_fiq": (unicorn.arm_const.UC_ARM_REG_INVALID, "r10_fiq", 0, 4),
+                "r11_fiq": (unicorn.arm_const.UC_ARM_REG_INVALID, "r11_fiq", 0, 4),
+                "r12_fiq": (unicorn.arm_const.UC_ARM_REG_INVALID, "r12_fiq", 0, 4),
+            }
+        )
+
+
+class ARMMachineMixinFP:
+    """Mixin for ARM machine models with basic FPUs"""
+
+    def __init__(self):
+        super().__init__()
+        self._registers.update(
+            {
+                "fpscr": (unicorn.arm_const.UC_ARM_REG_FPSCR, "fpscr", 0, 4),
+                "fpexc": (unicorn.arm_const.UC_ARM_REG_FPEXC, "fpexc", 0, 4),
+                "fpsid": (unicorn.arm_const.UC_ARM_REG_FPSID, "fpsid", 0, 4),
+                "mvfr0": (unicorn.arm_const.UC_ARM_REG_INVALID, "mvfr0", 0, 4),
+                "mvfr1": (unicorn.arm_const.UC_ARM_REG_INVALID, "mvfr1", 0, 4),
+                "d0": (unicorn.arm_const.UC_ARM_REG_D0, "d0", 0, 8),
+                "s0": (unicorn.arm_const.UC_ARM_REG_S0, "d0", 0, 4),
+                "s1": (unicorn.arm_const.UC_ARM_REG_S1, "d0", 4, 4),
+                "d1": (unicorn.arm_const.UC_ARM_REG_D1, "d1", 0, 8),
+                "s2": (unicorn.arm_const.UC_ARM_REG_S2, "d1", 0, 4),
+                "s3": (unicorn.arm_const.UC_ARM_REG_S3, "d1", 4, 4),
+                "d2": (unicorn.arm_const.UC_ARM_REG_D2, "d2", 0, 8),
+                "s4": (unicorn.arm_const.UC_ARM_REG_S4, "d2", 0, 4),
+                "s5": (unicorn.arm_const.UC_ARM_REG_S5, "d2", 4, 4),
+                "d3": (unicorn.arm_const.UC_ARM_REG_D3, "d3", 0, 8),
+                "s6": (unicorn.arm_const.UC_ARM_REG_S6, "d3", 0, 4),
+                "s7": (unicorn.arm_const.UC_ARM_REG_S7, "d3", 4, 4),
+                "d4": (unicorn.arm_const.UC_ARM_REG_D4, "d4", 0, 8),
+                "s8": (unicorn.arm_const.UC_ARM_REG_S8, "d4", 0, 4),
+                "s9": (unicorn.arm_const.UC_ARM_REG_S9, "d4", 4, 4),
+                "d5": (unicorn.arm_const.UC_ARM_REG_D5, "d5", 0, 8),
+                "s10": (unicorn.arm_const.UC_ARM_REG_S10, "d5", 0, 4),
+                "s11": (unicorn.arm_const.UC_ARM_REG_S11, "d5", 4, 4),
+                "d6": (unicorn.arm_const.UC_ARM_REG_D6, "d6", 0, 8),
+                "s12": (unicorn.arm_const.UC_ARM_REG_S12, "d6", 0, 4),
+                "s13": (unicorn.arm_const.UC_ARM_REG_S13, "d6", 4, 4),
+                "d7": (unicorn.arm_const.UC_ARM_REG_D7, "d7", 0, 8),
+                "s14": (unicorn.arm_const.UC_ARM_REG_S14, "d7", 0, 4),
+                "s15": (unicorn.arm_const.UC_ARM_REG_S15, "d7", 4, 4),
+                "d8": (unicorn.arm_const.UC_ARM_REG_D8, "d8", 0, 8),
+                "s16": (unicorn.arm_const.UC_ARM_REG_S16, "d8", 0, 4),
+                "s17": (unicorn.arm_const.UC_ARM_REG_S17, "d8", 4, 4),
+                "d9": (unicorn.arm_const.UC_ARM_REG_D9, "d9", 0, 8),
+                "s18": (unicorn.arm_const.UC_ARM_REG_S18, "d9", 0, 4),
+                "s19": (unicorn.arm_const.UC_ARM_REG_S19, "d9", 4, 4),
+                "d10": (unicorn.arm_const.UC_ARM_REG_D10, "d10", 0, 8),
+                "s20": (unicorn.arm_const.UC_ARM_REG_S20, "d10", 0, 4),
+                "s21": (unicorn.arm_const.UC_ARM_REG_S21, "d10", 4, 4),
+                "d11": (unicorn.arm_const.UC_ARM_REG_D11, "d11", 0, 8),
+                "s22": (unicorn.arm_const.UC_ARM_REG_S22, "d11", 0, 4),
+                "s23": (unicorn.arm_const.UC_ARM_REG_S23, "d11", 4, 4),
+                "d12": (unicorn.arm_const.UC_ARM_REG_D12, "d12", 0, 8),
+                "s24": (unicorn.arm_const.UC_ARM_REG_S24, "d12", 0, 4),
+                "s25": (unicorn.arm_const.UC_ARM_REG_S25, "d12", 4, 4),
+                "d13": (unicorn.arm_const.UC_ARM_REG_D13, "d13", 0, 8),
+                "s26": (unicorn.arm_const.UC_ARM_REG_S26, "d13", 0, 4),
+                "s27": (unicorn.arm_const.UC_ARM_REG_S27, "d13", 4, 4),
+                "d14": (unicorn.arm_const.UC_ARM_REG_D14, "d14", 0, 8),
+                "s28": (unicorn.arm_const.UC_ARM_REG_S28, "d14", 0, 4),
+                "s29": (unicorn.arm_const.UC_ARM_REG_S29, "d14", 4, 4),
+                "d15": (unicorn.arm_const.UC_ARM_REG_D15, "d15", 0, 8),
+                "s30": (unicorn.arm_const.UC_ARM_REG_S30, "d15", 0, 4),
+                "s31": (unicorn.arm_const.UC_ARM_REG_S31, "d15", 4, 4),
+            }
+        )
+
+
+class ARMMachineMixinVFP:
+    """Mixin for ARM machine models with VFP/NEON support"""
+
+    def __init__(self):
+        super().__init__()
+        self._registers.update(
+            {
+                "fpscr": (unicorn.arm_const.UC_ARM_REG_FPSCR, "fpscr", 0, 4),
+                "fpexc": (unicorn.arm_const.UC_ARM_REG_FPEXC, "fpexc", 0, 4),
+                "fpsid": (unicorn.arm_const.UC_ARM_REG_FPSID, "fpsid", 0, 4),
+                "mvfr0": (unicorn.arm_const.UC_ARM_REG_INVALID, "mvfr0", 0, 4),
+                "mvfr1": (unicorn.arm_const.UC_ARM_REG_INVALID, "mvfr1", 0, 4),
+                "q0": (unicorn.arm_const.UC_ARM_REG_Q0, "q0", 0, 16),
+                "d0": (unicorn.arm_const.UC_ARM_REG_D0, "q0", 0, 8),
+                "s0": (unicorn.arm_const.UC_ARM_REG_S0, "q0", 0, 4),
+                "s1": (unicorn.arm_const.UC_ARM_REG_S1, "q0", 4, 4),
+                "d1": (unicorn.arm_const.UC_ARM_REG_D1, "q0", 8, 8),
+                "s2": (unicorn.arm_const.UC_ARM_REG_S2, "q0", 8, 4),
+                "s3": (unicorn.arm_const.UC_ARM_REG_S3, "q0", 12, 4),
+                "q1": (unicorn.arm_const.UC_ARM_REG_Q1, "q1", 0, 16),
+                "d2": (unicorn.arm_const.UC_ARM_REG_D2, "q1", 0, 8),
+                "s4": (unicorn.arm_const.UC_ARM_REG_S4, "q1", 0, 4),
+                "s5": (unicorn.arm_const.UC_ARM_REG_S5, "q1", 4, 4),
+                "d3": (unicorn.arm_const.UC_ARM_REG_D3, "q1", 8, 8),
+                "s6": (unicorn.arm_const.UC_ARM_REG_S6, "q1", 8, 4),
+                "s7": (unicorn.arm_const.UC_ARM_REG_S7, "q1", 12, 4),
+                "q2": (unicorn.arm_const.UC_ARM_REG_Q2, "q2", 0, 16),
+                "d4": (unicorn.arm_const.UC_ARM_REG_D4, "q2", 0, 8),
+                "s8": (unicorn.arm_const.UC_ARM_REG_S8, "q2", 0, 4),
+                "s9": (unicorn.arm_const.UC_ARM_REG_S9, "q2", 4, 4),
+                "d5": (unicorn.arm_const.UC_ARM_REG_D5, "q2", 8, 8),
+                "s10": (unicorn.arm_const.UC_ARM_REG_S10, "q2", 8, 4),
+                "s11": (unicorn.arm_const.UC_ARM_REG_S11, "q2", 12, 4),
+                "q3": (unicorn.arm_const.UC_ARM_REG_Q3, "q3", 0, 16),
+                "d6": (unicorn.arm_const.UC_ARM_REG_D6, "q3", 0, 8),
+                "s12": (unicorn.arm_const.UC_ARM_REG_S12, "q3", 0, 4),
+                "s13": (unicorn.arm_const.UC_ARM_REG_S13, "q3", 4, 4),
+                "d7": (unicorn.arm_const.UC_ARM_REG_D7, "q3", 8, 8),
+                "s14": (unicorn.arm_const.UC_ARM_REG_S14, "q3", 8, 4),
+                "s15": (unicorn.arm_const.UC_ARM_REG_S15, "q3", 12, 4),
+                "q4": (unicorn.arm_const.UC_ARM_REG_Q4, "q4", 0, 16),
+                "d8": (unicorn.arm_const.UC_ARM_REG_D8, "q4", 0, 8),
+                "s16": (unicorn.arm_const.UC_ARM_REG_S16, "q4", 0, 4),
+                "s17": (unicorn.arm_const.UC_ARM_REG_S17, "q4", 4, 4),
+                "d9": (unicorn.arm_const.UC_ARM_REG_D9, "q4", 8, 8),
+                "s18": (unicorn.arm_const.UC_ARM_REG_S18, "q4", 8, 4),
+                "s19": (unicorn.arm_const.UC_ARM_REG_S19, "q4", 12, 4),
+                "q5": (unicorn.arm_const.UC_ARM_REG_Q5, "q5", 0, 16),
+                "d10": (unicorn.arm_const.UC_ARM_REG_D10, "q5", 0, 8),
+                "s20": (unicorn.arm_const.UC_ARM_REG_S20, "q5", 0, 4),
+                "s21": (unicorn.arm_const.UC_ARM_REG_S21, "q5", 4, 4),
+                "d11": (unicorn.arm_const.UC_ARM_REG_D11, "q5", 8, 8),
+                "s22": (unicorn.arm_const.UC_ARM_REG_S22, "q5", 8, 4),
+                "s23": (unicorn.arm_const.UC_ARM_REG_S23, "q5", 12, 4),
+                "q6": (unicorn.arm_const.UC_ARM_REG_Q6, "q6", 0, 16),
+                "d12": (unicorn.arm_const.UC_ARM_REG_D12, "q6", 0, 8),
+                "s24": (unicorn.arm_const.UC_ARM_REG_S24, "q6", 0, 4),
+                "s25": (unicorn.arm_const.UC_ARM_REG_S25, "q6", 4, 4),
+                "d13": (unicorn.arm_const.UC_ARM_REG_D13, "q6", 8, 8),
+                "s26": (unicorn.arm_const.UC_ARM_REG_S26, "q6", 8, 4),
+                "s27": (unicorn.arm_const.UC_ARM_REG_S27, "q6", 12, 4),
+                "q7": (unicorn.arm_const.UC_ARM_REG_Q7, "q7", 0, 16),
+                "d14": (unicorn.arm_const.UC_ARM_REG_D14, "q7", 0, 8),
+                "s28": (unicorn.arm_const.UC_ARM_REG_S28, "q7", 0, 4),
+                "s29": (unicorn.arm_const.UC_ARM_REG_S29, "q7", 4, 4),
+                "d15": (unicorn.arm_const.UC_ARM_REG_D15, "q7", 8, 8),
+                "s30": (unicorn.arm_const.UC_ARM_REG_S30, "q7", 8, 4),
+                "s31": (unicorn.arm_const.UC_ARM_REG_S31, "q7", 12, 4),
+                "q8": (unicorn.arm_const.UC_ARM_REG_Q8, "q8", 0, 16),
+                "d16": (unicorn.arm_const.UC_ARM_REG_D16, "q8", 0, 8),
+                "d17": (unicorn.arm_const.UC_ARM_REG_D17, "q8", 8, 8),
+                "q9": (unicorn.arm_const.UC_ARM_REG_Q9, "q9", 0, 16),
+                "d18": (unicorn.arm_const.UC_ARM_REG_D18, "q9", 0, 8),
+                "d19": (unicorn.arm_const.UC_ARM_REG_D19, "q9", 8, 8),
+                "q10": (unicorn.arm_const.UC_ARM_REG_Q10, "q10", 0, 16),
+                "d20": (unicorn.arm_const.UC_ARM_REG_D20, "q10", 0, 8),
+                "d21": (unicorn.arm_const.UC_ARM_REG_D21, "q10", 8, 8),
+                "q11": (unicorn.arm_const.UC_ARM_REG_Q11, "q11", 0, 16),
+                "d22": (unicorn.arm_const.UC_ARM_REG_D22, "q11", 0, 8),
+                "d23": (unicorn.arm_const.UC_ARM_REG_D23, "q11", 8, 8),
+                "q12": (unicorn.arm_const.UC_ARM_REG_Q12, "q12", 0, 16),
+                "d24": (unicorn.arm_const.UC_ARM_REG_D24, "q12", 0, 8),
+                "d25": (unicorn.arm_const.UC_ARM_REG_D25, "q12", 8, 8),
+                "q13": (unicorn.arm_const.UC_ARM_REG_Q13, "q13", 0, 16),
+                "d26": (unicorn.arm_const.UC_ARM_REG_D26, "q13", 0, 8),
+                "d27": (unicorn.arm_const.UC_ARM_REG_D27, "q13", 8, 8),
+                "q14": (unicorn.arm_const.UC_ARM_REG_Q14, "q14", 0, 16),
+                "d28": (unicorn.arm_const.UC_ARM_REG_D28, "q14", 0, 8),
+                "d29": (unicorn.arm_const.UC_ARM_REG_D29, "q14", 8, 8),
+                "q15": (unicorn.arm_const.UC_ARM_REG_Q15, "q15", 0, 16),
+                "d30": (unicorn.arm_const.UC_ARM_REG_D30, "q15", 0, 8),
+                "d31": (unicorn.arm_const.UC_ARM_REG_D31, "q15", 8, 8),
+            }
+        )
+
+
+class ARMv5TMachineDef(ARMMachineMixinM, ARMMachineDef):
+    """Unicorn machine definition for ARMv5T little-endian"""
+
+    arch = Architecture.ARM_V5T
+    byteorder = Byteorder.LITTLE
+
+
+class ARMv6MMachineDef(ARMMachineMixinFP, ARMMachineMixinM, ARMMachineDef):
+    """Unicorn machine definition for ARMv6-M little-endian"""
+
+    arch = Architecture.ARM_V6M
+    byteorder = Byteorder.LITTLE
+
+
+class ARMv6MThumbMachineDef(ARMv6MMachineDef):
+    """Unicorn machine definition for ARMv6-M little-endian, THUMB ISA"""
+
+    arch = Architecture.ARM_V6M_THUMB
+    uc_mode = unicorn.UC_MODE_THUMB
+    cs_mode = capstone.CS_MODE_THUMB
+
+
+class ARMv7MMachineDef(ARMMachineMixinFP, ARMMachineMixinM, ARMMachineDef):
+    """Unicorn machine definition for ARMv7-M little-endian"""
+
+    arch = Architecture.ARM_V7M
+    byteorder = Byteorder.LITTLE
+
+
+class ARMv7RMachineDef(ARMMachineMixinVFP, ARMMachineMixinRA, ARMMachineDef):
+    """Unicorn machine definition for ARMv7-R little-endian"""
+
+    arch = Architecture.ARM_V7R
+    byteorder = Byteorder.LITTLE
+
+
+class ARMv7AMachineDef(ARMMachineMixinVFP, ARMMachineMixinRA, ARMMachineDef):
+    """Unicorn machine definition for ARMv7-A little-endian"""
+
+    arch = Architecture.ARM_V7A
+    byteorder = Byteorder.LITTLE

smallworld/emulators/unicorn/machdefs/i386.py

@@ -0,0 +1,137 @@
+import capstone
+import unicorn
+
+from ....platforms import Architecture, Byteorder
+from .machdef import UnicornMachineDef
+
+
+class i386MachineDef(UnicornMachineDef):
+    """Unicorn machine definition for i386"""
+
+    arch = Architecture.X86_32
+    byteorder = Byteorder.LITTLE
+
+    uc_arch = unicorn.UC_ARCH_X86
+    uc_mode = unicorn.UC_MODE_32
+
+    cs_arch = capstone.CS_ARCH_X86
+    cs_mode = capstone.CS_MODE_32
+
+    pc_reg = "eip"
+
+    _registers = {
+        # *** General Purpose Registers ***
+        "eax": (unicorn.x86_const.UC_X86_REG_EAX, "eax", 4, 0),
+        "ax": (unicorn.x86_const.UC_X86_REG_AX, "eax", 2, 0),
+        "al": (unicorn.x86_const.UC_X86_REG_AL, "eax", 1, 0),
+        "ah": (unicorn.x86_const.UC_X86_REG_AH, "eax", 1, 1),
+        "ebx": (unicorn.x86_const.UC_X86_REG_EBX, "ebx", 4, 0),
+        "bx": (unicorn.x86_const.UC_X86_REG_BX, "ebx", 2, 0),
+        "bl": (unicorn.x86_const.UC_X86_REG_BL, "ebx", 1, 0),
+        "bh": (unicorn.x86_const.UC_X86_REG_BH, "ebx", 1, 1),
+        "ecx": (unicorn.x86_const.UC_X86_REG_ECX, "ecx", 4, 0),
+        "cx": (unicorn.x86_const.UC_X86_REG_CX, "ecx", 2, 0),
+        "cl": (unicorn.x86_const.UC_X86_REG_CL, "ecx", 1, 0),
+        "ch": (unicorn.x86_const.UC_X86_REG_CH, "ecx", 1, 1),
+        "edx": (unicorn.x86_const.UC_X86_REG_EDX, "edx", 4, 0),
+        "dx": (unicorn.x86_const.UC_X86_REG_DX, "edx", 2, 0),
+        "dl": (unicorn.x86_const.UC_X86_REG_DL, "edx", 1, 0),
+        "dh": (unicorn.x86_const.UC_X86_REG_DH, "edx", 1, 1),
+        "esi": (unicorn.x86_const.UC_X86_REG_ESI, "esi", 4, 0),
+        "si": (unicorn.x86_const.UC_X86_REG_SI, "esi", 2, 0),
+        "sil": (unicorn.x86_const.UC_X86_REG_SIL, "esi", 1, 0),
+        "edi": (unicorn.x86_const.UC_X86_REG_EDI, "edi", 4, 0),
+        "di": (unicorn.x86_const.UC_X86_REG_DI, "edi", 2, 0),
+        "dil": (unicorn.x86_const.UC_X86_REG_DIL, "edi", 1, 0),
+        "ebp": (unicorn.x86_const.UC_X86_REG_EBP, "ebp", 4, 0),
+        "bp": (unicorn.x86_const.UC_X86_REG_BP, "ebp", 2, 0),
+        "bpl": (unicorn.x86_const.UC_X86_REG_BPL, "ebp", 1, 0),
+        "esp": (unicorn.x86_const.UC_X86_REG_ESP, "esp", 4, 0),
+        "sp": (unicorn.x86_const.UC_X86_REG_SP, "esp", 2, 0),
+        "spl": (unicorn.x86_const.UC_X86_REG_SPL, "esp", 1, 0),
+        # *** Instruction Pointer ***
+        "eip": (unicorn.x86_const.UC_X86_REG_EIP, "eip", 4, 0),
+        "ip": (unicorn.x86_const.UC_X86_REG_IP, "eip", 2, 0),
+        # *** Segment Registers ***
+        "cs": (unicorn.x86_const.UC_X86_REG_CS, "cs", 2, 0),
+        "ss": (unicorn.x86_const.UC_X86_REG_SS, "ss", 2, 0),
+        "ds": (unicorn.x86_const.UC_X86_REG_DS, "ds", 2, 0),
+        "es": (unicorn.x86_const.UC_X86_REG_ES, "es", 2, 0),
+        "fs": (unicorn.x86_const.UC_X86_REG_FS, "fs", 2, 0),
+        "gs": (unicorn.x86_const.UC_X86_REG_GS, "gs", 2, 0),
+        # *** Flags Registers ***
+        "eflags": (unicorn.x86_const.UC_X86_REG_EFLAGS, "eflags", 4, 0),
+        "flags": (unicorn.x86_const.UC_X86_REG_FLAGS, "eflags", 2, 0),
+        # *** Control Registers ***
+        "cr0": (unicorn.x86_const.UC_X86_REG_CR0, "cr0", 4, 0),
+        "cr1": (unicorn.x86_const.UC_X86_REG_CR1, "cr1", 4, 0),
+        "cr2": (unicorn.x86_const.UC_X86_REG_CR2, "cr2", 4, 0),
+        "cr3": (unicorn.x86_const.UC_X86_REG_CR3, "cr3", 4, 0),
+        "cr4": (unicorn.x86_const.UC_X86_REG_CR4, "cr4", 4, 0),
+        # NOTE: I've got conflicting reports whether cr8 exists in i386.
+        "cr8": (unicorn.x86_const.UC_X86_REG_INVALID, "cr8", 4, 0),
+        # *** Debug Registers ***
+        "dr0": (unicorn.x86_const.UC_X86_REG_DR0, "dr0", 4, 0),
+        "dr1": (unicorn.x86_const.UC_X86_REG_DR1, "dr1", 4, 0),
+        "dr2": (unicorn.x86_const.UC_X86_REG_DR2, "dr2", 4, 0),
+        "dr3": (unicorn.x86_const.UC_X86_REG_DR3, "dr3", 4, 0),
+        "dr6": (unicorn.x86_const.UC_X86_REG_DR6, "dr6", 4, 0),
+        "dr7": (unicorn.x86_const.UC_X86_REG_DR7, "dr7", 4, 0),
+        # *** Descriptor Table Registers
+        # NOTE: Yes, this is 6 bytes; 2 byte segment selector plus 4 byte offset
+        "gdtr": (unicorn.x86_const.UC_X86_REG_GDTR, "gdtr", 6, 0),
+        "idtr": (unicorn.x86_const.UC_X86_REG_IDTR, "idtr", 6, 0),
+        "ldtr": (unicorn.x86_const.UC_X86_REG_LDTR, "ldtr", 6, 0),
+        # *** Task Register ***
+        # NOTE: Yes, this is 6 bytes; 2 byte segment selector plus 4 byte offset
+        "tr": (unicorn.x86_const.UC_X86_REG_TR, "tr", 6, 0),
+        # *** x87 registers ***
+        # NOTE: x87 is supported by Unicorn, but not by SmallWorld.
+        # Values are represented as tuples (exponent: int, mantissa: int).
+        # If you need x87 support, open a ticket.
+        "fpr0": (unicorn.x86_const.UC_X86_REG_INVALID, "fpr0", 10, 0),
+        "fpr1": (unicorn.x86_const.UC_X86_REG_INVALID, "fpr1", 10, 0),
+        "fpr2": (unicorn.x86_const.UC_X86_REG_INVALID, "fpr2", 10, 0),
+        "fpr3": (unicorn.x86_const.UC_X86_REG_INVALID, "fpr3", 10, 0),
+        "fpr4": (unicorn.x86_const.UC_X86_REG_INVALID, "fpr4", 10, 0),
+        "fpr5": (unicorn.x86_const.UC_X86_REG_INVALID, "fpr5", 10, 0),
+        "fpr6": (unicorn.x86_const.UC_X86_REG_INVALID, "fpr6", 10, 0),
+        "fpr7": (unicorn.x86_const.UC_X86_REG_INVALID, "fpr7", 10, 0),
+        # x87 Control Register
+        "fctrl": (unicorn.x86_const.UC_X86_REG_FPCW, "fctrl", 2, 0),
+        # x87 Status Register
+        "fstat": (unicorn.x86_const.UC_X86_REG_FPSW, "fstat", 2, 0),
+        # x87 Tag Register
+        "ftag": (unicorn.x86_const.UC_X86_REG_FPTAG, "ftag", 2, 0),
+        # x87 Last Instruction Register
+        "fip": (unicorn.x86_const.UC_X86_REG_FIP, "fip", 8, 0),
+        # x87 Last Operand Pointer
+        "fdp": (unicorn.x86_const.UC_X86_REG_FDP, "fdp", 8, 0),
+        # x87 Last Opcode
+        "fop": (unicorn.x86_const.UC_X86_REG_FOP, "fop", 2, 0),
+        # NOTE: Docs disagree on the format of fip and fdp.
+        # One source describes them as 48-bit offset-plus-segment,
+        # the other describes them as 64-bit.
+        # There may also be separate segment registers.
+        # If you care about the x87 debug info, please feel free to update.
+        # *** MMX Registers ***
+        # NOTE: The MMX registers are aliases for the low 8 bytes of the x87 registers.
+        # The two subsystems cannot be used simultaneously.
+        "mm0": (unicorn.x86_const.UC_X86_REG_MM0, "fpr0", 8, 0),
+        "mm1": (unicorn.x86_const.UC_X86_REG_MM1, "fpr1", 8, 0),
+        "mm2": (unicorn.x86_const.UC_X86_REG_MM2, "fpr2", 8, 0),
+        "mm3": (unicorn.x86_const.UC_X86_REG_MM3, "fpr3", 8, 0),
+        "mm4": (unicorn.x86_const.UC_X86_REG_MM4, "fpr4", 8, 0),
+        "mm5": (unicorn.x86_const.UC_X86_REG_MM5, "fpr5", 8, 0),
+        "mm6": (unicorn.x86_const.UC_X86_REG_MM6, "fpr6", 8, 0),
+        "mm7": (unicorn.x86_const.UC_X86_REG_MM7, "fpr7", 8, 0),
+        # *** SSE Registers ***
+        "xmm0": (unicorn.x86_const.UC_X86_REG_XMM0, "xmm0", 16, 0),
+        "xmm1": (unicorn.x86_const.UC_X86_REG_XMM1, "xmm1", 16, 0),
+        "xmm2": (unicorn.x86_const.UC_X86_REG_XMM2, "xmm2", 16, 0),
+        "xmm3": (unicorn.x86_const.UC_X86_REG_XMM3, "xmm3", 16, 0),
+        "xmm4": (unicorn.x86_const.UC_X86_REG_XMM4, "xmm4", 16, 0),
+        "xmm5": (unicorn.x86_const.UC_X86_REG_XMM5, "xmm5", 16, 0),
+        "xmm6": (unicorn.x86_const.UC_X86_REG_XMM6, "xmm6", 16, 0),
+        "xmm7": (unicorn.x86_const.UC_X86_REG_XMM7, "xmm7", 16, 0),
+    }

smallworld/emulators/unicorn/machdefs/machdef.py

@@ -0,0 +1,117 @@
+import abc
+import inspect
+import typing
+
+from .... import platforms, utils
+
+# from ....platforms import Architecture
+
+
+class UnicornMachineDef(metaclass=abc.ABCMeta):
+    """Container class for Unicorn architecture-specific definitions"""
+
+    @property
+    @abc.abstractmethod
+    def arch(self) -> platforms.Architecture:
+        """The architecture ID"""
+        raise NotImplementedError("Abstract unicorn machine def has no architecture")
+
+    @property
+    @abc.abstractmethod
+    def byteorder(self) -> platforms.Byteorder:
+        """The byte order"""
+        raise NotImplementedError("Abstract unicorn machine def has no byteorder")
+
+    @property
+    @abc.abstractmethod
+    def uc_arch(self) -> int:
+        """The Unicorn architecture ID"""
+        return 0
+
+    @property
+    @abc.abstractmethod
+    def uc_mode(self) -> int:
+        """The unicorn mode ID
+
+        This must include an byteorder flag
+        """
+        return 0
+
+    @property
+    @abc.abstractmethod
+    def cs_arch(self) -> int:
+        """The capstone arch ID"""
+        return 0
+
+    @property
+    @abc.abstractmethod
+    def cs_mode(self) -> int:
+        """The capstone mode ID
+
+        This must include an byteorder flag
+        """
+        return 0
+
+    @property
+    @abc.abstractmethod
+    def pc_reg(self) -> str:
+        """The name of the Program Counter register for this machine"""
+        return ""
+
+    _registers: typing.Dict[str, typing.Tuple[typing.Any, str, int, int]] = {}
+
+    def uc_reg(self, name: str) -> typing.Tuple[typing.Any, str, int, int]:
+        """Convert a register name to unicorn constant
+
+        This must cover all names defined in the CPU state model
+        for this arch/mode/byteorder, or return 0,
+        which always indicates an invalid register
+        """
+        if name in self._registers:
+            return self._registers[name]
+        else:
+            raise ValueError(
+                f"Unknown register for {self.arch}:{self.byteorder}: {name}"
+            )
+
+    @classmethod
+    def for_platform(cls, platform: platforms.Platform):
+        """Find the appropriate MachineDef for your architecture
+
+        Arguments:
+            platform: platform metadata
+
+        Returns:
+            An instance of the appropriate MachineDef
+
+        Raises:
+            ValueError: If no MachineDef subclass matches your request
+        """
+
+        try:
+            return utils.find_subclass(
+                cls,
+                lambda x: x.arch == platform.architecture
+                and x.byteorder == platform.byteorder,
+            )
+        except:
+            raise ValueError(
+                f"No machine model for {platform.architecture}:{platform.byteorder}"
+            )
+
+
+def populate_registers(arch_info, unicorn_consts):
+    def find_uc_const(reg_name):
+        ew = f"_{reg_name.upper()}"
+        for name, num in inspect.getmembers(unicorn_consts):
+            if name.endswith(ew) and "REG" in name:
+                return (name, num)
+        return None
+
+    registers = {}
+    for reg_name, info in arch_info.items():
+        (base_reg_name, (start, end)) = info
+        (ucstr, ucnum) = find_uc_const(reg_name)
+        registers[reg_name] = (ucnum, base_reg_name, start, end)
+
+    return registers