smallworld-re 1.0.0__py3-none-any.whl

smallworld/emulators/unicorn/machdefs/aarch64.py

@@ -0,0 +1,310 @@
+import capstone
+import unicorn
+
+from ....platforms import Architecture, Byteorder
+from .machdef import UnicornMachineDef
+
+
+class AArch64MachineDef(UnicornMachineDef):
+    arch = Architecture.AARCH64
+    byteorder = Byteorder.LITTLE
+
+    uc_arch = unicorn.UC_ARCH_ARM64
+    uc_mode = unicorn.UC_MODE_ARM
+
+    cs_arch = capstone.CS_ARCH_ARM64
+    cs_mode = capstone.CS_MODE_ARM
+
+    pc_reg = "pc"
+
+    _registers = {
+        # *** General Purpose Registers ***
+        "x0": (unicorn.arm64_const.UC_ARM64_REG_X0, "x0", 8, 0),
+        "w0": (unicorn.arm64_const.UC_ARM64_REG_W0, "x0", 4, 0),
+        "x1": (unicorn.arm64_const.UC_ARM64_REG_X1, "x1", 8, 0),
+        "w1": (unicorn.arm64_const.UC_ARM64_REG_W1, "x1", 4, 0),
+        "x2": (unicorn.arm64_const.UC_ARM64_REG_X2, "x2", 8, 0),
+        "w2": (unicorn.arm64_const.UC_ARM64_REG_W2, "x2", 4, 0),
+        "x3": (unicorn.arm64_const.UC_ARM64_REG_X3, "x3", 8, 0),
+        "w3": (unicorn.arm64_const.UC_ARM64_REG_W3, "x3", 4, 0),
+        "x4": (unicorn.arm64_const.UC_ARM64_REG_X4, "x4", 8, 0),
+        "w4": (unicorn.arm64_const.UC_ARM64_REG_W4, "x4", 4, 0),
+        "x5": (unicorn.arm64_const.UC_ARM64_REG_X5, "x5", 8, 0),
+        "w5": (unicorn.arm64_const.UC_ARM64_REG_W5, "x5", 4, 0),
+        "x6": (unicorn.arm64_const.UC_ARM64_REG_X6, "x6", 8, 0),
+        "w6": (unicorn.arm64_const.UC_ARM64_REG_W6, "x6", 4, 0),
+        "x7": (unicorn.arm64_const.UC_ARM64_REG_X7, "x7", 8, 0),
+        "w7": (unicorn.arm64_const.UC_ARM64_REG_W7, "x7", 4, 0),
+        "x8": (unicorn.arm64_const.UC_ARM64_REG_X8, "x8", 8, 0),
+        "w8": (unicorn.arm64_const.UC_ARM64_REG_W8, "x8", 4, 0),
+        "x9": (unicorn.arm64_const.UC_ARM64_REG_X9, "x9", 8, 0),
+        "w9": (unicorn.arm64_const.UC_ARM64_REG_W9, "x9", 4, 0),
+        "x10": (unicorn.arm64_const.UC_ARM64_REG_X10, "x10", 8, 0),
+        "w10": (unicorn.arm64_const.UC_ARM64_REG_W10, "x10", 4, 0),
+        "x11": (unicorn.arm64_const.UC_ARM64_REG_X11, "x11", 8, 0),
+        "w11": (unicorn.arm64_const.UC_ARM64_REG_W11, "x11", 4, 0),
+        "x12": (unicorn.arm64_const.UC_ARM64_REG_X12, "x12", 8, 0),
+        "w12": (unicorn.arm64_const.UC_ARM64_REG_W12, "x12", 4, 0),
+        "x13": (unicorn.arm64_const.UC_ARM64_REG_X13, "x13", 8, 0),
+        "w13": (unicorn.arm64_const.UC_ARM64_REG_W13, "x13", 4, 0),
+        "x14": (unicorn.arm64_const.UC_ARM64_REG_X14, "x14", 8, 0),
+        "w14": (unicorn.arm64_const.UC_ARM64_REG_W14, "x14", 4, 0),
+        "x15": (unicorn.arm64_const.UC_ARM64_REG_X15, "x15", 8, 0),
+        "w15": (unicorn.arm64_const.UC_ARM64_REG_W15, "x15", 4, 0),
+        "x16": (unicorn.arm64_const.UC_ARM64_REG_X16, "x16", 8, 0),
+        "w16": (unicorn.arm64_const.UC_ARM64_REG_W16, "x16", 4, 0),
+        "x17": (unicorn.arm64_const.UC_ARM64_REG_X17, "x17", 8, 0),
+        "w17": (unicorn.arm64_const.UC_ARM64_REG_W17, "x17", 4, 0),
+        "x18": (unicorn.arm64_const.UC_ARM64_REG_X18, "x18", 8, 0),
+        "w18": (unicorn.arm64_const.UC_ARM64_REG_W18, "x18", 4, 0),
+        "x19": (unicorn.arm64_const.UC_ARM64_REG_X19, "x19", 8, 0),
+        "w19": (unicorn.arm64_const.UC_ARM64_REG_W19, "x19", 4, 0),
+        "x20": (unicorn.arm64_const.UC_ARM64_REG_X20, "x20", 8, 0),
+        "w20": (unicorn.arm64_const.UC_ARM64_REG_W20, "x20", 4, 0),
+        "x21": (unicorn.arm64_const.UC_ARM64_REG_X21, "x21", 8, 0),
+        "w21": (unicorn.arm64_const.UC_ARM64_REG_W21, "x21", 4, 0),
+        "x22": (unicorn.arm64_const.UC_ARM64_REG_X22, "x22", 8, 0),
+        "w22": (unicorn.arm64_const.UC_ARM64_REG_W22, "x22", 4, 0),
+        "x23": (unicorn.arm64_const.UC_ARM64_REG_X23, "x23", 8, 0),
+        "w23": (unicorn.arm64_const.UC_ARM64_REG_W23, "x23", 4, 0),
+        "x24": (unicorn.arm64_const.UC_ARM64_REG_X24, "x24", 8, 0),
+        "w24": (unicorn.arm64_const.UC_ARM64_REG_W24, "x24", 4, 0),
+        "x25": (unicorn.arm64_const.UC_ARM64_REG_X25, "x25", 8, 0),
+        "w25": (unicorn.arm64_const.UC_ARM64_REG_W25, "x25", 4, 0),
+        "x26": (unicorn.arm64_const.UC_ARM64_REG_X26, "x26", 8, 0),
+        "w26": (unicorn.arm64_const.UC_ARM64_REG_W26, "x26", 4, 0),
+        "x27": (unicorn.arm64_const.UC_ARM64_REG_X27, "x27", 8, 0),
+        "w27": (unicorn.arm64_const.UC_ARM64_REG_W27, "x27", 4, 0),
+        "x28": (unicorn.arm64_const.UC_ARM64_REG_X28, "x28", 8, 0),
+        "w28": (unicorn.arm64_const.UC_ARM64_REG_W28, "x28", 4, 0),
+        "x29": (unicorn.arm64_const.UC_ARM64_REG_X29, "x29", 8, 0),
+        "w29": (unicorn.arm64_const.UC_ARM64_REG_W29, "x29", 4, 0),
+        "x30": (unicorn.arm64_const.UC_ARM64_REG_X30, "x30", 8, 0),
+        "w30": (unicorn.arm64_const.UC_ARM64_REG_W30, "x30", 4, 0),
+        # *** Program Counter ***
+        "pc": (unicorn.arm64_const.UC_ARM64_REG_PC, "pc", 8, 0),
+        # *** Stack Pointer ***
+        "sp": (unicorn.arm64_const.UC_ARM64_REG_SP, "sp", 8, 0),
+        "wsp": (unicorn.arm64_const.UC_ARM64_REG_WSP, "wsp", 4, 0),
+        # *** Frame Pointer ***
+        "fp": (unicorn.arm64_const.UC_ARM64_REG_FP, "x29", 8, 0),
+        # *** Link Register ***
+        "lr": (unicorn.arm64_const.UC_ARM64_REG_LR, "x30", 8, 0),
+        # *** Zero Register ***
+        "xzr": (unicorn.arm64_const.UC_ARM64_REG_INVALID, "xzr", 8, 0),
+        "wzr": (unicorn.arm64_const.UC_ARM64_REG_INVALID, "wzr", 4, 0),
+        # *** System Control Registers ***
+        # NOTE: "_elX" indicates that only exception level X or greater can access this register.
+        # NOTE: This list is far from complete; it only covers what Unicorn supports
+        # Condition Code Register
+        "fpcr": (unicorn.arm64_const.UC_ARM64_REG_FPCR, "fpcr", 8, 0),
+        # Floating Point Status Register
+        "fpsr": (unicorn.arm64_const.UC_ARM64_REG_FPSR, "fpsr", 8, 0),
+        # Banked stack pointers for exception handlers
+        "sp_el0": (unicorn.arm64_const.UC_ARM64_REG_SP_EL0, "sp_el0", 8, 0),
+        "sp_el1": (unicorn.arm64_const.UC_ARM64_REG_SP_EL1, "sp_el1", 8, 0),
+        "sp_el2": (unicorn.arm64_const.UC_ARM64_REG_SP_EL2, "sp_el2", 8, 0),
+        "sp_el3": (unicorn.arm64_const.UC_ARM64_REG_SP_EL3, "sp_el3", 8, 0),
+        # Banked link registers for exception handlers
+        # NOTE: Unicorn thinks there's an elr_el0; according to docs, it doesn't exist
+        "elr_el1": (unicorn.arm64_const.UC_ARM64_REG_ELR_EL1, "elr_el1", 8, 0),
+        "elr_el2": (unicorn.arm64_const.UC_ARM64_REG_ELR_EL2, "elr_el2", 8, 0),
+        "elr_el3": (unicorn.arm64_const.UC_ARM64_REG_ELR_EL3, "elr_el3", 8, 0),
+        # Banked exception syndrome registers for exception handlers
+        # NOTE: Unicorn thinks there's a far_el0; according to docs, it doesn't exist
+        "far_el1": (unicorn.arm64_const.UC_ARM64_REG_FAR_EL1, "far_el1", 8, 0),
+        "far_el2": (unicorn.arm64_const.UC_ARM64_REG_FAR_EL2, "far_el2", 8, 0),
+        "far_el3": (unicorn.arm64_const.UC_ARM64_REG_FAR_EL3, "far_el3", 8, 0),
+        # Banked vector base address registers for exception handlers
+        # NOTE: vbar_el0 and vbar_el1 are aliases for each other.
+        # Since vbar_el0 doesn't exist in angr, vbar_el1 has to be the "real" copy.
+        "vbar_el1": (unicorn.arm64_const.UC_ARM64_REG_VBAR_EL1, "vbar_el1", 8, 0),
+        "vbar_el0": (unicorn.arm64_const.UC_ARM64_REG_VBAR_EL0, "vbar_el1", 8, 0),
+        "vbar_el2": (unicorn.arm64_const.UC_ARM64_REG_VBAR_EL2, "vbar_el2", 8, 0),
+        "vbar_el3": (unicorn.arm64_const.UC_ARM64_REG_VBAR_EL3, "vbar_el3", 8, 0),
+        # Coprocessor access control register
+        "cpacr_el1": (unicorn.arm64_const.UC_ARM64_REG_CPACR_EL1, "cpacr_el1", 8, 0),
+        # Memory Attribute Indirection Register
+        "mair_el1": (unicorn.arm64_const.UC_ARM64_REG_MAIR_EL1, "mair_el1", 8, 0),
+        # Physical Address Register
+        "par_el1": (unicorn.arm64_const.UC_ARM64_REG_PAR_EL1, "par_el1", 8, 0),
+        # Translation Table Zero Base Register
+        "ttbr0_el1": (unicorn.arm64_const.UC_ARM64_REG_TTBR0_EL1, "ttbr0_el1", 8, 0),
+        # Translation Table One Base Register
+        "ttbr1_el1": (unicorn.arm64_const.UC_ARM64_REG_TTBR1_EL1, "ttbr1_el1", 8, 0),
+        # Thread ID Register
+        # NOTE: According to docs, there should be an el2 and el3 copy, too.
+        "tpidr_el0": (unicorn.arm64_const.UC_ARM64_REG_TPIDR_EL0, "tpidr_el0", 8, 0),
+        "tpidr_el1": (unicorn.arm64_const.UC_ARM64_REG_TPIDR_EL1, "tpidr_el1", 8, 0),
+        # Userspace-visible Thread ID register
+        "tpidrro_el0": (
+            unicorn.arm64_const.UC_ARM64_REG_TPIDRRO_EL0,
+            "tpidrro_el0",
+            8,
+            0,
+        ),
+        # *** Floating Point Registers ***
+        # Scalar Floating Point Registers
+        "q0": (unicorn.arm64_const.UC_ARM64_REG_Q0, "q0", 16, 0),
+        "d0": (unicorn.arm64_const.UC_ARM64_REG_D0, "q0", 8, 0),
+        "s0": (unicorn.arm64_const.UC_ARM64_REG_S0, "q0", 4, 0),
+        "h0": (unicorn.arm64_const.UC_ARM64_REG_H0, "q0", 2, 0),
+        "b0": (unicorn.arm64_const.UC_ARM64_REG_B0, "q0", 1, 0),
+        "q1": (unicorn.arm64_const.UC_ARM64_REG_Q1, "q1", 16, 0),
+        "d1": (unicorn.arm64_const.UC_ARM64_REG_D1, "q1", 8, 0),
+        "s1": (unicorn.arm64_const.UC_ARM64_REG_S1, "q1", 4, 0),
+        "h1": (unicorn.arm64_const.UC_ARM64_REG_H1, "q1", 2, 0),
+        "b1": (unicorn.arm64_const.UC_ARM64_REG_B1, "q1", 1, 0),
+        "q2": (unicorn.arm64_const.UC_ARM64_REG_Q2, "q2", 16, 0),
+        "d2": (unicorn.arm64_const.UC_ARM64_REG_D2, "q2", 8, 0),
+        "s2": (unicorn.arm64_const.UC_ARM64_REG_S2, "q2", 4, 0),
+        "h2": (unicorn.arm64_const.UC_ARM64_REG_H2, "q2", 2, 0),
+        "b2": (unicorn.arm64_const.UC_ARM64_REG_B2, "q2", 1, 0),
+        "q3": (unicorn.arm64_const.UC_ARM64_REG_Q3, "q3", 16, 0),
+        "d3": (unicorn.arm64_const.UC_ARM64_REG_D3, "q3", 8, 0),
+        "s3": (unicorn.arm64_const.UC_ARM64_REG_S3, "q3", 4, 0),
+        "h3": (unicorn.arm64_const.UC_ARM64_REG_H3, "q3", 2, 0),
+        "b3": (unicorn.arm64_const.UC_ARM64_REG_B3, "q3", 1, 0),
+        "q4": (unicorn.arm64_const.UC_ARM64_REG_Q4, "q4", 16, 0),
+        "d4": (unicorn.arm64_const.UC_ARM64_REG_D4, "q4", 8, 0),
+        "s4": (unicorn.arm64_const.UC_ARM64_REG_S4, "q4", 4, 0),
+        "h4": (unicorn.arm64_const.UC_ARM64_REG_H4, "q4", 2, 0),
+        "b4": (unicorn.arm64_const.UC_ARM64_REG_B4, "q4", 1, 0),
+        "q5": (unicorn.arm64_const.UC_ARM64_REG_Q5, "q5", 16, 0),
+        "d5": (unicorn.arm64_const.UC_ARM64_REG_D5, "q5", 8, 0),
+        "s5": (unicorn.arm64_const.UC_ARM64_REG_S5, "q5", 4, 0),
+        "h5": (unicorn.arm64_const.UC_ARM64_REG_H5, "q5", 2, 0),
+        "b5": (unicorn.arm64_const.UC_ARM64_REG_B5, "q5", 1, 0),
+        "q6": (unicorn.arm64_const.UC_ARM64_REG_Q6, "q6", 16, 0),
+        "d6": (unicorn.arm64_const.UC_ARM64_REG_D6, "q6", 8, 0),
+        "s6": (unicorn.arm64_const.UC_ARM64_REG_S6, "q6", 4, 0),
+        "h6": (unicorn.arm64_const.UC_ARM64_REG_H6, "q6", 2, 0),
+        "b6": (unicorn.arm64_const.UC_ARM64_REG_B6, "q6", 1, 0),
+        "q7": (unicorn.arm64_const.UC_ARM64_REG_Q7, "q7", 16, 0),
+        "d7": (unicorn.arm64_const.UC_ARM64_REG_D7, "q7", 8, 0),
+        "s7": (unicorn.arm64_const.UC_ARM64_REG_S7, "q7", 4, 0),
+        "h7": (unicorn.arm64_const.UC_ARM64_REG_H7, "q7", 2, 0),
+        "b7": (unicorn.arm64_const.UC_ARM64_REG_B7, "q7", 1, 0),
+        "q8": (unicorn.arm64_const.UC_ARM64_REG_Q8, "q8", 16, 0),
+        "d8": (unicorn.arm64_const.UC_ARM64_REG_D8, "q8", 8, 0),
+        "s8": (unicorn.arm64_const.UC_ARM64_REG_S8, "q8", 4, 0),
+        "h8": (unicorn.arm64_const.UC_ARM64_REG_H8, "q8", 2, 0),
+        "b8": (unicorn.arm64_const.UC_ARM64_REG_B8, "q8", 1, 0),
+        "q9": (unicorn.arm64_const.UC_ARM64_REG_Q9, "q9", 16, 0),
+        "d9": (unicorn.arm64_const.UC_ARM64_REG_D9, "q9", 8, 0),
+        "s9": (unicorn.arm64_const.UC_ARM64_REG_S9, "q9", 4, 0),
+        "h9": (unicorn.arm64_const.UC_ARM64_REG_H9, "q9", 2, 0),
+        "b9": (unicorn.arm64_const.UC_ARM64_REG_B9, "q9", 1, 0),
+        "q10": (unicorn.arm64_const.UC_ARM64_REG_Q10, "q10", 16, 0),
+        "d10": (unicorn.arm64_const.UC_ARM64_REG_D10, "q10", 8, 0),
+        "s10": (unicorn.arm64_const.UC_ARM64_REG_S10, "q10", 4, 0),
+        "h10": (unicorn.arm64_const.UC_ARM64_REG_H10, "q10", 2, 0),
+        "b10": (unicorn.arm64_const.UC_ARM64_REG_B10, "q10", 1, 0),
+        "q11": (unicorn.arm64_const.UC_ARM64_REG_Q11, "q11", 16, 0),
+        "d11": (unicorn.arm64_const.UC_ARM64_REG_D11, "q11", 8, 0),
+        "s11": (unicorn.arm64_const.UC_ARM64_REG_S11, "q11", 4, 0),
+        "h11": (unicorn.arm64_const.UC_ARM64_REG_H11, "q11", 2, 0),
+        "b11": (unicorn.arm64_const.UC_ARM64_REG_B11, "q11", 1, 0),
+        "q12": (unicorn.arm64_const.UC_ARM64_REG_Q12, "q12", 16, 0),
+        "d12": (unicorn.arm64_const.UC_ARM64_REG_D12, "q12", 8, 0),
+        "s12": (unicorn.arm64_const.UC_ARM64_REG_S12, "q12", 4, 0),
+        "h12": (unicorn.arm64_const.UC_ARM64_REG_H12, "q12", 2, 0),
+        "b12": (unicorn.arm64_const.UC_ARM64_REG_B12, "q12", 1, 0),
+        "q13": (unicorn.arm64_const.UC_ARM64_REG_Q13, "q13", 16, 0),
+        "d13": (unicorn.arm64_const.UC_ARM64_REG_D13, "q13", 8, 0),
+        "s13": (unicorn.arm64_const.UC_ARM64_REG_S13, "q13", 4, 0),
+        "h13": (unicorn.arm64_const.UC_ARM64_REG_H13, "q13", 2, 0),
+        "b13": (unicorn.arm64_const.UC_ARM64_REG_B13, "q13", 1, 0),
+        "q14": (unicorn.arm64_const.UC_ARM64_REG_Q14, "q14", 16, 0),
+        "d14": (unicorn.arm64_const.UC_ARM64_REG_D14, "q14", 8, 0),
+        "s14": (unicorn.arm64_const.UC_ARM64_REG_S14, "q14", 4, 0),
+        "h14": (unicorn.arm64_const.UC_ARM64_REG_H14, "q14", 2, 0),
+        "b14": (unicorn.arm64_const.UC_ARM64_REG_B14, "q14", 1, 0),
+        "q15": (unicorn.arm64_const.UC_ARM64_REG_Q15, "q15", 16, 0),
+        "d15": (unicorn.arm64_const.UC_ARM64_REG_D15, "q15", 8, 0),
+        "s15": (unicorn.arm64_const.UC_ARM64_REG_S15, "q15", 4, 0),
+        "h15": (unicorn.arm64_const.UC_ARM64_REG_H15, "q15", 2, 0),
+        "b15": (unicorn.arm64_const.UC_ARM64_REG_B15, "q15", 1, 0),
+        "q16": (unicorn.arm64_const.UC_ARM64_REG_Q16, "q16", 16, 0),
+        "d16": (unicorn.arm64_const.UC_ARM64_REG_D16, "q16", 8, 0),
+        "s16": (unicorn.arm64_const.UC_ARM64_REG_S16, "q16", 4, 0),
+        "h16": (unicorn.arm64_const.UC_ARM64_REG_H16, "q16", 2, 0),
+        "b16": (unicorn.arm64_const.UC_ARM64_REG_B16, "q16", 1, 0),
+        "q17": (unicorn.arm64_const.UC_ARM64_REG_Q17, "q17", 16, 0),
+        "d17": (unicorn.arm64_const.UC_ARM64_REG_D17, "q17", 8, 0),
+        "s17": (unicorn.arm64_const.UC_ARM64_REG_S17, "q17", 4, 0),
+        "h17": (unicorn.arm64_const.UC_ARM64_REG_H17, "q17", 2, 0),
+        "b17": (unicorn.arm64_const.UC_ARM64_REG_B17, "q17", 1, 0),
+        "q18": (unicorn.arm64_const.UC_ARM64_REG_Q18, "q18", 16, 0),
+        "d18": (unicorn.arm64_const.UC_ARM64_REG_D18, "q18", 8, 0),
+        "s18": (unicorn.arm64_const.UC_ARM64_REG_S18, "q18", 4, 0),
+        "h18": (unicorn.arm64_const.UC_ARM64_REG_H18, "q18", 2, 0),
+        "b18": (unicorn.arm64_const.UC_ARM64_REG_B18, "q18", 1, 0),
+        "q19": (unicorn.arm64_const.UC_ARM64_REG_Q19, "q19", 16, 0),
+        "d19": (unicorn.arm64_const.UC_ARM64_REG_D19, "q19", 8, 0),
+        "s19": (unicorn.arm64_const.UC_ARM64_REG_S19, "q19", 4, 0),
+        "h19": (unicorn.arm64_const.UC_ARM64_REG_H19, "q19", 2, 0),
+        "b19": (unicorn.arm64_const.UC_ARM64_REG_B19, "q19", 1, 0),
+        "q20": (unicorn.arm64_const.UC_ARM64_REG_Q20, "q20", 16, 0),
+        "d20": (unicorn.arm64_const.UC_ARM64_REG_D20, "q20", 8, 0),
+        "s20": (unicorn.arm64_const.UC_ARM64_REG_S20, "q20", 4, 0),
+        "h20": (unicorn.arm64_const.UC_ARM64_REG_H20, "q20", 2, 0),
+        "b20": (unicorn.arm64_const.UC_ARM64_REG_B20, "q20", 1, 0),
+        "q21": (unicorn.arm64_const.UC_ARM64_REG_Q21, "q21", 16, 0),
+        "d21": (unicorn.arm64_const.UC_ARM64_REG_D21, "q21", 8, 0),
+        "s21": (unicorn.arm64_const.UC_ARM64_REG_S21, "q21", 4, 0),
+        "h21": (unicorn.arm64_const.UC_ARM64_REG_H21, "q21", 2, 0),
+        "b21": (unicorn.arm64_const.UC_ARM64_REG_B21, "q21", 1, 0),
+        "q22": (unicorn.arm64_const.UC_ARM64_REG_Q22, "q22", 16, 0),
+        "d22": (unicorn.arm64_const.UC_ARM64_REG_D22, "q22", 8, 0),
+        "s22": (unicorn.arm64_const.UC_ARM64_REG_S22, "q22", 4, 0),
+        "h22": (unicorn.arm64_const.UC_ARM64_REG_H22, "q22", 2, 0),
+        "b22": (unicorn.arm64_const.UC_ARM64_REG_B22, "q22", 1, 0),
+        "q23": (unicorn.arm64_const.UC_ARM64_REG_Q23, "q23", 16, 0),
+        "d23": (unicorn.arm64_const.UC_ARM64_REG_D23, "q23", 8, 0),
+        "s23": (unicorn.arm64_const.UC_ARM64_REG_S23, "q23", 4, 0),
+        "h23": (unicorn.arm64_const.UC_ARM64_REG_H23, "q23", 2, 0),
+        "b23": (unicorn.arm64_const.UC_ARM64_REG_B23, "q23", 1, 0),
+        "q24": (unicorn.arm64_const.UC_ARM64_REG_Q24, "q24", 16, 0),
+        "d24": (unicorn.arm64_const.UC_ARM64_REG_D24, "q24", 8, 0),
+        "s24": (unicorn.arm64_const.UC_ARM64_REG_S24, "q24", 4, 0),
+        "h24": (unicorn.arm64_const.UC_ARM64_REG_H24, "q24", 2, 0),
+        "b24": (unicorn.arm64_const.UC_ARM64_REG_B24, "q24", 1, 0),
+        "q25": (unicorn.arm64_const.UC_ARM64_REG_Q25, "q25", 16, 0),
+        "d25": (unicorn.arm64_const.UC_ARM64_REG_D25, "q25", 8, 0),
+        "s25": (unicorn.arm64_const.UC_ARM64_REG_S25, "q25", 4, 0),
+        "h25": (unicorn.arm64_const.UC_ARM64_REG_H25, "q25", 2, 0),
+        "b25": (unicorn.arm64_const.UC_ARM64_REG_B25, "q25", 1, 0),
+        "q26": (unicorn.arm64_const.UC_ARM64_REG_Q26, "q26", 16, 0),
+        "d26": (unicorn.arm64_const.UC_ARM64_REG_D26, "q26", 8, 0),
+        "s26": (unicorn.arm64_const.UC_ARM64_REG_S26, "q26", 4, 0),
+        "h26": (unicorn.arm64_const.UC_ARM64_REG_H26, "q26", 2, 0),
+        "b26": (unicorn.arm64_const.UC_ARM64_REG_B26, "q26", 1, 0),
+        "q27": (unicorn.arm64_const.UC_ARM64_REG_Q27, "q27", 16, 0),
+        "d27": (unicorn.arm64_const.UC_ARM64_REG_D27, "q27", 8, 0),
+        "s27": (unicorn.arm64_const.UC_ARM64_REG_S27, "q27", 4, 0),
+        "h27": (unicorn.arm64_const.UC_ARM64_REG_H27, "q27", 2, 0),
+        "b27": (unicorn.arm64_const.UC_ARM64_REG_B27, "q27", 1, 0),
+        "q28": (unicorn.arm64_const.UC_ARM64_REG_Q28, "q28", 16, 0),
+        "d28": (unicorn.arm64_const.UC_ARM64_REG_D28, "q28", 8, 0),
+        "s28": (unicorn.arm64_const.UC_ARM64_REG_S28, "q28", 4, 0),
+        "h28": (unicorn.arm64_const.UC_ARM64_REG_H28, "q28", 2, 0),
+        "b28": (unicorn.arm64_const.UC_ARM64_REG_B28, "q28", 1, 0),
+        "q29": (unicorn.arm64_const.UC_ARM64_REG_Q29, "q29", 16, 0),
+        "d29": (unicorn.arm64_const.UC_ARM64_REG_D29, "q29", 8, 0),
+        "s29": (unicorn.arm64_const.UC_ARM64_REG_S29, "q29", 4, 0),
+        "h29": (unicorn.arm64_const.UC_ARM64_REG_H29, "q29", 2, 0),
+        "b29": (unicorn.arm64_const.UC_ARM64_REG_B29, "q29", 1, 0),
+        "q30": (unicorn.arm64_const.UC_ARM64_REG_Q30, "q30", 16, 0),
+        "d30": (unicorn.arm64_const.UC_ARM64_REG_D30, "q30", 8, 0),
+        "s30": (unicorn.arm64_const.UC_ARM64_REG_S30, "q30", 4, 0),
+        "h30": (unicorn.arm64_const.UC_ARM64_REG_H30, "q30", 2, 0),
+        "b30": (unicorn.arm64_const.UC_ARM64_REG_B30, "q30", 1, 0),
+        "q31": (unicorn.arm64_const.UC_ARM64_REG_Q31, "q31", 16, 0),
+        "d31": (unicorn.arm64_const.UC_ARM64_REG_D31, "q31", 8, 0),
+        "s31": (unicorn.arm64_const.UC_ARM64_REG_S31, "q31", 4, 0),
+        "h31": (unicorn.arm64_const.UC_ARM64_REG_H31, "q31", 2, 0),
+        "b31": (unicorn.arm64_const.UC_ARM64_REG_B31, "q31", 1, 0),
+        # Vector registers
+        # TODO: Figure out how to model these
+    }

smallworld/emulators/unicorn/machdefs/amd64.py

@@ -0,0 +1,326 @@
+import capstone
+import unicorn
+
+from ....platforms import Architecture, Byteorder
+from .machdef import UnicornMachineDef
+
+
+class AMD64MachineDef(UnicornMachineDef):
+    """Unicorn machine definition for amd64"""
+
+    byteorder = Byteorder.LITTLE
+
+    uc_arch = unicorn.UC_ARCH_X86
+    uc_mode = unicorn.UC_MODE_64
+
+    cs_arch = capstone.CS_ARCH_X86
+    cs_mode = capstone.CS_MODE_64
+
+    pc_reg = "rip"
+
+    def __init__(self):
+        self._registers = {
+            # *** General Purpose Registers ***
+            "rax": (unicorn.x86_const.UC_X86_REG_RAX, "rax", 8, 0),
+            "eax": (unicorn.x86_const.UC_X86_REG_EAX, "rax", 4, 0),
+            "ax": (unicorn.x86_const.UC_X86_REG_AX, "rax", 2, 0),
+            "al": (unicorn.x86_const.UC_X86_REG_AL, "rax", 1, 0),
+            "ah": (unicorn.x86_const.UC_X86_REG_AH, "rax", 1, 1),
+            "rbx": (unicorn.x86_const.UC_X86_REG_RBX, "rbx", 8, 0),
+            "ebx": (unicorn.x86_const.UC_X86_REG_EBX, "rbx", 4, 0),
+            "bx": (unicorn.x86_const.UC_X86_REG_BX, "rbx", 2, 0),
+            "bl": (unicorn.x86_const.UC_X86_REG_BL, "rbx", 1, 0),
+            "bh": (unicorn.x86_const.UC_X86_REG_BH, "rbx", 1, 1),
+            "rcx": (unicorn.x86_const.UC_X86_REG_RCX, "rcx", 8, 0),
+            "ecx": (unicorn.x86_const.UC_X86_REG_ECX, "rcx", 4, 0),
+            "cx": (unicorn.x86_const.UC_X86_REG_CX, "rcx", 2, 0),
+            "cl": (unicorn.x86_const.UC_X86_REG_CL, "rcx", 1, 0),
+            "ch": (unicorn.x86_const.UC_X86_REG_CH, "rcx", 1, 1),
+            "rdx": (unicorn.x86_const.UC_X86_REG_RDX, "rdx", 8, 0),
+            "edx": (unicorn.x86_const.UC_X86_REG_EDX, "rdx", 4, 0),
+            "dx": (unicorn.x86_const.UC_X86_REG_DX, "rdx", 2, 0),
+            "dl": (unicorn.x86_const.UC_X86_REG_DL, "rdx", 1, 0),
+            "dh": (unicorn.x86_const.UC_X86_REG_DH, "rdx", 1, 1),
+            "r8": (unicorn.x86_const.UC_X86_REG_R8, "r8", 8, 0),
+            "r8d": (unicorn.x86_const.UC_X86_REG_R8D, "r8", 4, 0),
+            "r8w": (unicorn.x86_const.UC_X86_REG_R8W, "r8", 2, 0),
+            "r8b": (unicorn.x86_const.UC_X86_REG_R8B, "r8", 1, 0),
+            "r9": (unicorn.x86_const.UC_X86_REG_R9, "r9", 8, 0),
+            "r9d": (unicorn.x86_const.UC_X86_REG_R9D, "r9", 4, 0),
+            "r9w": (unicorn.x86_const.UC_X86_REG_R9W, "r9", 2, 0),
+            "r9b": (unicorn.x86_const.UC_X86_REG_R9B, "r9", 1, 0),
+            "r10": (unicorn.x86_const.UC_X86_REG_R10, "r10", 8, 0),
+            "r10d": (unicorn.x86_const.UC_X86_REG_R10D, "r10", 4, 0),
+            "r10w": (unicorn.x86_const.UC_X86_REG_R10W, "r10", 2, 0),
+            "r10b": (unicorn.x86_const.UC_X86_REG_R10B, "r10", 1, 0),
+            "r11": (unicorn.x86_const.UC_X86_REG_R11, "r11", 8, 0),
+            "r11d": (unicorn.x86_const.UC_X86_REG_R11D, "r11", 4, 0),
+            "r11w": (unicorn.x86_const.UC_X86_REG_R11W, "r11", 2, 0),
+            "r11b": (unicorn.x86_const.UC_X86_REG_R11B, "r11", 1, 0),
+            "r12": (unicorn.x86_const.UC_X86_REG_R12, "r12", 8, 0),
+            "r12d": (unicorn.x86_const.UC_X86_REG_R12D, "r12", 4, 0),
+            "r12w": (unicorn.x86_const.UC_X86_REG_R12W, "r12", 2, 0),
+            "r12b": (unicorn.x86_const.UC_X86_REG_R12B, "r12", 1, 0),
+            "r13": (unicorn.x86_const.UC_X86_REG_R13, "r13", 8, 0),
+            "r13d": (unicorn.x86_const.UC_X86_REG_R13D, "r13", 4, 0),
+            "r13w": (unicorn.x86_const.UC_X86_REG_R13W, "r13", 2, 0),
+            "r13b": (unicorn.x86_const.UC_X86_REG_R13B, "r13", 1, 0),
+            "r14": (unicorn.x86_const.UC_X86_REG_R14, "r14", 8, 0),
+            "r14d": (unicorn.x86_const.UC_X86_REG_R14D, "r14", 4, 0),
+            "r14w": (unicorn.x86_const.UC_X86_REG_R14W, "r14", 2, 0),
+            "r14b": (unicorn.x86_const.UC_X86_REG_R14B, "r14", 1, 0),
+            "r15": (unicorn.x86_const.UC_X86_REG_R15, "r15", 8, 0),
+            "r15d": (unicorn.x86_const.UC_X86_REG_R15D, "r15", 4, 0),
+            "r15w": (unicorn.x86_const.UC_X86_REG_R15W, "r15", 2, 0),
+            "r15b": (unicorn.x86_const.UC_X86_REG_R15B, "r15", 1, 0),
+            "rdi": (unicorn.x86_const.UC_X86_REG_RDI, "rdi", 8, 0),
+            "edi": (unicorn.x86_const.UC_X86_REG_EDI, "rdi", 4, 0),
+            "di": (unicorn.x86_const.UC_X86_REG_DI, "rdi", 2, 0),
+            "dil": (unicorn.x86_const.UC_X86_REG_DIL, "rdi", 1, 0),
+            "rsi": (unicorn.x86_const.UC_X86_REG_RSI, "rsi", 8, 0),
+            "esi": (unicorn.x86_const.UC_X86_REG_ESI, "rsi", 4, 0),
+            "si": (unicorn.x86_const.UC_X86_REG_SI, "rsi", 2, 0),
+            "sil": (unicorn.x86_const.UC_X86_REG_SIL, "rsi", 1, 0),
+            "rsp": (unicorn.x86_const.UC_X86_REG_RSP, "rsp", 8, 0),
+            "esp": (unicorn.x86_const.UC_X86_REG_ESP, "rsp", 4, 0),
+            "sp": (unicorn.x86_const.UC_X86_REG_SP, "rsp", 2, 0),
+            "spl": (unicorn.x86_const.UC_X86_REG_SPL, "rsp", 1, 0),
+            "rbp": (unicorn.x86_const.UC_X86_REG_RBP, "rbp", 8, 0),
+            "ebp": (unicorn.x86_const.UC_X86_REG_EBP, "rbp", 4, 0),
+            "bp": (unicorn.x86_const.UC_X86_REG_BP, "rbp", 2, 0),
+            "bpl": (unicorn.x86_const.UC_X86_REG_BPL, "rbp", 1, 0),
+            # *** Instruction Pointer ***
+            "rip": (unicorn.x86_const.UC_X86_REG_RIP, "rip", 8, 0),
+            "eip": (unicorn.x86_const.UC_X86_REG_EIP, "rip", 4, 0),
+            "ip": (unicorn.x86_const.UC_X86_REG_IP, "rip", 2, 0),
+            # *** Flags register ***
+            "rflags": (unicorn.x86_const.UC_X86_REG_RFLAGS, "rflags", 8, 0),
+            "eflags": (unicorn.x86_const.UC_X86_REG_EFLAGS, "rflags", 4, 0),
+            "flags": (unicorn.x86_const.UC_X86_REG_FLAGS, "rflags", 2, 0),
+            # *** Segment Registers ***
+            "cs": (unicorn.x86_const.UC_X86_REG_CS, "cs", 2, 0),
+            "ds": (unicorn.x86_const.UC_X86_REG_DS, "ds", 2, 0),
+            "es": (unicorn.x86_const.UC_X86_REG_ES, "es", 2, 0),
+            "fs": (unicorn.x86_const.UC_X86_REG_FS, "fs", 2, 0),
+            "gs": (unicorn.x86_const.UC_X86_REG_GS, "gs", 2, 0),
+            # *** Control Registers ***
+            "cr0": (unicorn.x86_const.UC_X86_REG_CR0, "cr0", 8, 0),
+            "cr1": (unicorn.x86_const.UC_X86_REG_CR1, "cr1", 8, 0),
+            "cr2": (unicorn.x86_const.UC_X86_REG_CR2, "cr2", 8, 0),
+            "cr3": (unicorn.x86_const.UC_X86_REG_CR3, "cr3", 8, 0),
+            "cr4": (unicorn.x86_const.UC_X86_REG_CR4, "cr4", 8, 0),
+            "cr8": (unicorn.x86_const.UC_X86_REG_INVALID, "cr8", 8, 0),
+            # *** Debug Registers ***
+            "dr0": (unicorn.x86_const.UC_X86_REG_DR0, "dr0", 8, 0),
+            "dr1": (unicorn.x86_const.UC_X86_REG_DR1, "dr1", 8, 0),
+            "dr2": (unicorn.x86_const.UC_X86_REG_DR2, "dr2", 8, 0),
+            "dr3": (unicorn.x86_const.UC_X86_REG_DR3, "dr3", 8, 0),
+            "dr6": (unicorn.x86_const.UC_X86_REG_DR6, "dr6", 8, 0),
+            "dr7": (unicorn.x86_const.UC_X86_REG_DR7, "dr7", 8, 0),
+            "dr8": (unicorn.x86_const.UC_X86_REG_INVALID, "dr8", 8, 0),
+            "dr9": (unicorn.x86_const.UC_X86_REG_INVALID, "dr9", 8, 0),
+            "dr10": (unicorn.x86_const.UC_X86_REG_INVALID, "dr10", 8, 0),
+            "dr11": (unicorn.x86_const.UC_X86_REG_INVALID, "dr11", 8, 0),
+            "dr12": (unicorn.x86_const.UC_X86_REG_INVALID, "dr12", 8, 0),
+            "dr13": (unicorn.x86_const.UC_X86_REG_INVALID, "dr13", 8, 0),
+            "dr14": (unicorn.x86_const.UC_X86_REG_INVALID, "dr14", 8, 0),
+            "dr15": (unicorn.x86_const.UC_X86_REG_INVALID, "dr15", 8, 0),
+            # *** Descriptor Table Registers ***
+            "gdtr": (unicorn.x86_const.UC_X86_REG_GDTR, "gdtr", 10, 0),
+            "idtr": (unicorn.x86_const.UC_X86_REG_IDTR, "idtr", 10, 0),
+            "ldtr": (unicorn.x86_const.UC_X86_REG_LDTR, "ldtr", 10, 0),
+            # *** Task Register ***
+            "tr": (unicorn.x86_const.UC_X86_REG_TR, "tr", 2, 0),
+            # *** x87 registers ***
+            # NOTE: x87 is supported by Unicorn, but not by SmallWorld.
+            # Values are represented as tuples (exponent: int, mantissa: int).
+            # If you need x87 support, open a ticket.
+            "fpr0": (unicorn.x86_const.UC_X86_REG_INVALID, "fpr0", 10, 0),
+            "fpr1": (unicorn.x86_const.UC_X86_REG_INVALID, "fpr1", 10, 0),
+            "fpr2": (unicorn.x86_const.UC_X86_REG_INVALID, "fpr2", 10, 0),
+            "fpr3": (unicorn.x86_const.UC_X86_REG_INVALID, "fpr3", 10, 0),
+            "fpr4": (unicorn.x86_const.UC_X86_REG_INVALID, "fpr4", 10, 0),
+            "fpr5": (unicorn.x86_const.UC_X86_REG_INVALID, "fpr5", 10, 0),
+            "fpr6": (unicorn.x86_const.UC_X86_REG_INVALID, "fpr6", 10, 0),
+            "fpr7": (unicorn.x86_const.UC_X86_REG_INVALID, "fpr7", 10, 0),
+            # x87 Control Register
+            "fctrl": (unicorn.x86_const.UC_X86_REG_FPCW, "fctrl", 2, 0),
+            # x87 Status Register
+            "fstat": (unicorn.x86_const.UC_X86_REG_FPCW, "fstat", 2, 0),
+            # x87 Tag Register
+            "ftag": (unicorn.x86_const.UC_X86_REG_FPTAG, "ftag", 2, 0),
+            # x87 Last Instruction Register
+            "fip": (unicorn.x86_const.UC_X86_REG_FIP, "fip", 8, 0),
+            # x87 Last Operand Pointer
+            "fdp": (unicorn.x86_const.UC_X86_REG_FDP, "fdp", 8, 0),
+            # x87 Last Opcode
+            "fop": (unicorn.x86_const.UC_X86_REG_FOP, "fop", 2, 0),
+            # NOTE: Docs disagree on the format of fip and fdp.
+            # One source describes them as 48-bit offset-plus-segment,
+            # the other describes them as 64-bit.
+            # There may also be separate segment registers.
+            # If you care about the x87 debug info, please feel free to update.
+            # *** MMX Registers ***
+            # NOTE: The MMX registers are aliases for the low 8 bytes of the x87 registers.
+            # The two subsystems cannot be used simultaneously.
+            "mm0": (unicorn.x86_const.UC_X86_REG_MM0, "fpr0", 8, 0),
+            "mm1": (unicorn.x86_const.UC_X86_REG_MM1, "fpr1", 8, 0),
+            "mm2": (unicorn.x86_const.UC_X86_REG_MM2, "fpr2", 8, 0),
+            "mm3": (unicorn.x86_const.UC_X86_REG_MM3, "fpr3", 8, 0),
+            "mm4": (unicorn.x86_const.UC_X86_REG_MM4, "fpr4", 8, 0),
+            "mm5": (unicorn.x86_const.UC_X86_REG_MM5, "fpr5", 8, 0),
+            "mm6": (unicorn.x86_const.UC_X86_REG_MM6, "fpr6", 8, 0),
+            "mm7": (unicorn.x86_const.UC_X86_REG_MM7, "fpr7", 8, 0),
+        }
+
+
+class AMD64AVX2MachineDef(AMD64MachineDef):
+    arch = Architecture.X86_64
+
+    def __init__(self):
+        super().__init__()
+        self._registers.update(
+            {
+                # *** SSE/AVX registers ***
+                "ymm0": (unicorn.x86_const.UC_X86_REG_YMM0, "ymm0", 32, 0),
+                "xmm0": (unicorn.x86_const.UC_X86_REG_XMM0, "ymm0", 16, 0),
+                "ymm1": (unicorn.x86_const.UC_X86_REG_YMM1, "ymm1", 32, 0),
+                "xmm1": (unicorn.x86_const.UC_X86_REG_XMM1, "ymm1", 16, 0),
+                "ymm2": (unicorn.x86_const.UC_X86_REG_YMM2, "ymm2", 32, 0),
+                "xmm2": (unicorn.x86_const.UC_X86_REG_XMM2, "ymm2", 16, 0),
+                "ymm3": (unicorn.x86_const.UC_X86_REG_YMM3, "ymm3", 32, 0),
+                "xmm3": (unicorn.x86_const.UC_X86_REG_XMM3, "ymm3", 16, 0),
+                "ymm4": (unicorn.x86_const.UC_X86_REG_YMM4, "ymm4", 32, 0),
+                "xmm4": (unicorn.x86_const.UC_X86_REG_XMM4, "ymm4", 16, 0),
+                "ymm5": (unicorn.x86_const.UC_X86_REG_YMM5, "ymm5", 32, 0),
+                "xmm5": (unicorn.x86_const.UC_X86_REG_XMM5, "ymm5", 16, 0),
+                "ymm6": (unicorn.x86_const.UC_X86_REG_YMM6, "ymm6", 32, 0),
+                "xmm6": (unicorn.x86_const.UC_X86_REG_XMM6, "ymm6", 16, 0),
+                "ymm7": (unicorn.x86_const.UC_X86_REG_YMM7, "ymm7", 32, 0),
+                "xmm7": (unicorn.x86_const.UC_X86_REG_XMM7, "ymm7", 16, 0),
+                "ymm8": (unicorn.x86_const.UC_X86_REG_YMM8, "ymm8", 32, 0),
+                "xmm8": (unicorn.x86_const.UC_X86_REG_XMM8, "ymm8", 16, 0),
+                "ymm9": (unicorn.x86_const.UC_X86_REG_YMM9, "ymm9", 32, 0),
+                "xmm9": (unicorn.x86_const.UC_X86_REG_XMM9, "ymm9", 16, 0),
+                "ymm10": (unicorn.x86_const.UC_X86_REG_YMM10, "ymm10", 32, 0),
+                "xmm10": (unicorn.x86_const.UC_X86_REG_XMM10, "ymm10", 16, 0),
+                "ymm11": (unicorn.x86_const.UC_X86_REG_YMM11, "ymm11", 32, 0),
+                "xmm11": (unicorn.x86_const.UC_X86_REG_XMM11, "ymm11", 16, 0),
+                "ymm12": (unicorn.x86_const.UC_X86_REG_YMM12, "ymm12", 32, 0),
+                "xmm12": (unicorn.x86_const.UC_X86_REG_XMM12, "ymm12", 16, 0),
+                "ymm13": (unicorn.x86_const.UC_X86_REG_YMM13, "ymm13", 32, 0),
+                "xmm13": (unicorn.x86_const.UC_X86_REG_XMM13, "ymm13", 16, 0),
+                "ymm14": (unicorn.x86_const.UC_X86_REG_YMM14, "ymm14", 32, 0),
+                "xmm14": (unicorn.x86_const.UC_X86_REG_XMM14, "ymm14", 16, 0),
+                "ymm15": (unicorn.x86_const.UC_X86_REG_YMM15, "ymm15", 32, 0),
+                "xmm15": (unicorn.x86_const.UC_X86_REG_XMM15, "ymm15", 16, 0),
+            }
+        )
+
+
+class AMD64AVX512MachineDef(AMD64MachineDef):
+    arch = Architecture.X86_64_AVX512
+
+    def __init__(self):
+        super().__init__()
+        self._registers.update(
+            {
+                # *** SSE/AVX registers ***
+                "zmm0": (unicorn.x86_const.UC_X86_REG_ZMM0, "zmm0", 64, 0),
+                "ymm0": (unicorn.x86_const.UC_X86_REG_YMM0, "zmm0", 32, 0),
+                "xmm0": (unicorn.x86_const.UC_X86_REG_XMM0, "zmm0", 16, 0),
+                "zmm1": (unicorn.x86_const.UC_X86_REG_ZMM1, "zmm1", 64, 0),
+                "ymm1": (unicorn.x86_const.UC_X86_REG_YMM1, "zmm1", 32, 0),
+                "xmm1": (unicorn.x86_const.UC_X86_REG_XMM1, "zmm1", 16, 0),
+                "zmm2": (unicorn.x86_const.UC_X86_REG_ZMM2, "zmm2", 64, 0),
+                "ymm2": (unicorn.x86_const.UC_X86_REG_YMM2, "zmm2", 32, 0),
+                "xmm2": (unicorn.x86_const.UC_X86_REG_XMM2, "zmm2", 16, 0),
+                "zmm3": (unicorn.x86_const.UC_X86_REG_ZMM3, "zmm3", 64, 0),
+                "ymm3": (unicorn.x86_const.UC_X86_REG_YMM3, "zmm3", 32, 0),
+                "xmm3": (unicorn.x86_const.UC_X86_REG_XMM3, "zmm3", 16, 0),
+                "zmm4": (unicorn.x86_const.UC_X86_REG_ZMM4, "zmm4", 64, 0),
+                "ymm4": (unicorn.x86_const.UC_X86_REG_YMM4, "zmm4", 32, 0),
+                "xmm4": (unicorn.x86_const.UC_X86_REG_XMM4, "zmm4", 16, 0),
+                "zmm5": (unicorn.x86_const.UC_X86_REG_ZMM5, "zmm5", 64, 0),
+                "ymm5": (unicorn.x86_const.UC_X86_REG_YMM5, "zmm5", 32, 0),
+                "xmm5": (unicorn.x86_const.UC_X86_REG_XMM5, "zmm5", 16, 0),
+                "zmm6": (unicorn.x86_const.UC_X86_REG_ZMM6, "zmm6", 64, 0),
+                "ymm6": (unicorn.x86_const.UC_X86_REG_YMM6, "zmm6", 32, 0),
+                "xmm6": (unicorn.x86_const.UC_X86_REG_XMM6, "zmm6", 16, 0),
+                "zmm7": (unicorn.x86_const.UC_X86_REG_ZMM7, "zmm7", 64, 0),
+                "ymm7": (unicorn.x86_const.UC_X86_REG_YMM7, "zmm7", 32, 0),
+                "xmm7": (unicorn.x86_const.UC_X86_REG_XMM7, "zmm7", 16, 0),
+                "zmm8": (unicorn.x86_const.UC_X86_REG_ZMM8, "zmm8", 64, 0),
+                "ymm8": (unicorn.x86_const.UC_X86_REG_YMM8, "zmm8", 32, 0),
+                "xmm8": (unicorn.x86_const.UC_X86_REG_XMM8, "zmm8", 16, 0),
+                "zmm9": (unicorn.x86_const.UC_X86_REG_ZMM9, "zmm9", 64, 0),
+                "ymm9": (unicorn.x86_const.UC_X86_REG_YMM9, "zmm9", 32, 0),
+                "xmm9": (unicorn.x86_const.UC_X86_REG_XMM9, "zmm9", 16, 0),
+                "zmm10": (unicorn.x86_const.UC_X86_REG_ZMM10, "zmm10", 64, 0),
+                "ymm10": (unicorn.x86_const.UC_X86_REG_YMM10, "zmm10", 32, 0),
+                "xmm10": (unicorn.x86_const.UC_X86_REG_XMM10, "zmm10", 16, 0),
+                "zmm11": (unicorn.x86_const.UC_X86_REG_ZMM11, "zmm11", 64, 0),
+                "ymm11": (unicorn.x86_const.UC_X86_REG_YMM11, "zmm11", 32, 0),
+                "xmm11": (unicorn.x86_const.UC_X86_REG_XMM11, "zmm11", 16, 0),
+                "zmm12": (unicorn.x86_const.UC_X86_REG_ZMM12, "zmm12", 64, 0),
+                "ymm12": (unicorn.x86_const.UC_X86_REG_YMM12, "zmm12", 32, 0),
+                "xmm12": (unicorn.x86_const.UC_X86_REG_XMM12, "zmm12", 16, 0),
+                "zmm13": (unicorn.x86_const.UC_X86_REG_ZMM13, "zmm13", 64, 0),
+                "ymm13": (unicorn.x86_const.UC_X86_REG_YMM13, "zmm13", 32, 0),
+                "xmm13": (unicorn.x86_const.UC_X86_REG_XMM13, "zmm13", 16, 0),
+                "zmm14": (unicorn.x86_const.UC_X86_REG_ZMM14, "zmm14", 64, 0),
+                "ymm14": (unicorn.x86_const.UC_X86_REG_YMM14, "zmm14", 32, 0),
+                "xmm14": (unicorn.x86_const.UC_X86_REG_XMM14, "zmm14", 16, 0),
+                "zmm15": (unicorn.x86_const.UC_X86_REG_ZMM15, "zmm15", 64, 0),
+                "ymm15": (unicorn.x86_const.UC_X86_REG_YMM15, "zmm15", 32, 0),
+                "xmm15": (unicorn.x86_const.UC_X86_REG_XMM15, "zmm15", 16, 0),
+                "zmm16": (unicorn.x86_const.UC_X86_REG_ZMM16, "zmm16", 64, 0),
+                "ymm16": (unicorn.x86_const.UC_X86_REG_YMM16, "zmm16", 32, 0),
+                "xmm16": (unicorn.x86_const.UC_X86_REG_XMM16, "zmm16", 16, 0),
+                "zmm17": (unicorn.x86_const.UC_X86_REG_ZMM17, "zmm17", 64, 0),
+                "ymm17": (unicorn.x86_const.UC_X86_REG_YMM17, "zmm17", 32, 0),
+                "xmm17": (unicorn.x86_const.UC_X86_REG_XMM17, "zmm17", 16, 0),
+                "zmm18": (unicorn.x86_const.UC_X86_REG_ZMM18, "zmm18", 64, 0),
+                "ymm18": (unicorn.x86_const.UC_X86_REG_YMM18, "zmm18", 32, 0),
+                "xmm18": (unicorn.x86_const.UC_X86_REG_XMM18, "zmm18", 16, 0),
+                "zmm19": (unicorn.x86_const.UC_X86_REG_ZMM19, "zmm19", 64, 0),
+                "ymm19": (unicorn.x86_const.UC_X86_REG_YMM19, "zmm19", 32, 0),
+                "xmm19": (unicorn.x86_const.UC_X86_REG_XMM19, "zmm19", 16, 0),
+                "zmm20": (unicorn.x86_const.UC_X86_REG_ZMM20, "zmm20", 64, 0),
+                "ymm20": (unicorn.x86_const.UC_X86_REG_YMM20, "zmm20", 32, 0),
+                "xmm20": (unicorn.x86_const.UC_X86_REG_XMM20, "zmm20", 16, 0),
+                "zmm21": (unicorn.x86_const.UC_X86_REG_ZMM21, "zmm21", 64, 0),
+                "ymm21": (unicorn.x86_const.UC_X86_REG_YMM21, "zmm21", 32, 0),
+                "xmm21": (unicorn.x86_const.UC_X86_REG_XMM21, "zmm21", 16, 0),
+                "zmm22": (unicorn.x86_const.UC_X86_REG_ZMM22, "zmm22", 64, 0),
+                "ymm22": (unicorn.x86_const.UC_X86_REG_YMM22, "zmm22", 32, 0),
+                "xmm22": (unicorn.x86_const.UC_X86_REG_XMM22, "zmm22", 16, 0),
+                "zmm23": (unicorn.x86_const.UC_X86_REG_ZMM23, "zmm23", 64, 0),
+                "ymm23": (unicorn.x86_const.UC_X86_REG_YMM23, "zmm23", 32, 0),
+                "xmm23": (unicorn.x86_const.UC_X86_REG_XMM23, "zmm23", 16, 0),
+                "zmm24": (unicorn.x86_const.UC_X86_REG_ZMM24, "zmm24", 64, 0),
+                "ymm24": (unicorn.x86_const.UC_X86_REG_YMM24, "zmm24", 32, 0),
+                "xmm24": (unicorn.x86_const.UC_X86_REG_XMM24, "zmm24", 16, 0),
+                "zmm25": (unicorn.x86_const.UC_X86_REG_ZMM25, "zmm25", 64, 0),
+                "ymm25": (unicorn.x86_const.UC_X86_REG_YMM25, "zmm25", 32, 0),
+                "xmm25": (unicorn.x86_const.UC_X86_REG_XMM25, "zmm25", 16, 0),
+                "zmm26": (unicorn.x86_const.UC_X86_REG_ZMM26, "zmm26", 64, 0),
+                "ymm26": (unicorn.x86_const.UC_X86_REG_YMM26, "zmm26", 32, 0),
+                "xmm26": (unicorn.x86_const.UC_X86_REG_XMM26, "zmm26", 16, 0),
+                "zmm27": (unicorn.x86_const.UC_X86_REG_ZMM27, "zmm27", 64, 0),
+                "ymm27": (unicorn.x86_const.UC_X86_REG_YMM27, "zmm27", 32, 0),
+                "xmm27": (unicorn.x86_const.UC_X86_REG_XMM27, "zmm27", 16, 0),
+                "zmm28": (unicorn.x86_const.UC_X86_REG_ZMM28, "zmm28", 64, 0),
+                "ymm28": (unicorn.x86_const.UC_X86_REG_YMM28, "zmm28", 32, 0),
+                "xmm28": (unicorn.x86_const.UC_X86_REG_XMM28, "zmm28", 16, 0),
+                "zmm29": (unicorn.x86_const.UC_X86_REG_ZMM29, "zmm29", 64, 0),
+                "ymm29": (unicorn.x86_const.UC_X86_REG_YMM29, "zmm29", 32, 0),
+                "xmm29": (unicorn.x86_const.UC_X86_REG_XMM29, "zmm29", 16, 0),
+                "zmm30": (unicorn.x86_const.UC_X86_REG_ZMM30, "zmm30", 64, 0),
+                "ymm30": (unicorn.x86_const.UC_X86_REG_YMM30, "zmm30", 32, 0),
+                "xmm30": (unicorn.x86_const.UC_X86_REG_XMM30, "zmm30", 16, 0),
+                "zmm31": (unicorn.x86_const.UC_X86_REG_ZMM31, "zmm31", 64, 0),
+                "ymm31": (unicorn.x86_const.UC_X86_REG_YMM31, "zmm31", 32, 0),
+                "xmm31": (unicorn.x86_const.UC_X86_REG_XMM31, "zmm31", 16, 0),
+            }
+        )