smallworld-re 1.0.0__py3-none-any.whl
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- smallworld/__init__.py +35 -0
- smallworld/analyses/__init__.py +14 -0
- smallworld/analyses/analysis.py +88 -0
- smallworld/analyses/code_coverage.py +31 -0
- smallworld/analyses/colorizer.py +682 -0
- smallworld/analyses/colorizer_summary.py +100 -0
- smallworld/analyses/field_detection/__init__.py +14 -0
- smallworld/analyses/field_detection/field_analysis.py +536 -0
- smallworld/analyses/field_detection/guards.py +26 -0
- smallworld/analyses/field_detection/hints.py +133 -0
- smallworld/analyses/field_detection/malloc.py +211 -0
- smallworld/analyses/forced_exec/__init__.py +3 -0
- smallworld/analyses/forced_exec/forced_exec.py +87 -0
- smallworld/analyses/underlays/__init__.py +4 -0
- smallworld/analyses/underlays/basic.py +13 -0
- smallworld/analyses/underlays/underlay.py +31 -0
- smallworld/analyses/unstable/__init__.py +4 -0
- smallworld/analyses/unstable/angr/__init__.py +0 -0
- smallworld/analyses/unstable/angr/base.py +12 -0
- smallworld/analyses/unstable/angr/divergence.py +274 -0
- smallworld/analyses/unstable/angr/model.py +383 -0
- smallworld/analyses/unstable/angr/nwbt.py +63 -0
- smallworld/analyses/unstable/angr/typedefs.py +170 -0
- smallworld/analyses/unstable/angr/utils.py +25 -0
- smallworld/analyses/unstable/angr/visitor.py +315 -0
- smallworld/analyses/unstable/angr_nwbt.py +106 -0
- smallworld/analyses/unstable/code_coverage.py +54 -0
- smallworld/analyses/unstable/code_reachable.py +44 -0
- smallworld/analyses/unstable/control_flow_tracer.py +71 -0
- smallworld/analyses/unstable/pointer_finder.py +90 -0
- smallworld/arch/__init__.py +0 -0
- smallworld/arch/aarch64_arch.py +286 -0
- smallworld/arch/amd64_arch.py +86 -0
- smallworld/arch/i386_arch.py +44 -0
- smallworld/emulators/__init__.py +14 -0
- smallworld/emulators/angr/__init__.py +7 -0
- smallworld/emulators/angr/angr.py +1652 -0
- smallworld/emulators/angr/default.py +15 -0
- smallworld/emulators/angr/exceptions.py +7 -0
- smallworld/emulators/angr/exploration/__init__.py +9 -0
- smallworld/emulators/angr/exploration/bounds.py +27 -0
- smallworld/emulators/angr/exploration/default.py +17 -0
- smallworld/emulators/angr/exploration/terminate.py +22 -0
- smallworld/emulators/angr/factory.py +55 -0
- smallworld/emulators/angr/machdefs/__init__.py +35 -0
- smallworld/emulators/angr/machdefs/aarch64.py +292 -0
- smallworld/emulators/angr/machdefs/amd64.py +192 -0
- smallworld/emulators/angr/machdefs/arm.py +387 -0
- smallworld/emulators/angr/machdefs/i386.py +221 -0
- smallworld/emulators/angr/machdefs/machdef.py +138 -0
- smallworld/emulators/angr/machdefs/mips.py +184 -0
- smallworld/emulators/angr/machdefs/mips64.py +189 -0
- smallworld/emulators/angr/machdefs/ppc.py +101 -0
- smallworld/emulators/angr/machdefs/riscv.py +261 -0
- smallworld/emulators/angr/machdefs/xtensa.py +255 -0
- smallworld/emulators/angr/memory/__init__.py +7 -0
- smallworld/emulators/angr/memory/default.py +10 -0
- smallworld/emulators/angr/memory/fixups.py +43 -0
- smallworld/emulators/angr/memory/memtrack.py +105 -0
- smallworld/emulators/angr/scratch.py +43 -0
- smallworld/emulators/angr/simos.py +53 -0
- smallworld/emulators/angr/utils.py +70 -0
- smallworld/emulators/emulator.py +1013 -0
- smallworld/emulators/hookable.py +252 -0
- smallworld/emulators/panda/__init__.py +5 -0
- smallworld/emulators/panda/machdefs/__init__.py +28 -0
- smallworld/emulators/panda/machdefs/aarch64.py +93 -0
- smallworld/emulators/panda/machdefs/amd64.py +71 -0
- smallworld/emulators/panda/machdefs/arm.py +89 -0
- smallworld/emulators/panda/machdefs/i386.py +36 -0
- smallworld/emulators/panda/machdefs/machdef.py +86 -0
- smallworld/emulators/panda/machdefs/mips.py +94 -0
- smallworld/emulators/panda/machdefs/mips64.py +91 -0
- smallworld/emulators/panda/machdefs/ppc.py +79 -0
- smallworld/emulators/panda/panda.py +575 -0
- smallworld/emulators/unicorn/__init__.py +13 -0
- smallworld/emulators/unicorn/machdefs/__init__.py +28 -0
- smallworld/emulators/unicorn/machdefs/aarch64.py +310 -0
- smallworld/emulators/unicorn/machdefs/amd64.py +326 -0
- smallworld/emulators/unicorn/machdefs/arm.py +321 -0
- smallworld/emulators/unicorn/machdefs/i386.py +137 -0
- smallworld/emulators/unicorn/machdefs/machdef.py +117 -0
- smallworld/emulators/unicorn/machdefs/mips.py +202 -0
- smallworld/emulators/unicorn/unicorn.py +684 -0
- smallworld/exceptions/__init__.py +5 -0
- smallworld/exceptions/exceptions.py +85 -0
- smallworld/exceptions/unstable/__init__.py +1 -0
- smallworld/exceptions/unstable/exceptions.py +25 -0
- smallworld/extern/__init__.py +4 -0
- smallworld/extern/ctypes.py +94 -0
- smallworld/extern/unstable/__init__.py +1 -0
- smallworld/extern/unstable/ghidra.py +129 -0
- smallworld/helpers.py +107 -0
- smallworld/hinting/__init__.py +8 -0
- smallworld/hinting/hinting.py +214 -0
- smallworld/hinting/hints.py +427 -0
- smallworld/hinting/unstable/__init__.py +2 -0
- smallworld/hinting/utils.py +19 -0
- smallworld/instructions/__init__.py +18 -0
- smallworld/instructions/aarch64.py +20 -0
- smallworld/instructions/arm.py +18 -0
- smallworld/instructions/bsid.py +67 -0
- smallworld/instructions/instructions.py +258 -0
- smallworld/instructions/mips.py +21 -0
- smallworld/instructions/x86.py +100 -0
- smallworld/logging.py +90 -0
- smallworld/platforms.py +95 -0
- smallworld/py.typed +0 -0
- smallworld/state/__init__.py +6 -0
- smallworld/state/cpus/__init__.py +32 -0
- smallworld/state/cpus/aarch64.py +563 -0
- smallworld/state/cpus/amd64.py +676 -0
- smallworld/state/cpus/arm.py +630 -0
- smallworld/state/cpus/cpu.py +71 -0
- smallworld/state/cpus/i386.py +239 -0
- smallworld/state/cpus/mips.py +374 -0
- smallworld/state/cpus/mips64.py +372 -0
- smallworld/state/cpus/powerpc.py +229 -0
- smallworld/state/cpus/riscv.py +357 -0
- smallworld/state/cpus/xtensa.py +80 -0
- smallworld/state/memory/__init__.py +7 -0
- smallworld/state/memory/code.py +70 -0
- smallworld/state/memory/elf/__init__.py +3 -0
- smallworld/state/memory/elf/elf.py +564 -0
- smallworld/state/memory/elf/rela/__init__.py +32 -0
- smallworld/state/memory/elf/rela/aarch64.py +27 -0
- smallworld/state/memory/elf/rela/amd64.py +32 -0
- smallworld/state/memory/elf/rela/arm.py +51 -0
- smallworld/state/memory/elf/rela/i386.py +32 -0
- smallworld/state/memory/elf/rela/mips.py +45 -0
- smallworld/state/memory/elf/rela/ppc.py +45 -0
- smallworld/state/memory/elf/rela/rela.py +63 -0
- smallworld/state/memory/elf/rela/riscv64.py +27 -0
- smallworld/state/memory/elf/rela/xtensa.py +15 -0
- smallworld/state/memory/elf/structs.py +55 -0
- smallworld/state/memory/heap.py +85 -0
- smallworld/state/memory/memory.py +181 -0
- smallworld/state/memory/stack/__init__.py +31 -0
- smallworld/state/memory/stack/aarch64.py +22 -0
- smallworld/state/memory/stack/amd64.py +42 -0
- smallworld/state/memory/stack/arm.py +66 -0
- smallworld/state/memory/stack/i386.py +22 -0
- smallworld/state/memory/stack/mips.py +34 -0
- smallworld/state/memory/stack/mips64.py +34 -0
- smallworld/state/memory/stack/ppc.py +34 -0
- smallworld/state/memory/stack/riscv.py +22 -0
- smallworld/state/memory/stack/stack.py +127 -0
- smallworld/state/memory/stack/xtensa.py +34 -0
- smallworld/state/models/__init__.py +6 -0
- smallworld/state/models/mmio.py +186 -0
- smallworld/state/models/model.py +163 -0
- smallworld/state/models/posix.py +455 -0
- smallworld/state/models/x86/__init__.py +2 -0
- smallworld/state/models/x86/microsoftcdecl.py +35 -0
- smallworld/state/models/x86/systemv.py +240 -0
- smallworld/state/state.py +962 -0
- smallworld/state/unstable/__init__.py +0 -0
- smallworld/state/unstable/elf.py +393 -0
- smallworld/state/x86_registers.py +30 -0
- smallworld/utils.py +935 -0
- smallworld_re-1.0.0.dist-info/LICENSE.txt +21 -0
- smallworld_re-1.0.0.dist-info/METADATA +189 -0
- smallworld_re-1.0.0.dist-info/RECORD +166 -0
- smallworld_re-1.0.0.dist-info/WHEEL +5 -0
- smallworld_re-1.0.0.dist-info/entry_points.txt +2 -0
- smallworld_re-1.0.0.dist-info/top_level.txt +1 -0
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import typing
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from ... import platforms, state
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from . import cpu
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class AArch64(cpu.CPU):
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"""Auto-generated CPU state for aarch64:v8a:little
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Generated from Pcode language AARCH64:LE:64:v8A, and Unicorn package
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unicorn.arm64_const.
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"""
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platform = platforms.Platform(
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platforms.Architecture.AARCH64, platforms.Byteorder.LITTLE
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)
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def get_general_purpose_registers(self) -> typing.List[str]:
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# Special registers:
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# x29: frame pointer
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# x30: link register
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# x31: stack pointer or zero, depending on instruction
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return [f"x{i}" for i in range(0, 29)]
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def __init__(self):
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super().__init__()
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# *** General Purpose Registers ***
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self.x0 = state.Register("x0", 8)
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self.add(self.x0)
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self.w0 = state.RegisterAlias("w0", self.x0, 4, 0)
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self.add(self.w0)
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self.x1 = state.Register("x1", 8)
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self.add(self.x1)
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self.w1 = state.RegisterAlias("w1", self.x1, 4, 0)
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self.add(self.w1)
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self.x2 = state.Register("x2", 8)
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self.add(self.x2)
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self.w2 = state.RegisterAlias("w2", self.x2, 4, 0)
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self.add(self.w2)
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self.x3 = state.Register("x3", 8)
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self.add(self.x3)
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self.w3 = state.RegisterAlias("w3", self.x3, 4, 0)
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self.add(self.w3)
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self.x4 = state.Register("x4", 8)
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self.add(self.x4)
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self.w4 = state.RegisterAlias("w4", self.x4, 4, 0)
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self.add(self.w4)
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self.x5 = state.Register("x5", 8)
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self.add(self.x5)
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self.w5 = state.RegisterAlias("w5", self.x5, 4, 0)
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self.add(self.w5)
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self.x6 = state.Register("x6", 8)
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self.add(self.x6)
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self.w6 = state.RegisterAlias("w6", self.x6, 4, 0)
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self.add(self.w6)
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self.x7 = state.Register("x7", 8)
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self.add(self.x7)
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self.w7 = state.RegisterAlias("w7", self.x7, 4, 0)
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self.add(self.w7)
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self.x8 = state.Register("x8", 8)
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self.add(self.x8)
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self.w8 = state.RegisterAlias("w8", self.x8, 4, 0)
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self.add(self.w8)
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self.x9 = state.Register("x9", 8)
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self.add(self.x9)
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self.w9 = state.RegisterAlias("w9", self.x9, 4, 0)
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self.add(self.w9)
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self.x10 = state.Register("x10", 8)
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self.add(self.x10)
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self.w10 = state.RegisterAlias("w10", self.x10, 4, 0)
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self.add(self.w10)
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self.x11 = state.Register("x11", 8)
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self.add(self.x11)
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self.w11 = state.RegisterAlias("w11", self.x10, 4, 0)
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self.add(self.w11)
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self.x12 = state.Register("x12", 8)
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self.add(self.x12)
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self.w12 = state.RegisterAlias("w12", self.x10, 4, 0)
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self.add(self.w12)
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self.x13 = state.Register("x13", 8)
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self.add(self.x13)
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self.w13 = state.RegisterAlias("w13", self.x13, 4, 0)
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self.add(self.w13)
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self.x14 = state.Register("x14", 8)
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self.add(self.x14)
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self.w14 = state.RegisterAlias("w14", self.x14, 4, 0)
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self.add(self.w14)
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self.x15 = state.Register("x15", 8)
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self.add(self.x15)
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self.w15 = state.RegisterAlias("w15", self.x15, 4, 0)
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self.add(self.w15)
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self.x16 = state.Register("x16", 8)
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self.add(self.x16)
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self.w16 = state.RegisterAlias("w16", self.x16, 4, 0)
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self.add(self.w16)
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self.x17 = state.Register("x17", 8)
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self.add(self.x17)
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self.w17 = state.RegisterAlias("w17", self.x17, 4, 0)
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self.add(self.w17)
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self.x18 = state.Register("x18", 8)
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self.add(self.x18)
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self.w18 = state.RegisterAlias("w18", self.x18, 4, 0)
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self.add(self.w18)
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self.x19 = state.Register("x19", 8)
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self.add(self.x19)
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self.w19 = state.RegisterAlias("w19", self.x19, 4, 0)
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self.add(self.w19)
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self.x20 = state.Register("x20", 8)
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self.add(self.x20)
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self.w20 = state.RegisterAlias("w20", self.x20, 4, 0)
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self.add(self.w20)
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self.x21 = state.Register("x21", 8)
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self.add(self.x21)
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self.w21 = state.RegisterAlias("w21", self.x20, 4, 0)
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self.add(self.w21)
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self.x22 = state.Register("x22", 8)
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self.add(self.x22)
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self.w22 = state.RegisterAlias("w22", self.x20, 4, 0)
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self.add(self.w22)
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self.x23 = state.Register("x23", 8)
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self.add(self.x23)
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self.w23 = state.RegisterAlias("w23", self.x23, 4, 0)
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self.add(self.w23)
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self.x24 = state.Register("x24", 8)
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self.add(self.x24)
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self.w24 = state.RegisterAlias("w24", self.x24, 4, 0)
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self.add(self.w24)
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self.x25 = state.Register("x25", 8)
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self.add(self.x25)
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self.w25 = state.RegisterAlias("w25", self.x25, 4, 0)
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self.add(self.w25)
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self.x26 = state.Register("x26", 8)
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self.add(self.x26)
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self.w26 = state.RegisterAlias("w26", self.x26, 4, 0)
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self.add(self.w26)
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self.x27 = state.Register("x27", 8)
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self.add(self.x27)
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self.w27 = state.RegisterAlias("w27", self.x27, 4, 0)
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self.add(self.w27)
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self.x28 = state.Register("x28", 8)
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self.add(self.x28)
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self.w28 = state.RegisterAlias("w28", self.x28, 4, 0)
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self.add(self.w28)
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self.x29 = state.Register("x29", 8)
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self.add(self.x29)
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self.w29 = state.RegisterAlias("w29", self.x29, 4, 0)
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self.add(self.w29)
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self.x30 = state.Register("x30", 8)
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self.add(self.x30)
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self.w30 = state.RegisterAlias("w30", self.x30, 4, 0)
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self.add(self.w30)
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# *** Program Counter ***
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self.pc = state.Register("pc", 8)
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self.add(self.pc)
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# *** Stack Pointer ***
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self.sp = state.Register("sp", 8)
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self.add(self.sp)
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self.wsp = state.RegisterAlias("wsp", self.sp, 4, 0)
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self.add(self.wsp)
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# *** Frame Pointer ***
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self.fp = state.RegisterAlias("fp", self.x29, 8, 0)
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self.add(self.fp)
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# *** Link Register ***
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self.lr = state.RegisterAlias("lr", self.x30, 8, 0)
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self.add(self.lr)
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# *** Zero Register ***
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self.xzr = state.FixedRegister("xzr", 8, 0)
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self.add(self.xzr)
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self.wzr = state.RegisterAlias("wzr", self.xzr, 4, 0)
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self.add(self.wzr)
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# *** System Control Registers ***
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# NOTE: "_elX" indicates that only exception level X or greater can access this register.
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# NOTE: This list is far from complete; it only covers what Unicorn supports
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# Condition Code Register
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self.fpcr = state.Register("fpcr", 8)
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self.add(self.fpcr)
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# Floating Point Status Register
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self.fpsr = state.Register("fpsr", 8)
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self.add(self.fpsr)
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# Banked stack pointers for exception handlers
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self.sp_el0 = state.Register("sp_el0", 8)
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182
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+
self.add(self.sp_el0)
|
183
|
+
self.sp_el1 = state.Register("sp_el1", 8)
|
184
|
+
self.add(self.sp_el1)
|
185
|
+
self.sp_el2 = state.Register("sp_el2", 8)
|
186
|
+
self.add(self.sp_el2)
|
187
|
+
self.sp_el3 = state.Register("sp_el3", 8)
|
188
|
+
self.add(self.sp_el3)
|
189
|
+
# Banked link registers for exception handlers
|
190
|
+
# NOTE: Unicorn thinks there's an elr_el0; according to docs, it doesn't exist
|
191
|
+
self.elr_el1 = state.Register("elr_el1", 8)
|
192
|
+
self.add(self.elr_el1)
|
193
|
+
self.elr_el2 = state.Register("elr_el2", 8)
|
194
|
+
self.add(self.elr_el2)
|
195
|
+
self.elr_el3 = state.Register("elr_el3", 8)
|
196
|
+
self.add(self.elr_el3)
|
197
|
+
# Banked exception syndrome registers for exception handlers
|
198
|
+
# NOTE: Unicorn thinks there's a far_el0; according to docs, it doesn't exist
|
199
|
+
self.far_el1 = state.Register("far_el1", 8)
|
200
|
+
self.add(self.far_el1)
|
201
|
+
self.far_el2 = state.Register("far_el2", 8)
|
202
|
+
self.add(self.far_el2)
|
203
|
+
self.far_el3 = state.Register("far_el3", 8)
|
204
|
+
self.add(self.far_el3)
|
205
|
+
# Banked vector base address registers for exception handlers
|
206
|
+
# NOTE: vbar_el0 and vbar_el1 are aliases for each other.
|
207
|
+
# Since vbar_el0 doesn't exist in angr, vbar_el1 has to be the "real" copy.
|
208
|
+
self.vbar_el1 = state.Register("vbar_el1", 8)
|
209
|
+
self.add(self.vbar_el1)
|
210
|
+
self.vbar_el0 = state.RegisterAlias("vbar_el0", self.vbar_el1, 8, 0)
|
211
|
+
self.add(self.vbar_el0)
|
212
|
+
self.vbar_el2 = state.Register("vbar_el2", 8)
|
213
|
+
self.add(self.vbar_el2)
|
214
|
+
self.vbar_el3 = state.Register("vbar_el3", 8)
|
215
|
+
self.add(self.vbar_el3)
|
216
|
+
# Coprocessor access control register
|
217
|
+
self.cpacr_el1 = state.Register("cpacr_el1", 8)
|
218
|
+
self.add(self.cpacr_el1)
|
219
|
+
# Memory Attribute Indirection Register
|
220
|
+
self.mair_el1 = state.Register("mair_el1", 8)
|
221
|
+
self.add(self.mair_el1)
|
222
|
+
# Physical Address Register
|
223
|
+
self.par_el1 = state.Register("par_el1", 8)
|
224
|
+
self.add(self.par_el1)
|
225
|
+
# Translation Table Zero Base Register
|
226
|
+
self.ttbr0_el1 = state.Register("ttbr0_el1", 8)
|
227
|
+
self.add(self.ttbr0_el1)
|
228
|
+
# Translation Table One Base Register
|
229
|
+
self.ttbr1_el1 = state.Register("ttbr1_el1", 8)
|
230
|
+
self.add(self.ttbr1_el1)
|
231
|
+
# Thread ID Register
|
232
|
+
# NOTE: According to docs, there should be an el2 and el3 copy, too.
|
233
|
+
self.tpidr_el0 = state.Register("tpidr_el0", 8)
|
234
|
+
self.add(self.tpidr_el0)
|
235
|
+
self.tpidr_el1 = state.Register("tpidr_el1", 8)
|
236
|
+
self.add(self.tpidr_el1)
|
237
|
+
# Userspace-visible Thread ID register
|
238
|
+
self.tpidrro_el0 = state.Register("tpidrro_el0", 8)
|
239
|
+
self.add(self.tpidrro_el0)
|
240
|
+
# *** Floating Point Registers ***
|
241
|
+
# Scalar Floating Point Registers
|
242
|
+
self.q0 = state.Register("q0", 16)
|
243
|
+
self.add(self.q0)
|
244
|
+
self.d0 = state.RegisterAlias("d0", self.q0, 8, 0)
|
245
|
+
self.add(self.d0)
|
246
|
+
self.s0 = state.RegisterAlias("s0", self.q0, 4, 0)
|
247
|
+
self.add(self.s0)
|
248
|
+
self.h0 = state.RegisterAlias("h0", self.q0, 2, 0)
|
249
|
+
self.add(self.h0)
|
250
|
+
self.b0 = state.RegisterAlias("b0", self.q0, 1, 0)
|
251
|
+
self.add(self.b0)
|
252
|
+
self.q1 = state.Register("q1", 16)
|
253
|
+
self.add(self.q1)
|
254
|
+
self.d1 = state.RegisterAlias("d1", self.q1, 8, 0)
|
255
|
+
self.add(self.d1)
|
256
|
+
self.s1 = state.RegisterAlias("s1", self.q1, 4, 0)
|
257
|
+
self.add(self.s1)
|
258
|
+
self.h1 = state.RegisterAlias("h1", self.q1, 2, 0)
|
259
|
+
self.add(self.h1)
|
260
|
+
self.b1 = state.RegisterAlias("b1", self.q1, 1, 0)
|
261
|
+
self.add(self.b1)
|
262
|
+
self.q2 = state.Register("q2", 16)
|
263
|
+
self.add(self.q2)
|
264
|
+
self.d2 = state.RegisterAlias("d2", self.q2, 8, 0)
|
265
|
+
self.add(self.d2)
|
266
|
+
self.s2 = state.RegisterAlias("s2", self.q2, 4, 0)
|
267
|
+
self.add(self.s2)
|
268
|
+
self.h2 = state.RegisterAlias("h2", self.q2, 2, 0)
|
269
|
+
self.add(self.h2)
|
270
|
+
self.b2 = state.RegisterAlias("b2", self.q2, 1, 0)
|
271
|
+
self.add(self.b2)
|
272
|
+
self.q3 = state.Register("q3", 16)
|
273
|
+
self.add(self.q3)
|
274
|
+
self.d3 = state.RegisterAlias("d3", self.q3, 8, 0)
|
275
|
+
self.add(self.d3)
|
276
|
+
self.s3 = state.RegisterAlias("s3", self.q3, 4, 0)
|
277
|
+
self.add(self.s3)
|
278
|
+
self.h3 = state.RegisterAlias("h3", self.q3, 2, 0)
|
279
|
+
self.add(self.h3)
|
280
|
+
self.b3 = state.RegisterAlias("b3", self.q3, 1, 0)
|
281
|
+
self.add(self.b3)
|
282
|
+
self.q4 = state.Register("q4", 16)
|
283
|
+
self.add(self.q4)
|
284
|
+
self.d4 = state.RegisterAlias("d4", self.q4, 8, 0)
|
285
|
+
self.add(self.d4)
|
286
|
+
self.s4 = state.RegisterAlias("s4", self.q4, 4, 0)
|
287
|
+
self.add(self.s4)
|
288
|
+
self.h4 = state.RegisterAlias("h4", self.q4, 2, 0)
|
289
|
+
self.add(self.h4)
|
290
|
+
self.b4 = state.RegisterAlias("b4", self.q4, 1, 0)
|
291
|
+
self.add(self.b4)
|
292
|
+
self.q5 = state.Register("q5", 16)
|
293
|
+
self.add(self.q5)
|
294
|
+
self.d5 = state.RegisterAlias("d5", self.q5, 8, 0)
|
295
|
+
self.add(self.d5)
|
296
|
+
self.s5 = state.RegisterAlias("s5", self.q5, 4, 0)
|
297
|
+
self.add(self.s5)
|
298
|
+
self.h5 = state.RegisterAlias("h5", self.q5, 2, 0)
|
299
|
+
self.add(self.h5)
|
300
|
+
self.b5 = state.RegisterAlias("b5", self.q5, 1, 0)
|
301
|
+
self.add(self.b5)
|
302
|
+
self.q6 = state.Register("q6", 16)
|
303
|
+
self.add(self.q6)
|
304
|
+
self.d6 = state.RegisterAlias("d6", self.q6, 8, 0)
|
305
|
+
self.add(self.d6)
|
306
|
+
self.s6 = state.RegisterAlias("s6", self.q6, 4, 0)
|
307
|
+
self.add(self.s6)
|
308
|
+
self.h6 = state.RegisterAlias("h6", self.q6, 2, 0)
|
309
|
+
self.add(self.h6)
|
310
|
+
self.b6 = state.RegisterAlias("b6", self.q6, 1, 0)
|
311
|
+
self.add(self.b6)
|
312
|
+
self.q7 = state.Register("q7", 16)
|
313
|
+
self.add(self.q7)
|
314
|
+
self.d7 = state.RegisterAlias("d7", self.q7, 8, 0)
|
315
|
+
self.add(self.d7)
|
316
|
+
self.s7 = state.RegisterAlias("s7", self.q7, 4, 0)
|
317
|
+
self.add(self.s7)
|
318
|
+
self.h7 = state.RegisterAlias("h7", self.q7, 2, 0)
|
319
|
+
self.add(self.h7)
|
320
|
+
self.b7 = state.RegisterAlias("b7", self.q7, 1, 0)
|
321
|
+
self.add(self.b7)
|
322
|
+
self.q8 = state.Register("q8", 16)
|
323
|
+
self.add(self.q8)
|
324
|
+
self.d8 = state.RegisterAlias("d8", self.q8, 8, 0)
|
325
|
+
self.add(self.d8)
|
326
|
+
self.s8 = state.RegisterAlias("s8", self.q8, 4, 0)
|
327
|
+
self.add(self.s8)
|
328
|
+
self.h8 = state.RegisterAlias("h8", self.q8, 2, 0)
|
329
|
+
self.add(self.h8)
|
330
|
+
self.b8 = state.RegisterAlias("b8", self.q8, 1, 0)
|
331
|
+
self.add(self.b8)
|
332
|
+
self.q9 = state.Register("q9", 16)
|
333
|
+
self.add(self.q9)
|
334
|
+
self.d9 = state.RegisterAlias("d9", self.q9, 8, 0)
|
335
|
+
self.add(self.d9)
|
336
|
+
self.s9 = state.RegisterAlias("s9", self.q9, 4, 0)
|
337
|
+
self.add(self.s9)
|
338
|
+
self.h9 = state.RegisterAlias("h9", self.q9, 2, 0)
|
339
|
+
self.add(self.h9)
|
340
|
+
self.b9 = state.RegisterAlias("b9", self.q9, 1, 0)
|
341
|
+
self.add(self.b9)
|
342
|
+
self.q10 = state.Register("q10", 16)
|
343
|
+
self.add(self.q10)
|
344
|
+
self.d10 = state.RegisterAlias("d10", self.q10, 8, 0)
|
345
|
+
self.add(self.d10)
|
346
|
+
self.s10 = state.RegisterAlias("s10", self.q10, 4, 0)
|
347
|
+
self.add(self.s10)
|
348
|
+
self.h10 = state.RegisterAlias("h10", self.q10, 2, 0)
|
349
|
+
self.add(self.h10)
|
350
|
+
self.b10 = state.RegisterAlias("b10", self.q10, 1, 0)
|
351
|
+
self.add(self.b10)
|
352
|
+
self.q11 = state.Register("q11", 16)
|
353
|
+
self.add(self.q11)
|
354
|
+
self.d11 = state.RegisterAlias("d11", self.q11, 8, 0)
|
355
|
+
self.add(self.d11)
|
356
|
+
self.s11 = state.RegisterAlias("s11", self.q11, 4, 0)
|
357
|
+
self.add(self.s11)
|
358
|
+
self.h11 = state.RegisterAlias("h11", self.q11, 2, 0)
|
359
|
+
self.add(self.h11)
|
360
|
+
self.b11 = state.RegisterAlias("b11", self.q11, 1, 0)
|
361
|
+
self.add(self.b11)
|
362
|
+
self.q12 = state.Register("q12", 16)
|
363
|
+
self.add(self.q12)
|
364
|
+
self.d12 = state.RegisterAlias("d12", self.q12, 8, 0)
|
365
|
+
self.add(self.d12)
|
366
|
+
self.s12 = state.RegisterAlias("s12", self.q12, 4, 0)
|
367
|
+
self.add(self.s12)
|
368
|
+
self.h12 = state.RegisterAlias("h12", self.q12, 2, 0)
|
369
|
+
self.add(self.h12)
|
370
|
+
self.b12 = state.RegisterAlias("b12", self.q12, 1, 0)
|
371
|
+
self.add(self.b12)
|
372
|
+
self.q13 = state.Register("q13", 16)
|
373
|
+
self.add(self.q13)
|
374
|
+
self.d13 = state.RegisterAlias("d13", self.q13, 8, 0)
|
375
|
+
self.add(self.d13)
|
376
|
+
self.s13 = state.RegisterAlias("s13", self.q13, 4, 0)
|
377
|
+
self.add(self.s13)
|
378
|
+
self.h13 = state.RegisterAlias("h13", self.q13, 2, 0)
|
379
|
+
self.add(self.h13)
|
380
|
+
self.b13 = state.RegisterAlias("b13", self.q13, 1, 0)
|
381
|
+
self.add(self.b13)
|
382
|
+
self.q14 = state.Register("q14", 16)
|
383
|
+
self.add(self.q14)
|
384
|
+
self.d14 = state.RegisterAlias("d14", self.q14, 8, 0)
|
385
|
+
self.add(self.d14)
|
386
|
+
self.s14 = state.RegisterAlias("s14", self.q14, 4, 0)
|
387
|
+
self.add(self.s14)
|
388
|
+
self.h14 = state.RegisterAlias("h14", self.q14, 2, 0)
|
389
|
+
self.add(self.h14)
|
390
|
+
self.b14 = state.RegisterAlias("b14", self.q14, 1, 0)
|
391
|
+
self.add(self.b14)
|
392
|
+
self.q15 = state.Register("q15", 16)
|
393
|
+
self.add(self.q15)
|
394
|
+
self.d15 = state.RegisterAlias("d15", self.q15, 8, 0)
|
395
|
+
self.add(self.d15)
|
396
|
+
self.s15 = state.RegisterAlias("s15", self.q15, 4, 0)
|
397
|
+
self.add(self.s15)
|
398
|
+
self.h15 = state.RegisterAlias("h15", self.q15, 2, 0)
|
399
|
+
self.add(self.h15)
|
400
|
+
self.b15 = state.RegisterAlias("b15", self.q15, 1, 0)
|
401
|
+
self.add(self.b15)
|
402
|
+
self.q16 = state.Register("q16", 16)
|
403
|
+
self.add(self.q16)
|
404
|
+
self.d16 = state.RegisterAlias("d16", self.q16, 8, 0)
|
405
|
+
self.add(self.d16)
|
406
|
+
self.s16 = state.RegisterAlias("s16", self.q16, 4, 0)
|
407
|
+
self.add(self.s16)
|
408
|
+
self.h16 = state.RegisterAlias("h16", self.q16, 2, 0)
|
409
|
+
self.add(self.h16)
|
410
|
+
self.b16 = state.RegisterAlias("b16", self.q16, 1, 0)
|
411
|
+
self.add(self.b16)
|
412
|
+
self.q17 = state.Register("q17", 16)
|
413
|
+
self.add(self.q17)
|
414
|
+
self.d17 = state.RegisterAlias("d17", self.q17, 8, 0)
|
415
|
+
self.add(self.d17)
|
416
|
+
self.s17 = state.RegisterAlias("s17", self.q17, 4, 0)
|
417
|
+
self.add(self.s17)
|
418
|
+
self.h17 = state.RegisterAlias("h17", self.q17, 2, 0)
|
419
|
+
self.add(self.h17)
|
420
|
+
self.b17 = state.RegisterAlias("b17", self.q17, 1, 0)
|
421
|
+
self.add(self.b17)
|
422
|
+
self.q18 = state.Register("q18", 16)
|
423
|
+
self.add(self.q18)
|
424
|
+
self.d18 = state.RegisterAlias("d18", self.q18, 8, 0)
|
425
|
+
self.add(self.d18)
|
426
|
+
self.s18 = state.RegisterAlias("s18", self.q18, 4, 0)
|
427
|
+
self.add(self.s18)
|
428
|
+
self.h18 = state.RegisterAlias("h18", self.q18, 2, 0)
|
429
|
+
self.add(self.h18)
|
430
|
+
self.b18 = state.RegisterAlias("b18", self.q18, 1, 0)
|
431
|
+
self.add(self.b18)
|
432
|
+
self.q19 = state.Register("q19", 16)
|
433
|
+
self.add(self.q19)
|
434
|
+
self.d19 = state.RegisterAlias("d19", self.q19, 8, 0)
|
435
|
+
self.add(self.d19)
|
436
|
+
self.s19 = state.RegisterAlias("s19", self.q19, 4, 0)
|
437
|
+
self.add(self.s19)
|
438
|
+
self.h19 = state.RegisterAlias("h19", self.q19, 2, 0)
|
439
|
+
self.add(self.h19)
|
440
|
+
self.b19 = state.RegisterAlias("b19", self.q19, 1, 0)
|
441
|
+
self.add(self.b19)
|
442
|
+
self.q20 = state.Register("q20", 16)
|
443
|
+
self.add(self.q20)
|
444
|
+
self.d20 = state.RegisterAlias("d20", self.q20, 8, 0)
|
445
|
+
self.add(self.d20)
|
446
|
+
self.s20 = state.RegisterAlias("s20", self.q20, 4, 0)
|
447
|
+
self.add(self.s20)
|
448
|
+
self.h20 = state.RegisterAlias("h20", self.q20, 2, 0)
|
449
|
+
self.add(self.h20)
|
450
|
+
self.b20 = state.RegisterAlias("b20", self.q20, 1, 0)
|
451
|
+
self.add(self.b20)
|
452
|
+
self.q21 = state.Register("q21", 16)
|
453
|
+
self.add(self.q21)
|
454
|
+
self.d21 = state.RegisterAlias("d21", self.q21, 8, 0)
|
455
|
+
self.add(self.d21)
|
456
|
+
self.s21 = state.RegisterAlias("s21", self.q21, 4, 0)
|
457
|
+
self.add(self.s21)
|
458
|
+
self.h21 = state.RegisterAlias("h21", self.q21, 2, 0)
|
459
|
+
self.add(self.h21)
|
460
|
+
self.b21 = state.RegisterAlias("b21", self.q21, 1, 0)
|
461
|
+
self.add(self.b21)
|
462
|
+
self.q22 = state.Register("q22", 16)
|
463
|
+
self.add(self.q22)
|
464
|
+
self.d22 = state.RegisterAlias("d22", self.q22, 8, 0)
|
465
|
+
self.add(self.d22)
|
466
|
+
self.s22 = state.RegisterAlias("s22", self.q22, 4, 0)
|
467
|
+
self.add(self.s22)
|
468
|
+
self.h22 = state.RegisterAlias("h22", self.q22, 2, 0)
|
469
|
+
self.add(self.h22)
|
470
|
+
self.b22 = state.RegisterAlias("b22", self.q22, 1, 0)
|
471
|
+
self.add(self.b22)
|
472
|
+
self.q23 = state.Register("q23", 16)
|
473
|
+
self.add(self.q23)
|
474
|
+
self.d23 = state.RegisterAlias("d23", self.q23, 8, 0)
|
475
|
+
self.add(self.d23)
|
476
|
+
self.s23 = state.RegisterAlias("s23", self.q23, 4, 0)
|
477
|
+
self.add(self.s23)
|
478
|
+
self.h23 = state.RegisterAlias("h23", self.q23, 2, 0)
|
479
|
+
self.add(self.h23)
|
480
|
+
self.b23 = state.RegisterAlias("b23", self.q23, 1, 0)
|
481
|
+
self.add(self.b23)
|
482
|
+
self.q24 = state.Register("q24", 16)
|
483
|
+
self.add(self.q24)
|
484
|
+
self.d24 = state.RegisterAlias("d24", self.q24, 8, 0)
|
485
|
+
self.add(self.d24)
|
486
|
+
self.s24 = state.RegisterAlias("s24", self.q24, 4, 0)
|
487
|
+
self.add(self.s24)
|
488
|
+
self.h24 = state.RegisterAlias("h24", self.q24, 2, 0)
|
489
|
+
self.add(self.h24)
|
490
|
+
self.b24 = state.RegisterAlias("b24", self.q24, 1, 0)
|
491
|
+
self.add(self.b24)
|
492
|
+
self.q25 = state.Register("q25", 16)
|
493
|
+
self.add(self.q25)
|
494
|
+
self.d25 = state.RegisterAlias("d25", self.q25, 8, 0)
|
495
|
+
self.add(self.d25)
|
496
|
+
self.s25 = state.RegisterAlias("s25", self.q25, 4, 0)
|
497
|
+
self.add(self.s25)
|
498
|
+
self.h25 = state.RegisterAlias("h25", self.q25, 2, 0)
|
499
|
+
self.add(self.h25)
|
500
|
+
self.b25 = state.RegisterAlias("b25", self.q25, 1, 0)
|
501
|
+
self.add(self.b25)
|
502
|
+
self.q26 = state.Register("q26", 16)
|
503
|
+
self.add(self.q26)
|
504
|
+
self.d26 = state.RegisterAlias("d26", self.q26, 8, 0)
|
505
|
+
self.add(self.d26)
|
506
|
+
self.s26 = state.RegisterAlias("s26", self.q26, 4, 0)
|
507
|
+
self.add(self.s26)
|
508
|
+
self.h26 = state.RegisterAlias("h26", self.q26, 2, 0)
|
509
|
+
self.add(self.h26)
|
510
|
+
self.b26 = state.RegisterAlias("b26", self.q26, 1, 0)
|
511
|
+
self.add(self.b26)
|
512
|
+
self.q27 = state.Register("q27", 16)
|
513
|
+
self.add(self.q27)
|
514
|
+
self.d27 = state.RegisterAlias("d27", self.q27, 8, 0)
|
515
|
+
self.add(self.d27)
|
516
|
+
self.s27 = state.RegisterAlias("s27", self.q27, 4, 0)
|
517
|
+
self.add(self.s27)
|
518
|
+
self.h27 = state.RegisterAlias("h27", self.q27, 2, 0)
|
519
|
+
self.add(self.h27)
|
520
|
+
self.b27 = state.RegisterAlias("b27", self.q27, 1, 0)
|
521
|
+
self.add(self.b27)
|
522
|
+
self.q28 = state.Register("q28", 16)
|
523
|
+
self.add(self.q28)
|
524
|
+
self.d28 = state.RegisterAlias("d28", self.q28, 8, 0)
|
525
|
+
self.add(self.d28)
|
526
|
+
self.s28 = state.RegisterAlias("s28", self.q28, 4, 0)
|
527
|
+
self.add(self.s28)
|
528
|
+
self.h28 = state.RegisterAlias("h28", self.q28, 2, 0)
|
529
|
+
self.add(self.h28)
|
530
|
+
self.b28 = state.RegisterAlias("b28", self.q28, 1, 0)
|
531
|
+
self.add(self.b28)
|
532
|
+
self.q29 = state.Register("q29", 16)
|
533
|
+
self.add(self.q29)
|
534
|
+
self.d29 = state.RegisterAlias("d29", self.q29, 8, 0)
|
535
|
+
self.add(self.d29)
|
536
|
+
self.s29 = state.RegisterAlias("s29", self.q29, 4, 0)
|
537
|
+
self.add(self.s29)
|
538
|
+
self.h29 = state.RegisterAlias("h29", self.q29, 2, 0)
|
539
|
+
self.add(self.h29)
|
540
|
+
self.b29 = state.RegisterAlias("b29", self.q29, 1, 0)
|
541
|
+
self.add(self.b29)
|
542
|
+
self.q30 = state.Register("q30", 16)
|
543
|
+
self.add(self.q30)
|
544
|
+
self.d30 = state.RegisterAlias("d30", self.q30, 8, 0)
|
545
|
+
self.add(self.d30)
|
546
|
+
self.s30 = state.RegisterAlias("s30", self.q30, 4, 0)
|
547
|
+
self.add(self.s30)
|
548
|
+
self.h30 = state.RegisterAlias("h30", self.q30, 2, 0)
|
549
|
+
self.add(self.h30)
|
550
|
+
self.b30 = state.RegisterAlias("b30", self.q30, 1, 0)
|
551
|
+
self.add(self.b30)
|
552
|
+
self.q31 = state.Register("q31", 16)
|
553
|
+
self.add(self.q31)
|
554
|
+
self.d31 = state.RegisterAlias("d31", self.q31, 8, 0)
|
555
|
+
self.add(self.d31)
|
556
|
+
self.s31 = state.RegisterAlias("s31", self.q31, 4, 0)
|
557
|
+
self.add(self.s31)
|
558
|
+
self.h31 = state.RegisterAlias("h31", self.q31, 2, 0)
|
559
|
+
self.add(self.h31)
|
560
|
+
self.b31 = state.RegisterAlias("b31", self.q31, 1, 0)
|
561
|
+
self.add(self.b31)
|
562
|
+
# Vector registers
|
563
|
+
# TODO: Figure out how to model these
|