smallworld-re 1.0.0__py3-none-any.whl

smallworld/emulators/panda/machdefs/mips.py

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+import capstone
+
+from ....platforms import Architecture, Byteorder
+from .machdef import PandaMachineDef
+
+
+class MIPSMachineDef(PandaMachineDef):
+    arch = Architecture.MIPS32
+    cs_arch = capstone.CS_ARCH_MIPS
+    cpu = "M14K"
+
+    # I'm going to define all the ones we are making possible as of now
+    # I need to submit a PR to change to X86 32 bit and to includ eflags
+    def __init__(self):
+        self._registers = {
+            "at": "at",
+            "1": "at",
+            "v0": "v0",
+            "2": "v0",
+            "v1": "v1",
+            "3": "v1",
+            "a0": "a0",
+            "4": "a0",
+            "a1": "a1",
+            "5": "a1",
+            "a2": "a2",
+            "6": "a2",
+            "a3": "a3",
+            "7": "a3",
+            "t0": "t0",
+            "8": "t0",
+            "t1": "t1",
+            "9": "t1",
+            "t2": "t2",
+            "10": "t2",
+            "t3": "t3",
+            "11": "t3",
+            "t4": "t4",
+            "12": "t4",
+            "t5": "t5",
+            "13": "t5",
+            "t6": "t6",
+            "14": "t6",
+            "t7": "t7",
+            "15": "t7",
+            "t8": "t8",
+            "24": "t8",
+            "t9": "t9",
+            "25": "t9",
+            "s0": "s0",
+            "16": "s0",
+            "s1": "s1",
+            "17": "s1",
+            "s2": "s2",
+            "18": "s2",
+            "s3": "s3",
+            "19": "s3",
+            "s4": "s4",
+            "20": "s4",
+            "s5": "s5",
+            "21": "s5",
+            "s6": "s6",
+            "22": "s6",
+            "s7": "s7",
+            "23": "s7",
+            "s8": "fp",
+            "fp": "fp",
+            "30": "fp",
+            "k0": "k0",
+            "26": "k0",
+            "k1": "k1",
+            "27": "k1",
+            "zero": "zero",
+            "0": "zero",
+            "gp": "gp",
+            "28": "gp",
+            "sp": "sp",
+            "29": "sp",
+            "ra": "ra",
+            "31": "ra",
+            "pc": "pc",
+        }
+
+
+class MIPSELMachineDef(MIPSMachineDef):
+    panda_arch = "mipsel"
+    byteorder = Byteorder.LITTLE
+    cs_mode = capstone.CS_MODE_MIPS32 | capstone.CS_MODE_LITTLE_ENDIAN
+
+
+class MIPSBEMachineDef(MIPSMachineDef):
+    panda_arch = "mips"
+    byteorder = Byteorder.BIG
+    cs_mode = capstone.CS_MODE_MIPS32 | capstone.CS_MODE_BIG_ENDIAN

smallworld/emulators/panda/machdefs/mips64.py

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+import capstone
+
+from ....platforms import Architecture, Byteorder
+from .machdef import PandaMachineDef
+
+
+class MIPS64MachineDef(PandaMachineDef):
+    arch = Architecture.MIPS64
+    cs_arch = capstone.CS_ARCH_MIPS
+
+    # We don't need this
+    panda_arch = "mips64"
+
+    # I'm going to define all the ones we are making possible as of now
+    # I need to submit a PR to change to X86 32 bit and to includ eflags
+    def __init__(self):
+        self._registers = {
+            "at": "at",
+            "1": "at",
+            "v0": "v0",
+            "2": "v0",
+            "v1": "v1",
+            "3": "v1",
+            "a0": "a0",
+            "4": "a0",
+            "a1": "a1",
+            "5": "a1",
+            "a2": "a2",
+            "6": "a2",
+            "a3": "a3",
+            "7": "a3",
+            "a4": "a4",
+            "8": "a4",
+            "a5": "a5",
+            "9": "a5",
+            "a6": "a6",
+            "10": "a6",
+            "a7": "a7",
+            "11": "a7",
+            "t0": "t0",
+            "12": "t0",
+            "t1": "t1",
+            "13": "t1",
+            "t2": "t2",
+            "14": "t2",
+            "t3": "t3",
+            "15": "t3",
+            "t8": "t8",
+            "24": "t8",
+            "t9": "t9",
+            "25": "t9",
+            "s0": "s0",
+            "16": "s0",
+            "s1": "s1",
+            "17": "s1",
+            "s2": "s2",
+            "18": "s2",
+            "s3": "s3",
+            "19": "s3",
+            "s4": "s4",
+            "20": "s4",
+            "s5": "s5",
+            "21": "s5",
+            "s6": "s6",
+            "22": "s6",
+            "s7": "s7",
+            "23": "s7",
+            "s8": "s8",
+            "fp": "s8",
+            "30": "s8",
+            "k0": "k0",
+            "26": "k0",
+            "k1": "k1",
+            "27": "k1",
+            "zero": "zero",
+            "0": "zero",
+            "gp": "gp",
+            "28": "gp",
+            "sp": "sp",
+            "29": "sp",
+            "ra": "ra",
+            "31": "ra",
+            "pc": "pc",
+        }
+
+
+class MIPS64BEMachineDef(MIPS64MachineDef):
+    byteorder = Byteorder.BIG
+    machine = "malta"
+    cpu = "MIPS64R2-generic"
+    cs_mode = capstone.CS_MODE_MIPS64 | capstone.CS_MODE_BIG_ENDIAN

smallworld/emulators/panda/machdefs/ppc.py

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+import capstone
+
+from ....platforms import Architecture, Byteorder
+from .machdef import PandaMachineDef
+
+
+class PowerPCMachineDef(PandaMachineDef):
+    byteorder = Byteorder.BIG
+
+    cs_arch = capstone.CS_ARCH_PPC
+    cs_mode = capstone.CS_MODE_32 | capstone.CS_MODE_BIG_ENDIAN
+
+    panda_arch = "ppc"
+
+    # I'm going to define all the ones we are making possible as of now
+    # I need to submit a PR to change to X86 32 bit and to includ eflags
+    _registers_identity = {
+        "r0",
+        "r2",
+        "r3",
+        "r4",
+        "r5",
+        "r6",
+        "r7",
+        "r8",
+        "r9",
+        "r10",
+        "r11",
+        "r12",
+        "r13",
+        "r14",
+        "r15",
+        "r16",
+        "r17",
+        "r18",
+        "r19",
+        "r20",
+        "r21",
+        "r22",
+        "r23",
+        "r24",
+        "r25",
+        "r26",
+        "r27",
+        "r28",
+        "r29",
+        "r30",
+        "r31",
+        "cr0",
+        "cr1",
+        "cr2",
+        "cr3",
+        "cr4",
+        "cr5",
+        "cr6",
+        "cr7",
+        "pc",
+        "sp",
+        "lr",
+        "ctr",
+    }
+    _registers_mapping = {
+        "r1": "sp",
+    }
+    _registers = {i: j for i, j in _registers_mapping.items()}
+    _registers = _registers | {i: i for i in _registers_identity}
+
+
+class PowerPC32MachineDef(PowerPCMachineDef):
+    arch = Architecture.POWERPC32
+    cs_mode = capstone.CS_MODE_32 | capstone.CS_MODE_BIG_ENDIAN
+    cpu = "ppc32"
+
+
+# TODO: Do we have a panda PPC 64 bit cpu?
+class PowerPC64MachineDef(PowerPCMachineDef):
+    arch = Architecture.POWERPC64
+    cs_mode = capstone.CS_MODE_64 | capstone.CS_MODE_BIG_ENDIAN
+    # cpu = "970"