sequenzo 0.1.31__cp310-cp310-macosx_10_9_x86_64.whl
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- _sequenzo_fastcluster.cpython-310-darwin.so +0 -0
- sequenzo/__init__.py +349 -0
- sequenzo/big_data/__init__.py +12 -0
- sequenzo/big_data/clara/__init__.py +26 -0
- sequenzo/big_data/clara/clara.py +476 -0
- sequenzo/big_data/clara/utils/__init__.py +27 -0
- sequenzo/big_data/clara/utils/aggregatecases.py +92 -0
- sequenzo/big_data/clara/utils/davies_bouldin.py +91 -0
- sequenzo/big_data/clara/utils/get_weighted_diss.cpython-310-darwin.so +0 -0
- sequenzo/big_data/clara/utils/wfcmdd.py +205 -0
- sequenzo/big_data/clara/visualization.py +88 -0
- sequenzo/clustering/KMedoids.py +178 -0
- sequenzo/clustering/__init__.py +30 -0
- sequenzo/clustering/clustering_c_code.cpython-310-darwin.so +0 -0
- sequenzo/clustering/hierarchical_clustering.py +1256 -0
- sequenzo/clustering/sequenzo_fastcluster/fastcluster.py +495 -0
- sequenzo/clustering/sequenzo_fastcluster/src/fastcluster.cpp +1877 -0
- sequenzo/clustering/sequenzo_fastcluster/src/fastcluster_python.cpp +1264 -0
- sequenzo/clustering/src/KMedoid.cpp +263 -0
- sequenzo/clustering/src/PAM.cpp +237 -0
- sequenzo/clustering/src/PAMonce.cpp +265 -0
- sequenzo/clustering/src/cluster_quality.cpp +496 -0
- sequenzo/clustering/src/cluster_quality.h +128 -0
- sequenzo/clustering/src/cluster_quality_backup.cpp +570 -0
- sequenzo/clustering/src/module.cpp +228 -0
- sequenzo/clustering/src/weightedinertia.cpp +111 -0
- sequenzo/clustering/utils/__init__.py +27 -0
- sequenzo/clustering/utils/disscenter.py +122 -0
- sequenzo/data_preprocessing/__init__.py +22 -0
- sequenzo/data_preprocessing/helpers.py +303 -0
- sequenzo/datasets/__init__.py +41 -0
- sequenzo/datasets/biofam.csv +2001 -0
- sequenzo/datasets/biofam_child_domain.csv +2001 -0
- sequenzo/datasets/biofam_left_domain.csv +2001 -0
- sequenzo/datasets/biofam_married_domain.csv +2001 -0
- sequenzo/datasets/chinese_colonial_territories.csv +12 -0
- sequenzo/datasets/country_co2_emissions.csv +194 -0
- sequenzo/datasets/country_co2_emissions_global_deciles.csv +195 -0
- sequenzo/datasets/country_co2_emissions_global_quintiles.csv +195 -0
- sequenzo/datasets/country_co2_emissions_local_deciles.csv +195 -0
- sequenzo/datasets/country_co2_emissions_local_quintiles.csv +195 -0
- sequenzo/datasets/country_gdp_per_capita.csv +194 -0
- sequenzo/datasets/dyadic_children.csv +61 -0
- sequenzo/datasets/dyadic_parents.csv +61 -0
- sequenzo/datasets/mvad.csv +713 -0
- sequenzo/datasets/pairfam_activity_by_month.csv +1028 -0
- sequenzo/datasets/pairfam_activity_by_year.csv +1028 -0
- sequenzo/datasets/pairfam_family_by_month.csv +1028 -0
- sequenzo/datasets/pairfam_family_by_year.csv +1028 -0
- sequenzo/datasets/political_science_aid_shock.csv +166 -0
- sequenzo/datasets/political_science_donor_fragmentation.csv +157 -0
- sequenzo/define_sequence_data.py +1400 -0
- sequenzo/dissimilarity_measures/__init__.py +31 -0
- sequenzo/dissimilarity_measures/c_code.cpython-310-darwin.so +0 -0
- sequenzo/dissimilarity_measures/get_distance_matrix.py +762 -0
- sequenzo/dissimilarity_measures/get_substitution_cost_matrix.py +246 -0
- sequenzo/dissimilarity_measures/src/DHDdistance.cpp +148 -0
- sequenzo/dissimilarity_measures/src/LCPdistance.cpp +114 -0
- sequenzo/dissimilarity_measures/src/LCPspellDistance.cpp +215 -0
- sequenzo/dissimilarity_measures/src/OMdistance.cpp +247 -0
- sequenzo/dissimilarity_measures/src/OMspellDistance.cpp +281 -0
- sequenzo/dissimilarity_measures/src/__init__.py +0 -0
- sequenzo/dissimilarity_measures/src/dist2matrix.cpp +63 -0
- sequenzo/dissimilarity_measures/src/dp_utils.h +160 -0
- sequenzo/dissimilarity_measures/src/module.cpp +40 -0
- sequenzo/dissimilarity_measures/src/setup.py +30 -0
- sequenzo/dissimilarity_measures/src/utils.h +25 -0
- sequenzo/dissimilarity_measures/src/xsimd/.github/cmake-test/main.cpp +6 -0
- sequenzo/dissimilarity_measures/src/xsimd/benchmark/main.cpp +159 -0
- sequenzo/dissimilarity_measures/src/xsimd/benchmark/xsimd_benchmark.hpp +565 -0
- sequenzo/dissimilarity_measures/src/xsimd/docs/source/conf.py +37 -0
- sequenzo/dissimilarity_measures/src/xsimd/examples/mandelbrot.cpp +330 -0
- sequenzo/dissimilarity_measures/src/xsimd/examples/pico_bench.hpp +246 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/common/xsimd_common_arithmetic.hpp +266 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/common/xsimd_common_complex.hpp +112 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/common/xsimd_common_details.hpp +323 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/common/xsimd_common_logical.hpp +218 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/common/xsimd_common_math.hpp +2583 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/common/xsimd_common_memory.hpp +880 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/common/xsimd_common_rounding.hpp +72 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/common/xsimd_common_swizzle.hpp +174 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/common/xsimd_common_trigo.hpp +978 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_avx.hpp +1924 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_avx2.hpp +1144 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_avx512bw.hpp +656 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_avx512cd.hpp +28 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_avx512dq.hpp +244 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_avx512er.hpp +20 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_avx512f.hpp +2650 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_avx512ifma.hpp +20 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_avx512pf.hpp +20 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_avx512vbmi.hpp +77 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_avx512vbmi2.hpp +131 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_avx512vnni_avx512bw.hpp +20 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_avx512vnni_avx512vbmi2.hpp +20 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_avxvnni.hpp +20 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_common.hpp +24 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_common_fwd.hpp +77 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_constants.hpp +393 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_emulated.hpp +788 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_fma3_avx.hpp +93 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_fma3_avx2.hpp +46 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_fma3_sse.hpp +97 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_fma4.hpp +92 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_i8mm_neon64.hpp +17 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_isa.hpp +142 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_neon.hpp +3142 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_neon64.hpp +1543 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_rvv.hpp +1513 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_scalar.hpp +1260 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_sse2.hpp +2024 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_sse3.hpp +67 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_sse4_1.hpp +339 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_sse4_2.hpp +44 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_ssse3.hpp +186 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_sve.hpp +1155 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_vsx.hpp +892 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_wasm.hpp +1780 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/config/xsimd_arch.hpp +240 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/config/xsimd_config.hpp +484 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/config/xsimd_cpuid.hpp +269 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/config/xsimd_inline.hpp +27 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/math/xsimd_rem_pio2.hpp +719 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/memory/xsimd_aligned_allocator.hpp +349 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/memory/xsimd_alignment.hpp +91 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_all_registers.hpp +55 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_api.hpp +2765 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_avx2_register.hpp +44 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_avx512bw_register.hpp +51 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_avx512cd_register.hpp +51 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_avx512dq_register.hpp +51 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_avx512er_register.hpp +51 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_avx512f_register.hpp +77 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_avx512ifma_register.hpp +51 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_avx512pf_register.hpp +51 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_avx512vbmi2_register.hpp +51 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_avx512vbmi_register.hpp +51 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_avx512vnni_avx512bw_register.hpp +54 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_avx512vnni_avx512vbmi2_register.hpp +53 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_avx_register.hpp +64 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_avxvnni_register.hpp +44 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_batch.hpp +1524 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_batch_constant.hpp +300 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_common_arch.hpp +47 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_emulated_register.hpp +80 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_fma3_avx2_register.hpp +50 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_fma3_avx_register.hpp +50 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_fma3_sse_register.hpp +50 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_fma4_register.hpp +50 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_i8mm_neon64_register.hpp +55 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_neon64_register.hpp +55 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_neon_register.hpp +154 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_register.hpp +94 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_rvv_register.hpp +506 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_sse2_register.hpp +59 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_sse3_register.hpp +49 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_sse4_1_register.hpp +48 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_sse4_2_register.hpp +48 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_ssse3_register.hpp +48 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_sve_register.hpp +156 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_traits.hpp +337 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_utils.hpp +536 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_vsx_register.hpp +77 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_wasm_register.hpp +59 -0
- sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/xsimd.hpp +75 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/architectures/dummy.cpp +7 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/doc/explicit_use_of_an_instruction_set.cpp +13 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/doc/explicit_use_of_an_instruction_set_mean.cpp +24 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/doc/explicit_use_of_an_instruction_set_mean_aligned.cpp +25 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/doc/explicit_use_of_an_instruction_set_mean_arch_independent.cpp +28 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/doc/explicit_use_of_an_instruction_set_mean_tag_dispatch.cpp +25 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/doc/manipulating_abstract_batches.cpp +7 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/doc/manipulating_parametric_batches.cpp +8 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/doc/sum.hpp +31 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/doc/sum_avx2.cpp +3 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/doc/sum_sse2.cpp +3 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/doc/writing_vectorized_code.cpp +11 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/main.cpp +31 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_api.cpp +230 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_arch.cpp +217 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_basic_math.cpp +183 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_batch.cpp +1049 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_batch_bool.cpp +508 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_batch_cast.cpp +409 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_batch_complex.cpp +712 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_batch_constant.cpp +286 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_batch_float.cpp +141 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_batch_int.cpp +365 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_batch_manip.cpp +308 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_bitwise_cast.cpp +222 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_complex_exponential.cpp +226 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_complex_hyperbolic.cpp +183 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_complex_power.cpp +265 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_complex_trigonometric.cpp +236 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_conversion.cpp +248 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_custom_default_arch.cpp +28 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_error_gamma.cpp +170 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_explicit_batch_instantiation.cpp +32 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_exponential.cpp +202 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_extract_pair.cpp +92 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_fp_manipulation.cpp +77 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_gnu_source.cpp +30 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_hyperbolic.cpp +167 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_load_store.cpp +304 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_memory.cpp +61 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_poly_evaluation.cpp +64 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_power.cpp +184 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_rounding.cpp +199 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_select.cpp +101 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_shuffle.cpp +760 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_sum.cpp +4 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_sum.hpp +34 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_traits.cpp +172 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_trigonometric.cpp +208 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_utils.hpp +611 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_wasm/test_wasm_playwright.py +123 -0
- sequenzo/dissimilarity_measures/src/xsimd/test/test_xsimd_api.cpp +1460 -0
- sequenzo/dissimilarity_measures/utils/__init__.py +16 -0
- sequenzo/dissimilarity_measures/utils/get_LCP_length_for_2_seq.py +44 -0
- sequenzo/dissimilarity_measures/utils/get_sm_trate_substitution_cost_matrix.cpython-310-darwin.so +0 -0
- sequenzo/dissimilarity_measures/utils/seqconc.cpython-310-darwin.so +0 -0
- sequenzo/dissimilarity_measures/utils/seqdss.cpython-310-darwin.so +0 -0
- sequenzo/dissimilarity_measures/utils/seqdur.cpython-310-darwin.so +0 -0
- sequenzo/dissimilarity_measures/utils/seqlength.cpython-310-darwin.so +0 -0
- sequenzo/multidomain/__init__.py +23 -0
- sequenzo/multidomain/association_between_domains.py +311 -0
- sequenzo/multidomain/cat.py +597 -0
- sequenzo/multidomain/combt.py +519 -0
- sequenzo/multidomain/dat.py +81 -0
- sequenzo/multidomain/idcd.py +139 -0
- sequenzo/multidomain/linked_polyad.py +292 -0
- sequenzo/openmp_setup.py +233 -0
- sequenzo/prefix_tree/__init__.py +62 -0
- sequenzo/prefix_tree/hub.py +114 -0
- sequenzo/prefix_tree/individual_level_indicators.py +1321 -0
- sequenzo/prefix_tree/spell_individual_level_indicators.py +580 -0
- sequenzo/prefix_tree/spell_level_indicators.py +297 -0
- sequenzo/prefix_tree/system_level_indicators.py +544 -0
- sequenzo/prefix_tree/utils.py +54 -0
- sequenzo/seqhmm/__init__.py +95 -0
- sequenzo/seqhmm/advanced_optimization.py +305 -0
- sequenzo/seqhmm/bootstrap.py +411 -0
- sequenzo/seqhmm/build_hmm.py +142 -0
- sequenzo/seqhmm/build_mhmm.py +136 -0
- sequenzo/seqhmm/build_nhmm.py +121 -0
- sequenzo/seqhmm/fit_mhmm.py +62 -0
- sequenzo/seqhmm/fit_model.py +61 -0
- sequenzo/seqhmm/fit_nhmm.py +76 -0
- sequenzo/seqhmm/formulas.py +289 -0
- sequenzo/seqhmm/forward_backward_nhmm.py +276 -0
- sequenzo/seqhmm/gradients_nhmm.py +306 -0
- sequenzo/seqhmm/hmm.py +291 -0
- sequenzo/seqhmm/mhmm.py +314 -0
- sequenzo/seqhmm/model_comparison.py +238 -0
- sequenzo/seqhmm/multichannel_em.py +282 -0
- sequenzo/seqhmm/multichannel_utils.py +138 -0
- sequenzo/seqhmm/nhmm.py +270 -0
- sequenzo/seqhmm/nhmm_utils.py +191 -0
- sequenzo/seqhmm/predict.py +137 -0
- sequenzo/seqhmm/predict_mhmm.py +142 -0
- sequenzo/seqhmm/simulate.py +878 -0
- sequenzo/seqhmm/utils.py +218 -0
- sequenzo/seqhmm/visualization.py +910 -0
- sequenzo/sequence_characteristics/__init__.py +40 -0
- sequenzo/sequence_characteristics/complexity_index.py +49 -0
- sequenzo/sequence_characteristics/overall_cross_sectional_entropy.py +220 -0
- sequenzo/sequence_characteristics/plot_characteristics.py +593 -0
- sequenzo/sequence_characteristics/simple_characteristics.py +311 -0
- sequenzo/sequence_characteristics/state_frequencies_and_entropy_per_sequence.py +39 -0
- sequenzo/sequence_characteristics/turbulence.py +155 -0
- sequenzo/sequence_characteristics/variance_of_spell_durations.py +86 -0
- sequenzo/sequence_characteristics/within_sequence_entropy.py +43 -0
- sequenzo/suffix_tree/__init__.py +66 -0
- sequenzo/suffix_tree/hub.py +114 -0
- sequenzo/suffix_tree/individual_level_indicators.py +1679 -0
- sequenzo/suffix_tree/spell_individual_level_indicators.py +493 -0
- sequenzo/suffix_tree/spell_level_indicators.py +248 -0
- sequenzo/suffix_tree/system_level_indicators.py +535 -0
- sequenzo/suffix_tree/utils.py +56 -0
- sequenzo/version_check.py +283 -0
- sequenzo/visualization/__init__.py +29 -0
- sequenzo/visualization/plot_mean_time.py +222 -0
- sequenzo/visualization/plot_modal_state.py +276 -0
- sequenzo/visualization/plot_most_frequent_sequences.py +147 -0
- sequenzo/visualization/plot_relative_frequency.py +405 -0
- sequenzo/visualization/plot_sequence_index.py +1175 -0
- sequenzo/visualization/plot_single_medoid.py +153 -0
- sequenzo/visualization/plot_state_distribution.py +651 -0
- sequenzo/visualization/plot_transition_matrix.py +190 -0
- sequenzo/visualization/utils/__init__.py +23 -0
- sequenzo/visualization/utils/utils.py +310 -0
- sequenzo/with_event_history_analysis/__init__.py +35 -0
- sequenzo/with_event_history_analysis/sequence_analysis_multi_state_model.py +850 -0
- sequenzo/with_event_history_analysis/sequence_history_analysis.py +283 -0
- sequenzo-0.1.31.dist-info/METADATA +286 -0
- sequenzo-0.1.31.dist-info/RECORD +299 -0
- sequenzo-0.1.31.dist-info/WHEEL +5 -0
- sequenzo-0.1.31.dist-info/licenses/LICENSE +28 -0
- sequenzo-0.1.31.dist-info/top_level.txt +2 -0
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/***************************************************************************
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* Copyright (c) Rivos Inc. *
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* *
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* Distributed under the terms of the BSD 3-Clause License. *
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* *
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* The full license is in the file LICENSE, distributed with this software. *
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****************************************************************************/
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#ifndef XSIMD_RVV_HPP
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#define XSIMD_RVV_HPP
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#include <complex>
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#include <type_traits>
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#include <utility>
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#include "../types/xsimd_rvv_register.hpp"
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#include "xsimd_constants.hpp"
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// This set of macros allows the synthesis of identifiers using a template and
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// variable macro arguments. A single template can then be used by multiple
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// macros, or multiple instances of a macro to define the same logic for
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// different data types.
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//
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// First some logic to paste text together...
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//
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#define XSIMD_RVV_JOIN_(x, y) x##y
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#define XSIMD_RVV_JOIN(x, y) XSIMD_RVV_JOIN_(x, y)
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#define XSIMD_RVV_PREFIX_T(T, S, then) XSIMD_RVV_JOIN(T, then)
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#define XSIMD_RVV_PREFIX_S(T, S, then) XSIMD_RVV_JOIN(S, then)
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#define XSIMD_RVV_PREFIX_M(T, S, then) XSIMD_RVV_JOIN(m1, then)
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#define XSIMD_RVV_PREFIX(T, S, then) then
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//
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// XSIMD_RVV_IDENTIFIER accepts type and size parameters, and a template for
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// the identifier. The template is a comma-separated list of alternating
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// literal and parameter segments. Each parameter is appended to XSIMD_RVV_PREFIX to
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// form a new macro name which decides which parameter should be inserted.
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// Then a literal segment is inserted after that. Empty literals are used to
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// join two or more variables together.
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//
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#define XSIMD_RVV_IDENTIFIER9(T, S, t, ...) t
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#define XSIMD_RVV_IDENTIFIER8(T, S, t, p, ...) XSIMD_RVV_JOIN(t, XSIMD_RVV_PREFIX##p(T, S, XSIMD_RVV_IDENTIFIER9(T, S, __VA_ARGS__)))
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#define XSIMD_RVV_IDENTIFIER7(T, S, t, p, ...) XSIMD_RVV_JOIN(t, XSIMD_RVV_PREFIX##p(T, S, XSIMD_RVV_IDENTIFIER8(T, S, __VA_ARGS__)))
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#define XSIMD_RVV_IDENTIFIER6(T, S, t, p, ...) XSIMD_RVV_JOIN(t, XSIMD_RVV_PREFIX##p(T, S, XSIMD_RVV_IDENTIFIER7(T, S, __VA_ARGS__)))
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#define XSIMD_RVV_IDENTIFIER5(T, S, t, p, ...) XSIMD_RVV_JOIN(t, XSIMD_RVV_PREFIX##p(T, S, XSIMD_RVV_IDENTIFIER6(T, S, __VA_ARGS__)))
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#define XSIMD_RVV_IDENTIFIER4(T, S, t, p, ...) XSIMD_RVV_JOIN(t, XSIMD_RVV_PREFIX##p(T, S, XSIMD_RVV_IDENTIFIER5(T, S, __VA_ARGS__)))
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#define XSIMD_RVV_IDENTIFIER3(T, S, t, p, ...) XSIMD_RVV_JOIN(t, XSIMD_RVV_PREFIX##p(T, S, XSIMD_RVV_IDENTIFIER4(T, S, __VA_ARGS__)))
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#define XSIMD_RVV_IDENTIFIER2(T, S, t, p, ...) XSIMD_RVV_JOIN(t, XSIMD_RVV_PREFIX##p(T, S, XSIMD_RVV_IDENTIFIER3(T, S, __VA_ARGS__)))
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#define XSIMD_RVV_IDENTIFIER1(T, S, t, p, ...) XSIMD_RVV_JOIN(t, XSIMD_RVV_PREFIX##p(T, S, XSIMD_RVV_IDENTIFIER2(T, S, __VA_ARGS__)))
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#define XSIMD_RVV_IDENTIFIER0(T, S, t, p, ...) XSIMD_RVV_JOIN(t, XSIMD_RVV_PREFIX##p(T, S, XSIMD_RVV_IDENTIFIER1(T, S, __VA_ARGS__)))
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//
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// UNBRACKET and REPARSE force the preprocessor to handle expansion in a
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// specific order. XSIMD_RVV_UNBRACKET strips the parentheses from the template
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// (which were necessary to keep the template as a single, named macro
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// parameter up to this point). XSIMD_RVV_ARG_LIST then forms the new parameter list
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// to pass to XSIMD_RVV_IDENTIFIER0, with trailing commas to ensure the unrolled
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// XSIMD_RVV_IDENTIFIER loop runs to completion adding empty strings.
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//
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// However XSIMD_RVV_IDENTIFIER0 is not expanded immediately because it does not
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// match a function-like macro in this pass. XSIMD_RVV_REPARSE forces another
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// evaluation after the expansion of XSIMD_RVV_ARG_LIST, where XSIMD_RVV_IDENTIFIER0 will
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// now match as a function-like macro, and the cycle of substitutions and
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// insertions can begin.
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//
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#define XSIMD_RVV_REPARSE(v) (v)
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#define XSIMD_RVV_UNBRACKET(...) __VA_ARGS__
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#define XSIMD_RVV_ARG_LIST(T, S, name) (T, S, XSIMD_RVV_UNBRACKET name, , , , , , , , , , , , , , , , , , , , , )
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#define XSIMD_RVV_IDENTIFIER(T, S, name) XSIMD_RVV_REPARSE(XSIMD_RVV_IDENTIFIER0 XSIMD_RVV_ARG_LIST(T, S, name))
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//
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// To avoid comma-counting bugs, replace the variable references with macros
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// which include enough commas to keep proper phase, and then use no commas at
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// all in the templates.
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//
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#define XSIMD_RVV_T , _T,
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#define XSIMD_RVV_S , _S,
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#define XSIMD_RVV_M , _M,
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#define XSIMD_RVV_TSM XSIMD_RVV_T XSIMD_RVV_S XSIMD_RVV_M
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// XSIMD_RVV_OVERLOAD, below, expands to a head section, a number of body sections
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// (depending on which types are supported), and a tail section. Different
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// variants of these sections are implemented with different suffixes on the
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// three macro names XSIMD_RVV_WRAPPER_HEAD, XSIMD_RVV_WRAPPER, and XSIMD_RVV_WRAPPER_TAIL and
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// specified as an argument to XSIMD_RVV_OVERLOAD (the empty string is the default,
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// but still needs an extra comma to hold its place).
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//
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// The default XSIMD_RVV_WRAPPER_HEAD provides a class containing convenient names
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// for the function signature argument(s) to XSIMD_RVV_OVERLOAD. That signature can
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// also reference the template argument T, because it's a text substitution
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// into the template.
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#define XSIMD_RVV_WRAPPER_HEAD(NAME, SIGNATURE, ...) \
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namespace NAME##_cruft \
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{ \
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template <class T> \
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struct ctx \
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{ \
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static constexpr size_t width = XSIMD_RVV_BITS; \
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static constexpr size_t vl = width / (sizeof(T) * 8); \
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using vec = rvv_reg_t<T, width>; \
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using uvec = rvv_reg_t<as_unsigned_relaxed_t<T>, width>; \
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using svec = rvv_reg_t<as_signed_relaxed_t<T>, width>; \
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using fvec = rvv_reg_t<as_float_relaxed_t<T>, width>; \
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using bvec = rvv_bool_t<T, width>; \
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using scalar_vec = rvv_reg_t<T, types::detail::rvv_width_m1>; \
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using wide_vec = rvv_reg_t<T, width * 2>; \
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using narrow_vec = rvv_reg_t<T, width / 2>; \
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using type = SIGNATURE; \
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}; \
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template <class T> \
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using sig_t = typename ctx<T>::type; \
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template <class K, class T> \
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struct impl \
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{ \
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void operator()() const noexcept {}; \
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}; \
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template <class K> \
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using impl_t = impl<K, sig_t<K>>;
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#define XSIMD_RVV_WRAPPER_HEAD_NOVL(...) XSIMD_RVV_WRAPPER_HEAD(__VA_ARGS__)
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#define XSIMD_RVV_WRAPPER_HEAD_DROP_1ST(...) XSIMD_RVV_WRAPPER_HEAD(__VA_ARGS__)
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#define XSIMD_RVV_WRAPPER_HEAD_DROP_1ST_CUSTOM_ARGS(...) XSIMD_RVV_WRAPPER_HEAD(__VA_ARGS__)
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#define XSIMD_RVV_WRAPPER_HEAD_DROP_1ST_CUSTOM_ARGS_NOVL(...) XSIMD_RVV_WRAPPER_HEAD(__VA_ARGS__)
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// The body of the wrapper defines a functor (because partial specialisation of
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// functions is not legal) which forwards its arguments to the named intrinsic
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// with a few manipulations. In general, vector types are handled as
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// rvv_reg_t<> and rely on the conversion operators in that class for
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// compatibility with the intrinsics.
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//
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// The function signature is not mentioned here. Instead it's provided in the
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// tail code as the template argument for which this is a specialisation, which
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// overcomes the problem of converting a function signature type to an argument
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// list to pass to another function.
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//
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#define XSIMD_RVV_WRAPPER(KEY, CALLEE, ...) \
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template <class Ret, class... Args> \
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struct impl<KEY, Ret(Args...)> \
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{ \
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using ctx = ctx<KEY>; \
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constexpr Ret operator()(Args... args) const noexcept \
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{ \
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return CALLEE(args..., ctx::vl); \
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}; \
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};
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#define XSIMD_RVV_WRAPPER_NOVL(KEY, CALLEE, ...) \
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template <class Ret, class... Args> \
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struct impl<KEY, Ret(Args...)> \
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{ \
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constexpr Ret operator()(Args... args) const noexcept \
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{ \
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return CALLEE(args...); \
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}; \
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};
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#define XSIMD_RVV_WRAPPER_DROP_1ST(KEY, CALLEE, ...) \
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template <class Ret, class First, class... Args> \
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struct impl<KEY, Ret(First, Args...)> \
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{ \
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using ctx = ctx<KEY>; \
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constexpr Ret operator()(First, Args... args) const noexcept \
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{ \
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return CALLEE(args..., ctx::vl); \
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}; \
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};
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#define XSIMD_RVV_WRAPPER_DROP_1ST_CUSTOM_ARGS(KEY, CALLEE, SIGNATURE, ...) \
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template <class Ret, class First, class... Args> \
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struct impl<KEY, Ret(First, Args...)> \
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{ \
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using ctx = ctx<KEY>; \
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constexpr Ret operator()(First, Args... args) const noexcept \
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{ \
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return CALLEE(__VA_ARGS__, ctx::vl); \
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}; \
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};
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#define XSIMD_RVV_WRAPPER_DROP_1ST_CUSTOM_ARGS_NOVL(KEY, CALLEE, SIGNATURE, ...) \
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template <class Ret, class First, class... Args> \
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struct impl<KEY, Ret(First, Args...)> \
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{ \
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constexpr Ret operator()(First, Args... args) const noexcept \
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{ \
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return CALLEE(__VA_ARGS__); \
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}; \
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};
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// This part folds all the above templates down into a single functor instance
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// with all the different function signatures available under the one name.
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// Not all of the base classes necessarily contain useful code, but there's a
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// default implementation so that filtering them out isn't really necessary.
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#define XSIMD_RVV_WRAPPER_TAIL(NAME, ...) \
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} /* namespace NAME##_cruft */ \
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static constexpr struct : NAME##_cruft::impl_t<int8_t>, \
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NAME##_cruft::impl_t<uint8_t>, \
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NAME##_cruft::impl_t<int16_t>, \
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NAME##_cruft::impl_t<uint16_t>, \
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NAME##_cruft::impl_t<int32_t>, \
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NAME##_cruft::impl_t<uint32_t>, \
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NAME##_cruft::impl_t<int64_t>, \
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NAME##_cruft::impl_t<uint64_t>, \
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NAME##_cruft::impl_t<float>, \
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NAME##_cruft::impl_t<double> \
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{ \
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using NAME##_cruft::impl_t<int8_t>::operator(); \
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using NAME##_cruft::impl_t<uint8_t>::operator(); \
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using NAME##_cruft::impl_t<int16_t>::operator(); \
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using NAME##_cruft::impl_t<uint16_t>::operator(); \
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using NAME##_cruft::impl_t<int32_t>::operator(); \
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using NAME##_cruft::impl_t<uint32_t>::operator(); \
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using NAME##_cruft::impl_t<int64_t>::operator(); \
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using NAME##_cruft::impl_t<uint64_t>::operator(); \
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using NAME##_cruft::impl_t<float>::operator(); \
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using NAME##_cruft::impl_t<double>::operator(); \
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} NAME {};
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#define XSIMD_RVV_WRAPPER_TAIL_NOVL(...) XSIMD_RVV_WRAPPER_TAIL(__VA_ARGS__)
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212
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+
#define XSIMD_RVV_WRAPPER_TAIL_DROP_1ST(...) XSIMD_RVV_WRAPPER_TAIL(__VA_ARGS__)
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213
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#define XSIMD_RVV_WRAPPER_TAIL_DROP_1ST_CUSTOM_ARGS(...) XSIMD_RVV_WRAPPER_TAIL(__VA_ARGS__)
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214
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#define XSIMD_RVV_WRAPPER_TAIL_DROP_1ST_CUSTOM_ARGS_NOVL(...) XSIMD_RVV_WRAPPER_TAIL(__VA_ARGS__)
|
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215
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+
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216
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+
// clang-format off
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217
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+
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218
|
+
#define XSIMD_RVV_OVERLOAD_head(my_name, variant, ...) \
|
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219
|
+
XSIMD_RVV_WRAPPER_HEAD##variant(my_name, __VA_ARGS__)
|
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220
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+
#define XSIMD_RVV_OVERLOAD_i(name, variant, ...) \
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221
|
+
XSIMD_RVV_WRAPPER##variant(int8_t, XSIMD_RVV_IDENTIFIER(i, 8, name), __VA_ARGS__) \
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222
|
+
XSIMD_RVV_WRAPPER##variant(int16_t, XSIMD_RVV_IDENTIFIER(i, 16, name), __VA_ARGS__) \
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223
|
+
XSIMD_RVV_WRAPPER##variant(int32_t, XSIMD_RVV_IDENTIFIER(i, 32, name), __VA_ARGS__) \
|
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224
|
+
XSIMD_RVV_WRAPPER##variant(int64_t, XSIMD_RVV_IDENTIFIER(i, 64, name), __VA_ARGS__)
|
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225
|
+
#define XSIMD_RVV_OVERLOAD_u(name, variant, ...) \
|
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226
|
+
XSIMD_RVV_WRAPPER##variant(uint8_t, XSIMD_RVV_IDENTIFIER(u, 8, name), __VA_ARGS__) \
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227
|
+
XSIMD_RVV_WRAPPER##variant(uint16_t, XSIMD_RVV_IDENTIFIER(u, 16, name), __VA_ARGS__) \
|
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228
|
+
XSIMD_RVV_WRAPPER##variant(uint32_t, XSIMD_RVV_IDENTIFIER(u, 32, name), __VA_ARGS__) \
|
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229
|
+
XSIMD_RVV_WRAPPER##variant(uint64_t, XSIMD_RVV_IDENTIFIER(u, 64, name), __VA_ARGS__)
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230
|
+
#define XSIMD_RVV_OVERLOAD_f(name, variant, ...) \
|
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231
|
+
XSIMD_RVV_WRAPPER##variant(float, XSIMD_RVV_IDENTIFIER(f, 32, name), __VA_ARGS__) \
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232
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+
XSIMD_RVV_WRAPPER##variant(double, XSIMD_RVV_IDENTIFIER(f, 64, name), __VA_ARGS__)
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233
|
+
#define XSIMD_RVV_OVERLOAD_tail(my_name, variant, ...) \
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234
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+
XSIMD_RVV_WRAPPER_TAIL##variant(my_name, __VA_ARGS__)
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235
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+
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236
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+
// Use these to create function (actually functor, sorry) wrappers overloaded
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// for whichever types are supported. Being functors means they can't take a
|
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238
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+
// template argument (until C++14), so if a type can't be deduced then a junk
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239
|
+
// value can be passed as the first argument and discarded by using the
|
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240
|
+
// _DROP_1ST variant, instead.
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+
//
|
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242
|
+
// The wrappers use the rvv_reg_t<> types for template accessibility, and
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243
|
+
// because some types (eg., vfloat64mf2_t) don't exist and need extra
|
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244
|
+
// abstraction to emulate.
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245
|
+
//
|
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246
|
+
// In many cases the intrinsic names are different for signed, unsigned, or
|
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247
|
+
// float variants, the macros OVERLOAD2 and OVERLOAD3 (depending on whether or
|
|
248
|
+
// not a float variant exists) take multiple intrinsic names and bring them
|
|
249
|
+
// together under a single overloaded identifier where they can be used within
|
|
250
|
+
// templates.
|
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251
|
+
//
|
|
252
|
+
#define XSIMD_RVV_OVERLOAD2(my_name, name_i, name_u, variant, ...) \
|
|
253
|
+
XSIMD_RVV_OVERLOAD_head(my_name, variant, __VA_ARGS__) \
|
|
254
|
+
XSIMD_RVV_OVERLOAD_i(name_i, variant, __VA_ARGS__) \
|
|
255
|
+
XSIMD_RVV_OVERLOAD_u(name_u, variant, __VA_ARGS__) \
|
|
256
|
+
XSIMD_RVV_OVERLOAD_tail(my_name, variant, __VA_ARGS__)
|
|
257
|
+
|
|
258
|
+
#define XSIMD_RVV_OVERLOAD3(my_name, name_i, name_u, name_f, variant, ...) \
|
|
259
|
+
XSIMD_RVV_OVERLOAD_head(my_name, variant, __VA_ARGS__) \
|
|
260
|
+
XSIMD_RVV_OVERLOAD_i(name_i, variant, __VA_ARGS__) \
|
|
261
|
+
XSIMD_RVV_OVERLOAD_u(name_u, variant, __VA_ARGS__) \
|
|
262
|
+
XSIMD_RVV_OVERLOAD_f(name_f, variant, __VA_ARGS__) \
|
|
263
|
+
XSIMD_RVV_OVERLOAD_tail(my_name, variant, __VA_ARGS__)
|
|
264
|
+
|
|
265
|
+
#define XSIMD_RVV_OVERLOAD(my_name, name, ...) XSIMD_RVV_OVERLOAD3(my_name, name, name, name, __VA_ARGS__)
|
|
266
|
+
#define XSIMD_RVV_OVERLOAD_INTS(my_name, name, ...) XSIMD_RVV_OVERLOAD2(my_name, name, name, __VA_ARGS__)
|
|
267
|
+
|
|
268
|
+
#define XSIMD_RVV_OVERLOAD_SINTS(my_name, name, variant, ...) \
|
|
269
|
+
XSIMD_RVV_OVERLOAD_head(my_name, variant, __VA_ARGS__) \
|
|
270
|
+
XSIMD_RVV_OVERLOAD_i(name, variant, __VA_ARGS__) \
|
|
271
|
+
XSIMD_RVV_OVERLOAD_tail(my_name, variant, __VA_ARGS__)
|
|
272
|
+
|
|
273
|
+
#define XSIMD_RVV_OVERLOAD_UINTS(my_name, name, variant, ...) \
|
|
274
|
+
XSIMD_RVV_OVERLOAD_head(my_name, variant, __VA_ARGS__) \
|
|
275
|
+
XSIMD_RVV_OVERLOAD_u(name, variant, __VA_ARGS__) \
|
|
276
|
+
XSIMD_RVV_OVERLOAD_tail(my_name, variant, __VA_ARGS__)
|
|
277
|
+
|
|
278
|
+
#define XSIMD_RVV_OVERLOAD_FLOATS(my_name, name, variant, ...) \
|
|
279
|
+
XSIMD_RVV_OVERLOAD_head(my_name, variant, __VA_ARGS__) \
|
|
280
|
+
XSIMD_RVV_OVERLOAD_f(name, variant, __VA_ARGS__) \
|
|
281
|
+
XSIMD_RVV_OVERLOAD_tail(my_name, variant, __VA_ARGS__)
|
|
282
|
+
|
|
283
|
+
// clang-format on
|
|
284
|
+
|
|
285
|
+
namespace xsimd
|
|
286
|
+
{
|
|
287
|
+
template <typename T, class A, T... Values>
|
|
288
|
+
struct batch_constant;
|
|
289
|
+
|
|
290
|
+
namespace kernel
|
|
291
|
+
{
|
|
292
|
+
namespace detail
|
|
293
|
+
{
|
|
294
|
+
template <class T>
|
|
295
|
+
using rvv_fix_char_t = types::detail::rvv_fix_char_t<T>;
|
|
296
|
+
template <class T, size_t Width = XSIMD_RVV_BITS>
|
|
297
|
+
using rvv_reg_t = types::detail::rvv_reg_t<T, Width>;
|
|
298
|
+
template <class T, size_t Width = XSIMD_RVV_BITS>
|
|
299
|
+
using rvv_bool_t = types::detail::rvv_bool_t<T, Width>;
|
|
300
|
+
|
|
301
|
+
template <size_t>
|
|
302
|
+
struct as_signed_relaxed;
|
|
303
|
+
template <>
|
|
304
|
+
struct as_signed_relaxed<1>
|
|
305
|
+
{
|
|
306
|
+
using type = int8_t;
|
|
307
|
+
};
|
|
308
|
+
template <>
|
|
309
|
+
struct as_signed_relaxed<2>
|
|
310
|
+
{
|
|
311
|
+
using type = int16_t;
|
|
312
|
+
};
|
|
313
|
+
template <>
|
|
314
|
+
struct as_signed_relaxed<4>
|
|
315
|
+
{
|
|
316
|
+
using type = int32_t;
|
|
317
|
+
};
|
|
318
|
+
template <>
|
|
319
|
+
struct as_signed_relaxed<8>
|
|
320
|
+
{
|
|
321
|
+
using type = int64_t;
|
|
322
|
+
};
|
|
323
|
+
template <class T>
|
|
324
|
+
using as_signed_relaxed_t = typename as_signed_relaxed<sizeof(T)>::type;
|
|
325
|
+
template <size_t>
|
|
326
|
+
struct as_unsigned_relaxed;
|
|
327
|
+
template <>
|
|
328
|
+
struct as_unsigned_relaxed<1>
|
|
329
|
+
{
|
|
330
|
+
using type = uint8_t;
|
|
331
|
+
};
|
|
332
|
+
template <>
|
|
333
|
+
struct as_unsigned_relaxed<2>
|
|
334
|
+
{
|
|
335
|
+
using type = uint16_t;
|
|
336
|
+
};
|
|
337
|
+
template <>
|
|
338
|
+
struct as_unsigned_relaxed<4>
|
|
339
|
+
{
|
|
340
|
+
using type = uint32_t;
|
|
341
|
+
};
|
|
342
|
+
template <>
|
|
343
|
+
struct as_unsigned_relaxed<8>
|
|
344
|
+
{
|
|
345
|
+
using type = uint64_t;
|
|
346
|
+
};
|
|
347
|
+
template <class T>
|
|
348
|
+
using as_unsigned_relaxed_t = typename as_unsigned_relaxed<sizeof(T)>::type;
|
|
349
|
+
template <size_t>
|
|
350
|
+
struct as_float_relaxed;
|
|
351
|
+
template <>
|
|
352
|
+
struct as_float_relaxed<1>
|
|
353
|
+
{
|
|
354
|
+
using type = int8_t;
|
|
355
|
+
};
|
|
356
|
+
template <>
|
|
357
|
+
struct as_float_relaxed<2>
|
|
358
|
+
{
|
|
359
|
+
using type = int16_t;
|
|
360
|
+
};
|
|
361
|
+
template <>
|
|
362
|
+
struct as_float_relaxed<4>
|
|
363
|
+
{
|
|
364
|
+
using type = float;
|
|
365
|
+
};
|
|
366
|
+
template <>
|
|
367
|
+
struct as_float_relaxed<8>
|
|
368
|
+
{
|
|
369
|
+
using type = double;
|
|
370
|
+
};
|
|
371
|
+
template <class T>
|
|
372
|
+
using as_float_relaxed_t = typename as_float_relaxed<sizeof(T)>::type;
|
|
373
|
+
|
|
374
|
+
template <class T, class U>
|
|
375
|
+
rvv_reg_t<T, U::width> rvvreinterpret(U const& arg) noexcept
|
|
376
|
+
{
|
|
377
|
+
return rvv_reg_t<T, U::width>(arg, types::detail::XSIMD_RVV_BITCAST);
|
|
378
|
+
}
|
|
379
|
+
template <class T, class A, class U>
|
|
380
|
+
rvv_reg_t<T, A::width> rvvreinterpret(batch<U, A> const& arg) noexcept
|
|
381
|
+
{
|
|
382
|
+
typename batch<U, A>::register_type r = arg;
|
|
383
|
+
return rvvreinterpret<T>(r);
|
|
384
|
+
}
|
|
385
|
+
|
|
386
|
+
template <class A, class T, class U = as_unsigned_integer_t<T>>
|
|
387
|
+
XSIMD_INLINE batch<U, A> rvv_to_unsigned_batch(batch<T, A> const& arg) noexcept
|
|
388
|
+
{
|
|
389
|
+
return rvvreinterpret<U>(arg.data);
|
|
390
|
+
}
|
|
391
|
+
|
|
392
|
+
XSIMD_RVV_OVERLOAD(rvvid,
|
|
393
|
+
(__riscv_vid_v_u XSIMD_RVV_S XSIMD_RVV_M), _DROP_1ST, uvec(T))
|
|
394
|
+
|
|
395
|
+
XSIMD_RVV_OVERLOAD3(rvvmv_splat,
|
|
396
|
+
(__riscv_vmv_v_x_ XSIMD_RVV_TSM),
|
|
397
|
+
(__riscv_vmv_v_x_ XSIMD_RVV_TSM),
|
|
398
|
+
(__riscv_vfmv_v_f_ XSIMD_RVV_TSM), , vec(T))
|
|
399
|
+
|
|
400
|
+
XSIMD_RVV_OVERLOAD3(rvvmv_lane0,
|
|
401
|
+
(__riscv_vmv_x),
|
|
402
|
+
(__riscv_vmv_x),
|
|
403
|
+
(__riscv_vfmv_f), _NOVL, T(vec))
|
|
404
|
+
|
|
405
|
+
XSIMD_RVV_OVERLOAD(rvvmerge, (__riscv_vmerge), , vec(vec, vec, bvec))
|
|
406
|
+
XSIMD_RVV_OVERLOAD3(rvvmerge_splat,
|
|
407
|
+
(__riscv_vmerge),
|
|
408
|
+
(__riscv_vmerge),
|
|
409
|
+
(__riscv_vfmerge), , vec(vec, T, bvec))
|
|
410
|
+
|
|
411
|
+
// count active lanes in a predicate
|
|
412
|
+
XSIMD_RVV_OVERLOAD(rvvcpop, (__riscv_vcpop),
|
|
413
|
+
, size_t(bvec));
|
|
414
|
+
|
|
415
|
+
template <class T, size_t Width>
|
|
416
|
+
XSIMD_INLINE rvv_bool_t<T, Width> pmask8(uint8_t mask) noexcept
|
|
417
|
+
{
|
|
418
|
+
return rvv_bool_t<T, Width>(mask);
|
|
419
|
+
}
|
|
420
|
+
template <class T, size_t Width>
|
|
421
|
+
XSIMD_INLINE rvv_bool_t<T, Width> pmask(uint64_t mask) noexcept
|
|
422
|
+
{
|
|
423
|
+
return rvv_bool_t<T, Width>(mask);
|
|
424
|
+
}
|
|
425
|
+
|
|
426
|
+
template <class A, class T, size_t offset = 0, int shift = 0>
|
|
427
|
+
XSIMD_INLINE rvv_reg_t<T, A::width> vindex() noexcept
|
|
428
|
+
{
|
|
429
|
+
auto index = rvvid(T {});
|
|
430
|
+
if (shift < 0)
|
|
431
|
+
index = __riscv_vsrl(index, -shift, batch<T, A>::size);
|
|
432
|
+
else
|
|
433
|
+
index = __riscv_vsll(index, shift, batch<T, A>::size);
|
|
434
|
+
return __riscv_vadd(index, T(offset), batch<T, A>::size);
|
|
435
|
+
}
|
|
436
|
+
|
|
437
|
+
// enable for signed integers
|
|
438
|
+
template <class T>
|
|
439
|
+
using rvv_enable_signed_int_t = typename std::enable_if<std::is_integral<T>::value && std::is_signed<T>::value, int>::type;
|
|
440
|
+
|
|
441
|
+
// enable for unsigned integers
|
|
442
|
+
template <class T>
|
|
443
|
+
using rvv_enable_unsigned_int_t = typename std::enable_if<std::is_integral<T>::value && std::is_unsigned<T>::value, int>::type;
|
|
444
|
+
|
|
445
|
+
// enable for floating points
|
|
446
|
+
template <class T>
|
|
447
|
+
using rvv_enable_floating_point_t = typename std::enable_if<std::is_floating_point<T>::value, int>::type;
|
|
448
|
+
|
|
449
|
+
// enable for signed integers or floating points
|
|
450
|
+
template <class T>
|
|
451
|
+
using rvv_enable_signed_int_or_floating_point_t = typename std::enable_if<std::is_signed<T>::value, int>::type;
|
|
452
|
+
|
|
453
|
+
// enable for all RVE supported types
|
|
454
|
+
template <class T>
|
|
455
|
+
using rvv_enable_all_t = typename std::enable_if<std::is_arithmetic<T>::value, int>::type;
|
|
456
|
+
} // namespace detail
|
|
457
|
+
|
|
458
|
+
/********************
|
|
459
|
+
* Scalar to vector *
|
|
460
|
+
********************/
|
|
461
|
+
|
|
462
|
+
namespace detail
|
|
463
|
+
{
|
|
464
|
+
template <class T, size_t Width>
|
|
465
|
+
XSIMD_INLINE detail::rvv_reg_t<T, Width> broadcast(T arg) noexcept
|
|
466
|
+
{
|
|
467
|
+
// A bit of a dance, here, because rvvmv_splat has no other
|
|
468
|
+
// argument from which to deduce type, and T=char is not
|
|
469
|
+
// supported.
|
|
470
|
+
detail::rvv_fix_char_t<T> arg_not_char(arg);
|
|
471
|
+
const auto splat = detail::rvvmv_splat(arg_not_char);
|
|
472
|
+
return detail::rvv_reg_t<T, Width>(splat.get_bytes(), types::detail::XSIMD_RVV_BITCAST);
|
|
473
|
+
}
|
|
474
|
+
}
|
|
475
|
+
|
|
476
|
+
// broadcast
|
|
477
|
+
template <class A, class T>
|
|
478
|
+
XSIMD_INLINE batch<T, A> broadcast(T arg, requires_arch<rvv>) noexcept
|
|
479
|
+
{
|
|
480
|
+
return detail::broadcast<T, A::width>(arg);
|
|
481
|
+
}
|
|
482
|
+
|
|
483
|
+
/*********
|
|
484
|
+
* Load *
|
|
485
|
+
*********/
|
|
486
|
+
|
|
487
|
+
namespace detail
|
|
488
|
+
{
|
|
489
|
+
XSIMD_RVV_OVERLOAD(rvvle, (__riscv_vle XSIMD_RVV_S _v_ XSIMD_RVV_TSM), , vec(T const*))
|
|
490
|
+
XSIMD_RVV_OVERLOAD(rvvse, (__riscv_vse XSIMD_RVV_S _v_ XSIMD_RVV_TSM), , void(T*, vec))
|
|
491
|
+
}
|
|
492
|
+
|
|
493
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
494
|
+
XSIMD_INLINE batch<T, A> load_aligned(T const* src, convert<T>, requires_arch<rvv>) noexcept
|
|
495
|
+
{
|
|
496
|
+
return detail::rvvle(reinterpret_cast<detail::rvv_fix_char_t<T> const*>(src));
|
|
497
|
+
}
|
|
498
|
+
|
|
499
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
500
|
+
XSIMD_INLINE batch<T, A> load_unaligned(T const* src, convert<T>, requires_arch<rvv>) noexcept
|
|
501
|
+
{
|
|
502
|
+
return load_aligned<A>(src, convert<T>(), rvv {});
|
|
503
|
+
}
|
|
504
|
+
|
|
505
|
+
// load_complex
|
|
506
|
+
namespace detail
|
|
507
|
+
{
|
|
508
|
+
template <class T, size_t W, typename std::enable_if<W >= types::detail::rvv_width_m1, int>::type = 0>
|
|
509
|
+
XSIMD_INLINE rvv_reg_t<T, W * 2> rvvabut(rvv_reg_t<T, W> const& lo, rvv_reg_t<T, W> const& hi) noexcept
|
|
510
|
+
{
|
|
511
|
+
typename rvv_reg_t<T, W * 2>::register_type tmp;
|
|
512
|
+
tmp = __riscv_vset(tmp, 0, lo);
|
|
513
|
+
return __riscv_vset(tmp, 1, hi);
|
|
514
|
+
}
|
|
515
|
+
|
|
516
|
+
template <class T, size_t W, typename std::enable_if<W<types::detail::rvv_width_m1, int>::type = 0> XSIMD_INLINE rvv_reg_t<T, W * 2> rvvabut(rvv_reg_t<T, W> const& lo, rvv_reg_t<T, W> const& hi) noexcept
|
|
517
|
+
{
|
|
518
|
+
return __riscv_vslideup(lo, hi, lo.vl, lo.vl * 2);
|
|
519
|
+
}
|
|
520
|
+
|
|
521
|
+
XSIMD_RVV_OVERLOAD(rvvget_lo_, (__riscv_vget_ XSIMD_RVV_TSM), _DROP_1ST_CUSTOM_ARGS_NOVL, vec(T, wide_vec), args..., 0)
|
|
522
|
+
XSIMD_RVV_OVERLOAD(rvvget_hi_, (__riscv_vget_ XSIMD_RVV_TSM), _DROP_1ST_CUSTOM_ARGS_NOVL, vec(T, wide_vec), args..., 1)
|
|
523
|
+
|
|
524
|
+
template <class T, size_t W, typename std::enable_if<W >= types::detail::rvv_width_m1, int>::type = 0>
|
|
525
|
+
rvv_reg_t<T, W> rvvget_lo(rvv_reg_t<T, W * 2> const& vv) noexcept
|
|
526
|
+
{
|
|
527
|
+
typename rvv_reg_t<T, W>::register_type tmp = rvvget_lo_(T {}, vv);
|
|
528
|
+
return tmp;
|
|
529
|
+
}
|
|
530
|
+
template <class T, size_t W, typename std::enable_if<W >= types::detail::rvv_width_m1, int>::type = 0>
|
|
531
|
+
rvv_reg_t<T, W> rvvget_hi(rvv_reg_t<T, W * 2> const& vv) noexcept
|
|
532
|
+
{
|
|
533
|
+
typename rvv_reg_t<T, W>::register_type tmp = rvvget_hi_(T {}, vv);
|
|
534
|
+
return tmp;
|
|
535
|
+
}
|
|
536
|
+
template <class T, size_t W, typename std::enable_if<W<types::detail::rvv_width_m1, int>::type = 0> rvv_reg_t<T, W> rvvget_lo(rvv_reg_t<T, W * 2> const& vv) noexcept
|
|
537
|
+
{
|
|
538
|
+
typename rvv_reg_t<T, W>::register_type tmp = vv;
|
|
539
|
+
return tmp;
|
|
540
|
+
}
|
|
541
|
+
template <class T, size_t W, typename std::enable_if<W<types::detail::rvv_width_m1, int>::type = 0> rvv_reg_t<T, W> rvvget_hi(rvv_reg_t<T, W * 2> const& vv) noexcept
|
|
542
|
+
{
|
|
543
|
+
return __riscv_vslidedown(vv, vv.vl / 2, vv.vl);
|
|
544
|
+
}
|
|
545
|
+
|
|
546
|
+
template <class A, class T, detail::rvv_enable_floating_point_t<T> = 0>
|
|
547
|
+
XSIMD_INLINE batch<std::complex<T>, A> load_complex(batch<T, A> const& lo, batch<T, A> const& hi, requires_arch<rvv>) noexcept
|
|
548
|
+
{
|
|
549
|
+
const auto real_index = vindex<A, as_unsigned_integer_t<T>, 0, 1>();
|
|
550
|
+
const auto imag_index = vindex<A, as_unsigned_integer_t<T>, 1, 1>();
|
|
551
|
+
const auto index = rvvabut<as_unsigned_integer_t<T>, A::width>(real_index, imag_index);
|
|
552
|
+
const auto input = rvvabut<T, A::width>(lo.data, hi.data);
|
|
553
|
+
const rvv_reg_t<T, A::width * 2> result = __riscv_vrgather(input, index, index.vl);
|
|
554
|
+
|
|
555
|
+
return { rvvget_lo<T, A::width>(result), rvvget_hi<T, A::width>(result) };
|
|
556
|
+
}
|
|
557
|
+
}
|
|
558
|
+
|
|
559
|
+
/*********
|
|
560
|
+
* Store *
|
|
561
|
+
*********/
|
|
562
|
+
|
|
563
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
564
|
+
XSIMD_INLINE void store_aligned(T* dst, batch<T, A> const& src, requires_arch<rvv>) noexcept
|
|
565
|
+
{
|
|
566
|
+
detail::rvvse(reinterpret_cast<detail::rvv_fix_char_t<T>*>(dst), src);
|
|
567
|
+
}
|
|
568
|
+
|
|
569
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
570
|
+
XSIMD_INLINE void store_unaligned(T* dst, batch<T, A> const& src, requires_arch<rvv>) noexcept
|
|
571
|
+
{
|
|
572
|
+
store_aligned<A>(dst, src, rvv {});
|
|
573
|
+
}
|
|
574
|
+
|
|
575
|
+
/******************
|
|
576
|
+
* scatter/gather *
|
|
577
|
+
******************/
|
|
578
|
+
|
|
579
|
+
namespace detail
|
|
580
|
+
{
|
|
581
|
+
template <class T, class U>
|
|
582
|
+
using rvv_enable_sg_t = typename std::enable_if<(sizeof(T) == sizeof(U) && (sizeof(T) == 4 || sizeof(T) == 8)), int>::type;
|
|
583
|
+
XSIMD_RVV_OVERLOAD(rvvloxei, (__riscv_vloxei XSIMD_RVV_S), , vec(T const*, uvec))
|
|
584
|
+
XSIMD_RVV_OVERLOAD(rvvsoxei, (__riscv_vsoxei XSIMD_RVV_S), , void(T*, uvec, vec))
|
|
585
|
+
XSIMD_RVV_OVERLOAD3(rvvmul_splat,
|
|
586
|
+
(__riscv_vmul),
|
|
587
|
+
(__riscv_vmul),
|
|
588
|
+
(__riscv_vfmul), , vec(vec, T))
|
|
589
|
+
}
|
|
590
|
+
|
|
591
|
+
// scatter
|
|
592
|
+
template <class A, class T, class U, detail::rvv_enable_sg_t<T, U> = 0>
|
|
593
|
+
XSIMD_INLINE void scatter(batch<T, A> const& vals, T* dst, batch<U, A> const& index, kernel::requires_arch<rvv>) noexcept
|
|
594
|
+
{
|
|
595
|
+
using UU = as_unsigned_integer_t<U>;
|
|
596
|
+
const auto uindex = detail::rvv_to_unsigned_batch(index);
|
|
597
|
+
auto* base = reinterpret_cast<detail::rvv_fix_char_t<T>*>(dst);
|
|
598
|
+
// or rvvsuxei
|
|
599
|
+
const auto bi = detail::rvvmul_splat(uindex, sizeof(T));
|
|
600
|
+
detail::rvvsoxei(base, bi, vals);
|
|
601
|
+
}
|
|
602
|
+
|
|
603
|
+
// gather
|
|
604
|
+
template <class A, class T, class U, detail::rvv_enable_sg_t<T, U> = 0>
|
|
605
|
+
XSIMD_INLINE batch<T, A> gather(batch<T, A> const&, T const* src, batch<U, A> const& index, kernel::requires_arch<rvv>) noexcept
|
|
606
|
+
{
|
|
607
|
+
using UU = as_unsigned_integer_t<U>;
|
|
608
|
+
const auto uindex = detail::rvv_to_unsigned_batch(index);
|
|
609
|
+
auto const* base = reinterpret_cast<detail::rvv_fix_char_t<T> const*>(src);
|
|
610
|
+
// or rvvluxei
|
|
611
|
+
const auto bi = detail::rvvmul_splat(uindex, sizeof(T));
|
|
612
|
+
return detail::rvvloxei(base, bi);
|
|
613
|
+
}
|
|
614
|
+
|
|
615
|
+
/**************
|
|
616
|
+
* Arithmetic *
|
|
617
|
+
**************/
|
|
618
|
+
|
|
619
|
+
namespace detail
|
|
620
|
+
{
|
|
621
|
+
XSIMD_RVV_OVERLOAD3(rvvadd,
|
|
622
|
+
(__riscv_vadd),
|
|
623
|
+
(__riscv_vadd),
|
|
624
|
+
(__riscv_vfadd), , vec(vec, vec))
|
|
625
|
+
XSIMD_RVV_OVERLOAD2(rvvsadd,
|
|
626
|
+
(__riscv_vsadd),
|
|
627
|
+
(__riscv_vsaddu), , vec(vec, vec))
|
|
628
|
+
XSIMD_RVV_OVERLOAD3(rvvsub,
|
|
629
|
+
(__riscv_vsub),
|
|
630
|
+
(__riscv_vsub),
|
|
631
|
+
(__riscv_vfsub), , vec(vec, vec))
|
|
632
|
+
XSIMD_RVV_OVERLOAD2(rvvssub,
|
|
633
|
+
(__riscv_vssub),
|
|
634
|
+
(__riscv_vssubu), , vec(vec, vec))
|
|
635
|
+
XSIMD_RVV_OVERLOAD2(rvvaadd,
|
|
636
|
+
(__riscv_vaadd),
|
|
637
|
+
(__riscv_vaaddu), , vec(vec, vec))
|
|
638
|
+
XSIMD_RVV_OVERLOAD3(rvvmul,
|
|
639
|
+
(__riscv_vmul),
|
|
640
|
+
(__riscv_vmul),
|
|
641
|
+
(__riscv_vfmul), , vec(vec, vec))
|
|
642
|
+
XSIMD_RVV_OVERLOAD3(rvvdiv,
|
|
643
|
+
(__riscv_vdiv),
|
|
644
|
+
(__riscv_vdivu),
|
|
645
|
+
(__riscv_vfdiv), , vec(vec, vec))
|
|
646
|
+
XSIMD_RVV_OVERLOAD3(rvvmax,
|
|
647
|
+
(__riscv_vmax),
|
|
648
|
+
(__riscv_vmaxu),
|
|
649
|
+
(__riscv_vfmax), , vec(vec, vec))
|
|
650
|
+
XSIMD_RVV_OVERLOAD3(rvvmin,
|
|
651
|
+
(__riscv_vmin),
|
|
652
|
+
(__riscv_vminu),
|
|
653
|
+
(__riscv_vfmin), , vec(vec, vec))
|
|
654
|
+
XSIMD_RVV_OVERLOAD3(rvvneg,
|
|
655
|
+
(__riscv_vneg),
|
|
656
|
+
(abort),
|
|
657
|
+
(__riscv_vfneg), , vec(vec))
|
|
658
|
+
XSIMD_RVV_OVERLOAD_FLOATS(rvvabs,
|
|
659
|
+
(__riscv_vfabs), , vec(vec))
|
|
660
|
+
XSIMD_RVV_OVERLOAD3(rvvmacc,
|
|
661
|
+
(__riscv_vmacc),
|
|
662
|
+
(__riscv_vmacc),
|
|
663
|
+
(__riscv_vfmacc), , vec(vec, vec, vec))
|
|
664
|
+
XSIMD_RVV_OVERLOAD3(rvvnmsac,
|
|
665
|
+
(__riscv_vnmsac),
|
|
666
|
+
(__riscv_vnmsac),
|
|
667
|
+
(__riscv_vfnmsac), , vec(vec, vec, vec))
|
|
668
|
+
XSIMD_RVV_OVERLOAD3(rvvmadd,
|
|
669
|
+
(__riscv_vmadd),
|
|
670
|
+
(__riscv_vmadd),
|
|
671
|
+
(__riscv_vfmadd), , vec(vec, vec, vec))
|
|
672
|
+
XSIMD_RVV_OVERLOAD3(rvvnmsub,
|
|
673
|
+
(__riscv_vnmsub),
|
|
674
|
+
(__riscv_vnmsub),
|
|
675
|
+
(__riscv_vfnmsub), , vec(vec, vec, vec))
|
|
676
|
+
|
|
677
|
+
#define RISCV_VMSXX(XX) \
|
|
678
|
+
XSIMD_RVV_OVERLOAD3(rvvms##XX, \
|
|
679
|
+
(__riscv_vms##XX), \
|
|
680
|
+
(__riscv_vms##XX##u), \
|
|
681
|
+
(__riscv_vmf##XX), , bvec(vec, vec)) \
|
|
682
|
+
XSIMD_RVV_OVERLOAD3(rvvms##XX##_splat, \
|
|
683
|
+
(__riscv_vms##XX), \
|
|
684
|
+
(__riscv_vms##XX##u), \
|
|
685
|
+
(__riscv_vmf##XX), , bvec(vec, T))
|
|
686
|
+
#define __riscv_vmsequ __riscv_vmseq
|
|
687
|
+
#define __riscv_vmsneu __riscv_vmsne
|
|
688
|
+
RISCV_VMSXX(eq)
|
|
689
|
+
RISCV_VMSXX(ne)
|
|
690
|
+
RISCV_VMSXX(lt)
|
|
691
|
+
RISCV_VMSXX(le)
|
|
692
|
+
RISCV_VMSXX(gt)
|
|
693
|
+
RISCV_VMSXX(ge)
|
|
694
|
+
#undef __riscv_vmsequ
|
|
695
|
+
#undef __riscv_vmsneu
|
|
696
|
+
#undef RISCV_VMSXX
|
|
697
|
+
} // namespace detail
|
|
698
|
+
|
|
699
|
+
// add
|
|
700
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
701
|
+
XSIMD_INLINE batch<T, A> add(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
702
|
+
{
|
|
703
|
+
return detail::rvvadd(lhs, rhs);
|
|
704
|
+
}
|
|
705
|
+
|
|
706
|
+
// sadd
|
|
707
|
+
template <class A, class T, detail::enable_integral_t<T> = 0>
|
|
708
|
+
XSIMD_INLINE batch<T, A> sadd(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
709
|
+
{
|
|
710
|
+
return detail::rvvsadd(lhs, rhs);
|
|
711
|
+
}
|
|
712
|
+
|
|
713
|
+
// sub
|
|
714
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
715
|
+
XSIMD_INLINE batch<T, A> sub(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
716
|
+
{
|
|
717
|
+
return detail::rvvsub(lhs, rhs);
|
|
718
|
+
}
|
|
719
|
+
|
|
720
|
+
// ssub
|
|
721
|
+
template <class A, class T, detail::enable_integral_t<T> = 0>
|
|
722
|
+
XSIMD_INLINE batch<T, A> ssub(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
723
|
+
{
|
|
724
|
+
return detail::rvvssub(lhs, rhs);
|
|
725
|
+
}
|
|
726
|
+
|
|
727
|
+
// mul
|
|
728
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
729
|
+
XSIMD_INLINE batch<T, A> mul(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
730
|
+
{
|
|
731
|
+
return detail::rvvmul(lhs, rhs);
|
|
732
|
+
}
|
|
733
|
+
|
|
734
|
+
// div
|
|
735
|
+
template <class A, class T, typename detail::rvv_enable_all_t<T> = 0>
|
|
736
|
+
XSIMD_INLINE batch<T, A> div(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
737
|
+
{
|
|
738
|
+
return detail::rvvdiv(lhs, rhs);
|
|
739
|
+
}
|
|
740
|
+
|
|
741
|
+
// max
|
|
742
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
743
|
+
XSIMD_INLINE batch<T, A> max(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
744
|
+
{
|
|
745
|
+
return detail::rvvmax(lhs, rhs);
|
|
746
|
+
}
|
|
747
|
+
|
|
748
|
+
// min
|
|
749
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
750
|
+
XSIMD_INLINE batch<T, A> min(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
751
|
+
{
|
|
752
|
+
return detail::rvvmin(lhs, rhs);
|
|
753
|
+
}
|
|
754
|
+
|
|
755
|
+
// neg
|
|
756
|
+
template <class A, class T, detail::rvv_enable_unsigned_int_t<T> = 0>
|
|
757
|
+
XSIMD_INLINE batch<T, A> neg(batch<T, A> const& arg, requires_arch<rvv>) noexcept
|
|
758
|
+
{
|
|
759
|
+
using S = as_signed_integer_t<T>;
|
|
760
|
+
const auto as_signed = detail::rvvreinterpret<S>(arg);
|
|
761
|
+
const auto result = detail::rvvneg(as_signed);
|
|
762
|
+
return detail::rvvreinterpret<T>(result);
|
|
763
|
+
}
|
|
764
|
+
|
|
765
|
+
template <class A, class T, detail::rvv_enable_signed_int_or_floating_point_t<T> = 0>
|
|
766
|
+
XSIMD_INLINE batch<T, A> neg(batch<T, A> const& arg, requires_arch<rvv>) noexcept
|
|
767
|
+
{
|
|
768
|
+
return detail::rvvneg(arg);
|
|
769
|
+
}
|
|
770
|
+
|
|
771
|
+
// abs
|
|
772
|
+
template <class A, class T, detail::rvv_enable_unsigned_int_t<T> = 0>
|
|
773
|
+
XSIMD_INLINE batch<T, A> abs(batch<T, A> const& arg, requires_arch<rvv>) noexcept
|
|
774
|
+
{
|
|
775
|
+
return arg;
|
|
776
|
+
}
|
|
777
|
+
|
|
778
|
+
template <class A, class T, detail::rvv_enable_floating_point_t<T> = 0>
|
|
779
|
+
XSIMD_INLINE batch<T, A> abs(batch<T, A> const& arg, requires_arch<rvv>) noexcept
|
|
780
|
+
{
|
|
781
|
+
return detail::rvvabs(arg);
|
|
782
|
+
}
|
|
783
|
+
|
|
784
|
+
// fma: x * y + z
|
|
785
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
786
|
+
XSIMD_INLINE batch<T, A> fma(batch<T, A> const& x, batch<T, A> const& y, batch<T, A> const& z, requires_arch<rvv>) noexcept
|
|
787
|
+
{
|
|
788
|
+
// also detail::rvvmadd(x, y, z);
|
|
789
|
+
return detail::rvvmacc(z, x, y);
|
|
790
|
+
}
|
|
791
|
+
|
|
792
|
+
// fnma: z - x * y
|
|
793
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
794
|
+
XSIMD_INLINE batch<T, A> fnma(batch<T, A> const& x, batch<T, A> const& y, batch<T, A> const& z, requires_arch<rvv>) noexcept
|
|
795
|
+
{
|
|
796
|
+
// also detail::rvvnmsub(x, y, z);
|
|
797
|
+
return detail::rvvnmsac(z, x, y);
|
|
798
|
+
}
|
|
799
|
+
|
|
800
|
+
// fms: x * y - z
|
|
801
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
802
|
+
XSIMD_INLINE batch<T, A> fms(batch<T, A> const& x, batch<T, A> const& y, batch<T, A> const& z, requires_arch<rvv>) noexcept
|
|
803
|
+
{
|
|
804
|
+
// also vfmsac(z, x, y), but lacking integer version
|
|
805
|
+
// also vfmsub(x, y, z), but lacking integer version
|
|
806
|
+
return -fnma(x, y, z);
|
|
807
|
+
}
|
|
808
|
+
|
|
809
|
+
// fnms: - x * y - z
|
|
810
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
811
|
+
XSIMD_INLINE batch<T, A> fnms(batch<T, A> const& x, batch<T, A> const& y, batch<T, A> const& z, requires_arch<rvv>) noexcept
|
|
812
|
+
{
|
|
813
|
+
// also vfnmacc(z, x, y), but lacking integer version
|
|
814
|
+
// also vfnmadd(x, y, z), but lacking integer version
|
|
815
|
+
return -fma(z, x, y);
|
|
816
|
+
}
|
|
817
|
+
|
|
818
|
+
/**********************
|
|
819
|
+
* Logical operations *
|
|
820
|
+
**********************/
|
|
821
|
+
|
|
822
|
+
namespace detail
|
|
823
|
+
{
|
|
824
|
+
XSIMD_RVV_OVERLOAD_INTS(rvvand, (__riscv_vand), , vec(vec, vec))
|
|
825
|
+
XSIMD_RVV_OVERLOAD_INTS(rvvor, (__riscv_vor), , vec(vec, vec))
|
|
826
|
+
XSIMD_RVV_OVERLOAD_INTS(rvvor_splat, (__riscv_vor), , vec(vec, T))
|
|
827
|
+
XSIMD_RVV_OVERLOAD_INTS(rvvxor, (__riscv_vxor), , vec(vec, vec))
|
|
828
|
+
XSIMD_RVV_OVERLOAD_INTS(rvvnot, (__riscv_vnot), , vec(vec))
|
|
829
|
+
XSIMD_RVV_OVERLOAD(rvvmand, (__riscv_vmand_mm_b XSIMD_RVV_S), , bvec(bvec, bvec))
|
|
830
|
+
XSIMD_RVV_OVERLOAD(rvvmor, (__riscv_vmor_mm_b XSIMD_RVV_S), , bvec(bvec, bvec))
|
|
831
|
+
XSIMD_RVV_OVERLOAD(rvvmxor, (__riscv_vmxor_mm_b XSIMD_RVV_S), , bvec(bvec, bvec))
|
|
832
|
+
XSIMD_RVV_OVERLOAD(rvvmandn, (__riscv_vmandn_mm_b XSIMD_RVV_S), , bvec(bvec, bvec))
|
|
833
|
+
XSIMD_RVV_OVERLOAD(rvvmnot, (__riscv_vmnot), , bvec(bvec))
|
|
834
|
+
}
|
|
835
|
+
|
|
836
|
+
// bitwise_and
|
|
837
|
+
template <class A, class T, detail::enable_integral_t<T> = 0>
|
|
838
|
+
XSIMD_INLINE batch<T, A> bitwise_and(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
839
|
+
{
|
|
840
|
+
return detail::rvvand(lhs, rhs);
|
|
841
|
+
}
|
|
842
|
+
|
|
843
|
+
template <class A, class T, detail::rvv_enable_floating_point_t<T> = 0>
|
|
844
|
+
XSIMD_INLINE batch<T, A> bitwise_and(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
845
|
+
{
|
|
846
|
+
const auto lhs_bits = detail::rvv_to_unsigned_batch(lhs);
|
|
847
|
+
const auto rhs_bits = detail::rvv_to_unsigned_batch(rhs);
|
|
848
|
+
const auto result_bits = detail::rvvand(lhs_bits, rhs_bits);
|
|
849
|
+
return detail::rvvreinterpret<T>(result_bits);
|
|
850
|
+
}
|
|
851
|
+
|
|
852
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
853
|
+
XSIMD_INLINE batch_bool<T, A> bitwise_and(batch_bool<T, A> const& lhs, batch_bool<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
854
|
+
{
|
|
855
|
+
return detail::rvvmand(lhs, rhs);
|
|
856
|
+
}
|
|
857
|
+
|
|
858
|
+
// bitwise_andnot
|
|
859
|
+
template <class A, class T, detail::enable_integral_t<T> = 0>
|
|
860
|
+
XSIMD_INLINE batch<T, A> bitwise_andnot(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
861
|
+
{
|
|
862
|
+
const auto not_rhs = detail::rvvnot(rhs);
|
|
863
|
+
return detail::rvvand(lhs, not_rhs);
|
|
864
|
+
}
|
|
865
|
+
|
|
866
|
+
template <class A, class T, detail::rvv_enable_floating_point_t<T> = 0>
|
|
867
|
+
XSIMD_INLINE batch<T, A> bitwise_andnot(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
868
|
+
{
|
|
869
|
+
const auto lhs_bits = detail::rvv_to_unsigned_batch(lhs);
|
|
870
|
+
const auto rhs_bits = detail::rvv_to_unsigned_batch(rhs);
|
|
871
|
+
const auto not_rhs = detail::rvvnot(rhs_bits);
|
|
872
|
+
const auto result_bits = detail::rvvand(lhs_bits, not_rhs);
|
|
873
|
+
return detail::rvvreinterpret<T>(result_bits);
|
|
874
|
+
}
|
|
875
|
+
|
|
876
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
877
|
+
XSIMD_INLINE batch_bool<T, A> bitwise_andnot(batch_bool<T, A> const& lhs, batch_bool<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
878
|
+
{
|
|
879
|
+
return detail::rvvmandn(lhs, rhs);
|
|
880
|
+
}
|
|
881
|
+
|
|
882
|
+
// bitwise_or
|
|
883
|
+
template <class A, class T, detail::enable_integral_t<T> = 0>
|
|
884
|
+
XSIMD_INLINE batch<T, A> bitwise_or(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
885
|
+
{
|
|
886
|
+
return detail::rvvor(lhs, rhs);
|
|
887
|
+
}
|
|
888
|
+
|
|
889
|
+
template <class A, class T, detail::rvv_enable_floating_point_t<T> = 0>
|
|
890
|
+
XSIMD_INLINE batch<T, A> bitwise_or(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
891
|
+
{
|
|
892
|
+
const auto lhs_bits = detail::rvv_to_unsigned_batch(lhs);
|
|
893
|
+
const auto rhs_bits = detail::rvv_to_unsigned_batch(rhs);
|
|
894
|
+
const auto result_bits = detail::rvvor(lhs_bits, rhs_bits);
|
|
895
|
+
return detail::rvvreinterpret<T>(result_bits);
|
|
896
|
+
}
|
|
897
|
+
|
|
898
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
899
|
+
XSIMD_INLINE batch_bool<T, A> bitwise_or(batch_bool<T, A> const& lhs, batch_bool<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
900
|
+
{
|
|
901
|
+
return detail::rvvmor(lhs, rhs);
|
|
902
|
+
}
|
|
903
|
+
|
|
904
|
+
// bitwise_xor
|
|
905
|
+
template <class A, class T, detail::enable_integral_t<T> = 0>
|
|
906
|
+
XSIMD_INLINE batch<T, A> bitwise_xor(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
907
|
+
{
|
|
908
|
+
return detail::rvvxor(lhs, rhs);
|
|
909
|
+
}
|
|
910
|
+
|
|
911
|
+
template <class A, class T, detail::rvv_enable_floating_point_t<T> = 0>
|
|
912
|
+
XSIMD_INLINE batch<T, A> bitwise_xor(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
913
|
+
{
|
|
914
|
+
const auto lhs_bits = detail::rvv_to_unsigned_batch(lhs);
|
|
915
|
+
const auto rhs_bits = detail::rvv_to_unsigned_batch(rhs);
|
|
916
|
+
const auto result_bits = detail::rvvxor(lhs_bits, rhs_bits);
|
|
917
|
+
return detail::rvvreinterpret<T>(result_bits);
|
|
918
|
+
}
|
|
919
|
+
|
|
920
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
921
|
+
XSIMD_INLINE batch_bool<T, A> bitwise_xor(batch_bool<T, A> const& lhs, batch_bool<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
922
|
+
{
|
|
923
|
+
return detail::rvvmxor(lhs, rhs);
|
|
924
|
+
}
|
|
925
|
+
|
|
926
|
+
// bitwise_not
|
|
927
|
+
template <class A, class T, detail::enable_integral_t<T> = 0>
|
|
928
|
+
XSIMD_INLINE batch<T, A> bitwise_not(batch<T, A> const& arg, requires_arch<rvv>) noexcept
|
|
929
|
+
{
|
|
930
|
+
return detail::rvvnot(arg);
|
|
931
|
+
}
|
|
932
|
+
|
|
933
|
+
template <class A, class T, detail::rvv_enable_floating_point_t<T> = 0>
|
|
934
|
+
XSIMD_INLINE batch<T, A> bitwise_not(batch<T, A> const& arg, requires_arch<rvv>) noexcept
|
|
935
|
+
{
|
|
936
|
+
const auto arg_bits = detail::rvv_to_unsigned_batch(arg);
|
|
937
|
+
const auto result_bits = detail::rvvnot(arg_bits);
|
|
938
|
+
return detail::rvvreinterpret<T>(result_bits);
|
|
939
|
+
}
|
|
940
|
+
|
|
941
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
942
|
+
XSIMD_INLINE batch_bool<T, A> bitwise_not(batch_bool<T, A> const& arg, requires_arch<rvv>) noexcept
|
|
943
|
+
{
|
|
944
|
+
return detail::rvvmnot(arg);
|
|
945
|
+
}
|
|
946
|
+
|
|
947
|
+
/**********
|
|
948
|
+
* Shifts *
|
|
949
|
+
**********/
|
|
950
|
+
|
|
951
|
+
namespace detail
|
|
952
|
+
{
|
|
953
|
+
XSIMD_RVV_OVERLOAD_INTS(rvvsll_splat, (__riscv_vsll), , vec(vec, size_t))
|
|
954
|
+
XSIMD_RVV_OVERLOAD_INTS(rvvsll, (__riscv_vsll), , vec(vec, uvec))
|
|
955
|
+
XSIMD_RVV_OVERLOAD2(rvvsr_splat,
|
|
956
|
+
(__riscv_vsra),
|
|
957
|
+
(__riscv_vsrl), , vec(vec, size_t))
|
|
958
|
+
XSIMD_RVV_OVERLOAD2(rvvsr,
|
|
959
|
+
(__riscv_vsra),
|
|
960
|
+
(__riscv_vsrl), , vec(vec, uvec))
|
|
961
|
+
} // namespace detail
|
|
962
|
+
|
|
963
|
+
// bitwise_lshift
|
|
964
|
+
template <class A, class T, detail::enable_integral_t<T> = 0>
|
|
965
|
+
XSIMD_INLINE batch<T, A> bitwise_lshift(batch<T, A> const& arg, int n, requires_arch<rvv>) noexcept
|
|
966
|
+
{
|
|
967
|
+
constexpr size_t size = sizeof(typename batch<T, A>::value_type) * 8;
|
|
968
|
+
assert(0 <= n && static_cast<size_t>(n) < size && "index in bounds");
|
|
969
|
+
return detail::rvvsll_splat(arg, n);
|
|
970
|
+
}
|
|
971
|
+
|
|
972
|
+
template <class A, class T, detail::enable_integral_t<T> = 0>
|
|
973
|
+
XSIMD_INLINE batch<T, A> bitwise_lshift(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
974
|
+
{
|
|
975
|
+
return detail::rvvsll(lhs, detail::rvv_to_unsigned_batch<A, T>(rhs));
|
|
976
|
+
}
|
|
977
|
+
|
|
978
|
+
// bitwise_rshift
|
|
979
|
+
template <class A, class T, detail::enable_integral_t<T> = 0>
|
|
980
|
+
XSIMD_INLINE batch<T, A> bitwise_rshift(batch<T, A> const& arg, int n, requires_arch<rvv>) noexcept
|
|
981
|
+
{
|
|
982
|
+
constexpr size_t size = sizeof(typename batch<T, A>::value_type) * 8;
|
|
983
|
+
assert(0 <= n && static_cast<size_t>(n) < size && "index in bounds");
|
|
984
|
+
return detail::rvvsr_splat(arg, n);
|
|
985
|
+
}
|
|
986
|
+
|
|
987
|
+
template <class A, class T, detail::enable_integral_t<T> = 0>
|
|
988
|
+
XSIMD_INLINE batch<T, A> bitwise_rshift(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
989
|
+
{
|
|
990
|
+
return detail::rvvsr(lhs, detail::rvv_to_unsigned_batch<A, T>(rhs));
|
|
991
|
+
}
|
|
992
|
+
|
|
993
|
+
/**************
|
|
994
|
+
* Reductions *
|
|
995
|
+
**************/
|
|
996
|
+
|
|
997
|
+
namespace detail
|
|
998
|
+
{
|
|
999
|
+
XSIMD_RVV_OVERLOAD3(rvvredsum,
|
|
1000
|
+
(__riscv_vredsum),
|
|
1001
|
+
(__riscv_vredsum),
|
|
1002
|
+
(__riscv_vfredosum), // or __riscv_vfredusum
|
|
1003
|
+
, scalar_vec(vec, scalar_vec))
|
|
1004
|
+
XSIMD_RVV_OVERLOAD3(rvvredmax,
|
|
1005
|
+
(__riscv_vredmax),
|
|
1006
|
+
(__riscv_vredmaxu),
|
|
1007
|
+
(__riscv_vfredmax), , scalar_vec(vec, scalar_vec))
|
|
1008
|
+
XSIMD_RVV_OVERLOAD3(rvvredmin,
|
|
1009
|
+
(__riscv_vredmin),
|
|
1010
|
+
(__riscv_vredminu),
|
|
1011
|
+
(__riscv_vfredmin), , scalar_vec(vec, scalar_vec))
|
|
1012
|
+
XSIMD_RVV_OVERLOAD3(rvvslide1up,
|
|
1013
|
+
(__riscv_vslide1up),
|
|
1014
|
+
(__riscv_vslide1up),
|
|
1015
|
+
(__riscv_vfslide1up), , vec(vec, vec))
|
|
1016
|
+
XSIMD_RVV_OVERLOAD3(rvvslide1down,
|
|
1017
|
+
(__riscv_vslide1down),
|
|
1018
|
+
(__riscv_vslide1down),
|
|
1019
|
+
(__riscv_vfslide1down), , vec(vec, T))
|
|
1020
|
+
|
|
1021
|
+
template <class A, class T>
|
|
1022
|
+
XSIMD_INLINE T reduce_scalar(rvv_reg_t<T, types::detail::rvv_width_m1> const& arg)
|
|
1023
|
+
{
|
|
1024
|
+
return detail::rvvmv_lane0(rvv_reg_t<T, A::width>(arg.get_bytes(), types::detail::XSIMD_RVV_BITCAST));
|
|
1025
|
+
}
|
|
1026
|
+
}
|
|
1027
|
+
// reduce_add
|
|
1028
|
+
template <class A, class T, class V = typename batch<T, A>::value_type, detail::rvv_enable_all_t<T> = 0>
|
|
1029
|
+
XSIMD_INLINE V reduce_add(batch<T, A> const& arg, requires_arch<rvv>) noexcept
|
|
1030
|
+
{
|
|
1031
|
+
const auto zero = detail::broadcast<T, types::detail::rvv_width_m1>(T(0));
|
|
1032
|
+
const auto r = detail::rvvredsum(arg, zero);
|
|
1033
|
+
return detail::reduce_scalar<A, T>(r);
|
|
1034
|
+
}
|
|
1035
|
+
|
|
1036
|
+
// reduce_max
|
|
1037
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
1038
|
+
XSIMD_INLINE T reduce_max(batch<T, A> const& arg, requires_arch<rvv>) noexcept
|
|
1039
|
+
{
|
|
1040
|
+
const auto lowest = detail::broadcast<T, types::detail::rvv_width_m1>(std::numeric_limits<T>::lowest());
|
|
1041
|
+
const auto r = detail::rvvredmax(arg, lowest);
|
|
1042
|
+
return detail::reduce_scalar<A, T>(r);
|
|
1043
|
+
}
|
|
1044
|
+
|
|
1045
|
+
// reduce_min
|
|
1046
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
1047
|
+
XSIMD_INLINE T reduce_min(batch<T, A> const& arg, requires_arch<rvv>) noexcept
|
|
1048
|
+
{
|
|
1049
|
+
const auto max = detail::broadcast<T, types::detail::rvv_width_m1>(std::numeric_limits<T>::max());
|
|
1050
|
+
const auto r = detail::rvvredmin(arg, max);
|
|
1051
|
+
return detail::reduce_scalar<A, T>(r);
|
|
1052
|
+
}
|
|
1053
|
+
|
|
1054
|
+
// haddp
|
|
1055
|
+
template <class A, class T, detail::rvv_enable_floating_point_t<T> = 0>
|
|
1056
|
+
XSIMD_INLINE batch<T, A> haddp(const batch<T, A>* row, requires_arch<rvv>) noexcept
|
|
1057
|
+
{
|
|
1058
|
+
constexpr std::size_t size = batch<T, A>::size;
|
|
1059
|
+
T sums[size];
|
|
1060
|
+
#pragma unroll size
|
|
1061
|
+
for (std::size_t i = 0; i < size; ++i)
|
|
1062
|
+
{
|
|
1063
|
+
sums[i] = reduce_add(row[i], rvv {});
|
|
1064
|
+
}
|
|
1065
|
+
return load_aligned<A>(sums, convert<T>(), rvv {});
|
|
1066
|
+
}
|
|
1067
|
+
|
|
1068
|
+
/***************
|
|
1069
|
+
* Comparisons *
|
|
1070
|
+
***************/
|
|
1071
|
+
|
|
1072
|
+
// eq
|
|
1073
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
1074
|
+
XSIMD_INLINE batch_bool<T, A> eq(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
1075
|
+
{
|
|
1076
|
+
return detail::rvvmseq(lhs, rhs);
|
|
1077
|
+
}
|
|
1078
|
+
|
|
1079
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
1080
|
+
XSIMD_INLINE batch_bool<T, A> eq(batch_bool<T, A> const& lhs, batch_bool<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
1081
|
+
{
|
|
1082
|
+
const auto neq_result = detail::rvvmxor(lhs, rhs);
|
|
1083
|
+
return detail::rvvmnot(neq_result);
|
|
1084
|
+
}
|
|
1085
|
+
|
|
1086
|
+
// neq
|
|
1087
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
1088
|
+
XSIMD_INLINE batch_bool<T, A> neq(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
1089
|
+
{
|
|
1090
|
+
return detail::rvvmsne(lhs, rhs);
|
|
1091
|
+
}
|
|
1092
|
+
|
|
1093
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
1094
|
+
XSIMD_INLINE batch_bool<T, A> neq(batch_bool<T, A> const& lhs, batch_bool<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
1095
|
+
{
|
|
1096
|
+
return detail::rvvmxor(lhs, rhs);
|
|
1097
|
+
}
|
|
1098
|
+
|
|
1099
|
+
// lt
|
|
1100
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
1101
|
+
XSIMD_INLINE batch_bool<T, A> lt(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
1102
|
+
{
|
|
1103
|
+
return detail::rvvmslt(lhs, rhs);
|
|
1104
|
+
}
|
|
1105
|
+
|
|
1106
|
+
// le
|
|
1107
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
1108
|
+
XSIMD_INLINE batch_bool<T, A> le(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
1109
|
+
{
|
|
1110
|
+
return detail::rvvmsle(lhs, rhs);
|
|
1111
|
+
}
|
|
1112
|
+
|
|
1113
|
+
// gt
|
|
1114
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
1115
|
+
XSIMD_INLINE batch_bool<T, A> gt(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
1116
|
+
{
|
|
1117
|
+
return detail::rvvmsgt(lhs, rhs);
|
|
1118
|
+
}
|
|
1119
|
+
|
|
1120
|
+
// ge
|
|
1121
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
1122
|
+
XSIMD_INLINE batch_bool<T, A> ge(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
1123
|
+
{
|
|
1124
|
+
return detail::rvvmsge(lhs, rhs);
|
|
1125
|
+
}
|
|
1126
|
+
|
|
1127
|
+
/*************
|
|
1128
|
+
* Selection *
|
|
1129
|
+
*************/
|
|
1130
|
+
namespace detail
|
|
1131
|
+
{
|
|
1132
|
+
XSIMD_RVV_OVERLOAD(rvvcompress, (__riscv_vcompress_tu), , vec(vec, vec, bvec))
|
|
1133
|
+
}
|
|
1134
|
+
// compress
|
|
1135
|
+
template <class A, class T>
|
|
1136
|
+
XSIMD_INLINE batch<T, A> compress(batch<T, A> const& x, batch_bool<T, A> const& mask, requires_arch<rvv>) noexcept
|
|
1137
|
+
{
|
|
1138
|
+
auto zero = broadcast<A>(T(0), rvv {});
|
|
1139
|
+
return detail::rvvcompress(zero, x, mask);
|
|
1140
|
+
}
|
|
1141
|
+
|
|
1142
|
+
/***************
|
|
1143
|
+
* Permutation *
|
|
1144
|
+
***************/
|
|
1145
|
+
namespace detail
|
|
1146
|
+
{
|
|
1147
|
+
XSIMD_RVV_OVERLOAD(rvvrgather, (__riscv_vrgather), , vec(vec, uvec))
|
|
1148
|
+
XSIMD_RVV_OVERLOAD(rvvslideup, (__riscv_vslideup), , vec(vec, vec, size_t))
|
|
1149
|
+
XSIMD_RVV_OVERLOAD(rvvslidedown, (__riscv_vslidedown), , vec(vec, size_t))
|
|
1150
|
+
}
|
|
1151
|
+
|
|
1152
|
+
// swizzle
|
|
1153
|
+
template <class A, class T, class I, I... idx>
|
|
1154
|
+
XSIMD_INLINE batch<T, A> swizzle(batch<T, A> const& arg, batch_constant<I, A, idx...>, requires_arch<rvv>) noexcept
|
|
1155
|
+
{
|
|
1156
|
+
static_assert(batch<T, A>::size == sizeof...(idx), "invalid swizzle indices");
|
|
1157
|
+
const batch<I, A> indices { idx... };
|
|
1158
|
+
return detail::rvvrgather(arg, indices);
|
|
1159
|
+
}
|
|
1160
|
+
|
|
1161
|
+
template <class A, class T, class I, I... idx>
|
|
1162
|
+
XSIMD_INLINE batch<std::complex<T>, A> swizzle(batch<std::complex<T>, A> const& self,
|
|
1163
|
+
batch_constant<I, A, idx...>,
|
|
1164
|
+
requires_arch<rvv>) noexcept
|
|
1165
|
+
{
|
|
1166
|
+
const auto real = swizzle(self.real(), batch_constant<I, A, idx...> {}, rvv {});
|
|
1167
|
+
const auto imag = swizzle(self.imag(), batch_constant<I, A, idx...> {}, rvv {});
|
|
1168
|
+
return batch<std::complex<T>>(real, imag);
|
|
1169
|
+
}
|
|
1170
|
+
|
|
1171
|
+
/*************
|
|
1172
|
+
* Selection *
|
|
1173
|
+
*************/
|
|
1174
|
+
|
|
1175
|
+
// extract_pair
|
|
1176
|
+
|
|
1177
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
1178
|
+
XSIMD_INLINE batch<T, A> extract_pair(batch<T, A> const& lhs, batch<T, A> const& rhs, size_t n, requires_arch<rvv>) noexcept
|
|
1179
|
+
{
|
|
1180
|
+
const auto tmp = detail::rvvslidedown(rhs, n);
|
|
1181
|
+
return detail::rvvslideup(tmp, lhs, lhs.size - n);
|
|
1182
|
+
}
|
|
1183
|
+
|
|
1184
|
+
// select
|
|
1185
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
1186
|
+
XSIMD_INLINE batch<T, A> select(batch_bool<T, A> const& cond, batch<T, A> const& a, batch<T, A> const& b, requires_arch<rvv>) noexcept
|
|
1187
|
+
{
|
|
1188
|
+
return detail::rvvmerge(b, a, cond);
|
|
1189
|
+
}
|
|
1190
|
+
|
|
1191
|
+
template <class A, class T, bool... b>
|
|
1192
|
+
XSIMD_INLINE batch<T, A> select(batch_bool_constant<T, A, b...> const&, batch<T, A> const& true_br, batch<T, A> const& false_br, requires_arch<rvv>) noexcept
|
|
1193
|
+
{
|
|
1194
|
+
return select(batch_bool<T, A> { b... }, true_br, false_br, rvv {});
|
|
1195
|
+
}
|
|
1196
|
+
|
|
1197
|
+
// zip_lo
|
|
1198
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
1199
|
+
XSIMD_INLINE batch<T, A> zip_lo(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
1200
|
+
{
|
|
1201
|
+
const auto index = detail::vindex<A, as_unsigned_integer_t<T>, 0, -1>();
|
|
1202
|
+
const auto mask = detail::pmask8<T, A::width>(0xaa);
|
|
1203
|
+
return detail::rvvmerge(detail::rvvrgather(lhs, index),
|
|
1204
|
+
detail::rvvrgather(rhs, index),
|
|
1205
|
+
mask);
|
|
1206
|
+
}
|
|
1207
|
+
|
|
1208
|
+
// zip_hi
|
|
1209
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
1210
|
+
XSIMD_INLINE batch<T, A> zip_hi(batch<T, A> const& lhs, batch<T, A> const& rhs, requires_arch<rvv>) noexcept
|
|
1211
|
+
{
|
|
1212
|
+
const auto index = detail::vindex<A, as_unsigned_integer_t<T>, batch<T, A>::size / 2, -1>();
|
|
1213
|
+
const auto mask = detail::pmask8<T, A::width>(0xaa);
|
|
1214
|
+
return detail::rvvmerge(detail::rvvrgather(lhs, index),
|
|
1215
|
+
detail::rvvrgather(rhs, index),
|
|
1216
|
+
mask);
|
|
1217
|
+
}
|
|
1218
|
+
|
|
1219
|
+
// store_complex
|
|
1220
|
+
template <class A, class T, detail::rvv_enable_floating_point_t<T> = 0>
|
|
1221
|
+
XSIMD_INLINE void store_complex_aligned(std::complex<T>* dst, batch<std::complex<T>, A> const& src, requires_arch<rvv>) noexcept
|
|
1222
|
+
{
|
|
1223
|
+
const auto lo = zip_lo(src.real(), src.imag());
|
|
1224
|
+
const auto hi = zip_hi(src.real(), src.imag());
|
|
1225
|
+
T* buf = reinterpret_cast<T*>(dst);
|
|
1226
|
+
store_aligned(buf, lo, rvv {});
|
|
1227
|
+
store_aligned(buf + lo.size, hi, rvv {});
|
|
1228
|
+
}
|
|
1229
|
+
|
|
1230
|
+
template <class A, class T, detail::rvv_enable_floating_point_t<T> = 0>
|
|
1231
|
+
XSIMD_INLINE void store_complex_unaligned(std::complex<T>* dst, batch<std::complex<T>, A> const& src, requires_arch<rvv>) noexcept
|
|
1232
|
+
{
|
|
1233
|
+
store_complex_aligned(dst, src, rvv {});
|
|
1234
|
+
}
|
|
1235
|
+
|
|
1236
|
+
/*****************************
|
|
1237
|
+
* Floating-point arithmetic *
|
|
1238
|
+
*****************************/
|
|
1239
|
+
|
|
1240
|
+
namespace detail
|
|
1241
|
+
{
|
|
1242
|
+
XSIMD_RVV_OVERLOAD_FLOATS(rvvfsqrt, (__riscv_vfsqrt), , vec(vec))
|
|
1243
|
+
XSIMD_RVV_OVERLOAD_FLOATS(rvvfrec7, (__riscv_vfrec7), , vec(vec))
|
|
1244
|
+
XSIMD_RVV_OVERLOAD_FLOATS(rvvfrsqrt7, (__riscv_vfrsqrt7), , vec(vec))
|
|
1245
|
+
}
|
|
1246
|
+
|
|
1247
|
+
// rsqrt
|
|
1248
|
+
template <class A, class T, detail::rvv_enable_floating_point_t<T> = 0>
|
|
1249
|
+
XSIMD_INLINE batch<T, A> rsqrt(batch<T, A> const& arg, requires_arch<rvv>) noexcept
|
|
1250
|
+
{
|
|
1251
|
+
auto approx = detail::rvvfrsqrt7(arg);
|
|
1252
|
+
approx = approx * (1.5 - (0.5 * arg * approx * approx));
|
|
1253
|
+
return approx;
|
|
1254
|
+
}
|
|
1255
|
+
|
|
1256
|
+
// sqrt
|
|
1257
|
+
template <class A, class T, detail::rvv_enable_floating_point_t<T> = 0>
|
|
1258
|
+
XSIMD_INLINE batch<T, A> sqrt(batch<T, A> const& arg, requires_arch<rvv>) noexcept
|
|
1259
|
+
{
|
|
1260
|
+
return detail::rvvfsqrt(arg);
|
|
1261
|
+
}
|
|
1262
|
+
|
|
1263
|
+
// reciprocal
|
|
1264
|
+
template <class A, class T, detail::rvv_enable_floating_point_t<T> = 0>
|
|
1265
|
+
XSIMD_INLINE batch<T, A> reciprocal(const batch<T, A>& arg, requires_arch<rvv>) noexcept
|
|
1266
|
+
{
|
|
1267
|
+
return detail::rvvfrec7(arg);
|
|
1268
|
+
}
|
|
1269
|
+
|
|
1270
|
+
/******************************
|
|
1271
|
+
* Floating-point conversions *
|
|
1272
|
+
******************************/
|
|
1273
|
+
|
|
1274
|
+
// fast_cast
|
|
1275
|
+
namespace detail
|
|
1276
|
+
{
|
|
1277
|
+
XSIMD_RVV_OVERLOAD2(rvvfcvt_rtz, // truncating conversion, like C.
|
|
1278
|
+
(__riscv_vfcvt_rtz_x),
|
|
1279
|
+
(__riscv_vfcvt_rtz_xu), _DROP_1ST, vec(T, fvec))
|
|
1280
|
+
XSIMD_RVV_OVERLOAD2(rvvfcvt_rne, // round to nearest, ties to even
|
|
1281
|
+
(__riscv_vfcvt_x),
|
|
1282
|
+
(__riscv_vfcvt_xu), _DROP_1ST_CUSTOM_ARGS, vec(T, fvec), args..., __RISCV_FRM_RNE)
|
|
1283
|
+
XSIMD_RVV_OVERLOAD2(rvvfcvt_rmm, // round to nearest, ties to max magnitude
|
|
1284
|
+
(__riscv_vfcvt_x),
|
|
1285
|
+
(__riscv_vfcvt_xu), _DROP_1ST_CUSTOM_ARGS, vec(T, fvec), args..., __RISCV_FRM_RMM)
|
|
1286
|
+
XSIMD_RVV_OVERLOAD2(rvvfcvt, // round to current rounding mode.
|
|
1287
|
+
(__riscv_vfcvt_x),
|
|
1288
|
+
(__riscv_vfcvt_xu), _DROP_1ST, vec(T, fvec))
|
|
1289
|
+
XSIMD_RVV_OVERLOAD_INTS(rvvfcvt_f, (__riscv_vfcvt_f), , fvec(vec))
|
|
1290
|
+
|
|
1291
|
+
template <class T, class U>
|
|
1292
|
+
using rvv_enable_ftoi_t = typename std::enable_if<(sizeof(T) == sizeof(U) && std::is_floating_point<T>::value && !std::is_floating_point<U>::value), int>::type;
|
|
1293
|
+
template <class T, class U>
|
|
1294
|
+
using rvv_enable_itof_t = typename std::enable_if<(sizeof(T) == sizeof(U) && !std::is_floating_point<T>::value && std::is_floating_point<U>::value), int>::type;
|
|
1295
|
+
|
|
1296
|
+
template <class A, class T, class U, rvv_enable_ftoi_t<T, U> = 0>
|
|
1297
|
+
XSIMD_INLINE batch<U, A> fast_cast(batch<T, A> const& arg, batch<U, A> const&, requires_arch<rvv>) noexcept
|
|
1298
|
+
{
|
|
1299
|
+
return rvvfcvt_rtz(U {}, arg);
|
|
1300
|
+
}
|
|
1301
|
+
template <class A, class T, class U, rvv_enable_itof_t<T, U> = 0>
|
|
1302
|
+
XSIMD_INLINE batch<U, A> fast_cast(batch<T, A> const& arg, batch<U, A> const&, requires_arch<rvv>) noexcept
|
|
1303
|
+
{
|
|
1304
|
+
return rvvfcvt_f(arg);
|
|
1305
|
+
}
|
|
1306
|
+
}
|
|
1307
|
+
|
|
1308
|
+
/*********
|
|
1309
|
+
* Miscs *
|
|
1310
|
+
*********/
|
|
1311
|
+
|
|
1312
|
+
// set
|
|
1313
|
+
template <class A, class T, class... Args>
|
|
1314
|
+
XSIMD_INLINE batch<T, A> set(batch<T, A> const&, requires_arch<rvv>, Args... args) noexcept
|
|
1315
|
+
{
|
|
1316
|
+
const std::array<T, batch<T, A>::size> tmp { args... };
|
|
1317
|
+
return load_unaligned<A>(tmp.data(), convert<T>(), rvv {});
|
|
1318
|
+
}
|
|
1319
|
+
|
|
1320
|
+
template <class A, class T, class... Args>
|
|
1321
|
+
XSIMD_INLINE batch<std::complex<T>, A> set(batch<std::complex<T>, A> const&, requires_arch<rvv>,
|
|
1322
|
+
Args... args_complex) noexcept
|
|
1323
|
+
{
|
|
1324
|
+
return batch<std::complex<T>>(set(batch<T, rvv> {}, rvv {}, args_complex.real()...),
|
|
1325
|
+
set(batch<T, rvv> {}, rvv {}, args_complex.imag()...));
|
|
1326
|
+
}
|
|
1327
|
+
|
|
1328
|
+
template <class A, class T, class... Args>
|
|
1329
|
+
XSIMD_INLINE batch_bool<T, A> set(batch_bool<T, A> const&, requires_arch<rvv>, Args... args) noexcept
|
|
1330
|
+
{
|
|
1331
|
+
using U = as_unsigned_integer_t<T>;
|
|
1332
|
+
const auto values = set(batch<U, rvv> {}, rvv {}, static_cast<U>(args)...);
|
|
1333
|
+
const auto zero = broadcast<A>(U(0), rvv {});
|
|
1334
|
+
detail::rvv_bool_t<T> result = detail::rvvmsne(values, zero);
|
|
1335
|
+
return result;
|
|
1336
|
+
}
|
|
1337
|
+
|
|
1338
|
+
// first
|
|
1339
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
1340
|
+
XSIMD_INLINE T first(batch<T, A> const& arg, requires_arch<rvv>) noexcept
|
|
1341
|
+
{
|
|
1342
|
+
return detail::rvvmv_lane0(arg);
|
|
1343
|
+
}
|
|
1344
|
+
|
|
1345
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
1346
|
+
XSIMD_INLINE std::complex<T> first(batch<std::complex<T>, A> const& arg, requires_arch<rvv>) noexcept
|
|
1347
|
+
{
|
|
1348
|
+
return std::complex<T> { detail::rvvmv_lane0(arg.real()), detail::rvvmv_lane0(arg.imag()) };
|
|
1349
|
+
}
|
|
1350
|
+
|
|
1351
|
+
// insert
|
|
1352
|
+
template <class A, class T, size_t I, detail::rvv_enable_all_t<T> = 0>
|
|
1353
|
+
XSIMD_INLINE batch<T, A> insert(batch<T, A> const& arg, T val, index<I>, requires_arch<rvv>) noexcept
|
|
1354
|
+
{
|
|
1355
|
+
const auto mask = detail::pmask<T, A::width>(uint64_t(1) << I);
|
|
1356
|
+
return detail::rvvmerge_splat(arg, val, mask);
|
|
1357
|
+
}
|
|
1358
|
+
|
|
1359
|
+
// get
|
|
1360
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
1361
|
+
XSIMD_INLINE T get(batch<T, A> const& arg, size_t i, requires_arch<rvv>) noexcept
|
|
1362
|
+
{
|
|
1363
|
+
const auto tmp = detail::rvvslidedown(arg, i);
|
|
1364
|
+
return detail::rvvmv_lane0(tmp);
|
|
1365
|
+
}
|
|
1366
|
+
|
|
1367
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
1368
|
+
XSIMD_INLINE std::complex<T> get(batch<std::complex<T>, A> const& arg, size_t i, requires_arch<rvv>) noexcept
|
|
1369
|
+
{
|
|
1370
|
+
const auto tmpr = detail::rvvslidedown(arg.real(), i);
|
|
1371
|
+
const auto tmpi = detail::rvvslidedown(arg.imag(), i);
|
|
1372
|
+
return std::complex<T> { detail::rvvmv_lane0(tmpr), detail::rvvmv_lane0(tmpi) };
|
|
1373
|
+
}
|
|
1374
|
+
|
|
1375
|
+
// all
|
|
1376
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
1377
|
+
XSIMD_INLINE bool all(batch_bool<T, A> const& arg, requires_arch<rvv>) noexcept
|
|
1378
|
+
{
|
|
1379
|
+
return detail::rvvcpop(arg) == batch_bool<T, A>::size;
|
|
1380
|
+
}
|
|
1381
|
+
|
|
1382
|
+
// any
|
|
1383
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
1384
|
+
XSIMD_INLINE bool any(batch_bool<T, A> const& arg, requires_arch<rvv>) noexcept
|
|
1385
|
+
{
|
|
1386
|
+
return detail::rvvcpop(arg) > 0;
|
|
1387
|
+
}
|
|
1388
|
+
|
|
1389
|
+
// bitwise_cast
|
|
1390
|
+
template <class A, class T, class R, detail::rvv_enable_all_t<T> = 0, detail::rvv_enable_all_t<R> = 0>
|
|
1391
|
+
XSIMD_INLINE batch<R, A> bitwise_cast(batch<T, A> const& arg, batch<R, A> const&, requires_arch<rvv>) noexcept
|
|
1392
|
+
{
|
|
1393
|
+
return detail::rvv_reg_t<R, A::width>(arg.data.get_bytes(), types::detail::XSIMD_RVV_BITCAST);
|
|
1394
|
+
}
|
|
1395
|
+
|
|
1396
|
+
// batch_bool_cast
|
|
1397
|
+
template <class A, class T_out, class T_in, detail::rvv_enable_all_t<T_in> = 0>
|
|
1398
|
+
XSIMD_INLINE batch_bool<T_out, A> batch_bool_cast(batch_bool<T_in, A> const& arg, batch_bool<T_out, A> const&, requires_arch<rvv>) noexcept
|
|
1399
|
+
{
|
|
1400
|
+
using intermediate_t = typename detail::rvv_bool_t<T_out>;
|
|
1401
|
+
return intermediate_t(arg.data);
|
|
1402
|
+
}
|
|
1403
|
+
|
|
1404
|
+
// from_bool
|
|
1405
|
+
template <class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
1406
|
+
XSIMD_INLINE batch<T, A> from_bool(batch_bool<T, A> const& arg, requires_arch<rvv>) noexcept
|
|
1407
|
+
{
|
|
1408
|
+
const auto zero = broadcast<A>(T(0), rvv {});
|
|
1409
|
+
return detail::rvvmerge_splat(zero, T(1), arg);
|
|
1410
|
+
}
|
|
1411
|
+
|
|
1412
|
+
namespace detail
|
|
1413
|
+
{
|
|
1414
|
+
template <size_t Width>
|
|
1415
|
+
XSIMD_INLINE vuint8m1_t rvvslidedownbytes(vuint8m1_t arg, size_t i)
|
|
1416
|
+
{
|
|
1417
|
+
return __riscv_vslidedown(arg, i, types::detail::rvv_width_m1 / 8);
|
|
1418
|
+
}
|
|
1419
|
+
template <>
|
|
1420
|
+
XSIMD_INLINE vuint8m1_t rvvslidedownbytes<types::detail::rvv_width_mf2>(vuint8m1_t arg, size_t i)
|
|
1421
|
+
{
|
|
1422
|
+
const auto bytes = __riscv_vlmul_trunc_u8mf2(arg);
|
|
1423
|
+
const auto result = __riscv_vslidedown(bytes, i, types::detail::rvv_width_mf2 / 8);
|
|
1424
|
+
return __riscv_vlmul_ext_u8m1(result);
|
|
1425
|
+
}
|
|
1426
|
+
template <>
|
|
1427
|
+
XSIMD_INLINE vuint8m1_t rvvslidedownbytes<types::detail::rvv_width_mf4>(vuint8m1_t arg, size_t i)
|
|
1428
|
+
{
|
|
1429
|
+
const auto bytes = __riscv_vlmul_trunc_u8mf4(arg);
|
|
1430
|
+
const auto result = __riscv_vslidedown(bytes, i, types::detail::rvv_width_mf4 / 8);
|
|
1431
|
+
return __riscv_vlmul_ext_u8m1(result);
|
|
1432
|
+
}
|
|
1433
|
+
template <>
|
|
1434
|
+
XSIMD_INLINE vuint8m1_t rvvslidedownbytes<types::detail::rvv_width_mf8>(vuint8m1_t arg, size_t i)
|
|
1435
|
+
{
|
|
1436
|
+
const auto bytes = __riscv_vlmul_trunc_u8mf8(arg);
|
|
1437
|
+
const auto result = __riscv_vslidedown(bytes, i, types::detail::rvv_width_mf8 / 8);
|
|
1438
|
+
return __riscv_vlmul_ext_u8m1(result);
|
|
1439
|
+
}
|
|
1440
|
+
}
|
|
1441
|
+
|
|
1442
|
+
// slide_left
|
|
1443
|
+
template <size_t N, class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
1444
|
+
XSIMD_INLINE batch<T, A> slide_left(batch<T, A> const& arg, requires_arch<rvv>) noexcept
|
|
1445
|
+
{
|
|
1446
|
+
const auto zero = broadcast<A>(uint8_t(0), rvv {});
|
|
1447
|
+
const auto bytes = arg.data.get_bytes();
|
|
1448
|
+
return detail::rvvreinterpret<T>(detail::rvvslideup(zero, bytes, N));
|
|
1449
|
+
}
|
|
1450
|
+
|
|
1451
|
+
// slide_right
|
|
1452
|
+
template <size_t N, class A, class T, detail::rvv_enable_all_t<T> = 0>
|
|
1453
|
+
XSIMD_INLINE batch<T, A> slide_right(batch<T, A> const& arg, requires_arch<rvv>) noexcept
|
|
1454
|
+
{
|
|
1455
|
+
using reg_t = detail::rvv_reg_t<T, A::width>;
|
|
1456
|
+
const auto bytes = arg.data.get_bytes();
|
|
1457
|
+
return reg_t(detail::rvvslidedownbytes<A::width>(bytes, N), types::detail::XSIMD_RVV_BITCAST);
|
|
1458
|
+
}
|
|
1459
|
+
|
|
1460
|
+
// isnan
|
|
1461
|
+
template <class A, class T, detail::rvv_enable_floating_point_t<T> = 0>
|
|
1462
|
+
XSIMD_INLINE batch_bool<T, A> isnan(batch<T, A> const& arg, requires_arch<rvv>) noexcept
|
|
1463
|
+
{
|
|
1464
|
+
return !(arg == arg);
|
|
1465
|
+
}
|
|
1466
|
+
|
|
1467
|
+
namespace detail
|
|
1468
|
+
{
|
|
1469
|
+
template <class T>
|
|
1470
|
+
using rvv_as_signed_integer_t = as_signed_integer_t<as_unsigned_integer_t<T>>;
|
|
1471
|
+
|
|
1472
|
+
template <class A, class T, class U = rvv_as_signed_integer_t<T>>
|
|
1473
|
+
XSIMD_INLINE batch<U, A> rvvfcvt_default(batch<T, A> const& arg) noexcept
|
|
1474
|
+
{
|
|
1475
|
+
return rvvfcvt_rne(U {}, arg);
|
|
1476
|
+
}
|
|
1477
|
+
|
|
1478
|
+
template <class A, class T, class U = rvv_as_signed_integer_t<T>>
|
|
1479
|
+
XSIMD_INLINE batch<U, A> rvvfcvt_afz(batch<T, A> const& arg) noexcept
|
|
1480
|
+
{
|
|
1481
|
+
return rvvfcvt_rmm(U {}, arg);
|
|
1482
|
+
}
|
|
1483
|
+
}
|
|
1484
|
+
|
|
1485
|
+
// nearbyint_as_int
|
|
1486
|
+
template <class A, class T, class U = detail::rvv_as_signed_integer_t<T>>
|
|
1487
|
+
XSIMD_INLINE batch<U, A> nearbyint_as_int(batch<T, A> const& arg, requires_arch<rvv>) noexcept
|
|
1488
|
+
{
|
|
1489
|
+
// Reference rounds ties to nearest even
|
|
1490
|
+
return detail::rvvfcvt_default(arg);
|
|
1491
|
+
}
|
|
1492
|
+
|
|
1493
|
+
// round
|
|
1494
|
+
template <class A, class T, detail::rvv_enable_floating_point_t<T> = 0>
|
|
1495
|
+
XSIMD_INLINE batch<T, A> round(batch<T, A> const& arg, requires_arch<rvv>) noexcept
|
|
1496
|
+
{
|
|
1497
|
+
// Round ties away from zero.
|
|
1498
|
+
const auto mask = abs(arg) < constants::maxflint<batch<T, A>>();
|
|
1499
|
+
return select(mask, to_float(detail::rvvfcvt_afz(arg)), arg, rvv {});
|
|
1500
|
+
}
|
|
1501
|
+
|
|
1502
|
+
// nearbyint
|
|
1503
|
+
template <class A, class T, detail::rvv_enable_floating_point_t<T> = 0>
|
|
1504
|
+
XSIMD_INLINE batch<T, A> nearbyint(batch<T, A> const& arg, requires_arch<rvv>) noexcept
|
|
1505
|
+
{
|
|
1506
|
+
// Round according to current rounding mode.
|
|
1507
|
+
const auto mask = abs(arg) < constants::maxflint<batch<T, A>>();
|
|
1508
|
+
return select(mask, to_float(detail::rvvfcvt_default(arg)), arg, rvv {});
|
|
1509
|
+
}
|
|
1510
|
+
} // namespace kernel
|
|
1511
|
+
} // namespace xsimd
|
|
1512
|
+
|
|
1513
|
+
#endif
|