sequenzo 0.1.17__cp311-cp311-win_amd64.whl → 0.1.19__cp311-cp311-win_amd64.whl

sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/arch/xsimd_wasm.hpp

@@ -531,6 +531,42 @@ namespace xsimd
                     static_cast<int32_t>(wasm_f32x4_extract_lane(self, 3)));
             }
         }
+        // first
+        template <class A>
+        XSIMD_INLINE float first(batch<float, A> const& self, requires_arch<wasm>) noexcept
+        {
+            return wasm_f32x4_extract_lane(self, 0);
+        }
+        template <class A, class T, class = typename std::enable_if<std::is_integral<T>::value, void>::type>
+        XSIMD_INLINE T first(batch<T, A> const& self, requires_arch<wasm>) noexcept
+        {
+            XSIMD_IF_CONSTEXPR(sizeof(T) == 1)
+            {
+                return wasm_i8x16_extract_lane(self, 0);
+            }
+            else XSIMD_IF_CONSTEXPR(sizeof(T) == 2)
+            {
+                return wasm_i16x8_extract_lane(self, 0);
+            }
+            else XSIMD_IF_CONSTEXPR(sizeof(T) == 4)
+            {
+                return wasm_i32x4_extract_lane(self, 0);
+            }
+            else XSIMD_IF_CONSTEXPR(sizeof(T) == 8)
+            {
+                return wasm_i64x2_extract_lane(self, 0);
+            }
+            else
+            {
+                assert(false && "unsupported arch/op combination");
+                return {};
+            }
+        }
+        template <class A>
+        XSIMD_INLINE double first(batch<double, A> const& self, requires_arch<wasm>) noexcept
+        {
+            return wasm_f64x2_extract_lane(self, 0);
+        }
 
         // floor
         template <class A>
@@ -1170,7 +1206,7 @@ namespace xsimd
             }
             else
             {
-                return hadd(self, common {});
+                return reduce_add(self, common {});
             }
         }
         template <class A>
@@ -1182,6 +1218,47 @@ namespace xsimd
             return wasm_f64x2_extract_lane(tmp2, 0);
         }
 
+        // reduce_mul
+        template <class A>
+        XSIMD_INLINE float reduce_mul(batch<float, A> const& self, requires_arch<wasm>) noexcept
+        {
+            v128_t tmp0 = wasm_f32x4_mul(self, wasm_i32x4_shuffle(self, self, 6, 7, 2, 3));
+            v128_t tmp1 = wasm_i32x4_shuffle(tmp0, tmp0, 1, 0, 4, 4);
+            v128_t tmp2 = wasm_f32x4_mul(tmp0, tmp1);
+            v128_t tmp3 = wasm_i32x4_shuffle(tmp0, tmp2, 4, 1, 2, 3);
+            return wasm_f32x4_extract_lane(tmp3, 0);
+        }
+        template <class A, class T, class = typename std::enable_if<std::is_integral<T>::value, void>::type>
+        XSIMD_INLINE T reduce_mul(batch<T, A> const& self, requires_arch<wasm>) noexcept
+        {
+            XSIMD_IF_CONSTEXPR(sizeof(T) == 4)
+            {
+                v128_t tmp0 = wasm_i32x4_shuffle(self, wasm_i32x4_splat(0), 2, 3, 0, 0);
+                v128_t tmp1 = wasm_i32x4_mul(self, tmp0);
+                v128_t tmp2 = wasm_i32x4_shuffle(tmp1, wasm_i32x4_splat(0), 1, 0, 0, 0);
+                v128_t tmp3 = wasm_i32x4_mul(tmp1, tmp2);
+                return wasm_i32x4_extract_lane(tmp3, 0);
+            }
+            else XSIMD_IF_CONSTEXPR(sizeof(T) == 8)
+            {
+                v128_t tmp0 = wasm_i32x4_shuffle(self, wasm_i32x4_splat(0), 2, 3, 0, 0);
+                v128_t tmp1 = wasm_i64x2_mul(self, tmp0);
+                return wasm_i64x2_extract_lane(tmp1, 0);
+            }
+            else
+            {
+                return reduce_mul(self, common {});
+            }
+        }
+        template <class A>
+        XSIMD_INLINE double reduce_mul(batch<double, A> const& self, requires_arch<wasm>) noexcept
+        {
+            v128_t tmp0 = wasm_i64x2_shuffle(self, self, 1, 3);
+            v128_t tmp1 = wasm_f64x2_mul(self, tmp0);
+            v128_t tmp2 = wasm_i64x2_shuffle(tmp0, tmp1, 2, 1);
+            return wasm_f64x2_extract_lane(tmp2, 0);
+        }
+
         // rsqrt
         template <class A>
         XSIMD_INLINE batch<float, A> rsqrt(batch<float, A> const& self, requires_arch<wasm>) noexcept

sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/config/xsimd_arch.hpp

@@ -169,14 +169,16 @@ namespace xsimd
     using all_sve_architectures = arch_list<detail::sve<512>, detail::sve<256>, detail::sve<128>>;
     using all_rvv_architectures = arch_list<detail::rvv<512>, detail::rvv<256>, detail::rvv<128>>;
     using all_arm_architectures = typename detail::join<all_sve_architectures, arch_list<i8mm<neon64>, neon64, neon>>::type;
+    using all_power_architectures = arch_list<vsx>;
     using all_riscv_architectures = all_rvv_architectures;
     using all_wasm_architectures = arch_list<wasm>;
-    using all_architectures = typename detail::join<all_riscv_architectures, all_wasm_architectures, all_arm_architectures, all_x86_architectures>::type;
+    using all_architectures = typename detail::join<all_power_architectures, all_riscv_architectures, all_wasm_architectures, all_arm_architectures, all_x86_architectures>::type;
 
     using supported_architectures = typename detail::supported<all_architectures>::type;
 
     using x86_arch = typename detail::supported<all_x86_architectures>::type::best;
     using arm_arch = typename detail::supported<all_arm_architectures>::type::best;
+    using power_arch = typename detail::supported<all_power_architectures>::type::best;
     using riscv_arch = typename detail::supported<all_riscv_architectures>::type::best;
     using best_arch = typename supported_architectures::best;
 

sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/config/xsimd_config.hpp

@@ -408,6 +408,17 @@
 #define XSIMD_WITH_WASM 0
 #endif
 
+/**
+ * @ingroup xsimd_config_macro
+ *
+ * Set to 1 if VMX with VSX extension is available at compile-time, to 0 otherwise.
+ */
+#if defined(__VEC__) && defined(__VSX__)
+#define XSIMD_WITH_VSX 1
+#else
+#define XSIMD_WITH_VSX 0
+#endif
+
 // Workaround for MSVC compiler
 #ifdef _MSC_VER
 
@@ -459,14 +470,14 @@
 
 #endif
 
-#if XSIMD_WITH_SSE3 || defined(_M_AMD64) || defined(_M_X64) || (defined(_M_IX86_FP) && _M_IX86_FP >= 2)
+#if XSIMD_WITH_SSE3 || ((defined(_M_AMD64) || defined(_M_X64)) && !defined(_M_ARM64EC)) || (defined(_M_IX86_FP) && _M_IX86_FP >= 2)
 #undef XSIMD_WITH_SSE2
 #define XSIMD_WITH_SSE2 1
 #endif
 
 #endif
 
-#if !XSIMD_WITH_SSE2 && !XSIMD_WITH_SSE3 && !XSIMD_WITH_SSSE3 && !XSIMD_WITH_SSE4_1 && !XSIMD_WITH_SSE4_2 && !XSIMD_WITH_AVX && !XSIMD_WITH_AVX2 && !XSIMD_WITH_AVXVNNI && !XSIMD_WITH_FMA3_SSE && !XSIMD_WITH_FMA4 && !XSIMD_WITH_FMA3_AVX && !XSIMD_WITH_FMA3_AVX2 && !XSIMD_WITH_AVX512F && !XSIMD_WITH_AVX512CD && !XSIMD_WITH_AVX512DQ && !XSIMD_WITH_AVX512BW && !XSIMD_WITH_AVX512ER && !XSIMD_WITH_AVX512PF && !XSIMD_WITH_AVX512IFMA && !XSIMD_WITH_AVX512VBMI && !XSIMD_WITH_AVX512VBMI2 && !XSIMD_WITH_NEON && !XSIMD_WITH_NEON64 && !XSIMD_WITH_SVE && !XSIMD_WITH_RVV && !XSIMD_WITH_WASM
+#if !XSIMD_WITH_SSE2 && !XSIMD_WITH_SSE3 && !XSIMD_WITH_SSSE3 && !XSIMD_WITH_SSE4_1 && !XSIMD_WITH_SSE4_2 && !XSIMD_WITH_AVX && !XSIMD_WITH_AVX2 && !XSIMD_WITH_AVXVNNI && !XSIMD_WITH_FMA3_SSE && !XSIMD_WITH_FMA4 && !XSIMD_WITH_FMA3_AVX && !XSIMD_WITH_FMA3_AVX2 && !XSIMD_WITH_AVX512F && !XSIMD_WITH_AVX512CD && !XSIMD_WITH_AVX512DQ && !XSIMD_WITH_AVX512BW && !XSIMD_WITH_AVX512ER && !XSIMD_WITH_AVX512PF && !XSIMD_WITH_AVX512IFMA && !XSIMD_WITH_AVX512VBMI && !XSIMD_WITH_AVX512VBMI2 && !XSIMD_WITH_NEON && !XSIMD_WITH_NEON64 && !XSIMD_WITH_SVE && !XSIMD_WITH_RVV && !XSIMD_WITH_WASM && !XSIMD_WITH_VSX && !XSIMD_WITH_EMULATED
 #define XSIMD_NO_SUPPORTED_ARCHITECTURE
 #endif
 

sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/config/xsimd_cpuid.hpp

@@ -84,6 +84,7 @@ namespace xsimd
             ARCH_FIELD_EX_REUSE(detail::rvv<256>, rvv)
             ARCH_FIELD_EX_REUSE(detail::rvv<128>, rvv)
             ARCH_FIELD(wasm)
+            ARCH_FIELD(vsx)
 
 #undef ARCH_FIELD
 
@@ -95,6 +96,10 @@ namespace xsimd
                 wasm = 1;
 #endif
 
+#if XSIMD_WITH_VSX
+                vsx = 1;
+#endif
+
 #if defined(__aarch64__) || defined(_M_ARM64)
                 neon = 1;
                 neon64 = 1;

sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/config/xsimd_inline.hpp

@@ -12,8 +12,12 @@
 #ifndef XSIMD_INLINE_HPP
 #define XSIMD_INLINE_HPP
 
-#if defined(__GNUC__)
+#if defined(__VEC__)
+#define XSIMD_INLINE inline
+#elif defined __has_attribute
+#if __has_attribute(always_inline)
 #define XSIMD_INLINE inline __attribute__((always_inline))
+#endif
 #elif defined(_MSC_VER)
 #define XSIMD_INLINE inline __forceinline
 #else

sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_all_registers.hpp

@@ -48,6 +48,8 @@
 
 #include "xsimd_wasm_register.hpp"
 
+#include "xsimd_vsx_register.hpp"
+
 #if XSIMD_WITH_EMULATED
 #include "xsimd_emulated_register.hpp"
 #endif

sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_api.hpp

@@ -373,6 +373,12 @@ namespace xsimd
         detail::static_check_supported_config<T, A>();
         return kernel::bitwise_lshift<A>(x, shift, A {});
     }
+    template <size_t shift, class T, class A>
+    XSIMD_INLINE batch<T, A> bitwise_lshift(batch<T, A> const& x) noexcept
+    {
+        detail::static_check_supported_config<T, A>();
+        return kernel::bitwise_lshift<shift, A>(x, A {});
+    }
 
     /**
      * @ingroup batch_bitwise
@@ -452,6 +458,12 @@ namespace xsimd
         detail::static_check_supported_config<T, A>();
         return kernel::bitwise_rshift<A>(x, shift, A {});
     }
+    template <size_t shift, class T, class A>
+    XSIMD_INLINE batch<T, A> bitwise_rshift(batch<T, A> const& x) noexcept
+    {
+        detail::static_check_supported_config<T, A>();
+        return kernel::bitwise_rshift<shift, A>(x, A {});
+    }
 
     /**
      * @ingroup batch_bitwise
@@ -635,7 +647,7 @@ namespace xsimd
     }
 
     /**
-     * @ingroup batch_reducers
+     * @ingroup batch_bool_reducers
      *
      * Count the number of values set to true in the batch \c x
      * @param x boolean or batch of boolean
@@ -991,6 +1003,21 @@ namespace xsimd
         return kernel::fnms<A>(x, y, z, A {});
     }
 
+    /**
+     * @ingroup batch_arithmetic
+     *
+     * Computes <tt>-(x*y) - z</tt> in a single instruction when possible.
+     * @param x a batch of integer or floating point values.
+     * @param y a batch of integer or floating point values.
+     * @param z a batch of integer or floating point values.
+     * @return  a batch where each even-indexed element is computed as <tt>x * y - z</tt> and each odd-indexed element as <tt>x * y + z</tt>
+     */
+    template <class T, class A>
+    XSIMD_INLINE batch<T, A> fmas(batch<T, A> const& x, batch<T, A> const& y, batch<T, A> const& z) noexcept
+    {
+        detail::static_check_supported_config<T, A>();
+        return kernel::fmas<A>(x, y, z, A {});
+    }
     /**
      * @ingroup batch_fp
      *
@@ -1114,6 +1141,7 @@ namespace xsimd
         return kernel::incr_if<A>(x, mask, A {});
     }
 
+#ifndef __FAST_MATH__
     /**
      * @ingroup batch_constant
      *
@@ -1128,6 +1156,7 @@ namespace xsimd
         detail::static_check_supported_config<T, A>();
         return B(std::numeric_limits<T>::infinity());
     }
+#endif
 
     /**
      * @ingroup batch_data_transfer
@@ -1862,6 +1891,20 @@ namespace xsimd
         return kernel::reduce_min<A>(x, A {});
     }
 
+    /**
+     * @ingroup batch_reducers
+     *
+     * Multiplies of all the scalars of the batch \c x.
+     * @param x batch involved in the reduction
+     * @return the result of the reduction.
+     */
+    template <class T, class A>
+    XSIMD_INLINE T reduce_mul(batch<T, A> const& x) noexcept
+    {
+        detail::static_check_supported_config<T, A>();
+        return kernel::reduce_mul<A>(x, A {});
+    }
+
     /**
      * @ingroup batch_math
      *
@@ -1949,6 +1992,12 @@ namespace xsimd
         detail::static_check_supported_config<T, A>();
         return kernel::rotl<A>(x, shift, A {});
     }
+    template <size_t count, class T, class A>
+    XSIMD_INLINE batch<T, A> rotl(batch<T, A> const& x) noexcept
+    {
+        detail::static_check_supported_config<T, A>();
+        return kernel::rotl<count, A>(x, A {});
+    }
 
     /**
      * @ingroup batch_bitwise
@@ -1971,6 +2020,12 @@ namespace xsimd
         detail::static_check_supported_config<T, A>();
         return kernel::rotr<A>(x, shift, A {});
     }
+    template <size_t count, class T, class A>
+    XSIMD_INLINE batch<T, A> rotr(batch<T, A> const& x) noexcept
+    {
+        detail::static_check_supported_config<T, A>();
+        return kernel::rotr<count, A>(x, A {});
+    }
 
     /**
      * @ingroup batch_rounding
@@ -2107,6 +2162,7 @@ namespace xsimd
     shuffle(batch<T, A> const& x, batch<T, A> const& y, batch_constant<Vt, A, Values...> mask) noexcept
     {
         static_assert(sizeof(T) == sizeof(Vt), "consistent mask");
+        static_assert(std::is_unsigned<Vt>::value, "mask must hold unsigned indices");
         detail::static_check_supported_config<T, A>();
         return kernel::shuffle<A>(x, y, mask, A {});
     }
@@ -2188,6 +2244,9 @@ namespace xsimd
      * Slide the whole batch to the left by \c n bytes. This is different from
      * \c bitwise_lshift that shifts each batch element to the left.
      *
+     * @warning The behavior of this function is platform-dependent on big
+     * endian architectures.
+     *
      * @tparam N Amount of bytes to slide to the left.
      * @param x batch of integer values.
      * @return slided batch.
@@ -2206,6 +2265,9 @@ namespace xsimd
      * Slide the whole batch to the right by \c N bytes. This is different from
      * \c bitwise_rshift that shifts each batch element to the right.
      *
+     * @warning The behavior of this function is platform-dependent on big
+     * endian architectures.
+     *
      * @tparam N Amount of bytes to slide to the right.
      * @param x batch of integer values.
      * @return slided batch.
@@ -2416,6 +2478,7 @@ namespace xsimd
     XSIMD_INLINE batch<std::complex<T>, A> swizzle(batch<std::complex<T>, A> const& x, batch_constant<Vt, A, Values...> mask) noexcept
     {
         static_assert(sizeof(T) == sizeof(Vt), "consistent mask");
+        static_assert(std::is_unsigned<Vt>::value, "mask must hold unsigned indices");
         detail::static_check_supported_config<T, A>();
         return kernel::swizzle<A>(x, mask, A {});
     }

sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_batch.hpp

@@ -159,6 +159,8 @@ namespace xsimd
 
         XSIMD_INLINE T get(std::size_t i) const noexcept;
 
+        XSIMD_INLINE T first() const noexcept;
+
         // comparison operators. Defined as friend to enable automatic
         // conversion of parameters from scalar to batch, at the cost of using a
         // proxy implementation from details::.
@@ -271,8 +273,10 @@ namespace xsimd
         XSIMD_INLINE batch logical_or(batch const& other) const noexcept;
     };
 
+#if __cplusplus < 201703L
     template <class T, class A>
     constexpr std::size_t batch<T, A>::size;
+#endif
 
     /**
      * @brief batch of predicate over scalar or complex values.
@@ -314,6 +318,8 @@ namespace xsimd
 
         XSIMD_INLINE bool get(std::size_t i) const noexcept;
 
+        XSIMD_INLINE bool first() const noexcept;
+
         // mask operations
         XSIMD_INLINE uint64_t mask() const noexcept;
         XSIMD_INLINE static batch_bool from_mask(uint64_t mask) noexcept;
@@ -344,8 +350,10 @@ namespace xsimd
         static XSIMD_INLINE register_type make_register(detail::index_sequence<>, V... v) noexcept;
     };
 
+#if __cplusplus < 201703L
     template <class T, class A>
     constexpr std::size_t batch_bool<T, A>::size;
+#endif
 
     /**
      * @brief batch of complex values.
@@ -405,6 +413,8 @@ namespace xsimd
 
         XSIMD_INLINE value_type get(std::size_t i) const noexcept;
 
+        XSIMD_INLINE value_type first() const noexcept;
+
 #ifdef XSIMD_ENABLE_XTL_COMPLEX
         // xtl-related methods
         template <bool i3ec>
@@ -476,8 +486,10 @@ namespace xsimd
         real_batch m_imag;
     };
 
+#if __cplusplus < 201703L
     template <class T, class A>
     constexpr std::size_t batch<std::complex<T>, A>::size;
+#endif
 
 #ifdef XSIMD_ENABLE_XTL_COMPLEX
     template <typename T, bool i3ec, typename A>
@@ -693,6 +705,16 @@ namespace xsimd
         return kernel::get(*this, i, A {});
     }
 
+    /**
+     * Retrieve the first scalar element in this batch.
+     */
+    template <class T, class A>
+    XSIMD_INLINE T batch<T, A>::first() const noexcept
+    {
+        detail::static_check_supported_config<T, A>();
+        return kernel::first(*this, A {});
+    }
+
     /******************************
      * batch comparison operators *
      ******************************/
@@ -1005,6 +1027,13 @@ namespace xsimd
         return kernel::get(*this, i, A {});
     }
 
+    template <class T, class A>
+    XSIMD_INLINE bool batch_bool<T, A>::first() const noexcept
+    {
+        detail::static_check_supported_config<T, A>();
+        return kernel::first(*this, A {});
+    }
+
     /***********************************
      * batch_bool comparison operators *
      ***********************************/
@@ -1248,6 +1277,13 @@ namespace xsimd
         return kernel::get(*this, i, A {});
     }
 
+    template <class T, class A>
+    XSIMD_INLINE auto batch<std::complex<T>, A>::first() const noexcept -> value_type
+    {
+        detail::static_check_supported_config<std::complex<T>, A>();
+        return kernel::first(*this, A {});
+    }
+
     /**************************************
      * batch<complex> xtl-related methods *
      **************************************/

sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_rvv_register.hpp

@@ -62,9 +62,12 @@ namespace xsimd
             static constexpr size_t rvv_width_mf4 = XSIMD_RVV_BITS / 4;
             static constexpr size_t rvv_width_mf2 = XSIMD_RVV_BITS / 2;
             static constexpr size_t rvv_width_m1 = XSIMD_RVV_BITS;
-            static constexpr size_t rvv_width_m2 = XSIMD_RVV_BITS * 2;
-            static constexpr size_t rvv_width_m4 = XSIMD_RVV_BITS * 4;
-            static constexpr size_t rvv_width_m8 = XSIMD_RVV_BITS * 8;
+
+            // Cope with gcc limitation, see https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116484
+#define XSIMD_RVV_WIDTH_MF8 (XSIMD_RVV_BITS / 8)
+#define XSIMD_RVV_WIDTH_MF4 (XSIMD_RVV_BITS / 4)
+#define XSIMD_RVV_WIDTH_MF2 (XSIMD_RVV_BITS / 2)
+#define XSIMD_RVV_WIDTH_M1 XSIMD_RVV_BITS
 
             // rvv_type_info is a utility class to convert scalar type and
             // bitwidth into rvv register types.
@@ -79,30 +82,30 @@ namespace xsimd
             //
             template <class T, size_t Width>
             struct rvv_type_info;
-#define XSIMD_RVV_MAKE_TYPE(scalar, t, s, vmul)                                           \
-    template <>                                                                           \
-    struct rvv_type_info<scalar, rvv_width_m1 * vmul>                                     \
-    {                                                                                     \
-        static constexpr size_t width = rvv_width_m1 * vmul;                              \
-        using type = XSIMD_RVV_TYPE(t, s, vmul);                                          \
-        using byte_type = XSIMD_RVV_TYPE(u, 8, vmul);                                     \
-        using fixed_type = type __attribute__((riscv_rvv_vector_bits(width)));            \
-        template <class U>                                                                \
-        static XSIMD_INLINE type bitcast(U x) noexcept                                    \
-        {                                                                                 \
-            const auto words = XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, s, m, vmul)(x); \
-            return XSIMD_RVV_JOINT5(__riscv_vreinterpret_, t, s, m, vmul)(words);         \
-        }                                                                                 \
-        template <>                                                                       \
-        XSIMD_INLINE type bitcast<type>(type x) noexcept { return x; }                    \
-        template <class U>                                                                \
-        static XSIMD_INLINE byte_type as_bytes(U x) noexcept                              \
-        {                                                                                 \
-            static_assert(std::is_same<U, type>::value, "inconsistent conversion types"); \
-            const auto words = XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, s, m, vmul)(x); \
-            return XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, 8, m, vmul)(words);         \
-        }                                                                                 \
-    };
+#define XSIMD_RVV_MAKE_TYPE(scalar, t, s, vmul)                                                              \
+    template <>                                                                                              \
+    struct rvv_type_info<scalar, rvv_width_m1 * vmul>                                                        \
+    {                                                                                                        \
+        static constexpr size_t width = rvv_width_m1 * vmul;                                                 \
+        using type = XSIMD_RVV_TYPE(t, s, vmul);                                                             \
+        using byte_type = XSIMD_RVV_TYPE(u, 8, vmul);                                                        \
+        using fixed_type = type __attribute__((riscv_rvv_vector_bits(/*width=*/XSIMD_RVV_WIDTH_M1 * vmul))); \
+        template <class U>                                                                                   \
+        static XSIMD_INLINE type bitcast(U x) noexcept                                                       \
+        {                                                                                                    \
+            const auto words = XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, s, m, vmul)(x);                    \
+            return XSIMD_RVV_JOINT5(__riscv_vreinterpret_, t, s, m, vmul)(words);                            \
+        }                                                                                                    \
+        template <class U>                                                                                   \
+        static XSIMD_INLINE byte_type as_bytes(U x) noexcept                                                 \
+        {                                                                                                    \
+            static_assert(std::is_same<U, type>::value, "inconsistent conversion types");                    \
+            const auto words = XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, s, m, vmul)(x);                    \
+            return XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, 8, m, vmul)(words);                            \
+        }                                                                                                    \
+    };                                                                                                       \
+    template <>                                                                                              \
+    XSIMD_INLINE XSIMD_RVV_TYPE(t, s, vmul) rvv_type_info<scalar, rvv_width_m1 * vmul>::bitcast<XSIMD_RVV_TYPE(t, s, vmul)>(XSIMD_RVV_TYPE(t, s, vmul) x) noexcept { return x; }
 
 #define XSIMD_RVV_MAKE_TYPES(vmul)             \
     XSIMD_RVV_MAKE_TYPE(int8_t, i, 8, vmul)    \
@@ -235,17 +238,17 @@ namespace xsimd
                 template <>
                 struct semitype<2>
                 {
-                    using type = vuint8mf2_t __attribute__((riscv_rvv_vector_bits(rvv_width_mf2)));
+                    using type = vuint8mf2_t __attribute__((riscv_rvv_vector_bits(XSIMD_RVV_WIDTH_MF2)));
                 };
                 template <>
                 struct semitype<4>
                 {
-                    using type = vuint8mf4_t __attribute__((riscv_rvv_vector_bits(rvv_width_mf4)));
+                    using type = vuint8mf4_t __attribute__((riscv_rvv_vector_bits(XSIMD_RVV_WIDTH_MF4)));
                 };
                 template <>
                 struct semitype<8>
                 {
-                    using type = vuint8mf8_t __attribute__((riscv_rvv_vector_bits(rvv_width_mf8)));
+                    using type = vuint8mf8_t __attribute__((riscv_rvv_vector_bits(XSIMD_RVV_WIDTH_MF8)));
                 };
                 using fixed_type = typename semitype<divisor>::type;
                 using super::as_bytes;
@@ -374,7 +377,7 @@ namespace xsimd
             struct rvv_bool
             {
                 using bool_info = rvv_bool_info<rvv_width_m1 * sizeof(T) * 8 / Width>;
-                using storage_type = vuint8m1_t __attribute__((riscv_rvv_vector_bits(rvv_width_m1)));
+                using storage_type = vuint8m1_t __attribute__((riscv_rvv_vector_bits(XSIMD_RVV_WIDTH_M1)));
                 using type = typename bool_info::type;
                 storage_type value;
                 rvv_bool() = default;
@@ -489,6 +492,12 @@ namespace xsimd
             using type = detail::rvv_bool_simd_register<T>;
         };
     } // namespace types
+
+#undef XSIMD_RVV_WIDTH_MF8
+#undef XSIMD_RVV_WIDTH_MF4
+#undef XSIMD_RVV_WIDTH_MF2
+#undef XSIMD_RVV_WIDTH_M1
+
 #else
     using rvv = detail::rvv<0xFFFFFFFF>;
 #endif

sequenzo/dissimilarity_measures/src/xsimd/include/xsimd/types/xsimd_traits.hpp

@@ -53,8 +53,10 @@ namespace xsimd
             static constexpr size_t size = 1;
         };
 
+#if __cplusplus < 201703L
         template <class T>
         constexpr size_t simd_traits_impl<T, false>::size;
+#endif
 
         template <class T>
         struct simd_traits_impl<T, true>
@@ -64,8 +66,10 @@ namespace xsimd
             static constexpr size_t size = type::size;
         };
 
+#if __cplusplus < 201703L
         template <class T>
         constexpr size_t simd_traits_impl<T, true>::size;
+#endif
 
         template <class T, class A>
         struct static_check_supported_config_emitter
@@ -128,8 +132,10 @@ namespace xsimd
         static constexpr size_t size = simd_traits<type>::size;
     };
 
+#if __cplusplus < 201703L
     template <class T>
     constexpr size_t revert_simd_traits<T>::size;
+#endif
 
     template <class T>
     struct revert_simd_traits<batch<T>>
@@ -138,8 +144,10 @@ namespace xsimd
         static constexpr size_t size = batch<T>::size;
     };
 
+#if __cplusplus < 201703L
     template <class T>
     constexpr size_t revert_simd_traits<batch<T>>::size;
+#endif
 
     template <class T>
     using simd_type = typename simd_traits<T>::type;