wasmtime 28.0.0 → 29.0.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/Cargo.lock +155 -120
- data/ext/Cargo.toml +5 -5
- data/ext/cargo-vendor/bitflags-2.8.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/bitflags-2.8.0/CHANGELOG.md +581 -0
- data/ext/cargo-vendor/bitflags-2.8.0/Cargo.lock +384 -0
- data/ext/cargo-vendor/bitflags-2.8.0/Cargo.toml +130 -0
- data/ext/cargo-vendor/bitflags-2.8.0/README.md +77 -0
- data/ext/cargo-vendor/bitflags-2.8.0/examples/custom_derive.rs +23 -0
- data/ext/cargo-vendor/bitflags-2.8.0/src/external/arbitrary.rs +33 -0
- data/ext/cargo-vendor/bitflags-2.8.0/src/lib.rs +1025 -0
- data/ext/cargo-vendor/bitflags-2.8.0/src/tests/bitflags_match.rs +93 -0
- data/ext/cargo-vendor/bitflags-2.8.0/src/tests/truncate.rs +29 -0
- data/ext/cargo-vendor/bitflags-2.8.0/src/tests/unknown.rs +40 -0
- data/ext/cargo-vendor/bitflags-2.8.0/src/tests.rs +134 -0
- data/ext/cargo-vendor/bitflags-2.8.0/src/traits.rs +444 -0
- data/ext/cargo-vendor/cc-1.2.10/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cc-1.2.10/CHANGELOG.md +379 -0
- data/ext/cargo-vendor/cc-1.2.10/Cargo.lock +191 -0
- data/ext/cargo-vendor/cc-1.2.10/Cargo.toml +67 -0
- data/ext/cargo-vendor/cc-1.2.10/src/flags.rs +492 -0
- data/ext/cargo-vendor/cc-1.2.10/src/lib.rs +4216 -0
- data/ext/cargo-vendor/cc-1.2.10/src/target/generated.rs +3403 -0
- data/ext/cargo-vendor/cc-1.2.10/src/tool.rs +512 -0
- data/ext/cargo-vendor/cc-1.2.10/src/windows/windows_sys.rs +134 -0
- data/ext/cargo-vendor/cpufeatures-0.2.17/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cpufeatures-0.2.17/CHANGELOG.md +168 -0
- data/ext/cargo-vendor/cpufeatures-0.2.17/Cargo.lock +16 -0
- data/ext/cargo-vendor/cpufeatures-0.2.17/Cargo.toml +71 -0
- data/ext/cargo-vendor/cpufeatures-0.2.17/LICENSE-MIT +25 -0
- data/ext/cargo-vendor/cpufeatures-0.2.17/README.md +126 -0
- data/ext/cargo-vendor/cranelift-bforest-0.116.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-bforest-0.116.1/Cargo.lock +25 -0
- data/ext/cargo-vendor/cranelift-bforest-0.116.1/Cargo.toml +73 -0
- data/ext/cargo-vendor/cranelift-bitset-0.116.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-bitset-0.116.1/Cargo.lock +73 -0
- data/ext/cargo-vendor/cranelift-bitset-0.116.1/Cargo.toml +88 -0
- data/ext/cargo-vendor/cranelift-bitset-0.116.1/src/scalar.rs +629 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/Cargo.lock +1078 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/Cargo.toml +242 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/build.rs +223 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/binemit/mod.rs +174 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/ir/immediates.rs +1961 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/aarch64/abi.rs +1540 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/aarch64/inst/args.rs +711 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/aarch64/inst/emit.rs +3577 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/aarch64/inst/emit_tests.rs +7972 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/aarch64/inst/mod.rs +3056 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/aarch64/inst/regs.rs +281 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/aarch64/inst.isle +5102 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/aarch64/lower/isle.rs +765 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/aarch64/lower.isle +3161 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/aarch64/mod.rs +260 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/mod.rs +476 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/pulley_shared/abi.rs +943 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/pulley_shared/inst/args.rs +580 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/pulley_shared/inst/emit.rs +710 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/pulley_shared/inst/mod.rs +846 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/pulley_shared/inst/regs.rs +164 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/pulley_shared/inst.isle +489 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/pulley_shared/lower/isle.rs +162 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/pulley_shared/lower.isle +1414 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/pulley_shared/mod.rs +287 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/riscv64/abi.rs +995 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/riscv64/inst/args.rs +1957 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/riscv64/inst/emit_tests.rs +2277 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/s390x/abi.rs +1399 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/s390x/inst/emit.rs +3435 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/x64/abi.rs +1386 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/x64/inst.isle +5758 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/x64/lower/isle/generated_code.rs +16 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isa/x64/lower/isle.rs +997 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/isle_prelude.rs +1156 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/machinst/abi.rs +2451 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/machinst/buffer.rs +2496 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/machinst/lower.rs +1603 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/prelude.isle +836 -0
- data/ext/cargo-vendor/cranelift-codegen-0.116.0/src/prelude_lower.isle +1128 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.116.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.116.0/Cargo.lock +46 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.116.0/Cargo.toml +75 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.116.0/src/cdsl/instructions.rs +494 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.116.0/src/isa/pulley.rs +20 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.116.0/src/isle.rs +186 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.116.0/src/lib.rs +111 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.116.0/src/pulley.rs +401 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.116.0/src/shared/instructions.rs +3786 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.116.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.116.1/Cargo.lock +7 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.116.1/Cargo.toml +33 -0
- data/ext/cargo-vendor/cranelift-control-0.116.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-control-0.116.1/Cargo.lock +16 -0
- data/ext/cargo-vendor/cranelift-control-0.116.1/Cargo.toml +44 -0
- data/ext/cargo-vendor/cranelift-entity-0.116.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-entity-0.116.1/Cargo.lock +77 -0
- data/ext/cargo-vendor/cranelift-entity-0.116.1/Cargo.toml +89 -0
- data/ext/cargo-vendor/cranelift-entity-0.116.1/src/sparse.rs +411 -0
- data/ext/cargo-vendor/cranelift-frontend-0.116.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-frontend-0.116.0/Cargo.lock +544 -0
- data/ext/cargo-vendor/cranelift-frontend-0.116.0/Cargo.toml +111 -0
- data/ext/cargo-vendor/cranelift-isle-0.116.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-isle-0.116.0/Cargo.lock +294 -0
- data/ext/cargo-vendor/cranelift-isle-0.116.0/Cargo.toml +83 -0
- data/ext/cargo-vendor/cranelift-native-0.116.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-native-0.116.0/Cargo.lock +261 -0
- data/ext/cargo-vendor/cranelift-native-0.116.0/Cargo.toml +53 -0
- data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.29/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.29/Cargo.toml +70 -0
- data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.29/README.md +52 -0
- data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.29/tests/common/mod.rs +33 -0
- data/ext/cargo-vendor/indexmap-2.7.1/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/indexmap-2.7.1/Cargo.lock +333 -0
- data/ext/cargo-vendor/indexmap-2.7.1/Cargo.toml +150 -0
- data/ext/cargo-vendor/indexmap-2.7.1/RELEASES.md +541 -0
- data/ext/cargo-vendor/indexmap-2.7.1/src/lib.rs +273 -0
- data/ext/cargo-vendor/indexmap-2.7.1/src/map/core/entry.rs +571 -0
- data/ext/cargo-vendor/indexmap-2.7.1/src/map/core.rs +738 -0
- data/ext/cargo-vendor/indexmap-2.7.1/src/map/iter.rs +776 -0
- data/ext/cargo-vendor/indexmap-2.7.1/src/map.rs +1608 -0
- data/ext/cargo-vendor/indexmap-2.7.1/src/set/iter.rs +628 -0
- data/ext/cargo-vendor/indexmap-2.7.1/src/set.rs +1301 -0
- data/ext/cargo-vendor/indexmap-2.7.1/src/util.rs +58 -0
- data/ext/cargo-vendor/ipnet-2.11.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/ipnet-2.11.0/Cargo.lock +179 -0
- data/ext/cargo-vendor/ipnet-2.11.0/Cargo.toml +69 -0
- data/ext/cargo-vendor/ipnet-2.11.0/src/ipext.rs +989 -0
- data/ext/cargo-vendor/ipnet-2.11.0/src/ipnet.rs +2001 -0
- data/ext/cargo-vendor/ipnet-2.11.0/src/lib.rs +106 -0
- data/ext/cargo-vendor/js-sys-0.3.77/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/js-sys-0.3.77/Cargo.lock +127 -0
- data/ext/cargo-vendor/js-sys-0.3.77/Cargo.toml +69 -0
- data/ext/cargo-vendor/js-sys-0.3.77/src/lib.rs +6439 -0
- data/ext/cargo-vendor/log-0.4.25/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/log-0.4.25/CHANGELOG.md +368 -0
- data/ext/cargo-vendor/log-0.4.25/Cargo.toml +143 -0
- data/ext/cargo-vendor/log-0.4.25/README.md +134 -0
- data/ext/cargo-vendor/log-0.4.25/src/kv/key.rs +163 -0
- data/ext/cargo-vendor/log-0.4.25/src/kv/mod.rs +265 -0
- data/ext/cargo-vendor/log-0.4.25/src/kv/value.rs +1394 -0
- data/ext/cargo-vendor/log-0.4.25/src/lib.rs +1884 -0
- data/ext/cargo-vendor/log-0.4.25/src/serde.rs +397 -0
- data/ext/cargo-vendor/miniz_oxide-0.8.3/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/miniz_oxide-0.8.3/Cargo.lock +48 -0
- data/ext/cargo-vendor/miniz_oxide-0.8.3/Cargo.toml +90 -0
- data/ext/cargo-vendor/miniz_oxide-0.8.3/LICENSE +25 -0
- data/ext/cargo-vendor/miniz_oxide-0.8.3/LICENSE-MIT.md +24 -0
- data/ext/cargo-vendor/miniz_oxide-0.8.3/LICENSE-ZLIB.md +14 -0
- data/ext/cargo-vendor/miniz_oxide-0.8.3/src/deflate/core.rs +2459 -0
- data/ext/cargo-vendor/miniz_oxide-0.8.3/src/deflate/mod.rs +237 -0
- data/ext/cargo-vendor/miniz_oxide-0.8.3/src/deflate/stored.rs +306 -0
- data/ext/cargo-vendor/miniz_oxide-0.8.3/src/deflate/zlib.rs +112 -0
- data/ext/cargo-vendor/proc-macro2-1.0.93/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/proc-macro2-1.0.93/Cargo.lock +304 -0
- data/ext/cargo-vendor/proc-macro2-1.0.93/Cargo.toml +105 -0
- data/ext/cargo-vendor/proc-macro2-1.0.93/src/fallback.rs +1277 -0
- data/ext/cargo-vendor/proc-macro2-1.0.93/src/lib.rs +1389 -0
- data/ext/cargo-vendor/proc-macro2-1.0.93/src/rcvec.rs +146 -0
- data/ext/cargo-vendor/pulley-interpreter-29.0.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/pulley-interpreter-29.0.0/CONTRIBUTING.md +278 -0
- data/ext/cargo-vendor/pulley-interpreter-29.0.0/Cargo.lock +402 -0
- data/ext/cargo-vendor/pulley-interpreter-29.0.0/Cargo.toml +126 -0
- data/ext/cargo-vendor/pulley-interpreter-29.0.0/examples/objdump.rs +48 -0
- data/ext/cargo-vendor/pulley-interpreter-29.0.0/src/decode.rs +761 -0
- data/ext/cargo-vendor/pulley-interpreter-29.0.0/src/disas.rs +333 -0
- data/ext/cargo-vendor/pulley-interpreter-29.0.0/src/encode.rs +288 -0
- data/ext/cargo-vendor/pulley-interpreter-29.0.0/src/imms.rs +69 -0
- data/ext/cargo-vendor/pulley-interpreter-29.0.0/src/interp/debug.rs +128 -0
- data/ext/cargo-vendor/pulley-interpreter-29.0.0/src/interp/match_loop.rs +39 -0
- data/ext/cargo-vendor/pulley-interpreter-29.0.0/src/interp/tail_loop.rs +152 -0
- data/ext/cargo-vendor/pulley-interpreter-29.0.0/src/interp.rs +4655 -0
- data/ext/cargo-vendor/pulley-interpreter-29.0.0/src/lib.rs +1287 -0
- data/ext/cargo-vendor/pulley-interpreter-29.0.0/src/op.rs +279 -0
- data/ext/cargo-vendor/pulley-interpreter-29.0.0/src/opcode.rs +106 -0
- data/ext/cargo-vendor/pulley-interpreter-29.0.0/src/regs.rs +375 -0
- data/ext/cargo-vendor/pulley-interpreter-29.0.0/tests/all/disas.rs +189 -0
- data/ext/cargo-vendor/pulley-interpreter-29.0.0/tests/all/interp.rs +853 -0
- data/ext/cargo-vendor/rustix-0.38.44/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/rustix-0.38.44/Cargo.lock +1012 -0
- data/ext/cargo-vendor/rustix-0.38.44/Cargo.toml +308 -0
- data/ext/cargo-vendor/rustix-0.38.44/src/backend/libc/system/syscalls.rs +159 -0
- data/ext/cargo-vendor/rustix-0.38.44/src/backend/linux_raw/system/syscalls.rs +92 -0
- data/ext/cargo-vendor/rustix-0.38.44/src/lib.rs +408 -0
- data/ext/cargo-vendor/rustix-0.38.44/src/maybe_polyfill/std/mod.rs +41 -0
- data/ext/cargo-vendor/rustix-0.38.44/src/system.rs +284 -0
- data/ext/cargo-vendor/rustix-0.38.44/src/weak.rs +287 -0
- data/ext/cargo-vendor/rustversion-1.0.19/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/rustversion-1.0.19/Cargo.lock +294 -0
- data/ext/cargo-vendor/rustversion-1.0.19/Cargo.toml +62 -0
- data/ext/cargo-vendor/rustversion-1.0.19/README.md +167 -0
- data/ext/cargo-vendor/rustversion-1.0.19/build/build.rs +102 -0
- data/ext/cargo-vendor/rustversion-1.0.19/build/rustc.rs +126 -0
- data/ext/cargo-vendor/rustversion-1.0.19/src/attr.rs +35 -0
- data/ext/cargo-vendor/rustversion-1.0.19/src/bound.rs +63 -0
- data/ext/cargo-vendor/rustversion-1.0.19/src/constfn.rs +58 -0
- data/ext/cargo-vendor/rustversion-1.0.19/src/date.rs +50 -0
- data/ext/cargo-vendor/rustversion-1.0.19/src/error.rs +56 -0
- data/ext/cargo-vendor/rustversion-1.0.19/src/expand.rs +72 -0
- data/ext/cargo-vendor/rustversion-1.0.19/src/expr.rs +163 -0
- data/ext/cargo-vendor/rustversion-1.0.19/src/iter.rs +42 -0
- data/ext/cargo-vendor/rustversion-1.0.19/src/lib.rs +282 -0
- data/ext/cargo-vendor/rustversion-1.0.19/src/release.rs +34 -0
- data/ext/cargo-vendor/rustversion-1.0.19/src/time.rs +51 -0
- data/ext/cargo-vendor/rustversion-1.0.19/src/token.rs +78 -0
- data/ext/cargo-vendor/rustversion-1.0.19/src/version.rs +18 -0
- data/ext/cargo-vendor/rustversion-1.0.19/tests/test_const.rs +42 -0
- data/ext/cargo-vendor/rustversion-1.0.19/tests/test_eval.rs +20 -0
- data/ext/cargo-vendor/rustversion-1.0.19/tests/test_parse.rs +103 -0
- data/ext/cargo-vendor/rustversion-1.0.19/tests/ui/bad-bound.rs +7 -0
- data/ext/cargo-vendor/rustversion-1.0.19/tests/ui/bad-bound.stderr +11 -0
- data/ext/cargo-vendor/rustversion-1.0.19/tests/ui/bad-date.rs +7 -0
- data/ext/cargo-vendor/rustversion-1.0.19/tests/ui/bad-date.stderr +11 -0
- data/ext/cargo-vendor/rustversion-1.0.19/tests/ui/bad-not.rs +7 -0
- data/ext/cargo-vendor/rustversion-1.0.19/tests/ui/bad-not.stderr +11 -0
- data/ext/cargo-vendor/rustversion-1.0.19/tests/ui/bad-version.rs +7 -0
- data/ext/cargo-vendor/rustversion-1.0.19/tests/ui/bad-version.stderr +11 -0
- data/ext/cargo-vendor/rustversion-1.0.19/tests/ui/const-not-fn.rs +4 -0
- data/ext/cargo-vendor/rustversion-1.0.19/tests/ui/const-not-fn.stderr +5 -0
- data/ext/cargo-vendor/semver-1.0.25/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/semver-1.0.25/Cargo.lock +65 -0
- data/ext/cargo-vendor/semver-1.0.25/Cargo.toml +74 -0
- data/ext/cargo-vendor/semver-1.0.25/src/lib.rs +580 -0
- data/ext/cargo-vendor/serde_json-1.0.137/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/serde_json-1.0.137/Cargo.lock +417 -0
- data/ext/cargo-vendor/serde_json-1.0.137/Cargo.toml +153 -0
- data/ext/cargo-vendor/serde_json-1.0.137/src/lib.rs +435 -0
- data/ext/cargo-vendor/serde_json-1.0.137/src/value/ser.rs +1063 -0
- data/ext/cargo-vendor/serde_json-1.0.137/tests/compiletest.rs +7 -0
- data/ext/cargo-vendor/syn-2.0.96/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/syn-2.0.96/Cargo.lock +1749 -0
- data/ext/cargo-vendor/syn-2.0.96/Cargo.toml +268 -0
- data/ext/cargo-vendor/syn-2.0.96/src/expr.rs +4102 -0
- data/ext/cargo-vendor/syn-2.0.96/src/fixup.rs +770 -0
- data/ext/cargo-vendor/syn-2.0.96/src/lib.rs +1010 -0
- data/ext/cargo-vendor/syn-2.0.96/tests/test_expr.rs +1646 -0
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//! The pulley bytecode for fast interpreters.
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#![cfg_attr(docsrs, feature(doc_auto_cfg))]
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#![cfg_attr(pulley_tail_calls, feature(explicit_tail_calls))]
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#![cfg_attr(pulley_tail_calls, allow(incomplete_features, unstable_features))]
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#![deny(missing_docs)]
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#![no_std]
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#![expect(clippy::allow_attributes_without_reason, reason = "crate not migrated")]
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#[cfg(feature = "std")]
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#[macro_use]
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extern crate std;
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#[allow(unused_extern_crates)] // Some cfg's don't use this.
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extern crate alloc;
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/// Calls the given macro with each opcode.
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///
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/// # Instruction Guidelines
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///
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/// We're inventing an instruction set here which naturally brings a whole set
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/// of design questions. Note that this is explicitly intended to be only ever
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/// used for Pulley where there are a different set of design constraints than
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/// other instruction sets (e.g. general-purpose CPU ISAs). Some examples of
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/// constraints for Pulley are:
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///
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/// * Instructions must be portable to many architectures.
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/// * The Pulley ISA is mostly target-independent as the compilation target is
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/// currently only parameterized on pointer width and endianness.
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/// * Pulley instructions should be balance of time-to-decode and code size. For
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/// example super fancy bit-packing tricks might be tough to decode in
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/// software but might be worthwhile if it's quite common and greatly reduces
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/// the size of bytecode. There's not a hard-and-fast answer here, but a
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/// balance to be made.
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/// * Many "macro ops" are present to reduce the size of compiled bytecode so
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/// there is a wide set of duplicate functionality between opcodes (and this
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/// is expected).
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///
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/// Given all this it's also useful to have a set of guidelines used to name and
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/// develop Pulley instructions. As of the time of this writing it's still
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/// pretty early days for Pulley so some of these guidelines may change over
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/// time. Additionally instructions don't necessarily all follow these
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/// conventions and that may also change over time. With that in mind, here's a
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/// rough set of guidelines:
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///
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/// * Most instructions are prefixed with `x`, `f`, or `v`, indicating which
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/// type of register they're operating on. (e.g. `xadd32` operates on the `x`
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/// integer registers and `fadd32` operates on the `f` float registers).
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///
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/// * Most instructions are suffixed or otherwise contain the bit width they're
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/// operating on. For example `xadd32` is a 32-bit addition.
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///
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/// * If an instruction operates on signed or unsigned data (such as division
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/// and remainder), then the instruction is suffixed with `_s` or `_u`.
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///
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/// * Instructions operate on either 32 or 64-bit parts of a register.
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/// Instructions modifying only 32-bits of a register always modify the "low"
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/// part of a register and leave the upper part unmodified. This is intended
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/// to help 32-bit platforms where if most operations are 32-bit there's no
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/// need for extra instructions to sign or zero extend and modify the upper
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/// half of the register.
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///
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/// * Binops use `BinaryOperands<T>` for the destination and argument registers.
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///
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/// * Instructions operating on memory contain a few pieces of information:
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///
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/// ```text
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/// xload16le_u32_offset32
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/// │└─┬┘└┤└┤ └┬┘ └──┬───┘
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/// │ │ │ │ │ ▼
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/// │ │ │ │ │ addressing mode
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/// │ │ │ │ ▼
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/// │ │ │ │ width of register modified + sign-extension (optional)
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/// │ │ │ ▼
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/// │ │ │ endianness of the operation (le/be)
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/// │ │ ▼
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/// │ │ bit-width of the operation
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/// │ ▼
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/// │ what's happening (load/store)
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/// ▼
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/// register being operated on (x/f/z)
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/// ```
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///
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/// More guidelines might get added here over time, and if you have any
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/// questions feel free to raise them and we can try to add them here as well!
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#[macro_export]
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macro_rules! for_each_op {
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( $macro:ident ) => {
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$macro! {
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/// Transfer control the address in the `lr` register.
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ret = Ret;
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/// Transfer control to the PC at the given offset and set the `lr`
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/// register to the PC just after this instruction.
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///
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/// This instruction generally assumes that the Pulley ABI is being
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|
+
/// respected where arguments are in argument registers (starting at
|
98
|
+
/// x0 for integer arguments) and results are in result registers.
|
99
|
+
/// This instruction itself assume that all arguments are already in
|
100
|
+
/// their registers. Subsequent instructions below enable moving
|
101
|
+
/// arguments into the correct registers as part of the same call
|
102
|
+
/// instruction.
|
103
|
+
call = Call { offset: PcRelOffset };
|
104
|
+
/// Like `call`, but also `x0 = arg1`
|
105
|
+
call1 = Call1 { arg1: XReg, offset: PcRelOffset };
|
106
|
+
/// Like `call`, but also `x0, x1 = arg1, arg2`
|
107
|
+
call2 = Call2 { arg1: XReg, arg2: XReg, offset: PcRelOffset };
|
108
|
+
/// Like `call`, but also `x0, x1, x2 = arg1, arg2, arg3`
|
109
|
+
call3 = Call3 { arg1: XReg, arg2: XReg, arg3: XReg, offset: PcRelOffset };
|
110
|
+
/// Like `call`, but also `x0, x1, x2, x3 = arg1, arg2, arg3, arg4`
|
111
|
+
call4 = Call4 { arg1: XReg, arg2: XReg, arg3: XReg, arg4: XReg, offset: PcRelOffset };
|
112
|
+
|
113
|
+
/// Transfer control to the PC in `reg` and set `lr` to the PC just
|
114
|
+
/// after this instruction.
|
115
|
+
call_indirect = CallIndirect { reg: XReg };
|
116
|
+
|
117
|
+
/// Unconditionally transfer control to the PC at the given offset.
|
118
|
+
jump = Jump { offset: PcRelOffset };
|
119
|
+
|
120
|
+
/// Unconditionally transfer control to the PC at specified
|
121
|
+
/// register.
|
122
|
+
xjump = XJump { reg: XReg };
|
123
|
+
|
124
|
+
/// Conditionally transfer control to the given PC offset if
|
125
|
+
/// `low32(cond)` contains a non-zero value.
|
126
|
+
br_if32 = BrIf { cond: XReg, offset: PcRelOffset };
|
127
|
+
|
128
|
+
/// Conditionally transfer control to the given PC offset if
|
129
|
+
/// `low32(cond)` contains a zero value.
|
130
|
+
br_if_not32 = BrIfNot { cond: XReg, offset: PcRelOffset };
|
131
|
+
|
132
|
+
/// Branch if `a == b`.
|
133
|
+
br_if_xeq32 = BrIfXeq32 { a: XReg, b: XReg, offset: PcRelOffset };
|
134
|
+
/// Branch if `a != `b.
|
135
|
+
br_if_xneq32 = BrIfXneq32 { a: XReg, b: XReg, offset: PcRelOffset };
|
136
|
+
/// Branch if signed `a < b`.
|
137
|
+
br_if_xslt32 = BrIfXslt32 { a: XReg, b: XReg, offset: PcRelOffset };
|
138
|
+
/// Branch if signed `a <= b`.
|
139
|
+
br_if_xslteq32 = BrIfXslteq32 { a: XReg, b: XReg, offset: PcRelOffset };
|
140
|
+
/// Branch if unsigned `a < b`.
|
141
|
+
br_if_xult32 = BrIfXult32 { a: XReg, b: XReg, offset: PcRelOffset };
|
142
|
+
/// Branch if unsigned `a <= b`.
|
143
|
+
br_if_xulteq32 = BrIfXulteq32 { a: XReg, b: XReg, offset: PcRelOffset };
|
144
|
+
/// Branch if `a == b`.
|
145
|
+
br_if_xeq64 = BrIfXeq64 { a: XReg, b: XReg, offset: PcRelOffset };
|
146
|
+
/// Branch if `a != `b.
|
147
|
+
br_if_xneq64 = BrIfXneq64 { a: XReg, b: XReg, offset: PcRelOffset };
|
148
|
+
/// Branch if signed `a < b`.
|
149
|
+
br_if_xslt64 = BrIfXslt64 { a: XReg, b: XReg, offset: PcRelOffset };
|
150
|
+
/// Branch if signed `a <= b`.
|
151
|
+
br_if_xslteq64 = BrIfXslteq64 { a: XReg, b: XReg, offset: PcRelOffset };
|
152
|
+
/// Branch if unsigned `a < b`.
|
153
|
+
br_if_xult64 = BrIfXult64 { a: XReg, b: XReg, offset: PcRelOffset };
|
154
|
+
/// Branch if unsigned `a <= b`.
|
155
|
+
br_if_xulteq64 = BrIfXulteq64 { a: XReg, b: XReg, offset: PcRelOffset };
|
156
|
+
|
157
|
+
/// Branch if `a == b`.
|
158
|
+
br_if_xeq32_i8 = BrIfXeq32I8 { a: XReg, b: i8, offset: PcRelOffset };
|
159
|
+
/// Branch if `a == b`.
|
160
|
+
br_if_xeq32_i32 = BrIfXeq32I32 { a: XReg, b: i32, offset: PcRelOffset };
|
161
|
+
/// Branch if `a != `b.
|
162
|
+
br_if_xneq32_i8 = BrIfXneq32I8 { a: XReg, b: i8, offset: PcRelOffset };
|
163
|
+
/// Branch if `a != `b.
|
164
|
+
br_if_xneq32_i32 = BrIfXneq32I32 { a: XReg, b: i32, offset: PcRelOffset };
|
165
|
+
/// Branch if signed `a < b`.
|
166
|
+
br_if_xslt32_i8 = BrIfXslt32I8 { a: XReg, b: i8, offset: PcRelOffset };
|
167
|
+
/// Branch if signed `a < b`.
|
168
|
+
br_if_xslt32_i32 = BrIfXslt32I32 { a: XReg, b: i32, offset: PcRelOffset };
|
169
|
+
/// Branch if signed `a > b`.
|
170
|
+
br_if_xsgt32_i8 = BrIfXsgt32I8 { a: XReg, b: i8, offset: PcRelOffset };
|
171
|
+
/// Branch if signed `a > b`.
|
172
|
+
br_if_xsgt32_i32 = BrIfXsgt32I32 { a: XReg, b: i32, offset: PcRelOffset };
|
173
|
+
/// Branch if signed `a <= b`.
|
174
|
+
br_if_xslteq32_i8 = BrIfXslteq32I8 { a: XReg, b: i8, offset: PcRelOffset };
|
175
|
+
/// Branch if signed `a <= b`.
|
176
|
+
br_if_xslteq32_i32 = BrIfXslteq32I32 { a: XReg, b: i32, offset: PcRelOffset };
|
177
|
+
/// Branch if signed `a >= b`.
|
178
|
+
br_if_xsgteq32_i8 = BrIfXsgteq32I8 { a: XReg, b: i8, offset: PcRelOffset };
|
179
|
+
/// Branch if signed `a >= b`.
|
180
|
+
br_if_xsgteq32_i32 = BrIfXsgteq32I32 { a: XReg, b: i32, offset: PcRelOffset };
|
181
|
+
/// Branch if unsigned `a < b`.
|
182
|
+
br_if_xult32_u8 = BrIfXult32U8 { a: XReg, b: u8, offset: PcRelOffset };
|
183
|
+
/// Branch if unsigned `a < b`.
|
184
|
+
br_if_xult32_u32 = BrIfXult32U32 { a: XReg, b: u32, offset: PcRelOffset };
|
185
|
+
/// Branch if unsigned `a <= b`.
|
186
|
+
br_if_xulteq32_u8 = BrIfXulteq32U8 { a: XReg, b: u8, offset: PcRelOffset };
|
187
|
+
/// Branch if unsigned `a <= b`.
|
188
|
+
br_if_xulteq32_u32 = BrIfXulteq32U32 { a: XReg, b: u32, offset: PcRelOffset };
|
189
|
+
/// Branch if unsigned `a > b`.
|
190
|
+
br_if_xugt32_u8 = BrIfXugt32U8 { a: XReg, b: u8, offset: PcRelOffset };
|
191
|
+
/// Branch if unsigned `a > b`.
|
192
|
+
br_if_xugt32_u32 = BrIfXugt32U32 { a: XReg, b: u32, offset: PcRelOffset };
|
193
|
+
/// Branch if unsigned `a >= b`.
|
194
|
+
br_if_xugteq32_u8 = BrIfXugteq32U8 { a: XReg, b: u8, offset: PcRelOffset };
|
195
|
+
/// Branch if unsigned `a >= b`.
|
196
|
+
br_if_xugteq32_u32 = BrIfXugteq32U32 { a: XReg, b: u32, offset: PcRelOffset };
|
197
|
+
|
198
|
+
/// Branch if `a == b`.
|
199
|
+
br_if_xeq64_i8 = BrIfXeq64I8 { a: XReg, b: i8, offset: PcRelOffset };
|
200
|
+
/// Branch if `a == b`.
|
201
|
+
br_if_xeq64_i32 = BrIfXeq64I32 { a: XReg, b: i32, offset: PcRelOffset };
|
202
|
+
/// Branch if `a != `b.
|
203
|
+
br_if_xneq64_i8 = BrIfXneq64I8 { a: XReg, b: i8, offset: PcRelOffset };
|
204
|
+
/// Branch if `a != `b.
|
205
|
+
br_if_xneq64_i32 = BrIfXneq64I32 { a: XReg, b: i32, offset: PcRelOffset };
|
206
|
+
/// Branch if signed `a < b`.
|
207
|
+
br_if_xslt64_i8 = BrIfXslt64I8 { a: XReg, b: i8, offset: PcRelOffset };
|
208
|
+
/// Branch if signed `a < b`.
|
209
|
+
br_if_xslt64_i32 = BrIfXslt64I32 { a: XReg, b: i32, offset: PcRelOffset };
|
210
|
+
/// Branch if signed `a > b`.
|
211
|
+
br_if_xsgt64_i8 = BrIfXsgt64I8 { a: XReg, b: i8, offset: PcRelOffset };
|
212
|
+
/// Branch if signed `a > b`.
|
213
|
+
br_if_xsgt64_i32 = BrIfXsgt64I32 { a: XReg, b: i32, offset: PcRelOffset };
|
214
|
+
/// Branch if signed `a <= b`.
|
215
|
+
br_if_xslteq64_i8 = BrIfXslteq64I8 { a: XReg, b: i8, offset: PcRelOffset };
|
216
|
+
/// Branch if signed `a <= b`.
|
217
|
+
br_if_xslteq64_i32 = BrIfXslteq64I32 { a: XReg, b: i32, offset: PcRelOffset };
|
218
|
+
/// Branch if signed `a >= b`.
|
219
|
+
br_if_xsgteq64_i8 = BrIfXsgteq64I8 { a: XReg, b: i8, offset: PcRelOffset };
|
220
|
+
/// Branch if signed `a >= b`.
|
221
|
+
br_if_xsgteq64_i32 = BrIfXsgteq64I32 { a: XReg, b: i32, offset: PcRelOffset };
|
222
|
+
/// Branch if unsigned `a < b`.
|
223
|
+
br_if_xult64_u8 = BrIfXult64U8 { a: XReg, b: u8, offset: PcRelOffset };
|
224
|
+
/// Branch if unsigned `a < b`.
|
225
|
+
br_if_xult64_u32 = BrIfXult64U32 { a: XReg, b: u32, offset: PcRelOffset };
|
226
|
+
/// Branch if unsigned `a <= b`.
|
227
|
+
br_if_xulteq64_u8 = BrIfXulteq64U8 { a: XReg, b: u8, offset: PcRelOffset };
|
228
|
+
/// Branch if unsigned `a <= b`.
|
229
|
+
br_if_xulteq64_u32 = BrIfXulteq64U32 { a: XReg, b: u32, offset: PcRelOffset };
|
230
|
+
/// Branch if unsigned `a > b`.
|
231
|
+
br_if_xugt64_u8 = BrIfXugt64U8 { a: XReg, b: u8, offset: PcRelOffset };
|
232
|
+
/// Branch if unsigned `a > b`.
|
233
|
+
br_if_xugt64_u32 = BrIfXugt64U32 { a: XReg, b: u32, offset: PcRelOffset };
|
234
|
+
/// Branch if unsigned `a >= b`.
|
235
|
+
br_if_xugteq64_u8 = BrIfXugteq64U8 { a: XReg, b: u8, offset: PcRelOffset };
|
236
|
+
/// Branch if unsigned `a >= b`.
|
237
|
+
br_if_xugteq64_u32 = BrIfXugteq64U32 { a: XReg, b: u32, offset: PcRelOffset };
|
238
|
+
|
239
|
+
/// Branch to the label indicated by `low32(idx)`.
|
240
|
+
///
|
241
|
+
/// After this instruction are `amt` instances of `PcRelOffset`
|
242
|
+
/// and the `idx` selects which one will be branched to. The value
|
243
|
+
/// of `idx` is clamped to `amt - 1` (e.g. the last offset is the
|
244
|
+
/// "default" one.
|
245
|
+
br_table32 = BrTable32 { idx: XReg, amt: u32 };
|
246
|
+
|
247
|
+
/// Move between `x` registers.
|
248
|
+
xmov = Xmov { dst: XReg, src: XReg };
|
249
|
+
|
250
|
+
/// Set `dst = sign_extend(imm8)`.
|
251
|
+
xconst8 = Xconst8 { dst: XReg, imm: i8 };
|
252
|
+
/// Set `dst = sign_extend(imm16)`.
|
253
|
+
xconst16 = Xconst16 { dst: XReg, imm: i16 };
|
254
|
+
/// Set `dst = sign_extend(imm32)`.
|
255
|
+
xconst32 = Xconst32 { dst: XReg, imm: i32 };
|
256
|
+
/// Set `dst = imm64`.
|
257
|
+
xconst64 = Xconst64 { dst: XReg, imm: i64 };
|
258
|
+
|
259
|
+
/// 32-bit wrapping addition: `low32(dst) = low32(src1) + low32(src2)`.
|
260
|
+
///
|
261
|
+
/// The upper 32-bits of `dst` are unmodified.
|
262
|
+
xadd32 = Xadd32 { operands: BinaryOperands<XReg> };
|
263
|
+
/// Same as `xadd32` but `src2` is a zero-extended 8-bit immediate.
|
264
|
+
xadd32_u8 = Xadd32U8 { dst: XReg, src1: XReg, src2: u8 };
|
265
|
+
/// Same as `xadd32` but `src2` is a 32-bit immediate.
|
266
|
+
xadd32_u32 = Xadd32U32 { dst: XReg, src1: XReg, src2: u32 };
|
267
|
+
|
268
|
+
/// 64-bit wrapping addition: `dst = src1 + src2`.
|
269
|
+
xadd64 = Xadd64 { operands: BinaryOperands<XReg> };
|
270
|
+
/// Same as `xadd64` but `src2` is a zero-extended 8-bit immediate.
|
271
|
+
xadd64_u8 = Xadd64U8 { dst: XReg, src1: XReg, src2: u8 };
|
272
|
+
/// Same as `xadd64` but `src2` is a zero-extended 32-bit immediate.
|
273
|
+
xadd64_u32 = Xadd64U32 { dst: XReg, src1: XReg, src2: u32 };
|
274
|
+
|
275
|
+
/// 32-bit wrapping subtraction: `low32(dst) = low32(src1) - low32(src2)`.
|
276
|
+
///
|
277
|
+
/// The upper 32-bits of `dst` are unmodified.
|
278
|
+
xsub32 = Xsub32 { operands: BinaryOperands<XReg> };
|
279
|
+
/// Same as `xsub32` but `src2` is a zero-extended 8-bit immediate.
|
280
|
+
xsub32_u8 = Xsub32U8 { dst: XReg, src1: XReg, src2: u8 };
|
281
|
+
/// Same as `xsub32` but `src2` is a 32-bit immediate.
|
282
|
+
xsub32_u32 = Xsub32U32 { dst: XReg, src1: XReg, src2: u32 };
|
283
|
+
|
284
|
+
/// 64-bit wrapping subtraction: `dst = src1 - src2`.
|
285
|
+
xsub64 = Xsub64 { operands: BinaryOperands<XReg> };
|
286
|
+
/// Same as `xsub64` but `src2` is a zero-extended 8-bit immediate.
|
287
|
+
xsub64_u8 = Xsub64U8 { dst: XReg, src1: XReg, src2: u8 };
|
288
|
+
/// Same as `xsub64` but `src2` is a zero-extended 32-bit immediate.
|
289
|
+
xsub64_u32 = Xsub64U32 { dst: XReg, src1: XReg, src2: u32 };
|
290
|
+
|
291
|
+
/// `low32(dst) = low32(src1) * low32(src2)`
|
292
|
+
xmul32 = XMul32 { operands: BinaryOperands<XReg> };
|
293
|
+
/// Same as `xmul64` but `src2` is a sign-extended 8-bit immediate.
|
294
|
+
xmul32_s8 = Xmul32S8 { dst: XReg, src1: XReg, src2: i8 };
|
295
|
+
/// Same as `xmul32` but `src2` is a sign-extended 32-bit immediate.
|
296
|
+
xmul32_s32 = Xmul32S32 { dst: XReg, src1: XReg, src2: i32 };
|
297
|
+
|
298
|
+
/// `dst = src1 * src2`
|
299
|
+
xmul64 = XMul64 { operands: BinaryOperands<XReg> };
|
300
|
+
/// Same as `xmul64` but `src2` is a sign-extended 8-bit immediate.
|
301
|
+
xmul64_s8 = Xmul64S8 { dst: XReg, src1: XReg, src2: i8 };
|
302
|
+
/// Same as `xmul64` but `src2` is a sign-extended 64-bit immediate.
|
303
|
+
xmul64_s32 = Xmul64S32 { dst: XReg, src1: XReg, src2: i32 };
|
304
|
+
|
305
|
+
/// `low32(dst) = trailing_zeros(low32(src))`
|
306
|
+
xctz32 = Xctz32 { dst: XReg, src: XReg };
|
307
|
+
/// `dst = trailing_zeros(src)`
|
308
|
+
xctz64 = Xctz64 { dst: XReg, src: XReg };
|
309
|
+
|
310
|
+
/// `low32(dst) = leading_zeros(low32(src))`
|
311
|
+
xclz32 = Xclz32 { dst: XReg, src: XReg };
|
312
|
+
/// `dst = leading_zeros(src)`
|
313
|
+
xclz64 = Xclz64 { dst: XReg, src: XReg };
|
314
|
+
|
315
|
+
/// `low32(dst) = count_ones(low32(src))`
|
316
|
+
xpopcnt32 = Xpopcnt32 { dst: XReg, src: XReg };
|
317
|
+
/// `dst = count_ones(src)`
|
318
|
+
xpopcnt64 = Xpopcnt64 { dst: XReg, src: XReg };
|
319
|
+
|
320
|
+
/// `low32(dst) = rotate_left(low32(src1), low32(src2))`
|
321
|
+
xrotl32 = Xrotl32 { operands: BinaryOperands<XReg> };
|
322
|
+
/// `dst = rotate_left(src1, src2)`
|
323
|
+
xrotl64 = Xrotl64 { operands: BinaryOperands<XReg> };
|
324
|
+
|
325
|
+
/// `low32(dst) = rotate_right(low32(src1), low32(src2))`
|
326
|
+
xrotr32 = Xrotr32 { operands: BinaryOperands<XReg> };
|
327
|
+
/// `dst = rotate_right(src1, src2)`
|
328
|
+
xrotr64 = Xrotr64 { operands: BinaryOperands<XReg> };
|
329
|
+
|
330
|
+
/// `low32(dst) = low32(src1) << low5(src2)`
|
331
|
+
xshl32 = Xshl32 { operands: BinaryOperands<XReg> };
|
332
|
+
/// `low32(dst) = low32(src1) >> low5(src2)`
|
333
|
+
xshr32_s = Xshr32S { operands: BinaryOperands<XReg> };
|
334
|
+
/// `low32(dst) = low32(src1) >> low5(src2)`
|
335
|
+
xshr32_u = Xshr32U { operands: BinaryOperands<XReg> };
|
336
|
+
/// `dst = src1 << low5(src2)`
|
337
|
+
xshl64 = Xshl64 { operands: BinaryOperands<XReg> };
|
338
|
+
/// `dst = src1 >> low6(src2)`
|
339
|
+
xshr64_s = Xshr64S { operands: BinaryOperands<XReg> };
|
340
|
+
/// `dst = src1 >> low6(src2)`
|
341
|
+
xshr64_u = Xshr64U { operands: BinaryOperands<XReg> };
|
342
|
+
|
343
|
+
/// `low32(dst) = low32(src1) << low5(src2)`
|
344
|
+
xshl32_u6 = Xshl32U6 { operands: BinaryOperands<XReg, XReg, U6> };
|
345
|
+
/// `low32(dst) = low32(src1) >> low5(src2)`
|
346
|
+
xshr32_s_u6 = Xshr32SU6 { operands: BinaryOperands<XReg, XReg, U6> };
|
347
|
+
/// `low32(dst) = low32(src1) >> low5(src2)`
|
348
|
+
xshr32_u_u6 = Xshr32UU6 { operands: BinaryOperands<XReg, XReg, U6> };
|
349
|
+
/// `dst = src1 << low5(src2)`
|
350
|
+
xshl64_u6 = Xshl64U6 { operands: BinaryOperands<XReg, XReg, U6> };
|
351
|
+
/// `dst = src1 >> low6(src2)`
|
352
|
+
xshr64_s_u6 = Xshr64SU6 { operands: BinaryOperands<XReg, XReg, U6> };
|
353
|
+
/// `dst = src1 >> low6(src2)`
|
354
|
+
xshr64_u_u6 = Xshr64UU6 { operands: BinaryOperands<XReg, XReg, U6> };
|
355
|
+
|
356
|
+
/// `low32(dst) = -low32(src)`
|
357
|
+
xneg32 = Xneg32 { dst: XReg, src: XReg };
|
358
|
+
/// `dst = -src`
|
359
|
+
xneg64 = Xneg64 { dst: XReg, src: XReg };
|
360
|
+
|
361
|
+
/// `low32(dst) = src1 == src2`
|
362
|
+
xeq64 = Xeq64 { operands: BinaryOperands<XReg> };
|
363
|
+
/// `low32(dst) = src1 != src2`
|
364
|
+
xneq64 = Xneq64 { operands: BinaryOperands<XReg> };
|
365
|
+
/// `low32(dst) = src1 < src2` (signed)
|
366
|
+
xslt64 = Xslt64 { operands: BinaryOperands<XReg> };
|
367
|
+
/// `low32(dst) = src1 <= src2` (signed)
|
368
|
+
xslteq64 = Xslteq64 { operands: BinaryOperands<XReg> };
|
369
|
+
/// `low32(dst) = src1 < src2` (unsigned)
|
370
|
+
xult64 = Xult64 { operands: BinaryOperands<XReg> };
|
371
|
+
/// `low32(dst) = src1 <= src2` (unsigned)
|
372
|
+
xulteq64 = Xulteq64 { operands: BinaryOperands<XReg> };
|
373
|
+
/// `low32(dst) = low32(src1) == low32(src2)`
|
374
|
+
xeq32 = Xeq32 { operands: BinaryOperands<XReg> };
|
375
|
+
/// `low32(dst) = low32(src1) != low32(src2)`
|
376
|
+
xneq32 = Xneq32 { operands: BinaryOperands<XReg> };
|
377
|
+
/// `low32(dst) = low32(src1) < low32(src2)` (signed)
|
378
|
+
xslt32 = Xslt32 { operands: BinaryOperands<XReg> };
|
379
|
+
/// `low32(dst) = low32(src1) <= low32(src2)` (signed)
|
380
|
+
xslteq32 = Xslteq32 { operands: BinaryOperands<XReg> };
|
381
|
+
/// `low32(dst) = low32(src1) < low32(src2)` (unsigned)
|
382
|
+
xult32 = Xult32 { operands: BinaryOperands<XReg> };
|
383
|
+
/// `low32(dst) = low32(src1) <= low32(src2)` (unsigned)
|
384
|
+
xulteq32 = Xulteq32 { operands: BinaryOperands<XReg> };
|
385
|
+
|
386
|
+
/// `low32(dst) = zext(*(ptr + offset))`
|
387
|
+
xload8_u32_offset32 = XLoad8U32Offset32 { dst: XReg, ptr: XReg, offset: i32 };
|
388
|
+
/// `low32(dst) = sext(*(ptr + offset))`
|
389
|
+
xload8_s32_offset32 = XLoad8S32Offset32 { dst: XReg, ptr: XReg, offset: i32 };
|
390
|
+
/// `low32(dst) = zext(*(ptr + offset))`
|
391
|
+
xload16le_u32_offset32 = XLoad16LeU32Offset32 { dst: XReg, ptr: XReg, offset: i32 };
|
392
|
+
/// `low32(dst) = sext(*(ptr + offset))`
|
393
|
+
xload16le_s32_offset32 = XLoad16LeS32Offset32 { dst: XReg, ptr: XReg, offset: i32 };
|
394
|
+
/// `low32(dst) = *(ptr + offset)`
|
395
|
+
xload32le_offset32 = XLoad32LeOffset32 { dst: XReg, ptr: XReg, offset: i32 };
|
396
|
+
|
397
|
+
/// `dst = zext(*(ptr + offset))`
|
398
|
+
xload8_u64_offset32 = XLoad8U64Offset32 { dst: XReg, ptr: XReg, offset: i32 };
|
399
|
+
/// `dst = sext(*(ptr + offset))`
|
400
|
+
xload8_s64_offset32 = XLoad8S64Offset32 { dst: XReg, ptr: XReg, offset: i32 };
|
401
|
+
/// `dst = zext(*(ptr + offset))`
|
402
|
+
xload16le_u64_offset32 = XLoad16LeU64Offset32 { dst: XReg, ptr: XReg, offset: i32 };
|
403
|
+
/// `dst = sext(*(ptr + offset))`
|
404
|
+
xload16le_s64_offset32 = XLoad16LeS64Offset32 { dst: XReg, ptr: XReg, offset: i32 };
|
405
|
+
/// `dst = zext(*(ptr + offset))`
|
406
|
+
xload32le_u64_offset32 = XLoad32LeU64Offset32 { dst: XReg, ptr: XReg, offset: i32 };
|
407
|
+
/// `dst = sext(*(ptr + offset))`
|
408
|
+
xload32le_s64_offset32 = XLoad32LeS64Offset32 { dst: XReg, ptr: XReg, offset: i32 };
|
409
|
+
/// `dst = *(ptr + offset)`
|
410
|
+
xload64le_offset32 = XLoad64LeOffset32 { dst: XReg, ptr: XReg, offset: i32 };
|
411
|
+
|
412
|
+
/// `*(ptr + offset) = low8(src)`
|
413
|
+
xstore8_offset32 = XStore8Offset32 { ptr: XReg, offset: i32, src: XReg };
|
414
|
+
/// `*(ptr + offset) = low16(src)`
|
415
|
+
xstore16le_offset32 = XStore16LeOffset32 { ptr: XReg, offset: i32, src: XReg };
|
416
|
+
/// `*(ptr + offset) = low32(src)`
|
417
|
+
xstore32le_offset32 = XStore32LeOffset32 { ptr: XReg, offset: i32, src: XReg };
|
418
|
+
/// `*(ptr + offset) = low64(src)`
|
419
|
+
xstore64le_offset32 = XStore64LeOffset32 { ptr: XReg, offset: i32, src: XReg };
|
420
|
+
|
421
|
+
/// `low32(dst) = zext(*(ptr + offset))`
|
422
|
+
xload8_u32_offset8 = XLoad8U32Offset8 { dst: XReg, ptr: XReg, offset: u8 };
|
423
|
+
/// `low32(dst) = sext(*(ptr + offset))`
|
424
|
+
xload8_s32_offset8 = XLoad8S32Offset8 { dst: XReg, ptr: XReg, offset: u8 };
|
425
|
+
/// `low32(dst) = zext(*(ptr + offset))`
|
426
|
+
xload16le_u32_offset8 = XLoad16LeU32Offset8 { dst: XReg, ptr: XReg, offset: u8 };
|
427
|
+
/// `low32(dst) = sext(*(ptr + offset))`
|
428
|
+
xload16le_s32_offset8 = XLoad16LeS32Offset8 { dst: XReg, ptr: XReg, offset: u8 };
|
429
|
+
/// `low32(dst) = *(ptr + offset)`
|
430
|
+
xload32le_offset8 = XLoad32LeOffset8 { dst: XReg, ptr: XReg, offset: u8 };
|
431
|
+
|
432
|
+
/// `dst = zext(*(ptr + offset))`
|
433
|
+
xload8_u64_offset8 = XLoad8U64Offset8 { dst: XReg, ptr: XReg, offset: u8 };
|
434
|
+
/// `dst = sext(*(ptr + offset))`
|
435
|
+
xload8_s64_offset8 = XLoad8S64Offset8 { dst: XReg, ptr: XReg, offset: u8 };
|
436
|
+
/// `dst = zext(*(ptr + offset))`
|
437
|
+
xload16le_u64_offset8 = XLoad16LeU64Offset8 { dst: XReg, ptr: XReg, offset: u8 };
|
438
|
+
/// `dst = sext(*(ptr + offset))`
|
439
|
+
xload16le_s64_offset8 = XLoad16LeS64Offset8 { dst: XReg, ptr: XReg, offset: u8 };
|
440
|
+
/// `dst = zext(*(ptr + offset))`
|
441
|
+
xload32le_u64_offset8 = XLoad32LeU64Offset8 { dst: XReg, ptr: XReg, offset: u8 };
|
442
|
+
/// `dst = sext(*(ptr + offset))`
|
443
|
+
xload32le_s64_offset8 = XLoad32LeS64Offset8 { dst: XReg, ptr: XReg, offset: u8 };
|
444
|
+
/// `dst = *(ptr + offset)`
|
445
|
+
xload64le_offset8 = XLoad64LeOffset8 { dst: XReg, ptr: XReg, offset: u8 };
|
446
|
+
|
447
|
+
/// `*(ptr + offset) = low8(src)`
|
448
|
+
xstore8_offset8 = XStore8Offset8 { ptr: XReg, offset: u8, src: XReg };
|
449
|
+
/// `*(ptr + offset) = low16(src)`
|
450
|
+
xstore16le_offset8 = XStore16LeOffset8 { ptr: XReg, offset: u8, src: XReg };
|
451
|
+
/// `*(ptr + offset) = low32(src)`
|
452
|
+
xstore32le_offset8 = XStore32LeOffset8 { ptr: XReg, offset: u8, src: XReg };
|
453
|
+
/// `*(ptr + offset) = low64(src)`
|
454
|
+
xstore64le_offset8 = XStore64LeOffset8 { ptr: XReg, offset: u8, src: XReg };
|
455
|
+
|
456
|
+
/// `push lr; push fp; fp = sp`
|
457
|
+
push_frame = PushFrame ;
|
458
|
+
/// `sp = fp; pop fp; pop lr`
|
459
|
+
pop_frame = PopFrame ;
|
460
|
+
|
461
|
+
/// Macro-instruction to enter a function, allocate some stack, and
|
462
|
+
/// then save some registers.
|
463
|
+
///
|
464
|
+
/// This is equivalent to `push_frame`, `stack_alloc32 amt`, then
|
465
|
+
/// saving all of `regs` to the top of the stack just allocated.
|
466
|
+
push_frame_save = PushFrameSave { amt: u32, regs: RegSet<XReg> };
|
467
|
+
/// Inverse of `push_frame_save`. Restores `regs` from the top of
|
468
|
+
/// the stack, then runs `stack_free32 amt`, then runs `pop_frame`.
|
469
|
+
pop_frame_restore = PopFrameRestore { amt: u32, regs: RegSet<XReg> };
|
470
|
+
|
471
|
+
/// `sp = sp.checked_sub(amt)`
|
472
|
+
stack_alloc32 = StackAlloc32 { amt: u32 };
|
473
|
+
|
474
|
+
/// `sp = sp + amt`
|
475
|
+
stack_free32 = StackFree32 { amt: u32 };
|
476
|
+
|
477
|
+
/// `dst = zext(low8(src))`
|
478
|
+
zext8 = Zext8 { dst: XReg, src: XReg };
|
479
|
+
/// `dst = zext(low16(src))`
|
480
|
+
zext16 = Zext16 { dst: XReg, src: XReg };
|
481
|
+
/// `dst = zext(low32(src))`
|
482
|
+
zext32 = Zext32 { dst: XReg, src: XReg };
|
483
|
+
/// `dst = sext(low8(src))`
|
484
|
+
sext8 = Sext8 { dst: XReg, src: XReg };
|
485
|
+
/// `dst = sext(low16(src))`
|
486
|
+
sext16 = Sext16 { dst: XReg, src: XReg };
|
487
|
+
/// `dst = sext(low32(src))`
|
488
|
+
sext32 = Sext32 { dst: XReg, src: XReg };
|
489
|
+
|
490
|
+
/// `low32(dst) = |low32(src)|`
|
491
|
+
xabs32 = XAbs32 { dst: XReg, src: XReg };
|
492
|
+
/// `dst = |src|`
|
493
|
+
xabs64 = XAbs64 { dst: XReg, src: XReg };
|
494
|
+
|
495
|
+
/// `low32(dst) = low32(src1) / low32(src2)` (signed)
|
496
|
+
xdiv32_s = XDiv32S { operands: BinaryOperands<XReg> };
|
497
|
+
|
498
|
+
/// `dst = src1 / src2` (signed)
|
499
|
+
xdiv64_s = XDiv64S { operands: BinaryOperands<XReg> };
|
500
|
+
|
501
|
+
/// `low32(dst) = low32(src1) / low32(src2)` (unsigned)
|
502
|
+
xdiv32_u = XDiv32U { operands: BinaryOperands<XReg> };
|
503
|
+
|
504
|
+
/// `dst = src1 / src2` (unsigned)
|
505
|
+
xdiv64_u = XDiv64U { operands: BinaryOperands<XReg> };
|
506
|
+
|
507
|
+
/// `low32(dst) = low32(src1) % low32(src2)` (signed)
|
508
|
+
xrem32_s = XRem32S { operands: BinaryOperands<XReg> };
|
509
|
+
|
510
|
+
/// `dst = src1 / src2` (signed)
|
511
|
+
xrem64_s = XRem64S { operands: BinaryOperands<XReg> };
|
512
|
+
|
513
|
+
/// `low32(dst) = low32(src1) % low32(src2)` (unsigned)
|
514
|
+
xrem32_u = XRem32U { operands: BinaryOperands<XReg> };
|
515
|
+
|
516
|
+
/// `dst = src1 / src2` (unsigned)
|
517
|
+
xrem64_u = XRem64U { operands: BinaryOperands<XReg> };
|
518
|
+
|
519
|
+
/// `low32(dst) = low32(src1) & low32(src2)`
|
520
|
+
xband32 = XBand32 { operands: BinaryOperands<XReg> };
|
521
|
+
/// Same as `xband64` but `src2` is a sign-extended 8-bit immediate.
|
522
|
+
xband32_s8 = Xband32S8 { dst: XReg, src1: XReg, src2: i8 };
|
523
|
+
/// Same as `xband32` but `src2` is a sign-extended 32-bit immediate.
|
524
|
+
xband32_s32 = Xband32S32 { dst: XReg, src1: XReg, src2: i32 };
|
525
|
+
/// `dst = src1 & src2`
|
526
|
+
xband64 = XBand64 { operands: BinaryOperands<XReg> };
|
527
|
+
/// Same as `xband64` but `src2` is a sign-extended 8-bit immediate.
|
528
|
+
xband64_s8 = Xband64S8 { dst: XReg, src1: XReg, src2: i8 };
|
529
|
+
/// Same as `xband64` but `src2` is a sign-extended 32-bit immediate.
|
530
|
+
xband64_s32 = Xband64S32 { dst: XReg, src1: XReg, src2: i32 };
|
531
|
+
/// `low32(dst) = low32(src1) | low32(src2)`
|
532
|
+
xbor32 = XBor32 { operands: BinaryOperands<XReg> };
|
533
|
+
/// Same as `xbor64` but `src2` is a sign-extended 8-bit immediate.
|
534
|
+
xbor32_s8 = Xbor32S8 { dst: XReg, src1: XReg, src2: i8 };
|
535
|
+
/// Same as `xbor32` but `src2` is a sign-extended 32-bit immediate.
|
536
|
+
xbor32_s32 = Xbor32S32 { dst: XReg, src1: XReg, src2: i32 };
|
537
|
+
/// `dst = src1 | src2`
|
538
|
+
xbor64 = XBor64 { operands: BinaryOperands<XReg> };
|
539
|
+
/// Same as `xbor64` but `src2` is a sign-extended 8-bit immediate.
|
540
|
+
xbor64_s8 = Xbor64S8 { dst: XReg, src1: XReg, src2: i8 };
|
541
|
+
/// Same as `xbor64` but `src2` is a sign-extended 32-bit immediate.
|
542
|
+
xbor64_s32 = Xbor64S32 { dst: XReg, src1: XReg, src2: i32 };
|
543
|
+
|
544
|
+
/// `low32(dst) = low32(src1) ^ low32(src2)`
|
545
|
+
xbxor32 = XBxor32 { operands: BinaryOperands<XReg> };
|
546
|
+
/// Same as `xbxor64` but `src2` is a sign-extended 8-bit immediate.
|
547
|
+
xbxor32_s8 = Xbxor32S8 { dst: XReg, src1: XReg, src2: i8 };
|
548
|
+
/// Same as `xbxor32` but `src2` is a sign-extended 32-bit immediate.
|
549
|
+
xbxor32_s32 = Xbxor32S32 { dst: XReg, src1: XReg, src2: i32 };
|
550
|
+
/// `dst = src1 ^ src2`
|
551
|
+
xbxor64 = XBxor64 { operands: BinaryOperands<XReg> };
|
552
|
+
/// Same as `xbxor64` but `src2` is a sign-extended 8-bit immediate.
|
553
|
+
xbxor64_s8 = Xbxor64S8 { dst: XReg, src1: XReg, src2: i8 };
|
554
|
+
/// Same as `xbxor64` but `src2` is a sign-extended 32-bit immediate.
|
555
|
+
xbxor64_s32 = Xbxor64S32 { dst: XReg, src1: XReg, src2: i32 };
|
556
|
+
|
557
|
+
/// `low32(dst) = !low32(src1)`
|
558
|
+
xbnot32 = XBnot32 { dst: XReg, src: XReg };
|
559
|
+
/// `dst = !src1`
|
560
|
+
xbnot64 = XBnot64 { dst: XReg, src: XReg };
|
561
|
+
|
562
|
+
/// `low32(dst) = min(low32(src1), low32(src2))` (unsigned)
|
563
|
+
xmin32_u = Xmin32U { operands: BinaryOperands<XReg> };
|
564
|
+
/// `low32(dst) = min(low32(src1), low32(src2))` (signed)
|
565
|
+
xmin32_s = Xmin32S { operands: BinaryOperands<XReg> };
|
566
|
+
/// `low32(dst) = max(low32(src1), low32(src2))` (unsigned)
|
567
|
+
xmax32_u = Xmax32U { operands: BinaryOperands<XReg> };
|
568
|
+
/// `low32(dst) = max(low32(src1), low32(src2))` (signed)
|
569
|
+
xmax32_s = Xmax32S { operands: BinaryOperands<XReg> };
|
570
|
+
/// `dst = min(src1, src2)` (unsigned)
|
571
|
+
xmin64_u = Xmin64U { operands: BinaryOperands<XReg> };
|
572
|
+
/// `dst = min(src1, src2)` (signed)
|
573
|
+
xmin64_s = Xmin64S { operands: BinaryOperands<XReg> };
|
574
|
+
/// `dst = max(src1, src2)` (unsigned)
|
575
|
+
xmax64_u = Xmax64U { operands: BinaryOperands<XReg> };
|
576
|
+
/// `dst = max(src1, src2)` (signed)
|
577
|
+
xmax64_s = Xmax64S { operands: BinaryOperands<XReg> };
|
578
|
+
|
579
|
+
/// `low32(dst) = low32(cond) ? low32(if_nonzero) : low32(if_zero)`
|
580
|
+
xselect32 = XSelect32 { dst: XReg, cond: XReg, if_nonzero: XReg, if_zero: XReg };
|
581
|
+
/// `dst = low32(cond) ? if_nonzero : if_zero`
|
582
|
+
xselect64 = XSelect64 { dst: XReg, cond: XReg, if_nonzero: XReg, if_zero: XReg };
|
583
|
+
}
|
584
|
+
};
|
585
|
+
}
|
586
|
+
|
587
|
+
/// Calls the given macro with each extended opcode.
|
588
|
+
#[macro_export]
|
589
|
+
macro_rules! for_each_extended_op {
|
590
|
+
( $macro:ident ) => {
|
591
|
+
$macro! {
|
592
|
+
/// Raise a trap.
|
593
|
+
trap = Trap;
|
594
|
+
|
595
|
+
/// Do nothing.
|
596
|
+
nop = Nop;
|
597
|
+
|
598
|
+
/// A special opcode to halt interpreter execution and yield control
|
599
|
+
/// back to the host.
|
600
|
+
///
|
601
|
+
/// This opcode results in `DoneReason::CallIndirectHost` where the
|
602
|
+
/// `id` here is shepherded along to the embedder. It's up to the
|
603
|
+
/// embedder to determine what to do with the `id` and the current
|
604
|
+
/// state of registers and the stack.
|
605
|
+
///
|
606
|
+
/// In Wasmtime this is used to implement interpreter-to-host calls.
|
607
|
+
/// This is modeled as a `call` instruction where the first
|
608
|
+
/// parameter is the native function pointer to invoke and all
|
609
|
+
/// remaining parameters for the native function are in following
|
610
|
+
/// parameter positions (e.g. `x1`, `x2`, ...). The results of the
|
611
|
+
/// host call are then store in `x0`.
|
612
|
+
///
|
613
|
+
/// Handling this in Wasmtime is done through a "relocation" which
|
614
|
+
/// is resolved at link-time when raw bytecode from Cranelift is
|
615
|
+
/// assembled into the final object that Wasmtime will interpret.
|
616
|
+
call_indirect_host = CallIndirectHost { id: u8 };
|
617
|
+
|
618
|
+
/// Gets the special "fp" register and moves it into `dst`.
|
619
|
+
xmov_fp = XmovFp { dst: XReg };
|
620
|
+
|
621
|
+
/// Gets the special "lr" register and moves it into `dst`.
|
622
|
+
xmov_lr = XmovLr { dst: XReg };
|
623
|
+
|
624
|
+
/// `dst = byteswap(low32(src))`
|
625
|
+
bswap32 = Bswap32 { dst: XReg, src: XReg };
|
626
|
+
/// `dst = byteswap(src)`
|
627
|
+
bswap64 = Bswap64 { dst: XReg, src: XReg };
|
628
|
+
|
629
|
+
/// 32-bit checked unsigned addition: `low32(dst) = low32(src1) +
|
630
|
+
/// low32(src2)`.
|
631
|
+
///
|
632
|
+
/// The upper 32-bits of `dst` are unmodified. Traps if the addition
|
633
|
+
/// overflows.
|
634
|
+
xadd32_uoverflow_trap = Xadd32UoverflowTrap { operands: BinaryOperands<XReg> };
|
635
|
+
|
636
|
+
/// 64-bit checked unsigned addition: `dst = src1 + src2`.
|
637
|
+
xadd64_uoverflow_trap = Xadd64UoverflowTrap { operands: BinaryOperands<XReg> };
|
638
|
+
|
639
|
+
/// `dst = high64(src1 * src2)` (signed)
|
640
|
+
xmulhi64_s = XMulHi64S { operands: BinaryOperands<XReg> };
|
641
|
+
/// `dst = high64(src1 * src2)` (unsigned)
|
642
|
+
xmulhi64_u = XMulHi64U { operands: BinaryOperands<XReg> };
|
643
|
+
|
644
|
+
/// low32(dst) = if low32(src) == 0 { 0 } else { -1 }
|
645
|
+
xbmask32 = Xbmask32 { dst: XReg, src: XReg };
|
646
|
+
/// dst = if src == 0 { 0 } else { -1 }
|
647
|
+
xbmask64 = Xbmask64 { dst: XReg, src: XReg };
|
648
|
+
|
649
|
+
/// `*sp = low32(src); sp = sp.checked_add(4)`
|
650
|
+
xpush32 = XPush32 { src: XReg };
|
651
|
+
/// `for src in srcs { xpush32 src }`
|
652
|
+
xpush32_many = XPush32Many { srcs: RegSet<XReg> };
|
653
|
+
/// `*sp = src; sp = sp.checked_add(8)`
|
654
|
+
xpush64 = XPush64 { src: XReg };
|
655
|
+
/// `for src in srcs { xpush64 src }`
|
656
|
+
xpush64_many = XPush64Many { srcs: RegSet<XReg> };
|
657
|
+
|
658
|
+
/// `*dst = *sp; sp -= 4`
|
659
|
+
xpop32 = XPop32 { dst: XReg };
|
660
|
+
/// `for dst in dsts.rev() { xpop32 dst }`
|
661
|
+
xpop32_many = XPop32Many { dsts: RegSet<XReg> };
|
662
|
+
/// `*dst = *sp; sp -= 8`
|
663
|
+
xpop64 = XPop64 { dst: XReg };
|
664
|
+
/// `for dst in dsts.rev() { xpop64 dst }`
|
665
|
+
xpop64_many = XPop64Many { dsts: RegSet<XReg> };
|
666
|
+
|
667
|
+
/// `dst = zext(*(ptr + offset))`
|
668
|
+
xload16be_u64_offset32 = XLoad16BeU64Offset32 { dst: XReg, ptr: XReg, offset: i32 };
|
669
|
+
/// `dst = sext(*(ptr + offset))`
|
670
|
+
xload16be_s64_offset32 = XLoad16BeS64Offset32 { dst: XReg, ptr: XReg, offset: i32 };
|
671
|
+
/// `dst = zext(*(ptr + offset))`
|
672
|
+
xload32be_u64_offset32 = XLoad32BeU64Offset32 { dst: XReg, ptr: XReg, offset: i32 };
|
673
|
+
/// `dst = sext(*(ptr + offset))`
|
674
|
+
xload32be_s64_offset32 = XLoad32BeS64Offset32 { dst: XReg, ptr: XReg, offset: i32 };
|
675
|
+
/// `dst = *(ptr + offset)`
|
676
|
+
xload64be_offset32 = XLoad64BeOffset32 { dst: XReg, ptr: XReg, offset: i32 };
|
677
|
+
|
678
|
+
/// `*(ptr + offset) = low16(src)`
|
679
|
+
xstore16be_offset32 = XStore16BeOffset32 { ptr: XReg, offset: i32, src: XReg };
|
680
|
+
/// `*(ptr + offset) = low32(src)`
|
681
|
+
xstore32be_offset32 = XStore32BeOffset32 { ptr: XReg, offset: i32, src: XReg };
|
682
|
+
/// `*(ptr + offset) = low64(src)`
|
683
|
+
xstore64be_offset32 = XStore64BeOffset32 { ptr: XReg, offset: i32, src: XReg };
|
684
|
+
|
685
|
+
/// `low32(dst) = zext(*(ptr + offset))`
|
686
|
+
fload32be_offset32 = Fload32BeOffset32 { dst: FReg, ptr: XReg, offset: i32 };
|
687
|
+
/// `dst = *(ptr + offset)`
|
688
|
+
fload64be_offset32 = Fload64BeOffset32 { dst: FReg, ptr: XReg, offset: i32 };
|
689
|
+
/// `*(ptr + offset) = low32(src)`
|
690
|
+
fstore32be_offset32 = Fstore32BeOffset32 { ptr: XReg, offset: i32, src: FReg };
|
691
|
+
/// `*(ptr + offset) = src`
|
692
|
+
fstore64be_offset32 = Fstore64BeOffset32 { ptr: XReg, offset: i32, src: FReg };
|
693
|
+
|
694
|
+
/// `low32(dst) = zext(*(ptr + offset))`
|
695
|
+
fload32le_offset32 = Fload32LeOffset32 { dst: FReg, ptr: XReg, offset: i32 };
|
696
|
+
/// `dst = *(ptr + offset)`
|
697
|
+
fload64le_offset32 = Fload64LeOffset32 { dst: FReg, ptr: XReg, offset: i32 };
|
698
|
+
/// `*(ptr + offset) = low32(src)`
|
699
|
+
fstore32le_offset32 = Fstore32LeOffset32 { ptr: XReg, offset: i32, src: FReg };
|
700
|
+
/// `*(ptr + offset) = src`
|
701
|
+
fstore64le_offset32 = Fstore64LeOffset32 { ptr: XReg, offset: i32, src: FReg };
|
702
|
+
|
703
|
+
/// `dst = *(ptr + offset)`
|
704
|
+
vload128le_offset32 = VLoad128Offset32 { dst: VReg, ptr: XReg, offset: i32 };
|
705
|
+
/// `*(ptr + offset) = src`
|
706
|
+
vstore128le_offset32 = Vstore128LeOffset32 { ptr: XReg, offset: i32, src: VReg };
|
707
|
+
|
708
|
+
/// Move between `f` registers.
|
709
|
+
fmov = Fmov { dst: FReg, src: FReg };
|
710
|
+
/// Move between `v` registers.
|
711
|
+
vmov = Vmov { dst: VReg, src: VReg };
|
712
|
+
|
713
|
+
/// `low32(dst) = bitcast low32(src) as i32`
|
714
|
+
bitcast_int_from_float_32 = BitcastIntFromFloat32 { dst: XReg, src: FReg };
|
715
|
+
/// `dst = bitcast src as i64`
|
716
|
+
bitcast_int_from_float_64 = BitcastIntFromFloat64 { dst: XReg, src: FReg };
|
717
|
+
/// `low32(dst) = bitcast low32(src) as f32`
|
718
|
+
bitcast_float_from_int_32 = BitcastFloatFromInt32 { dst: FReg, src: XReg };
|
719
|
+
/// `dst = bitcast src as f64`
|
720
|
+
bitcast_float_from_int_64 = BitcastFloatFromInt64 { dst: FReg, src: XReg };
|
721
|
+
|
722
|
+
/// `low32(dst) = bits`
|
723
|
+
fconst32 = FConst32 { dst: FReg, bits: u32 };
|
724
|
+
/// `dst = bits`
|
725
|
+
fconst64 = FConst64 { dst: FReg, bits: u64 };
|
726
|
+
|
727
|
+
/// `low32(dst) = zext(src1 == src2)`
|
728
|
+
feq32 = Feq32 { dst: XReg, src1: FReg, src2: FReg };
|
729
|
+
/// `low32(dst) = zext(src1 != src2)`
|
730
|
+
fneq32 = Fneq32 { dst: XReg, src1: FReg, src2: FReg };
|
731
|
+
/// `low32(dst) = zext(src1 < src2)`
|
732
|
+
flt32 = Flt32 { dst: XReg, src1: FReg, src2: FReg };
|
733
|
+
/// `low32(dst) = zext(src1 <= src2)`
|
734
|
+
flteq32 = Flteq32 { dst: XReg, src1: FReg, src2: FReg };
|
735
|
+
/// `low32(dst) = zext(src1 == src2)`
|
736
|
+
feq64 = Feq64 { dst: XReg, src1: FReg, src2: FReg };
|
737
|
+
/// `low32(dst) = zext(src1 != src2)`
|
738
|
+
fneq64 = Fneq64 { dst: XReg, src1: FReg, src2: FReg };
|
739
|
+
/// `low32(dst) = zext(src1 < src2)`
|
740
|
+
flt64 = Flt64 { dst: XReg, src1: FReg, src2: FReg };
|
741
|
+
/// `low32(dst) = zext(src1 <= src2)`
|
742
|
+
flteq64 = Flteq64 { dst: XReg, src1: FReg, src2: FReg };
|
743
|
+
|
744
|
+
/// `low32(dst) = low32(cond) ? low32(if_nonzero) : low32(if_zero)`
|
745
|
+
fselect32 = FSelect32 { dst: FReg, cond: XReg, if_nonzero: FReg, if_zero: FReg };
|
746
|
+
/// `dst = low32(cond) ? if_nonzero : if_zero`
|
747
|
+
fselect64 = FSelect64 { dst: FReg, cond: XReg, if_nonzero: FReg, if_zero: FReg };
|
748
|
+
|
749
|
+
/// `low32(dst) = demote(src)`
|
750
|
+
f32_from_f64 = F32FromF64 { dst: FReg, src: FReg };
|
751
|
+
/// `(st) = promote(low32(src))`
|
752
|
+
f64_from_f32 = F64FromF32 { dst: FReg, src: FReg };
|
753
|
+
|
754
|
+
/// `low32(dst) = checked_f32_from_signed(low32(src))`
|
755
|
+
f32_from_x32_s = F32FromX32S { dst: FReg, src: XReg };
|
756
|
+
/// `low32(dst) = checked_f32_from_unsigned(low32(src))`
|
757
|
+
f32_from_x32_u = F32FromX32U { dst: FReg, src: XReg };
|
758
|
+
/// `low32(dst) = checked_f32_from_signed(src)`
|
759
|
+
f32_from_x64_s = F32FromX64S { dst: FReg, src: XReg };
|
760
|
+
/// `low32(dst) = checked_f32_from_unsigned(src)`
|
761
|
+
f32_from_x64_u = F32FromX64U { dst: FReg, src: XReg };
|
762
|
+
/// `dst = checked_f64_from_signed(low32(src))`
|
763
|
+
f64_from_x32_s = F64FromX32S { dst: FReg, src: XReg };
|
764
|
+
/// `dst = checked_f64_from_unsigned(low32(src))`
|
765
|
+
f64_from_x32_u = F64FromX32U { dst: FReg, src: XReg };
|
766
|
+
/// `dst = checked_f64_from_signed(src)`
|
767
|
+
f64_from_x64_s = F64FromX64S { dst: FReg, src: XReg };
|
768
|
+
/// `dst = checked_f64_from_unsigned(src)`
|
769
|
+
f64_from_x64_u = F64FromX64U { dst: FReg, src: XReg };
|
770
|
+
|
771
|
+
/// `low32(dst) = checked_signed_from_f32(low32(src))`
|
772
|
+
x32_from_f32_s = X32FromF32S { dst: XReg, src: FReg };
|
773
|
+
/// `low32(dst) = checked_unsigned_from_f32(low32(src))`
|
774
|
+
x32_from_f32_u = X32FromF32U { dst: XReg, src: FReg };
|
775
|
+
/// `low32(dst) = checked_signed_from_f64(src)`
|
776
|
+
x32_from_f64_s = X32FromF64S { dst: XReg, src: FReg };
|
777
|
+
/// `low32(dst) = checked_unsigned_from_f64(src)`
|
778
|
+
x32_from_f64_u = X32FromF64U { dst: XReg, src: FReg };
|
779
|
+
/// `dst = checked_signed_from_f32(low32(src))`
|
780
|
+
x64_from_f32_s = X64FromF32S { dst: XReg, src: FReg };
|
781
|
+
/// `dst = checked_unsigned_from_f32(low32(src))`
|
782
|
+
x64_from_f32_u = X64FromF32U { dst: XReg, src: FReg };
|
783
|
+
/// `dst = checked_signed_from_f64(src)`
|
784
|
+
x64_from_f64_s = X64FromF64S { dst: XReg, src: FReg };
|
785
|
+
/// `dst = checked_unsigned_from_f64(src)`
|
786
|
+
x64_from_f64_u = X64FromF64U { dst: XReg, src: FReg };
|
787
|
+
|
788
|
+
/// `low32(dst) = saturating_signed_from_f32(low32(src))`
|
789
|
+
x32_from_f32_s_sat = X32FromF32SSat { dst: XReg, src: FReg };
|
790
|
+
/// `low32(dst) = saturating_unsigned_from_f32(low32(src))`
|
791
|
+
x32_from_f32_u_sat = X32FromF32USat { dst: XReg, src: FReg };
|
792
|
+
/// `low32(dst) = saturating_signed_from_f64(src)`
|
793
|
+
x32_from_f64_s_sat = X32FromF64SSat { dst: XReg, src: FReg };
|
794
|
+
/// `low32(dst) = saturating_unsigned_from_f64(src)`
|
795
|
+
x32_from_f64_u_sat = X32FromF64USat { dst: XReg, src: FReg };
|
796
|
+
/// `dst = saturating_signed_from_f32(low32(src))`
|
797
|
+
x64_from_f32_s_sat = X64FromF32SSat { dst: XReg, src: FReg };
|
798
|
+
/// `dst = saturating_unsigned_from_f32(low32(src))`
|
799
|
+
x64_from_f32_u_sat = X64FromF32USat { dst: XReg, src: FReg };
|
800
|
+
/// `dst = saturating_signed_from_f64(src)`
|
801
|
+
x64_from_f64_s_sat = X64FromF64SSat { dst: XReg, src: FReg };
|
802
|
+
/// `dst = saturating_unsigned_from_f64(src)`
|
803
|
+
x64_from_f64_u_sat = X64FromF64USat { dst: XReg, src: FReg };
|
804
|
+
|
805
|
+
/// `low32(dst) = copysign(low32(src1), low32(src2))`
|
806
|
+
fcopysign32 = FCopySign32 { operands: BinaryOperands<FReg> };
|
807
|
+
/// `dst = copysign(src1, src2)`
|
808
|
+
fcopysign64 = FCopySign64 { operands: BinaryOperands<FReg> };
|
809
|
+
|
810
|
+
/// `low32(dst) = low32(src1) + low32(src2)`
|
811
|
+
fadd32 = Fadd32 { operands: BinaryOperands<FReg> };
|
812
|
+
/// `low32(dst) = low32(src1) - low32(src2)`
|
813
|
+
fsub32 = Fsub32 { operands: BinaryOperands<FReg> };
|
814
|
+
/// `low32(dst) = low32(src1) * low32(src2)`
|
815
|
+
fmul32 = Fmul32 { operands: BinaryOperands<FReg> };
|
816
|
+
/// `low32(dst) = low32(src1) / low32(src2)`
|
817
|
+
fdiv32 = Fdiv32 { operands: BinaryOperands<FReg> };
|
818
|
+
/// `low128(dst) = low128(src1) / low128(src2)`
|
819
|
+
vdivf32x4 = Vdivf32x4 { operands: BinaryOperands<VReg> };
|
820
|
+
/// `low32(dst) = ieee_maximum(low32(src1), low32(src2))`
|
821
|
+
fmaximum32 = Fmaximum32 { operands: BinaryOperands<FReg> };
|
822
|
+
/// `low32(dst) = ieee_minimum(low32(src1), low32(src2))`
|
823
|
+
fminimum32 = Fminimum32 { operands: BinaryOperands<FReg> };
|
824
|
+
/// `low32(dst) = ieee_trunc(low32(src))`
|
825
|
+
ftrunc32 = Ftrunc32 { dst: FReg, src: FReg };
|
826
|
+
/// `low128(dst) = ieee_trunc(low128(src))`
|
827
|
+
vtrunc32x4 = Vtrunc32x4 { dst: VReg, src: VReg };
|
828
|
+
/// `low128(dst) = ieee_trunc(low128(src))`
|
829
|
+
vtrunc64x2 = Vtrunc64x2 { dst: VReg, src: VReg };
|
830
|
+
/// `low32(dst) = ieee_floor(low32(src))`
|
831
|
+
ffloor32 = Ffloor32 { dst: FReg, src: FReg };
|
832
|
+
/// `low128(dst) = ieee_floor(low128(src))`
|
833
|
+
vfloor32x4 = Vfloor32x4 { dst: VReg, src: VReg };
|
834
|
+
/// `low128(dst) = ieee_floor(low128(src))`
|
835
|
+
vfloor64x2 = Vfloor64x2 { dst: VReg, src: VReg };
|
836
|
+
/// `low32(dst) = ieee_ceil(low32(src))`
|
837
|
+
fceil32 = Fceil32 { dst: FReg, src: FReg };
|
838
|
+
/// `low128(dst) = ieee_ceil(low128(src))`
|
839
|
+
vceil32x4 = Vceil32x4 { dst: VReg, src: VReg };
|
840
|
+
/// `low128(dst) = ieee_ceil(low128(src))`
|
841
|
+
vceil64x2 = Vceil64x2 { dst: VReg, src: VReg };
|
842
|
+
/// `low32(dst) = ieee_nearest(low32(src))`
|
843
|
+
fnearest32 = Fnearest32 { dst: FReg, src: FReg };
|
844
|
+
/// `low32(dst) = ieee_sqrt(low32(src))`
|
845
|
+
fsqrt32 = Fsqrt32 { dst: FReg, src: FReg };
|
846
|
+
/// `low32(dst) = ieee_sqrt(low32(src))`
|
847
|
+
vsqrt32x4 = Vsqrt32x4 { dst: VReg, src: VReg };
|
848
|
+
/// `low32(dst) = ieee_sqrt(low32(src))`
|
849
|
+
vsqrt64x2 = Vsqrt64x2 { dst: VReg, src: VReg };
|
850
|
+
/// `low32(dst) = -low32(src)`
|
851
|
+
fneg32 = Fneg32 { dst: FReg, src: FReg };
|
852
|
+
/// `low32(dst) = |low32(src)|`
|
853
|
+
fabs32 = Fabs32 { dst: FReg, src: FReg };
|
854
|
+
|
855
|
+
/// `dst = src1 + src2`
|
856
|
+
fadd64 = Fadd64 { operands: BinaryOperands<FReg> };
|
857
|
+
/// `dst = src1 - src2`
|
858
|
+
fsub64 = Fsub64 { operands: BinaryOperands<FReg> };
|
859
|
+
/// `dst = src1 * src2`
|
860
|
+
fmul64 = Fmul64 { operands: BinaryOperands<FReg> };
|
861
|
+
/// `dst = src1 / src2`
|
862
|
+
fdiv64 = Fdiv64 { operands: BinaryOperands<FReg> };
|
863
|
+
/// `dst = src1 / src2`
|
864
|
+
vdivf64x2 = VDivF64x2 { operands: BinaryOperands<VReg> };
|
865
|
+
/// `dst = ieee_maximum(src1, src2)`
|
866
|
+
fmaximum64 = Fmaximum64 { operands: BinaryOperands<FReg> };
|
867
|
+
/// `dst = ieee_minimum(src1, src2)`
|
868
|
+
fminimum64 = Fminimum64 { operands: BinaryOperands<FReg> };
|
869
|
+
/// `dst = ieee_trunc(src)`
|
870
|
+
ftrunc64 = Ftrunc64 { dst: FReg, src: FReg };
|
871
|
+
/// `dst = ieee_floor(src)`
|
872
|
+
ffloor64 = Ffloor64 { dst: FReg, src: FReg };
|
873
|
+
/// `dst = ieee_ceil(src)`
|
874
|
+
fceil64 = Fceil64 { dst: FReg, src: FReg };
|
875
|
+
/// `dst = ieee_nearest(src)`
|
876
|
+
fnearest64 = Fnearest64 { dst: FReg, src: FReg };
|
877
|
+
/// `low128(dst) = ieee_nearest(low128(src))`
|
878
|
+
vnearest32x4 = Vnearest32x4 { dst: VReg, src: VReg };
|
879
|
+
/// `low128(dst) = ieee_nearest(low128(src))`
|
880
|
+
vnearest64x2 = Vnearest64x2 { dst: VReg, src: VReg };
|
881
|
+
/// `dst = ieee_sqrt(src)`
|
882
|
+
fsqrt64 = Fsqrt64 { dst: FReg, src: FReg };
|
883
|
+
/// `dst = -src`
|
884
|
+
fneg64 = Fneg64 { dst: FReg, src: FReg };
|
885
|
+
/// `dst = |src|`
|
886
|
+
fabs64 = Fabs64 { dst: FReg, src: FReg };
|
887
|
+
|
888
|
+
/// `dst = imm`
|
889
|
+
vconst128 = Vconst128 { dst: VReg, imm: u128 };
|
890
|
+
|
891
|
+
/// `dst = src1 + src2`
|
892
|
+
vaddi8x16 = VAddI8x16 { operands: BinaryOperands<VReg> };
|
893
|
+
/// `dst = src1 + src2`
|
894
|
+
vaddi16x8 = VAddI16x8 { operands: BinaryOperands<VReg> };
|
895
|
+
/// `dst = src1 + src2`
|
896
|
+
vaddi32x4 = VAddI32x4 { operands: BinaryOperands<VReg> };
|
897
|
+
/// `dst = src1 + src2`
|
898
|
+
vaddi64x2 = VAddI64x2 { operands: BinaryOperands<VReg> };
|
899
|
+
/// `dst = src1 + src2`
|
900
|
+
vaddf32x4 = VAddF32x4 { operands: BinaryOperands<VReg> };
|
901
|
+
/// `dst = src1 + src2`
|
902
|
+
vaddf64x2 = VAddF64x2 { operands: BinaryOperands<VReg> };
|
903
|
+
|
904
|
+
/// `dst = satruating_add(src1, src2)`
|
905
|
+
vaddi8x16_sat = VAddI8x16Sat { operands: BinaryOperands<VReg> };
|
906
|
+
/// `dst = satruating_add(src1, src2)`
|
907
|
+
vaddu8x16_sat = VAddU8x16Sat { operands: BinaryOperands<VReg> };
|
908
|
+
/// `dst = satruating_add(src1, src2)`
|
909
|
+
vaddi16x8_sat = VAddI16x8Sat { operands: BinaryOperands<VReg> };
|
910
|
+
/// `dst = satruating_add(src1, src2)`
|
911
|
+
vaddu16x8_sat = VAddU16x8Sat { operands: BinaryOperands<VReg> };
|
912
|
+
|
913
|
+
/// `dst = [src1[0] + src1[1], ..., src2[6] + src2[7]]`
|
914
|
+
vaddpairwisei16x8_s = VAddpairwiseI16x8S { operands: BinaryOperands<VReg> };
|
915
|
+
/// `dst = [src1[0] + src1[1], ..., src2[2] + src2[3]]`
|
916
|
+
vaddpairwisei32x4_s = VAddpairwiseI32x4S { operands: BinaryOperands<VReg> };
|
917
|
+
|
918
|
+
/// `dst = src1 << src2`
|
919
|
+
vshli8x16 = VShlI8x16 { operands: BinaryOperands<VReg, VReg, XReg> };
|
920
|
+
/// `dst = src1 << src2`
|
921
|
+
vshli16x8 = VShlI16x8 { operands: BinaryOperands<VReg, VReg, XReg> };
|
922
|
+
/// `dst = src1 << src2`
|
923
|
+
vshli32x4 = VShlI32x4 { operands: BinaryOperands<VReg, VReg, XReg> };
|
924
|
+
/// `dst = src1 << src2`
|
925
|
+
vshli64x2 = VShlI64x2 { operands: BinaryOperands<VReg, VReg, XReg> };
|
926
|
+
/// `dst = src1 >> src2` (signed)
|
927
|
+
vshri8x16_s = VShrI8x16S { operands: BinaryOperands<VReg, VReg, XReg> };
|
928
|
+
/// `dst = src1 >> src2` (signed)
|
929
|
+
vshri16x8_s = VShrI16x8S { operands: BinaryOperands<VReg, VReg, XReg> };
|
930
|
+
/// `dst = src1 >> src2` (signed)
|
931
|
+
vshri32x4_s = VShrI32x4S { operands: BinaryOperands<VReg, VReg, XReg> };
|
932
|
+
/// `dst = src1 >> src2` (signed)
|
933
|
+
vshri64x2_s = VShrI64x2S { operands: BinaryOperands<VReg, VReg, XReg> };
|
934
|
+
/// `dst = src1 >> src2` (unsigned)
|
935
|
+
vshri8x16_u = VShrI8x16U { operands: BinaryOperands<VReg, VReg, XReg> };
|
936
|
+
/// `dst = src1 >> src2` (unsigned)
|
937
|
+
vshri16x8_u = VShrI16x8U { operands: BinaryOperands<VReg, VReg, XReg> };
|
938
|
+
/// `dst = src1 >> src2` (unsigned)
|
939
|
+
vshri32x4_u = VShrI32x4U { operands: BinaryOperands<VReg, VReg, XReg> };
|
940
|
+
/// `dst = src1 >> src2` (unsigned)
|
941
|
+
vshri64x2_u = VShrI64x2U { operands: BinaryOperands<VReg, VReg, XReg> };
|
942
|
+
|
943
|
+
/// `dst = splat(low8(src))`
|
944
|
+
vsplatx8 = VSplatX8 { dst: VReg, src: XReg };
|
945
|
+
/// `dst = splat(low16(src))`
|
946
|
+
vsplatx16 = VSplatX16 { dst: VReg, src: XReg };
|
947
|
+
/// `dst = splat(low32(src))`
|
948
|
+
vsplatx32 = VSplatX32 { dst: VReg, src: XReg };
|
949
|
+
/// `dst = splat(src)`
|
950
|
+
vsplatx64 = VSplatX64 { dst: VReg, src: XReg };
|
951
|
+
/// `dst = splat(low32(src))`
|
952
|
+
vsplatf32 = VSplatF32 { dst: VReg, src: FReg };
|
953
|
+
/// `dst = splat(src)`
|
954
|
+
vsplatf64 = VSplatF64 { dst: VReg, src: FReg };
|
955
|
+
|
956
|
+
/// Load the 64-bit source as i8x8 and sign-extend to i16x8.
|
957
|
+
vload8x8_s_offset32 = VLoad8x8SOffset32 { dst: VReg, ptr: XReg, offset: i32 };
|
958
|
+
/// Load the 64-bit source as u8x8 and zero-extend to i16x8.
|
959
|
+
vload8x8_u_offset32 = VLoad8x8UOffset32 { dst: VReg, ptr: XReg, offset: i32 };
|
960
|
+
/// Load the 64-bit source as i16x4 and sign-extend to i32x4.
|
961
|
+
vload16x4le_s_offset32 = VLoad16x4LeSOffset32 { dst: VReg, ptr: XReg, offset: i32 };
|
962
|
+
/// Load the 64-bit source as u16x4 and zero-extend to i32x4.
|
963
|
+
vload16x4le_u_offset32 = VLoad16x4LeUOffset32 { dst: VReg, ptr: XReg, offset: i32 };
|
964
|
+
/// Load the 64-bit source as i32x2 and sign-extend to i64x2.
|
965
|
+
vload32x2le_s_offset32 = VLoad32x2LeSOffset32 { dst: VReg, ptr: XReg, offset: i32 };
|
966
|
+
/// Load the 64-bit source as u32x2 and zero-extend to i64x2.
|
967
|
+
vload32x2le_u_offset32 = VLoad32x2LeUOffset32 { dst: VReg, ptr: XReg, offset: i32 };
|
968
|
+
|
969
|
+
/// `dst = src1 & src2`
|
970
|
+
vband128 = VBand128 { operands: BinaryOperands<VReg> };
|
971
|
+
/// `dst = src1 | src2`
|
972
|
+
vbor128 = VBor128 { operands: BinaryOperands<VReg> };
|
973
|
+
/// `dst = src1 ^ src2`
|
974
|
+
vbxor128 = VBxor128 { operands: BinaryOperands<VReg> };
|
975
|
+
/// `dst = !src1`
|
976
|
+
vbnot128 = VBnot128 { dst: VReg, src: VReg };
|
977
|
+
/// `dst = (c & x) | (!c & y)`
|
978
|
+
vbitselect128 = VBitselect128 { dst: VReg, c: VReg, x: VReg, y: VReg };
|
979
|
+
/// Collect high bits of each lane into the low 32-bits of the
|
980
|
+
/// destination.
|
981
|
+
vbitmask8x16 = Vbitmask8x16 { dst: XReg, src: VReg };
|
982
|
+
/// Collect high bits of each lane into the low 32-bits of the
|
983
|
+
/// destination.
|
984
|
+
vbitmask16x8 = Vbitmask16x8 { dst: XReg, src: VReg };
|
985
|
+
/// Collect high bits of each lane into the low 32-bits of the
|
986
|
+
/// destination.
|
987
|
+
vbitmask32x4 = Vbitmask32x4 { dst: XReg, src: VReg };
|
988
|
+
/// Collect high bits of each lane into the low 32-bits of the
|
989
|
+
/// destination.
|
990
|
+
vbitmask64x2 = Vbitmask64x2 { dst: XReg, src: VReg };
|
991
|
+
/// Store whether all lanes are nonzero in `dst`.
|
992
|
+
valltrue8x16 = Valltrue8x16 { dst: XReg, src: VReg };
|
993
|
+
/// Store whether all lanes are nonzero in `dst`.
|
994
|
+
valltrue16x8 = Valltrue16x8 { dst: XReg, src: VReg };
|
995
|
+
/// Store whether all lanes are nonzero in `dst`.
|
996
|
+
valltrue32x4 = Valltrue32x4 { dst: XReg, src: VReg };
|
997
|
+
/// Store whether any lanes are nonzero in `dst`.
|
998
|
+
valltrue64x2 = Valltrue64x2 { dst: XReg, src: VReg };
|
999
|
+
/// Store whether any lanes are nonzero in `dst`.
|
1000
|
+
vanytrue8x16 = Vanytrue8x16 { dst: XReg, src: VReg };
|
1001
|
+
/// Store whether any lanes are nonzero in `dst`.
|
1002
|
+
vanytrue16x8 = Vanytrue16x8 { dst: XReg, src: VReg };
|
1003
|
+
/// Store whether any lanes are nonzero in `dst`.
|
1004
|
+
vanytrue32x4 = Vanytrue32x4 { dst: XReg, src: VReg };
|
1005
|
+
/// Store whether any lanes are nonzero in `dst`.
|
1006
|
+
vanytrue64x2 = Vanytrue64x2 { dst: XReg, src: VReg };
|
1007
|
+
|
1008
|
+
/// Int-to-float conversion (same as `f32_from_x32_s`)
|
1009
|
+
vf32x4_from_i32x4_s = VF32x4FromI32x4S { dst: VReg, src: VReg };
|
1010
|
+
/// Int-to-float conversion (same as `f32_from_x32_u`)
|
1011
|
+
vf32x4_from_i32x4_u = VF32x4FromI32x4U { dst: VReg, src: VReg };
|
1012
|
+
/// Int-to-float conversion (same as `f64_from_x64_s`)
|
1013
|
+
vf64x2_from_i64x2_s = VF64x2FromI64x2S { dst: VReg, src: VReg };
|
1014
|
+
/// Int-to-float conversion (same as `f64_from_x64_u`)
|
1015
|
+
vf64x2_from_i64x2_u = VF64x2FromI64x2U { dst: VReg, src: VReg };
|
1016
|
+
|
1017
|
+
/// Widens the low lanes of the input vector, as signed, to twice
|
1018
|
+
/// the width.
|
1019
|
+
vwidenlow8x16_s = VWidenLow8x16S { dst: VReg, src: VReg };
|
1020
|
+
/// Widens the low lanes of the input vector, as unsigned, to twice
|
1021
|
+
/// the width.
|
1022
|
+
vwidenlow8x16_u = VWidenLow8x16U { dst: VReg, src: VReg };
|
1023
|
+
/// Widens the low lanes of the input vector, as signed, to twice
|
1024
|
+
/// the width.
|
1025
|
+
vwidenlow16x8_s = VWidenLow16x8S { dst: VReg, src: VReg };
|
1026
|
+
/// Widens the low lanes of the input vector, as unsigned, to twice
|
1027
|
+
/// the width.
|
1028
|
+
vwidenlow16x8_u = VWidenLow16x8U { dst: VReg, src: VReg };
|
1029
|
+
/// Widens the low lanes of the input vector, as signed, to twice
|
1030
|
+
/// the width.
|
1031
|
+
vwidenlow32x4_s = VWidenLow32x4S { dst: VReg, src: VReg };
|
1032
|
+
/// Widens the low lanes of the input vector, as unsigned, to twice
|
1033
|
+
/// the width.
|
1034
|
+
vwidenlow32x4_u = VWidenLow32x4U { dst: VReg, src: VReg };
|
1035
|
+
/// Widens the high lanes of the input vector, as signed, to twice
|
1036
|
+
/// the width.
|
1037
|
+
vwidenhigh8x16_s = VWidenHigh8x16S { dst: VReg, src: VReg };
|
1038
|
+
/// Widens the high lanes of the input vector, as unsigned, to twice
|
1039
|
+
/// the width.
|
1040
|
+
vwidenhigh8x16_u = VWidenHigh8x16U { dst: VReg, src: VReg };
|
1041
|
+
/// Widens the high lanes of the input vector, as signed, to twice
|
1042
|
+
/// the width.
|
1043
|
+
vwidenhigh16x8_s = VWidenHigh16x8S { dst: VReg, src: VReg };
|
1044
|
+
/// Widens the high lanes of the input vector, as unsigned, to twice
|
1045
|
+
/// the width.
|
1046
|
+
vwidenhigh16x8_u = VWidenHigh16x8U { dst: VReg, src: VReg };
|
1047
|
+
/// Widens the high lanes of the input vector, as signed, to twice
|
1048
|
+
/// the width.
|
1049
|
+
vwidenhigh32x4_s = VWidenHigh32x4S { dst: VReg, src: VReg };
|
1050
|
+
/// Widens the high lanes of the input vector, as unsigned, to twice
|
1051
|
+
/// the width.
|
1052
|
+
vwidenhigh32x4_u = VWidenHigh32x4U { dst: VReg, src: VReg };
|
1053
|
+
|
1054
|
+
/// Narrows the two 16x8 vectors, assuming all input lanes are
|
1055
|
+
/// signed, to half the width. Narrowing is signed and saturating.
|
1056
|
+
vnarrow16x8_s = Vnarrow16x8S { operands: BinaryOperands<VReg> };
|
1057
|
+
/// Narrows the two 16x8 vectors, assuming all input lanes are
|
1058
|
+
/// signed, to half the width. Narrowing is unsigned and saturating.
|
1059
|
+
vnarrow16x8_u = Vnarrow16x8U { operands: BinaryOperands<VReg> };
|
1060
|
+
/// Narrows the two 32x4 vectors, assuming all input lanes are
|
1061
|
+
/// signed, to half the width. Narrowing is signed and saturating.
|
1062
|
+
vnarrow32x4_s = Vnarrow32x4S { operands: BinaryOperands<VReg> };
|
1063
|
+
/// Narrows the two 32x4 vectors, assuming all input lanes are
|
1064
|
+
/// signed, to half the width. Narrowing is unsigned and saturating.
|
1065
|
+
vnarrow32x4_u = Vnarrow32x4U { operands: BinaryOperands<VReg> };
|
1066
|
+
/// Promotes the low two lanes of the f32x4 input to f64x2.
|
1067
|
+
vfpromotelow = VFpromoteLow { dst: VReg, src: VReg };
|
1068
|
+
/// Demotes the two f64x2 lanes to f32x2 and then extends with two
|
1069
|
+
/// more zero lanes.
|
1070
|
+
vfdemote = VFdemote { dst: VReg, src: VReg };
|
1071
|
+
|
1072
|
+
/// `dst = src1 - src2`
|
1073
|
+
vsubi8x16 = VSubI8x16 { operands: BinaryOperands<VReg> };
|
1074
|
+
/// `dst = src1 - src2`
|
1075
|
+
vsubi16x8 = VSubI16x8 { operands: BinaryOperands<VReg> };
|
1076
|
+
/// `dst = src1 - src2`
|
1077
|
+
vsubi32x4 = VSubI32x4 { operands: BinaryOperands<VReg> };
|
1078
|
+
/// `dst = src1 - src2`
|
1079
|
+
vsubi64x2 = VSubI64x2 { operands: BinaryOperands<VReg> };
|
1080
|
+
/// `dst = src1 - src2`
|
1081
|
+
vsubf64x2 = VSubF64x2 { operands: BinaryOperands<VReg> };
|
1082
|
+
|
1083
|
+
/// `dst = saturating_sub(src1, src2)`
|
1084
|
+
vsubi8x16_sat = VSubI8x16Sat { operands: BinaryOperands<VReg> };
|
1085
|
+
/// `dst = saturating_sub(src1, src2)`
|
1086
|
+
vsubu8x16_sat = VSubU8x16Sat { operands: BinaryOperands<VReg> };
|
1087
|
+
/// `dst = saturating_sub(src1, src2)`
|
1088
|
+
vsubi16x8_sat = VSubI16x8Sat { operands: BinaryOperands<VReg> };
|
1089
|
+
/// `dst = saturating_sub(src1, src2)`
|
1090
|
+
vsubu16x8_sat = VSubU16x8Sat { operands: BinaryOperands<VReg> };
|
1091
|
+
|
1092
|
+
/// `dst = src1 * src2`
|
1093
|
+
vmuli8x16 = VMulI8x16 { operands: BinaryOperands<VReg> };
|
1094
|
+
/// `dst = src1 * src2`
|
1095
|
+
vmuli16x8 = VMulI16x8 { operands: BinaryOperands<VReg> };
|
1096
|
+
/// `dst = src1 * src2`
|
1097
|
+
vmuli32x4 = VMulI32x4 { operands: BinaryOperands<VReg> };
|
1098
|
+
/// `dst = src1 * src2`
|
1099
|
+
vmuli64x2 = VMulI64x2 { operands: BinaryOperands<VReg> };
|
1100
|
+
/// `dst = src1 * src2`
|
1101
|
+
vmulf64x2 = VMulF64x2 { operands: BinaryOperands<VReg> };
|
1102
|
+
|
1103
|
+
/// `dst = signed_saturate(src1 * src2 + (1 << (Q - 1)) >> Q)`
|
1104
|
+
vqmulrsi16x8 = VQmulrsI16x8 { operands: BinaryOperands<VReg> };
|
1105
|
+
|
1106
|
+
/// `dst = count_ones(src)`
|
1107
|
+
vpopcnt8x16 = VPopcnt8x16 { dst: VReg, src: VReg };
|
1108
|
+
|
1109
|
+
/// `low32(dst) = zext(src[lane])`
|
1110
|
+
xextractv8x16 = XExtractV8x16 { dst: XReg, src: VReg, lane: u8 };
|
1111
|
+
/// `low32(dst) = zext(src[lane])`
|
1112
|
+
xextractv16x8 = XExtractV16x8 { dst: XReg, src: VReg, lane: u8 };
|
1113
|
+
/// `low32(dst) = src[lane]`
|
1114
|
+
xextractv32x4 = XExtractV32x4 { dst: XReg, src: VReg, lane: u8 };
|
1115
|
+
/// `dst = src[lane]`
|
1116
|
+
xextractv64x2 = XExtractV64x2 { dst: XReg, src: VReg, lane: u8 };
|
1117
|
+
/// `low32(dst) = src[lane]`
|
1118
|
+
fextractv32x4 = FExtractV32x4 { dst: FReg, src: VReg, lane: u8 };
|
1119
|
+
/// `dst = src[lane]`
|
1120
|
+
fextractv64x2 = FExtractV64x2 { dst: FReg, src: VReg, lane: u8 };
|
1121
|
+
|
1122
|
+
/// `dst = src1; dst[lane] = src2`
|
1123
|
+
vinsertx8 = VInsertX8 { operands: BinaryOperands<VReg, VReg, XReg>, lane: u8 };
|
1124
|
+
/// `dst = src1; dst[lane] = src2`
|
1125
|
+
vinsertx16 = VInsertX16 { operands: BinaryOperands<VReg, VReg, XReg>, lane: u8 };
|
1126
|
+
/// `dst = src1; dst[lane] = src2`
|
1127
|
+
vinsertx32 = VInsertX32 { operands: BinaryOperands<VReg, VReg, XReg>, lane: u8 };
|
1128
|
+
/// `dst = src1; dst[lane] = src2`
|
1129
|
+
vinsertx64 = VInsertX64 { operands: BinaryOperands<VReg, VReg, XReg>, lane: u8 };
|
1130
|
+
/// `dst = src1; dst[lane] = src2`
|
1131
|
+
vinsertf32 = VInsertF32 { operands: BinaryOperands<VReg, VReg, FReg>, lane: u8 };
|
1132
|
+
/// `dst = src1; dst[lane] = src2`
|
1133
|
+
vinsertf64 = VInsertF64 { operands: BinaryOperands<VReg, VReg, FReg>, lane: u8 };
|
1134
|
+
|
1135
|
+
/// `dst = src == dst`
|
1136
|
+
veq8x16 = Veq8x16 { operands: BinaryOperands<VReg> };
|
1137
|
+
/// `dst = src != dst`
|
1138
|
+
vneq8x16 = Vneq8x16 { operands: BinaryOperands<VReg> };
|
1139
|
+
/// `dst = src < dst` (signed)
|
1140
|
+
vslt8x16 = Vslt8x16 { operands: BinaryOperands<VReg> };
|
1141
|
+
/// `dst = src <= dst` (signed)
|
1142
|
+
vslteq8x16 = Vslteq8x16 { operands: BinaryOperands<VReg> };
|
1143
|
+
/// `dst = src < dst` (unsigned)
|
1144
|
+
vult8x16 = Vult8x16 { operands: BinaryOperands<VReg> };
|
1145
|
+
/// `dst = src <= dst` (unsigned)
|
1146
|
+
vulteq8x16 = Vulteq8x16 { operands: BinaryOperands<VReg> };
|
1147
|
+
/// `dst = src == dst`
|
1148
|
+
veq16x8 = Veq16x8 { operands: BinaryOperands<VReg> };
|
1149
|
+
/// `dst = src != dst`
|
1150
|
+
vneq16x8 = Vneq16x8 { operands: BinaryOperands<VReg> };
|
1151
|
+
/// `dst = src < dst` (signed)
|
1152
|
+
vslt16x8 = Vslt16x8 { operands: BinaryOperands<VReg> };
|
1153
|
+
/// `dst = src <= dst` (signed)
|
1154
|
+
vslteq16x8 = Vslteq16x8 { operands: BinaryOperands<VReg> };
|
1155
|
+
/// `dst = src < dst` (unsigned)
|
1156
|
+
vult16x8 = Vult16x8 { operands: BinaryOperands<VReg> };
|
1157
|
+
/// `dst = src <= dst` (unsigned)
|
1158
|
+
vulteq16x8 = Vulteq16x8 { operands: BinaryOperands<VReg> };
|
1159
|
+
/// `dst = src == dst`
|
1160
|
+
veq32x4 = Veq32x4 { operands: BinaryOperands<VReg> };
|
1161
|
+
/// `dst = src != dst`
|
1162
|
+
vneq32x4 = Vneq32x4 { operands: BinaryOperands<VReg> };
|
1163
|
+
/// `dst = src < dst` (signed)
|
1164
|
+
vslt32x4 = Vslt32x4 { operands: BinaryOperands<VReg> };
|
1165
|
+
/// `dst = src <= dst` (signed)
|
1166
|
+
vslteq32x4 = Vslteq32x4 { operands: BinaryOperands<VReg> };
|
1167
|
+
/// `dst = src < dst` (unsigned)
|
1168
|
+
vult32x4 = Vult32x4 { operands: BinaryOperands<VReg> };
|
1169
|
+
/// `dst = src <= dst` (unsigned)
|
1170
|
+
vulteq32x4 = Vulteq32x4 { operands: BinaryOperands<VReg> };
|
1171
|
+
/// `dst = src == dst`
|
1172
|
+
veq64x2 = Veq64x2 { operands: BinaryOperands<VReg> };
|
1173
|
+
/// `dst = src != dst`
|
1174
|
+
vneq64x2 = Vneq64x2 { operands: BinaryOperands<VReg> };
|
1175
|
+
/// `dst = src < dst` (signed)
|
1176
|
+
vslt64x2 = Vslt64x2 { operands: BinaryOperands<VReg> };
|
1177
|
+
/// `dst = src <= dst` (signed)
|
1178
|
+
vslteq64x2 = Vslteq64x2 { operands: BinaryOperands<VReg> };
|
1179
|
+
/// `dst = src < dst` (unsigned)
|
1180
|
+
vult64x2 = Vult64x2 { operands: BinaryOperands<VReg> };
|
1181
|
+
/// `dst = src <= dst` (unsigned)
|
1182
|
+
vulteq64x2 = Vulteq64x2 { operands: BinaryOperands<VReg> };
|
1183
|
+
|
1184
|
+
/// `dst = -src`
|
1185
|
+
vneg8x16 = Vneg8x16 { dst: VReg, src: VReg };
|
1186
|
+
/// `dst = -src`
|
1187
|
+
vneg16x8 = Vneg16x8 { dst: VReg, src: VReg };
|
1188
|
+
/// `dst = -src`
|
1189
|
+
vneg32x4 = Vneg32x4 { dst: VReg, src: VReg };
|
1190
|
+
/// `dst = -src`
|
1191
|
+
vneg64x2 = Vneg64x2 { dst: VReg, src: VReg };
|
1192
|
+
/// `dst = -src`
|
1193
|
+
vnegf64x2 = VnegF64x2 { dst: VReg, src: VReg };
|
1194
|
+
|
1195
|
+
/// `dst = min(src1, src2)` (signed)
|
1196
|
+
vmin8x16_s = Vmin8x16S { operands: BinaryOperands<VReg> };
|
1197
|
+
/// `dst = min(src1, src2)` (unsigned)
|
1198
|
+
vmin8x16_u = Vmin8x16U { operands: BinaryOperands<VReg> };
|
1199
|
+
/// `dst = min(src1, src2)` (signed)
|
1200
|
+
vmin16x8_s = Vmin16x8S { operands: BinaryOperands<VReg> };
|
1201
|
+
/// `dst = min(src1, src2)` (unsigned)
|
1202
|
+
vmin16x8_u = Vmin16x8U { operands: BinaryOperands<VReg> };
|
1203
|
+
/// `dst = max(src1, src2)` (signed)
|
1204
|
+
vmax8x16_s = Vmax8x16S { operands: BinaryOperands<VReg> };
|
1205
|
+
/// `dst = max(src1, src2)` (unsigned)
|
1206
|
+
vmax8x16_u = Vmax8x16U { operands: BinaryOperands<VReg> };
|
1207
|
+
/// `dst = max(src1, src2)` (signed)
|
1208
|
+
vmax16x8_s = Vmax16x8S { operands: BinaryOperands<VReg> };
|
1209
|
+
/// `dst = max(src1, src2)` (unsigned)
|
1210
|
+
vmax16x8_u = Vmax16x8U { operands: BinaryOperands<VReg> };
|
1211
|
+
|
1212
|
+
/// `dst = min(src1, src2)` (signed)
|
1213
|
+
vmin32x4_s = Vmin32x4S { operands: BinaryOperands<VReg> };
|
1214
|
+
/// `dst = min(src1, src2)` (unsigned)
|
1215
|
+
vmin32x4_u = Vmin32x4U { operands: BinaryOperands<VReg> };
|
1216
|
+
/// `dst = max(src1, src2)` (signed)
|
1217
|
+
vmax32x4_s = Vmax32x4S { operands: BinaryOperands<VReg> };
|
1218
|
+
/// `dst = max(src1, src2)` (unsigned)
|
1219
|
+
vmax32x4_u = Vmax32x4U { operands: BinaryOperands<VReg> };
|
1220
|
+
|
1221
|
+
/// `dst = |src|`
|
1222
|
+
vabs8x16 = Vabs8x16 { dst: VReg, src: VReg };
|
1223
|
+
/// `dst = |src|`
|
1224
|
+
vabs16x8 = Vabs16x8 { dst: VReg, src: VReg };
|
1225
|
+
/// `dst = |src|`
|
1226
|
+
vabs32x4 = Vabs32x4 { dst: VReg, src: VReg };
|
1227
|
+
/// `dst = |src|`
|
1228
|
+
vabs64x2 = Vabs64x2 { dst: VReg, src: VReg };
|
1229
|
+
|
1230
|
+
/// `dst = |src|`
|
1231
|
+
vabsf32x4 = Vabsf32x4 { dst: VReg, src: VReg };
|
1232
|
+
/// `dst = |src|`
|
1233
|
+
vabsf64x2 = Vabsf64x2 { dst: VReg, src: VReg };
|
1234
|
+
/// `dst = ieee_maximum(src1, src2)`
|
1235
|
+
vmaximumf32x4 = Vmaximumf32x4 { operands: BinaryOperands<VReg> };
|
1236
|
+
/// `dst = ieee_maximum(src1, src2)`
|
1237
|
+
vmaximumf64x2 = Vmaximumf64x2 { operands: BinaryOperands<VReg> };
|
1238
|
+
/// `dst = ieee_minimum(src1, src2)`
|
1239
|
+
vminimumf32x4 = Vminimumf32x4 { operands: BinaryOperands<VReg> };
|
1240
|
+
/// `dst = ieee_minimum(src1, src2)`
|
1241
|
+
vminimumf64x2 = Vminimumf64x2 { operands: BinaryOperands<VReg> };
|
1242
|
+
|
1243
|
+
/// `dst = shuffle(src1, src2, mask)`
|
1244
|
+
vshuffle = VShuffle { dst: VReg, src1: VReg, src2: VReg, mask: u128 };
|
1245
|
+
|
1246
|
+
/// `dst = swizzle(src1, src2)`
|
1247
|
+
vswizzlei8x16 = Vswizzlei8x16 { operands: BinaryOperands<VReg> };
|
1248
|
+
|
1249
|
+
/// `dst = (src1 + src2 + 1) // 2`
|
1250
|
+
vavground8x16 = Vavground8x16 { operands: BinaryOperands<VReg> };
|
1251
|
+
/// `dst = (src1 + src2 + 1) // 2`
|
1252
|
+
vavground16x8 = Vavground16x8 { operands: BinaryOperands<VReg> };
|
1253
|
+
}
|
1254
|
+
};
|
1255
|
+
}
|
1256
|
+
|
1257
|
+
#[cfg(feature = "decode")]
|
1258
|
+
pub mod decode;
|
1259
|
+
#[cfg(feature = "disas")]
|
1260
|
+
pub mod disas;
|
1261
|
+
#[cfg(feature = "encode")]
|
1262
|
+
pub mod encode;
|
1263
|
+
#[cfg(feature = "interp")]
|
1264
|
+
pub mod interp;
|
1265
|
+
|
1266
|
+
pub mod regs;
|
1267
|
+
pub use regs::*;
|
1268
|
+
|
1269
|
+
pub mod imms;
|
1270
|
+
pub use imms::*;
|
1271
|
+
|
1272
|
+
pub mod op;
|
1273
|
+
pub use op::*;
|
1274
|
+
|
1275
|
+
pub mod opcode;
|
1276
|
+
pub use opcode::*;
|
1277
|
+
|
1278
|
+
#[allow(dead_code)] // Unused in some `cfg`s.
|
1279
|
+
pub(crate) unsafe fn unreachable_unchecked<T>() -> T {
|
1280
|
+
#[cfg(debug_assertions)]
|
1281
|
+
unreachable!();
|
1282
|
+
|
1283
|
+
#[cfg_attr(debug_assertions, allow(unreachable_code))]
|
1284
|
+
unsafe {
|
1285
|
+
core::hint::unreachable_unchecked()
|
1286
|
+
}
|
1287
|
+
}
|