wasmtime 15.0.1 → 16.0.0

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Files changed (1212) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +83 -103
  3. data/ext/Cargo.toml +6 -6
  4. data/ext/cargo-vendor/cranelift-bforest-0.103.0/.cargo-checksum.json +1 -0
  5. data/ext/cargo-vendor/cranelift-bforest-0.103.0/Cargo.toml +40 -0
  6. data/ext/cargo-vendor/cranelift-bforest-0.103.0/src/lib.rs +183 -0
  7. data/ext/cargo-vendor/cranelift-codegen-0.103.0/.cargo-checksum.json +1 -0
  8. data/ext/cargo-vendor/cranelift-codegen-0.103.0/Cargo.toml +175 -0
  9. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/binemit/mod.rs +171 -0
  10. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/egraph/cost.rs +171 -0
  11. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/egraph/elaborate.rs +750 -0
  12. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/egraph.rs +703 -0
  13. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/ir/dfg.rs +1735 -0
  14. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/ir/pcc.rs +1682 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isa/aarch64/lower/isle.rs +874 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isa/riscv64/inst/mod.rs +2041 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isa/riscv64/inst.isle +2928 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isa/riscv64/lower.isle +2864 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isa/s390x/lower/isle.rs +1029 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isa/x64/lower/isle.rs +1064 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isa/x64/pcc.rs +916 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isle_prelude.rs +977 -0
  23. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/lib.rs +106 -0
  24. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/machinst/isle.rs +896 -0
  25. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/opts/arithmetic.isle +152 -0
  26. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/opts/cprop.isle +237 -0
  27. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/opts/icmp.isle +199 -0
  28. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/opts/selects.isle +76 -0
  29. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/opts.rs +172 -0
  30. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/prelude.isle +649 -0
  31. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/timing.rs +297 -0
  32. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/unionfind.rs +75 -0
  33. data/ext/cargo-vendor/cranelift-codegen-meta-0.103.0/.cargo-checksum.json +1 -0
  34. data/ext/cargo-vendor/cranelift-codegen-meta-0.103.0/Cargo.toml +35 -0
  35. data/ext/cargo-vendor/cranelift-codegen-shared-0.103.0/.cargo-checksum.json +1 -0
  36. data/ext/cargo-vendor/cranelift-codegen-shared-0.103.0/Cargo.toml +22 -0
  37. data/ext/cargo-vendor/cranelift-codegen-shared-0.103.0/src/lib.rs +10 -0
  38. data/ext/cargo-vendor/cranelift-control-0.103.0/.cargo-checksum.json +1 -0
  39. data/ext/cargo-vendor/cranelift-control-0.103.0/Cargo.toml +30 -0
  40. data/ext/cargo-vendor/cranelift-entity-0.103.0/.cargo-checksum.json +1 -0
  41. data/ext/cargo-vendor/cranelift-entity-0.103.0/Cargo.toml +50 -0
  42. data/ext/cargo-vendor/cranelift-entity-0.103.0/src/lib.rs +317 -0
  43. data/ext/cargo-vendor/cranelift-entity-0.103.0/src/primary.rs +516 -0
  44. data/ext/cargo-vendor/cranelift-entity-0.103.0/src/unsigned.rs +71 -0
  45. data/ext/cargo-vendor/cranelift-frontend-0.103.0/.cargo-checksum.json +1 -0
  46. data/ext/cargo-vendor/cranelift-frontend-0.103.0/Cargo.toml +68 -0
  47. data/ext/cargo-vendor/cranelift-frontend-0.103.0/src/lib.rs +189 -0
  48. data/ext/cargo-vendor/cranelift-isle-0.103.0/.cargo-checksum.json +1 -0
  49. data/ext/cargo-vendor/cranelift-isle-0.103.0/Cargo.toml +46 -0
  50. data/ext/cargo-vendor/cranelift-isle-0.103.0/isle_examples/link/multi_constructor_main.rs +88 -0
  51. data/ext/cargo-vendor/cranelift-isle-0.103.0/isle_examples/link/multi_extractor_main.rs +63 -0
  52. data/ext/cargo-vendor/cranelift-isle-0.103.0/src/codegen.rs +886 -0
  53. data/ext/cargo-vendor/cranelift-native-0.103.0/.cargo-checksum.json +1 -0
  54. data/ext/cargo-vendor/cranelift-native-0.103.0/Cargo.toml +43 -0
  55. data/ext/cargo-vendor/cranelift-native-0.103.0/src/lib.rs +184 -0
  56. data/ext/cargo-vendor/cranelift-wasm-0.103.0/.cargo-checksum.json +1 -0
  57. data/ext/cargo-vendor/cranelift-wasm-0.103.0/Cargo.toml +106 -0
  58. data/ext/cargo-vendor/cranelift-wasm-0.103.0/src/environ/dummy.rs +953 -0
  59. data/ext/cargo-vendor/cranelift-wasm-0.103.0/src/lib.rs +62 -0
  60. data/ext/cargo-vendor/cranelift-wasm-0.103.0/src/translation_utils.rs +89 -0
  61. data/ext/cargo-vendor/wasi-cap-std-sync-16.0.0/.cargo-checksum.json +1 -0
  62. data/ext/cargo-vendor/wasi-cap-std-sync-16.0.0/Cargo.toml +102 -0
  63. data/ext/cargo-vendor/wasi-common-16.0.0/.cargo-checksum.json +1 -0
  64. data/ext/cargo-vendor/wasi-common-16.0.0/Cargo.toml +131 -0
  65. data/ext/cargo-vendor/wasi-common-16.0.0/src/lib.rs +76 -0
  66. data/ext/cargo-vendor/wasi-common-16.0.0/src/snapshots/preview_1.rs +1492 -0
  67. data/ext/cargo-vendor/wasmtime-16.0.0/.cargo-checksum.json +1 -0
  68. data/ext/cargo-vendor/wasmtime-16.0.0/Cargo.toml +211 -0
  69. data/ext/cargo-vendor/wasmtime-16.0.0/src/compiler.rs +682 -0
  70. data/ext/cargo-vendor/wasmtime-16.0.0/src/component/component.rs +505 -0
  71. data/ext/cargo-vendor/wasmtime-16.0.0/src/component/func/typed.rs +2400 -0
  72. data/ext/cargo-vendor/wasmtime-16.0.0/src/config.rs +2422 -0
  73. data/ext/cargo-vendor/wasmtime-16.0.0/src/func.rs +2391 -0
  74. data/ext/cargo-vendor/wasmtime-16.0.0/src/lib.rs +520 -0
  75. data/ext/cargo-vendor/wasmtime-16.0.0/src/memory.rs +998 -0
  76. data/ext/cargo-vendor/wasmtime-16.0.0/src/module.rs +1370 -0
  77. data/ext/cargo-vendor/wasmtime-16.0.0/src/stack.rs +73 -0
  78. data/ext/cargo-vendor/wasmtime-16.0.0/src/v128.rs +122 -0
  79. data/ext/cargo-vendor/wasmtime-asm-macros-16.0.0/.cargo-checksum.json +1 -0
  80. data/ext/cargo-vendor/wasmtime-asm-macros-16.0.0/Cargo.toml +22 -0
  81. data/ext/cargo-vendor/wasmtime-cache-16.0.0/.cargo-checksum.json +1 -0
  82. data/ext/cargo-vendor/wasmtime-cache-16.0.0/Cargo.toml +81 -0
  83. data/ext/cargo-vendor/wasmtime-cache-16.0.0/src/lib.rs +235 -0
  84. data/ext/cargo-vendor/wasmtime-cache-16.0.0/src/worker.rs +890 -0
  85. data/ext/cargo-vendor/wasmtime-component-macro-16.0.0/.cargo-checksum.json +1 -0
  86. data/ext/cargo-vendor/wasmtime-component-macro-16.0.0/Cargo.toml +67 -0
  87. data/ext/cargo-vendor/wasmtime-component-util-16.0.0/.cargo-checksum.json +1 -0
  88. data/ext/cargo-vendor/wasmtime-component-util-16.0.0/Cargo.toml +25 -0
  89. data/ext/cargo-vendor/wasmtime-cranelift-16.0.0/.cargo-checksum.json +1 -0
  90. data/ext/cargo-vendor/wasmtime-cranelift-16.0.0/Cargo.toml +112 -0
  91. data/ext/cargo-vendor/wasmtime-cranelift-16.0.0/src/compiler/component.rs +959 -0
  92. data/ext/cargo-vendor/wasmtime-cranelift-16.0.0/src/compiler.rs +1317 -0
  93. data/ext/cargo-vendor/wasmtime-cranelift-16.0.0/src/debug/transform/expression.rs +1252 -0
  94. data/ext/cargo-vendor/wasmtime-cranelift-16.0.0/src/debug/transform/simulate.rs +410 -0
  95. data/ext/cargo-vendor/wasmtime-cranelift-16.0.0/src/debug.rs +18 -0
  96. data/ext/cargo-vendor/wasmtime-cranelift-16.0.0/src/func_environ.rs +2750 -0
  97. data/ext/cargo-vendor/wasmtime-cranelift-shared-16.0.0/.cargo-checksum.json +1 -0
  98. data/ext/cargo-vendor/wasmtime-cranelift-shared-16.0.0/Cargo.toml +71 -0
  99. data/ext/cargo-vendor/wasmtime-environ-16.0.0/.cargo-checksum.json +1 -0
  100. data/ext/cargo-vendor/wasmtime-environ-16.0.0/Cargo.lock +660 -0
  101. data/ext/cargo-vendor/wasmtime-environ-16.0.0/Cargo.toml +125 -0
  102. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/compilation.rs +402 -0
  103. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/component/compiler.rs +47 -0
  104. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/component/translate.rs +951 -0
  105. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/component/types.rs +1876 -0
  106. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/lib.rs +59 -0
  107. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/module.rs +1075 -0
  108. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/module_environ.rs +892 -0
  109. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/module_types.rs +120 -0
  110. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/scopevec.rs +78 -0
  111. data/ext/cargo-vendor/wasmtime-fiber-16.0.0/.cargo-checksum.json +1 -0
  112. data/ext/cargo-vendor/wasmtime-fiber-16.0.0/Cargo.toml +63 -0
  113. data/ext/cargo-vendor/wasmtime-fiber-16.0.0/src/lib.rs +328 -0
  114. data/ext/cargo-vendor/wasmtime-fiber-16.0.0/src/unix.rs +265 -0
  115. data/ext/cargo-vendor/wasmtime-fiber-16.0.0/src/windows.c +9 -0
  116. data/ext/cargo-vendor/wasmtime-jit-16.0.0/.cargo-checksum.json +1 -0
  117. data/ext/cargo-vendor/wasmtime-jit-16.0.0/Cargo.toml +125 -0
  118. data/ext/cargo-vendor/wasmtime-jit-16.0.0/src/code_memory.rs +319 -0
  119. data/ext/cargo-vendor/wasmtime-jit-16.0.0/src/instantiate.rs +772 -0
  120. data/ext/cargo-vendor/wasmtime-jit-16.0.0/src/lib.rs +21 -0
  121. data/ext/cargo-vendor/wasmtime-jit-debug-16.0.0/.cargo-checksum.json +1 -0
  122. data/ext/cargo-vendor/wasmtime-jit-debug-16.0.0/Cargo.toml +67 -0
  123. data/ext/cargo-vendor/wasmtime-jit-icache-coherence-16.0.0/.cargo-checksum.json +1 -0
  124. data/ext/cargo-vendor/wasmtime-jit-icache-coherence-16.0.0/Cargo.toml +46 -0
  125. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/.cargo-checksum.json +1 -0
  126. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/Cargo.toml +139 -0
  127. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/build.rs +28 -0
  128. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/proptest-regressions/instance/allocator/pooling/memory_pool.txt +9 -0
  129. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/arch/aarch64.rs +120 -0
  130. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/arch/mod.rs +32 -0
  131. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/arch/riscv64.rs +88 -0
  132. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/arch/s390x.rs +61 -0
  133. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/arch/x86_64.rs +106 -0
  134. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/cow.rs +888 -0
  135. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/helpers.c +113 -0
  136. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/instance/allocator/pooling/memory_pool.rs +1005 -0
  137. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/instance/allocator/pooling/stack_pool.rs +242 -0
  138. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/instance/allocator/pooling/table_pool.rs +227 -0
  139. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/instance/allocator/pooling.rs +698 -0
  140. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/lib.rs +264 -0
  141. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/libcalls.rs +776 -0
  142. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/mmap.rs +214 -0
  143. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/mpk/enabled.rs +204 -0
  144. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/mpk/pkru.rs +102 -0
  145. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/miri/mod.rs +10 -0
  146. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/miri/traphandlers.rs +42 -0
  147. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/miri/unwind.rs +17 -0
  148. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/miri/vm.rs +63 -0
  149. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/mod.rs +30 -0
  150. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/unix/machports.rs +487 -0
  151. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/unix/macos_traphandlers.rs +28 -0
  152. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/unix/mod.rs +21 -0
  153. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/unix/signals.rs +402 -0
  154. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/unix/unwind.rs +91 -0
  155. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/unix/vm.rs +208 -0
  156. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/windows/mod.rs +6 -0
  157. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/windows/traphandlers.rs +105 -0
  158. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/windows/unwind.rs +46 -0
  159. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/windows/vm.rs +79 -0
  160. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/traphandlers/backtrace.rs +265 -0
  161. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/traphandlers.rs +733 -0
  162. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/vmcontext.rs +1197 -0
  163. data/ext/cargo-vendor/wasmtime-types-16.0.0/.cargo-checksum.json +1 -0
  164. data/ext/cargo-vendor/wasmtime-types-16.0.0/Cargo.toml +36 -0
  165. data/ext/cargo-vendor/wasmtime-types-16.0.0/src/lib.rs +504 -0
  166. data/ext/cargo-vendor/wasmtime-versioned-export-macros-16.0.0/.cargo-checksum.json +1 -0
  167. data/ext/cargo-vendor/wasmtime-versioned-export-macros-16.0.0/Cargo.toml +32 -0
  168. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/.cargo-checksum.json +1 -0
  169. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/Cargo.toml +261 -0
  170. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/lib.rs +137 -0
  171. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/host/io.rs +368 -0
  172. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/host/network.rs +570 -0
  173. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/host/tcp.rs +632 -0
  174. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/host/udp.rs +550 -0
  175. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/mod.rs +328 -0
  176. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/preview0.rs +870 -0
  177. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/preview1.rs +2348 -0
  178. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/stdio.rs +259 -0
  179. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/stream.rs +182 -0
  180. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/table.rs +337 -0
  181. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/tests/all/api.rs +218 -0
  182. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/tests/all/async_.rs +360 -0
  183. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/tests/all/main.rs +113 -0
  184. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/tests/all/preview1.rs +239 -0
  185. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/tests/all/sync.rs +299 -0
  186. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/tests/process_stdin.rs +165 -0
  187. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/wit/command-extended.wit +6 -0
  188. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/wit/deps/cli/command.wit +7 -0
  189. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/wit/deps/cli/imports.wit +20 -0
  190. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/wit/deps/http/proxy.wit +32 -0
  191. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/wit/deps/http/types.wit +570 -0
  192. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/wit/test.wit +22 -0
  193. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/witx/preview0/typenames.witx +746 -0
  194. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/witx/preview0/wasi_unstable.witx +513 -0
  195. data/ext/cargo-vendor/wasmtime-winch-16.0.0/.cargo-checksum.json +1 -0
  196. data/ext/cargo-vendor/wasmtime-winch-16.0.0/Cargo.toml +77 -0
  197. data/ext/cargo-vendor/wasmtime-winch-16.0.0/src/compiler.rs +243 -0
  198. data/ext/cargo-vendor/wasmtime-wit-bindgen-16.0.0/.cargo-checksum.json +1 -0
  199. data/ext/cargo-vendor/wasmtime-wit-bindgen-16.0.0/Cargo.toml +41 -0
  200. data/ext/cargo-vendor/wasmtime-wmemcheck-16.0.0/.cargo-checksum.json +1 -0
  201. data/ext/cargo-vendor/wasmtime-wmemcheck-16.0.0/Cargo.toml +29 -0
  202. data/ext/cargo-vendor/wiggle-16.0.0/.cargo-checksum.json +1 -0
  203. data/ext/cargo-vendor/wiggle-16.0.0/Cargo.toml +115 -0
  204. data/ext/cargo-vendor/wiggle-16.0.0/src/lib.rs +1198 -0
  205. data/ext/cargo-vendor/wiggle-generate-16.0.0/.cargo-checksum.json +1 -0
  206. data/ext/cargo-vendor/wiggle-generate-16.0.0/Cargo.toml +65 -0
  207. data/ext/cargo-vendor/wiggle-generate-16.0.0/src/types/handle.rs +84 -0
  208. data/ext/cargo-vendor/wiggle-generate-16.0.0/src/types/record.rs +132 -0
  209. data/ext/cargo-vendor/wiggle-generate-16.0.0/src/types/variant.rs +191 -0
  210. data/ext/cargo-vendor/wiggle-macro-16.0.0/.cargo-checksum.json +1 -0
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  610. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/aarch64/mod.rs +0 -0
  611. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/aarch64/pcc.rs +0 -0
  612. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/aarch64/settings.rs +0 -0
  613. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/call_conv.rs +0 -0
  614. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/mod.rs +0 -0
  615. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/abi.rs +0 -0
  616. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/args.rs +0 -0
  617. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/emit.rs +0 -0
  618. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/emit_tests.rs +0 -0
  619. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/encode.rs +0 -0
  620. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/imms.rs +0 -0
  621. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/regs.rs +0 -0
  622. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/unwind/systemv.rs +0 -0
  623. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/unwind.rs +0 -0
  624. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/vector.rs +0 -0
  625. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst_vector.isle +0 -0
  626. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/lower/isle/generated_code.rs +0 -0
  627. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/lower/isle.rs +0 -0
  628. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/lower.rs +0 -0
  629. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/mod.rs +0 -0
  630. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/settings.rs +0 -0
  631. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/abi.rs +0 -0
  632. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst/args.rs +0 -0
  633. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst/emit.rs +0 -0
  634. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst/emit_tests.rs +0 -0
  635. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst/imms.rs +0 -0
  636. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst/mod.rs +0 -0
  637. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst/regs.rs +0 -0
  638. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst/unwind/systemv.rs +0 -0
  639. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst/unwind.rs +0 -0
  640. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst.isle +0 -0
  641. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/lower/isle/generated_code.rs +0 -0
  642. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/lower.isle +0 -0
  643. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/lower.rs +0 -0
  644. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/mod.rs +0 -0
  645. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/settings.rs +0 -0
  646. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/unwind/systemv.rs +0 -0
  647. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/unwind/winx64.rs +0 -0
  648. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/unwind.rs +0 -0
  649. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/abi.rs +0 -0
  650. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/encoding/evex.rs +0 -0
  651. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/encoding/mod.rs +0 -0
  652. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/encoding/rex.rs +0 -0
  653. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/encoding/vex.rs +0 -0
  654. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/args.rs +0 -0
  655. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/emit.rs +0 -0
  656. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/emit_state.rs +0 -0
  657. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/emit_tests.rs +0 -0
  658. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/mod.rs +0 -0
  659. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/regs.rs +0 -0
  660. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/unwind/systemv.rs +0 -0
  661. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/unwind/winx64.rs +0 -0
  662. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/unwind.rs +0 -0
  663. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst.isle +0 -0
  664. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/lower/isle/generated_code.rs +0 -0
  665. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/lower.isle +0 -0
  666. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/lower.rs +0 -0
  667. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/mod.rs +0 -0
  668. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/settings.rs +0 -0
  669. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/iterators.rs +0 -0
  670. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/legalizer/globalvalue.rs +0 -0
  671. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/legalizer/mod.rs +0 -0
  672. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/legalizer/table.rs +0 -0
  673. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/loop_analysis.rs +0 -0
  674. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/abi.rs +0 -0
  675. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/blockorder.rs +0 -0
  676. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/buffer.rs +0 -0
  677. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/compile.rs +0 -0
  678. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/helpers.rs +0 -0
  679. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/inst_common.rs +0 -0
  680. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/lower.rs +0 -0
  681. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/mod.rs +0 -0
  682. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/pcc.rs +0 -0
  683. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/reg.rs +0 -0
  684. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/valueregs.rs +0 -0
  685. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/vcode.rs +0 -0
  686. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/nan_canonicalization.rs +0 -0
  687. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/opts/README.md +0 -0
  688. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/opts/bitops.isle +0 -0
  689. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/opts/extends.isle +0 -0
  690. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/opts/generated_code.rs +0 -0
  691. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/opts/remat.isle +0 -0
  692. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/opts/shifts.isle +0 -0
  693. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/opts/vector.isle +0 -0
  694. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/prelude_lower.isle +0 -0
  695. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/prelude_opt.isle +0 -0
  696. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/print_errors.rs +0 -0
  697. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/remove_constant_phis.rs +0 -0
  698. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/result.rs +0 -0
  699. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/scoped_hash_map.rs +0 -0
  700. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/settings.rs +0 -0
  701. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/souper_harvest.rs +0 -0
  702. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/unreachable_code.rs +0 -0
  703. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/value_label.rs +0 -0
  704. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/verifier/mod.rs +0 -0
  705. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/write.rs +0 -0
  706. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/LICENSE +0 -0
  707. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/README.md +0 -0
  708. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/cdsl/formats.rs +0 -0
  709. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/cdsl/instructions.rs +0 -0
  710. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/cdsl/isa.rs +0 -0
  711. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/cdsl/mod.rs +0 -0
  712. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/cdsl/operands.rs +0 -0
  713. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/cdsl/settings.rs +0 -0
  714. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/cdsl/types.rs +0 -0
  715. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/cdsl/typevar.rs +0 -0
  716. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/constant_hash.rs +0 -0
  717. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/error.rs +0 -0
  718. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/gen_inst.rs +0 -0
  719. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/gen_settings.rs +0 -0
  720. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/gen_types.rs +0 -0
  721. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/isa/arm64.rs +0 -0
  722. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/isa/mod.rs +0 -0
  723. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/isa/riscv64.rs +0 -0
  724. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/isa/s390x.rs +0 -0
  725. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/isa/x86.rs +0 -0
  726. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/lib.rs +0 -0
  727. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/shared/entities.rs +0 -0
  728. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/shared/formats.rs +0 -0
  729. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/shared/immediates.rs +0 -0
  730. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/shared/instructions.rs +0 -0
  731. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/shared/mod.rs +0 -0
  732. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/shared/settings.rs +0 -0
  733. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/shared/types.rs +0 -0
  734. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/srcgen.rs +0 -0
  735. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/unique_table.rs +0 -0
  736. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.102.1 → cranelift-codegen-shared-0.103.0}/LICENSE +0 -0
  737. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.102.1 → cranelift-codegen-shared-0.103.0}/README.md +0 -0
  738. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.102.1 → cranelift-codegen-shared-0.103.0}/src/constant_hash.rs +0 -0
  739. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.102.1 → cranelift-codegen-shared-0.103.0}/src/constants.rs +0 -0
  740. /data/ext/cargo-vendor/{cranelift-control-0.102.1 → cranelift-control-0.103.0}/LICENSE +0 -0
  741. /data/ext/cargo-vendor/{cranelift-control-0.102.1 → cranelift-control-0.103.0}/README.md +0 -0
  742. /data/ext/cargo-vendor/{cranelift-control-0.102.1 → cranelift-control-0.103.0}/src/chaos.rs +0 -0
  743. /data/ext/cargo-vendor/{cranelift-control-0.102.1 → cranelift-control-0.103.0}/src/lib.rs +0 -0
  744. /data/ext/cargo-vendor/{cranelift-control-0.102.1 → cranelift-control-0.103.0}/src/zero_sized.rs +0 -0
  745. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/LICENSE +0 -0
  746. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/README.md +0 -0
  747. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/src/boxed_slice.rs +0 -0
  748. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/src/iter.rs +0 -0
  749. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/src/keys.rs +0 -0
  750. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/src/list.rs +0 -0
  751. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/src/map.rs +0 -0
  752. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/src/packed_option.rs +0 -0
  753. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/src/set.rs +0 -0
  754. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/src/sparse.rs +0 -0
  755. /data/ext/cargo-vendor/{cranelift-frontend-0.102.1 → cranelift-frontend-0.103.0}/LICENSE +0 -0
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  757. /data/ext/cargo-vendor/{cranelift-frontend-0.102.1 → cranelift-frontend-0.103.0}/src/frontend.rs +0 -0
  758. /data/ext/cargo-vendor/{cranelift-frontend-0.102.1 → cranelift-frontend-0.103.0}/src/ssa.rs +0 -0
  759. /data/ext/cargo-vendor/{cranelift-frontend-0.102.1 → cranelift-frontend-0.103.0}/src/switch.rs +0 -0
  760. /data/ext/cargo-vendor/{cranelift-frontend-0.102.1 → cranelift-frontend-0.103.0}/src/variable.rs +0 -0
  761. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/README.md +0 -0
  762. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/build.rs +0 -0
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  764. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/fail/bound_var_type_mismatch.isle +0 -0
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  766. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/fail/error1.isle +0 -0
  767. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/fail/extra_parens.isle +0 -0
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  769. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/fail/impure_rhs.isle +0 -0
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  771. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/fail/multi_prio.isle +0 -0
  772. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/link/borrows.isle +0 -0
  773. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/link/borrows_main.rs +0 -0
  774. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/link/iflets.isle +0 -0
  775. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/link/iflets_main.rs +0 -0
  776. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/link/multi_constructor.isle +0 -0
  777. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/link/multi_extractor.isle +0 -0
  778. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/link/test.isle +0 -0
  779. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/link/test_main.rs +0 -0
  780. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/pass/bound_var.isle +0 -0
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  784. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/pass/let.isle +0 -0
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  786. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/pass/prio_trie_bug.isle +0 -0
  787. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/pass/test2.isle +0 -0
  788. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/pass/test3.isle +0 -0
  789. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/pass/test4.isle +0 -0
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  795. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/ast.rs +0 -0
  796. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/compile.rs +0 -0
  797. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/error.rs +0 -0
  798. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/lexer.rs +0 -0
  799. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/lib.rs +0 -0
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  801. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/overlap.rs +0 -0
  802. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/parser.rs +0 -0
  803. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/sema.rs +0 -0
  804. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/serialize.rs +0 -0
  805. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/trie_again.rs +0 -0
  806. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/tests/run_tests.rs +0 -0
  807. /data/ext/cargo-vendor/{cranelift-native-0.102.1 → cranelift-native-0.103.0}/LICENSE +0 -0
  808. /data/ext/cargo-vendor/{cranelift-native-0.102.1 → cranelift-native-0.103.0}/README.md +0 -0
  809. /data/ext/cargo-vendor/{cranelift-native-0.102.1 → cranelift-native-0.103.0}/src/riscv.rs +0 -0
  810. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/LICENSE +0 -0
  811. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/README.md +0 -0
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  814. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/src/environ/mod.rs +0 -0
  815. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/src/environ/spec.rs +0 -0
  816. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/src/func_translator.rs +0 -0
  817. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/src/heap.rs +0 -0
  818. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/src/module_translator.rs +0 -0
  819. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/src/sections_translator.rs +0 -0
  820. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/src/state.rs +0 -0
  821. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/tests/wasm_testsuite.rs +0 -0
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  829. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/embenchen_primes.wat +0 -0
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  831. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/fibonacci.wat +0 -0
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  834. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/icall.wat +0 -0
  835. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/if-reachability-translation-0.wat +0 -0
  836. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/if-reachability-translation-1.wat +0 -0
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  843. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/if-unreachable-else-params.wat +0 -0
  844. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/issue-1306-name-section-with-u32-max-function-index.wasm +0 -0
  845. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/memory.wat +0 -0
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  848. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/multi-10.wat +0 -0
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  864. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/nullref.wat +0 -0
  865. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/passive-data.wat +0 -0
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  867. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/pr2559.wat +0 -0
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  869. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/rust_fannkuch.wat +0 -0
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  874. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/unreachable_code.wat +0 -0
  875. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/LICENSE +0 -0
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  877. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/clocks.rs +0 -0
  878. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/dir.rs +0 -0
  879. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/file.rs +0 -0
  880. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/lib.rs +0 -0
  881. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/net.rs +0 -0
  882. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/sched/unix.rs +0 -0
  883. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/sched/windows.rs +0 -0
  884. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/sched.rs +0 -0
  885. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/stdio.rs +0 -0
  886. /data/ext/cargo-vendor/{wasi-common-15.0.1 → wasi-common-16.0.0}/LICENSE +0 -0
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  1050. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/fact/transcode.rs +0 -0
  1051. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/fact/traps.rs +0 -0
  1052. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/fact.rs +0 -0
  1053. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/obj.rs +0 -0
  1054. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/ref_bits.rs +0 -0
  1055. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/stack_map.rs +0 -0
  1056. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/trap_encoding.rs +0 -0
  1057. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/tunables.rs +0 -0
  1058. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/vmoffsets.rs +0 -0
  1059. /data/ext/cargo-vendor/{wasmtime-cranelift-15.0.1 → wasmtime-fiber-16.0.0}/LICENSE +0 -0
  1060. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-fiber-16.0.0}/build.rs +0 -0
  1061. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-fiber-16.0.0}/src/unix/aarch64.rs +0 -0
  1062. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-fiber-16.0.0}/src/unix/arm.rs +0 -0
  1063. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-fiber-16.0.0}/src/unix/riscv64.rs +0 -0
  1064. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-fiber-16.0.0}/src/unix/s390x.S +0 -0
  1065. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-fiber-16.0.0}/src/unix/x86.rs +0 -0
  1066. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-fiber-16.0.0}/src/unix/x86_64.rs +0 -0
  1067. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-fiber-16.0.0}/src/windows.rs +0 -0
  1068. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-jit-16.0.0}/LICENSE +0 -0
  1069. /data/ext/cargo-vendor/{wasmtime-jit-15.0.1 → wasmtime-jit-16.0.0}/src/debug.rs +0 -0
  1070. /data/ext/cargo-vendor/{wasmtime-jit-15.0.1 → wasmtime-jit-16.0.0}/src/demangling.rs +0 -0
  1071. /data/ext/cargo-vendor/{wasmtime-jit-15.0.1 → wasmtime-jit-16.0.0}/src/profiling/jitdump.rs +0 -0
  1072. /data/ext/cargo-vendor/{wasmtime-jit-15.0.1 → wasmtime-jit-16.0.0}/src/profiling/perfmap.rs +0 -0
  1073. /data/ext/cargo-vendor/{wasmtime-jit-15.0.1 → wasmtime-jit-16.0.0}/src/profiling/vtune.rs +0 -0
  1074. /data/ext/cargo-vendor/{wasmtime-jit-15.0.1 → wasmtime-jit-16.0.0}/src/profiling.rs +0 -0
  1075. /data/ext/cargo-vendor/{wasmtime-jit-debug-15.0.1 → wasmtime-jit-debug-16.0.0}/README.md +0 -0
  1076. /data/ext/cargo-vendor/{wasmtime-jit-debug-15.0.1 → wasmtime-jit-debug-16.0.0}/src/gdb_jit_int.rs +0 -0
  1077. /data/ext/cargo-vendor/{wasmtime-jit-debug-15.0.1 → wasmtime-jit-debug-16.0.0}/src/lib.rs +0 -0
  1078. /data/ext/cargo-vendor/{wasmtime-jit-debug-15.0.1 → wasmtime-jit-debug-16.0.0}/src/perf_jitdump.rs +0 -0
  1079. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-15.0.1 → wasmtime-jit-icache-coherence-16.0.0}/src/lib.rs +0 -0
  1080. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-15.0.1 → wasmtime-jit-icache-coherence-16.0.0}/src/libc.rs +0 -0
  1081. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-15.0.1 → wasmtime-jit-icache-coherence-16.0.0}/src/miri.rs +0 -0
  1082. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-15.0.1 → wasmtime-jit-icache-coherence-16.0.0}/src/win.rs +0 -0
  1083. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-runtime-16.0.0}/LICENSE +0 -0
  1084. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1/src/trampolines → wasmtime-runtime-16.0.0/src/arch}/s390x.S +0 -0
  1085. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/component/libcalls.rs +0 -0
  1086. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/component/resources.rs +0 -0
  1087. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/component.rs +0 -0
  1088. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/debug_builtins.rs +0 -0
  1089. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/export.rs +0 -0
  1090. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/externref.rs +0 -0
  1091. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/imports.rs +0 -0
  1092. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/instance/allocator/on_demand.rs +0 -0
  1093. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/instance/allocator/pooling/index_allocator.rs +0 -0
  1094. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/instance/allocator.rs +0 -0
  1095. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/instance.rs +0 -0
  1096. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/memory.rs +0 -0
  1097. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/mmap_vec.rs +0 -0
  1098. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/module_id.rs +0 -0
  1099. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/mpk/disabled.rs +0 -0
  1100. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/mpk/mod.rs +0 -0
  1101. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/mpk/sys.rs +0 -0
  1102. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/parking_spot.rs +0 -0
  1103. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/send_sync_ptr.rs +0 -0
  1104. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/store_box.rs +0 -0
  1105. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1/src/mmap/miri.rs → wasmtime-runtime-16.0.0/src/sys/miri/mmap.rs} +0 -0
  1106. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1/src/mmap/unix.rs → wasmtime-runtime-16.0.0/src/sys/unix/mmap.rs} +0 -0
  1107. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1/src/mmap/windows.rs → wasmtime-runtime-16.0.0/src/sys/windows/mmap.rs} +0 -0
  1108. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/table.rs +0 -0
  1109. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/traphandlers/coredump.rs +0 -0
  1110. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/vmcontext/vm_host_func_context.rs +0 -0
  1111. /data/ext/cargo-vendor/{wasmtime-jit-15.0.1 → wasmtime-types-16.0.0}/LICENSE +0 -0
  1112. /data/ext/cargo-vendor/{wasmtime-types-15.0.1 → wasmtime-types-16.0.0}/src/error.rs +0 -0
  1113. /data/ext/cargo-vendor/{wasmtime-versioned-export-macros-15.0.1 → wasmtime-versioned-export-macros-16.0.0}/src/lib.rs +0 -0
  1114. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-wasi-16.0.0}/LICENSE +0 -0
  1115. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/README.md +0 -0
  1116. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/build.rs +0 -0
  1117. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/clocks/host.rs +0 -0
  1118. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/clocks.rs +0 -0
  1119. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/command.rs +0 -0
  1120. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/ctx.rs +0 -0
  1121. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/error.rs +0 -0
  1122. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/filesystem.rs +0 -0
  1123. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/clocks.rs +0 -0
  1124. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/env.rs +0 -0
  1125. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/exit.rs +0 -0
  1126. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/filesystem/sync.rs +0 -0
  1127. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/filesystem.rs +0 -0
  1128. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/instance_network.rs +0 -0
  1129. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/mod.rs +0 -0
  1130. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/random.rs +0 -0
  1131. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/tcp_create_socket.rs +0 -0
  1132. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/udp_create_socket.rs +0 -0
  1133. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/ip_name_lookup.rs +0 -0
  1134. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/network.rs +0 -0
  1135. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/pipe.rs +0 -0
  1136. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/poll.rs +0 -0
  1137. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/random.rs +0 -0
  1138. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/stdio/worker_thread_stdin.rs +0 -0
  1139. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/tcp.rs +0 -0
  1140. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/udp.rs +0 -0
  1141. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/write_stream.rs +0 -0
  1142. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/cli/environment.wit +0 -0
  1143. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/cli/exit.wit +0 -0
  1144. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/cli/run.wit +0 -0
  1145. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/cli/stdio.wit +0 -0
  1146. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/cli/terminal.wit +0 -0
  1147. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/clocks/monotonic-clock.wit +0 -0
  1148. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/clocks/wall-clock.wit +0 -0
  1149. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/clocks/world.wit +0 -0
  1150. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/filesystem/preopens.wit +0 -0
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  1153. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/http/handler.wit +0 -0
  1154. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/io/error.wit +0 -0
  1155. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/io/poll.wit +0 -0
  1156. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/io/streams.wit +0 -0
  1157. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/io/world.wit +0 -0
  1158. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/random/insecure-seed.wit +0 -0
  1159. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/random/insecure.wit +0 -0
  1160. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/random/random.wit +0 -0
  1161. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/random/world.wit +0 -0
  1162. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/sockets/instance-network.wit +0 -0
  1163. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/sockets/ip-name-lookup.wit +0 -0
  1164. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/sockets/network.wit +0 -0
  1165. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/sockets/tcp-create-socket.wit +0 -0
  1166. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/sockets/tcp.wit +0 -0
  1167. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/sockets/udp-create-socket.wit +0 -0
  1168. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/sockets/udp.wit +0 -0
  1169. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/sockets/world.wit +0 -0
  1170. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1/witx → wasmtime-wasi-16.0.0/witx/preview1}/typenames.witx +0 -0
  1171. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1/witx → wasmtime-wasi-16.0.0/witx/preview1}/wasi_snapshot_preview1.witx +0 -0
  1172. /data/ext/cargo-vendor/{wasmtime-winch-15.0.1 → wasmtime-winch-16.0.0}/LICENSE +0 -0
  1173. /data/ext/cargo-vendor/{wasmtime-winch-15.0.1 → wasmtime-winch-16.0.0}/src/builder.rs +0 -0
  1174. /data/ext/cargo-vendor/{wasmtime-winch-15.0.1 → wasmtime-winch-16.0.0}/src/lib.rs +0 -0
  1175. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-15.0.1 → wasmtime-wit-bindgen-16.0.0}/src/lib.rs +0 -0
  1176. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-15.0.1 → wasmtime-wit-bindgen-16.0.0}/src/rust.rs +0 -0
  1177. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-15.0.1 → wasmtime-wit-bindgen-16.0.0}/src/source.rs +0 -0
  1178. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-15.0.1 → wasmtime-wit-bindgen-16.0.0}/src/types.rs +0 -0
  1179. /data/ext/cargo-vendor/{wasmtime-wmemcheck-15.0.1 → wasmtime-wmemcheck-16.0.0}/src/lib.rs +0 -0
  1180. /data/ext/cargo-vendor/{wasmtime-types-15.0.1 → wiggle-16.0.0}/LICENSE +0 -0
  1181. /data/ext/cargo-vendor/{wiggle-15.0.1 → wiggle-16.0.0}/README.md +0 -0
  1182. /data/ext/cargo-vendor/{wiggle-15.0.1 → wiggle-16.0.0}/src/borrow.rs +0 -0
  1183. /data/ext/cargo-vendor/{wiggle-15.0.1 → wiggle-16.0.0}/src/error.rs +0 -0
  1184. /data/ext/cargo-vendor/{wiggle-15.0.1 → wiggle-16.0.0}/src/guest_type.rs +0 -0
  1185. /data/ext/cargo-vendor/{wiggle-15.0.1 → wiggle-16.0.0}/src/region.rs +0 -0
  1186. /data/ext/cargo-vendor/{wiggle-15.0.1 → wiggle-16.0.0}/src/wasmtime.rs +0 -0
  1187. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wiggle-generate-16.0.0}/LICENSE +0 -0
  1188. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/README.md +0 -0
  1189. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/codegen_settings.rs +0 -0
  1190. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/config.rs +0 -0
  1191. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/funcs.rs +0 -0
  1192. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/lib.rs +0 -0
  1193. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/lifetimes.rs +0 -0
  1194. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/module_trait.rs +0 -0
  1195. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/names.rs +0 -0
  1196. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/types/error.rs +0 -0
  1197. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/types/flags.rs +0 -0
  1198. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/types/mod.rs +0 -0
  1199. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/wasmtime.rs +0 -0
  1200. /data/ext/cargo-vendor/{wiggle-15.0.1 → wiggle-macro-16.0.0}/LICENSE +0 -0
  1201. /data/ext/cargo-vendor/{wiggle-macro-15.0.1 → wiggle-macro-16.0.0}/src/lib.rs +0 -0
  1202. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/LICENSE +0 -0
  1203. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/build.rs +0 -0
  1204. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/codegen/builtin.rs +0 -0
  1205. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/isa/aarch64/address.rs +0 -0
  1206. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/isa/aarch64/asm.rs +0 -0
  1207. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/isa/aarch64/regs.rs +0 -0
  1208. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/isa/reg.rs +0 -0
  1209. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/isa/x64/address.rs +0 -0
  1210. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/lib.rs +0 -0
  1211. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/regalloc.rs +0 -0
  1212. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/regset.rs +0 -0
@@ -0,0 +1,2041 @@
1
+ //! This module defines riscv64-specific machine instruction types.
2
+
3
+ use super::lower::isle::generated_code::{VecAMode, VecElementWidth, VecOpMasking};
4
+ use crate::binemit::{Addend, CodeOffset, Reloc};
5
+ pub use crate::ir::condcodes::IntCC;
6
+ use crate::ir::types::{self, F32, F64, I128, I16, I32, I64, I8, I8X16, R32, R64};
7
+
8
+ pub use crate::ir::{ExternalName, MemFlags, Opcode, Type};
9
+ use crate::isa::{CallConv, FunctionAlignment};
10
+ use crate::machinst::*;
11
+ use crate::{settings, CodegenError, CodegenResult};
12
+
13
+ pub use crate::ir::condcodes::FloatCC;
14
+
15
+ use alloc::vec::Vec;
16
+ use regalloc2::{PRegSet, RegClass, VReg};
17
+ use smallvec::{smallvec, SmallVec};
18
+ use std::boxed::Box;
19
+ use std::fmt::Write;
20
+ use std::string::{String, ToString};
21
+
22
+ pub mod regs;
23
+ pub use self::regs::*;
24
+ pub mod imms;
25
+ pub use self::imms::*;
26
+ pub mod args;
27
+ pub use self::args::*;
28
+ pub mod emit;
29
+ pub use self::emit::*;
30
+ pub mod vector;
31
+ pub use self::vector::*;
32
+ pub mod encode;
33
+ pub use self::encode::*;
34
+ pub mod unwind;
35
+
36
+ use crate::isa::riscv64::abi::Riscv64MachineDeps;
37
+
38
+ #[cfg(test)]
39
+ mod emit_tests;
40
+
41
+ use std::fmt::{Display, Formatter};
42
+
43
+ pub(crate) type VecU8 = Vec<u8>;
44
+
45
+ //=============================================================================
46
+ // Instructions (top level): definition
47
+
48
+ pub use crate::isa::riscv64::lower::isle::generated_code::{
49
+ AluOPRRI, AluOPRRR, AtomicOP, CsrImmOP, CsrRegOP, FClassResult, FFlagsException, FloatRoundOP,
50
+ FpuOPRR, FpuOPRRR, FpuOPRRRR, LoadOP, MInst as Inst, StoreOP, CSR, FRM,
51
+ };
52
+ use crate::isa::riscv64::lower::isle::generated_code::{CjOp, MInst, VecAluOpRRImm5, VecAluOpRRR};
53
+
54
+ /// Additional information for (direct) Call instructions, left out of line to lower the size of
55
+ /// the Inst enum.
56
+ #[derive(Clone, Debug)]
57
+ pub struct CallInfo {
58
+ pub dest: ExternalName,
59
+ pub uses: CallArgList,
60
+ pub defs: CallRetList,
61
+ pub opcode: Opcode,
62
+ pub caller_callconv: CallConv,
63
+ pub callee_callconv: CallConv,
64
+ pub clobbers: PRegSet,
65
+ pub callee_pop_size: u32,
66
+ }
67
+
68
+ /// Additional information for CallInd instructions, left out of line to lower the size of the Inst
69
+ /// enum.
70
+ #[derive(Clone, Debug)]
71
+ pub struct CallIndInfo {
72
+ pub rn: Reg,
73
+ pub uses: CallArgList,
74
+ pub defs: CallRetList,
75
+ pub opcode: Opcode,
76
+ pub caller_callconv: CallConv,
77
+ pub callee_callconv: CallConv,
78
+ pub clobbers: PRegSet,
79
+ pub callee_pop_size: u32,
80
+ }
81
+
82
+ /// Additional information for `return_call[_ind]` instructions, left out of
83
+ /// line to lower the size of the `Inst` enum.
84
+ #[derive(Clone, Debug)]
85
+ pub struct ReturnCallInfo {
86
+ pub uses: CallArgList,
87
+ pub opcode: Opcode,
88
+ pub old_stack_arg_size: u32,
89
+ pub new_stack_arg_size: u32,
90
+ }
91
+
92
+ /// A conditional branch target.
93
+ #[derive(Clone, Copy, Debug, PartialEq, Eq)]
94
+ pub enum CondBrTarget {
95
+ /// An unresolved reference to a Label, as passed into
96
+ /// `lower_branch_group()`.
97
+ Label(MachLabel),
98
+ /// No jump; fall through to the next instruction.
99
+ Fallthrough,
100
+ }
101
+
102
+ impl CondBrTarget {
103
+ /// Return the target's label, if it is a label-based target.
104
+ pub(crate) fn as_label(self) -> Option<MachLabel> {
105
+ match self {
106
+ CondBrTarget::Label(l) => Some(l),
107
+ _ => None,
108
+ }
109
+ }
110
+
111
+ pub(crate) fn is_fallthrouh(&self) -> bool {
112
+ self == &CondBrTarget::Fallthrough
113
+ }
114
+ }
115
+
116
+ impl Display for CondBrTarget {
117
+ fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result {
118
+ match self {
119
+ CondBrTarget::Label(l) => write!(f, "{}", l.to_string()),
120
+ CondBrTarget::Fallthrough => write!(f, "0"),
121
+ }
122
+ }
123
+ }
124
+
125
+ pub(crate) fn enc_auipc(rd: Writable<Reg>, imm: Imm20) -> u32 {
126
+ let x = 0b0010111 | reg_to_gpr_num(rd.to_reg()) << 7 | imm.bits() << 12;
127
+ x
128
+ }
129
+
130
+ pub(crate) fn enc_jalr(rd: Writable<Reg>, base: Reg, offset: Imm12) -> u32 {
131
+ let x = 0b1100111
132
+ | reg_to_gpr_num(rd.to_reg()) << 7
133
+ | 0b000 << 12
134
+ | reg_to_gpr_num(base) << 15
135
+ | offset.bits() << 20;
136
+ x
137
+ }
138
+
139
+ /// rd and src must have the same length.
140
+ pub(crate) fn gen_moves(rd: &[Writable<Reg>], src: &[Reg]) -> SmallInstVec<Inst> {
141
+ assert!(rd.len() == src.len());
142
+ assert!(rd.len() > 0);
143
+ let mut insts = SmallInstVec::new();
144
+ for (dst, src) in rd.iter().zip(src.iter()) {
145
+ let ty = Inst::canonical_type_for_rc(dst.to_reg().class());
146
+ insts.push(Inst::gen_move(*dst, *src, ty));
147
+ }
148
+ insts
149
+ }
150
+
151
+ impl Inst {
152
+ /// RISC-V can have multiple instruction sizes. 2 bytes for compressed
153
+ /// instructions, 4 for regular instructions, 6 and 8 byte instructions
154
+ /// are also being considered.
155
+ const UNCOMPRESSED_INSTRUCTION_SIZE: i32 = 4;
156
+
157
+ #[inline]
158
+ pub(crate) fn load_imm12(rd: Writable<Reg>, imm: Imm12) -> Inst {
159
+ Inst::AluRRImm12 {
160
+ alu_op: AluOPRRI::Addi,
161
+ rd,
162
+ rs: zero_reg(),
163
+ imm12: imm,
164
+ }
165
+ }
166
+
167
+ /// Immediates can be loaded using lui and addi instructions.
168
+ fn load_const_imm(rd: Writable<Reg>, value: u64) -> Option<SmallInstVec<Inst>> {
169
+ Inst::generate_imm(value).map(|(imm20, imm12)| {
170
+ let mut insts = SmallVec::new();
171
+
172
+ let imm20_is_zero = imm20.as_i32() == 0;
173
+ let imm12_is_zero = imm12.as_i16() == 0;
174
+
175
+ let rs = if !imm20_is_zero {
176
+ insts.push(Inst::Lui { rd, imm: imm20 });
177
+ rd.to_reg()
178
+ } else {
179
+ zero_reg()
180
+ };
181
+
182
+ // We also need to emit the addi if the value is 0, otherwise we just
183
+ // won't produce any instructions.
184
+ if !imm12_is_zero || (imm20_is_zero && imm12_is_zero) {
185
+ insts.push(Inst::AluRRImm12 {
186
+ alu_op: AluOPRRI::Addi,
187
+ rd,
188
+ rs,
189
+ imm12,
190
+ })
191
+ }
192
+
193
+ insts
194
+ })
195
+ }
196
+
197
+ pub(crate) fn load_constant_u32(rd: Writable<Reg>, value: u64) -> SmallInstVec<Inst> {
198
+ let insts = Inst::load_const_imm(rd, value);
199
+ insts.unwrap_or_else(|| {
200
+ smallvec![Inst::LoadInlineConst {
201
+ rd,
202
+ ty: I32,
203
+ imm: value
204
+ }]
205
+ })
206
+ }
207
+
208
+ pub fn load_constant_u64(rd: Writable<Reg>, value: u64) -> SmallInstVec<Inst> {
209
+ let insts = Inst::load_const_imm(rd, value);
210
+ insts.unwrap_or_else(|| {
211
+ smallvec![Inst::LoadInlineConst {
212
+ rd,
213
+ ty: I64,
214
+ imm: value
215
+ }]
216
+ })
217
+ }
218
+
219
+ pub(crate) fn construct_auipc_and_jalr(
220
+ link: Option<Writable<Reg>>,
221
+ tmp: Writable<Reg>,
222
+ offset: i64,
223
+ ) -> [Inst; 2] {
224
+ Inst::generate_imm(offset as u64)
225
+ .map(|(imm20, imm12)| {
226
+ let a = Inst::Auipc {
227
+ rd: tmp,
228
+ imm: imm20,
229
+ };
230
+ let b = Inst::Jalr {
231
+ rd: link.unwrap_or(writable_zero_reg()),
232
+ base: tmp.to_reg(),
233
+ offset: imm12,
234
+ };
235
+ [a, b]
236
+ })
237
+ .expect("code range is too big.")
238
+ }
239
+
240
+ /// Create instructions that load a 32-bit floating-point constant.
241
+ pub fn load_fp_constant32<F: FnMut(Type) -> Writable<Reg>>(
242
+ rd: Writable<Reg>,
243
+ const_data: u32,
244
+ mut alloc_tmp: F,
245
+ ) -> SmallVec<[Inst; 4]> {
246
+ let mut insts = SmallVec::new();
247
+ let tmp = alloc_tmp(I64);
248
+ insts.extend(Self::load_constant_u32(tmp, const_data as u64));
249
+ insts.push(Inst::FpuRR {
250
+ frm: FRM::RNE,
251
+ alu_op: FpuOPRR::move_x_to_f_op(F32),
252
+ rd,
253
+ rs: tmp.to_reg(),
254
+ });
255
+ insts
256
+ }
257
+
258
+ /// Create instructions that load a 64-bit floating-point constant.
259
+ pub fn load_fp_constant64<F: FnMut(Type) -> Writable<Reg>>(
260
+ rd: Writable<Reg>,
261
+ const_data: u64,
262
+ mut alloc_tmp: F,
263
+ ) -> SmallVec<[Inst; 4]> {
264
+ let mut insts = SmallInstVec::new();
265
+ let tmp = alloc_tmp(I64);
266
+ insts.extend(Self::load_constant_u64(tmp, const_data));
267
+ insts.push(Inst::FpuRR {
268
+ frm: FRM::RNE,
269
+ alu_op: FpuOPRR::move_x_to_f_op(F64),
270
+ rd,
271
+ rs: tmp.to_reg(),
272
+ });
273
+ insts
274
+ }
275
+
276
+ /// Generic constructor for a load (zero-extending where appropriate).
277
+ pub fn gen_load(into_reg: Writable<Reg>, mem: AMode, ty: Type, flags: MemFlags) -> Inst {
278
+ if ty.is_vector() {
279
+ Inst::VecLoad {
280
+ eew: VecElementWidth::from_type(ty),
281
+ to: into_reg,
282
+ from: VecAMode::UnitStride { base: mem },
283
+ flags,
284
+ mask: VecOpMasking::Disabled,
285
+ vstate: VState::from_type(ty),
286
+ }
287
+ } else {
288
+ Inst::Load {
289
+ rd: into_reg,
290
+ op: LoadOP::from_type(ty),
291
+ from: mem,
292
+ flags,
293
+ }
294
+ }
295
+ }
296
+
297
+ /// Generic constructor for a store.
298
+ pub fn gen_store(mem: AMode, from_reg: Reg, ty: Type, flags: MemFlags) -> Inst {
299
+ if ty.is_vector() {
300
+ Inst::VecStore {
301
+ eew: VecElementWidth::from_type(ty),
302
+ to: VecAMode::UnitStride { base: mem },
303
+ from: from_reg,
304
+ flags,
305
+ mask: VecOpMasking::Disabled,
306
+ vstate: VState::from_type(ty),
307
+ }
308
+ } else {
309
+ Inst::Store {
310
+ src: from_reg,
311
+ op: StoreOP::from_type(ty),
312
+ to: mem,
313
+ flags,
314
+ }
315
+ }
316
+ }
317
+ }
318
+
319
+ //=============================================================================
320
+
321
+ fn vec_mask_operands<F: Fn(VReg) -> VReg>(
322
+ mask: &VecOpMasking,
323
+ collector: &mut OperandCollector<'_, F>,
324
+ ) {
325
+ match mask {
326
+ VecOpMasking::Enabled { reg } => {
327
+ collector.reg_fixed_use(*reg, pv_reg(0).into());
328
+ }
329
+ VecOpMasking::Disabled => {}
330
+ }
331
+ }
332
+ fn vec_mask_late_operands<F: Fn(VReg) -> VReg>(
333
+ mask: &VecOpMasking,
334
+ collector: &mut OperandCollector<'_, F>,
335
+ ) {
336
+ match mask {
337
+ VecOpMasking::Enabled { reg } => {
338
+ collector.reg_fixed_late_use(*reg, pv_reg(0).into());
339
+ }
340
+ VecOpMasking::Disabled => {}
341
+ }
342
+ }
343
+
344
+ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandCollector<'_, F>) {
345
+ match inst {
346
+ &Inst::Nop0 => {}
347
+ &Inst::Nop4 => {}
348
+ &Inst::BrTable {
349
+ index, tmp1, tmp2, ..
350
+ } => {
351
+ collector.reg_use(index);
352
+ collector.reg_early_def(tmp1);
353
+ collector.reg_early_def(tmp2);
354
+ }
355
+ &Inst::Auipc { rd, .. } => collector.reg_def(rd),
356
+ &Inst::Lui { rd, .. } => collector.reg_def(rd),
357
+ &Inst::LoadInlineConst { rd, .. } => collector.reg_def(rd),
358
+ &Inst::AluRRR { rd, rs1, rs2, .. } => {
359
+ collector.reg_use(rs1);
360
+ collector.reg_use(rs2);
361
+ collector.reg_def(rd);
362
+ }
363
+ &Inst::FpuRRR { rd, rs1, rs2, .. } => {
364
+ collector.reg_use(rs1);
365
+ collector.reg_use(rs2);
366
+ collector.reg_def(rd);
367
+ }
368
+ &Inst::AluRRImm12 { rd, rs, .. } => {
369
+ collector.reg_use(rs);
370
+ collector.reg_def(rd);
371
+ }
372
+ &Inst::CsrReg { rd, rs, .. } => {
373
+ collector.reg_use(rs);
374
+ collector.reg_def(rd);
375
+ }
376
+ &Inst::CsrImm { rd, .. } => {
377
+ collector.reg_def(rd);
378
+ }
379
+ &Inst::Load { rd, from, .. } => {
380
+ if let Some(r) = from.get_allocatable_register() {
381
+ collector.reg_use(r);
382
+ }
383
+ collector.reg_def(rd);
384
+ }
385
+ &Inst::Store { to, src, .. } => {
386
+ if let Some(r) = to.get_allocatable_register() {
387
+ collector.reg_use(r);
388
+ }
389
+ collector.reg_use(src);
390
+ }
391
+
392
+ &Inst::Args { ref args } => {
393
+ for arg in args {
394
+ collector.reg_fixed_def(arg.vreg, arg.preg);
395
+ }
396
+ }
397
+ &Inst::Rets { ref rets } => {
398
+ for ret in rets {
399
+ collector.reg_fixed_use(ret.vreg, ret.preg);
400
+ }
401
+ }
402
+ &Inst::Ret { .. } => {}
403
+
404
+ &Inst::Extend { rd, rn, .. } => {
405
+ collector.reg_use(rn);
406
+ collector.reg_def(rd);
407
+ }
408
+ &Inst::Call { ref info } => {
409
+ for u in &info.uses {
410
+ collector.reg_fixed_use(u.vreg, u.preg);
411
+ }
412
+ for d in &info.defs {
413
+ collector.reg_fixed_def(d.vreg, d.preg);
414
+ }
415
+ collector.reg_clobbers(info.clobbers);
416
+ }
417
+ &Inst::CallInd { ref info } => {
418
+ if info.callee_callconv == CallConv::Tail {
419
+ // TODO(https://github.com/bytecodealliance/regalloc2/issues/145):
420
+ // This shouldn't be a fixed register constraint.
421
+ collector.reg_fixed_use(info.rn, x_reg(5));
422
+ } else {
423
+ collector.reg_use(info.rn);
424
+ }
425
+
426
+ for u in &info.uses {
427
+ collector.reg_fixed_use(u.vreg, u.preg);
428
+ }
429
+ for d in &info.defs {
430
+ collector.reg_fixed_def(d.vreg, d.preg);
431
+ }
432
+ collector.reg_clobbers(info.clobbers);
433
+ }
434
+ &Inst::ReturnCall {
435
+ callee: _,
436
+ ref info,
437
+ } => {
438
+ for u in &info.uses {
439
+ collector.reg_fixed_use(u.vreg, u.preg);
440
+ }
441
+ }
442
+ &Inst::ReturnCallInd { ref info, callee } => {
443
+ collector.reg_use(callee);
444
+ for u in &info.uses {
445
+ collector.reg_fixed_use(u.vreg, u.preg);
446
+ }
447
+ }
448
+ &Inst::Jal { .. } => {
449
+ // JAL technically has a rd register, but we currently always
450
+ // hardcode it to x0.
451
+ }
452
+ &Inst::CondBr { kind, .. } => {
453
+ collector.reg_use(kind.rs1);
454
+ collector.reg_use(kind.rs2);
455
+ }
456
+ &Inst::LoadExtName { rd, .. } => {
457
+ collector.reg_def(rd);
458
+ }
459
+ &Inst::ElfTlsGetAddr { rd, .. } => {
460
+ // x10 is a0 which is both the first argument and the first return value.
461
+ collector.reg_fixed_def(rd, a0());
462
+ let mut clobbers = Riscv64MachineDeps::get_regs_clobbered_by_call(CallConv::SystemV);
463
+ clobbers.remove(px_reg(10));
464
+ collector.reg_clobbers(clobbers);
465
+ }
466
+ &Inst::LoadAddr { rd, mem } => {
467
+ if let Some(r) = mem.get_allocatable_register() {
468
+ collector.reg_use(r);
469
+ }
470
+ collector.reg_early_def(rd);
471
+ }
472
+
473
+ &Inst::VirtualSPOffsetAdj { .. } => {}
474
+ &Inst::Mov { rd, rm, .. } => {
475
+ collector.reg_use(rm);
476
+ collector.reg_def(rd);
477
+ }
478
+ &Inst::MovFromPReg { rd, rm } => {
479
+ debug_assert!([px_reg(2), px_reg(8)].contains(&rm));
480
+ collector.reg_def(rd);
481
+ }
482
+ &Inst::Fence { .. } => {}
483
+ &Inst::EBreak => {}
484
+ &Inst::Udf { .. } => {}
485
+ &Inst::FpuRR { rd, rs, .. } => {
486
+ collector.reg_use(rs);
487
+ collector.reg_def(rd);
488
+ }
489
+ &Inst::FpuRRRR {
490
+ rd, rs1, rs2, rs3, ..
491
+ } => {
492
+ collector.reg_uses(&[rs1, rs2, rs3]);
493
+ collector.reg_def(rd);
494
+ }
495
+
496
+ &Inst::Jalr { rd, base, .. } => {
497
+ collector.reg_use(base);
498
+ collector.reg_def(rd);
499
+ }
500
+ &Inst::Atomic { rd, addr, src, .. } => {
501
+ collector.reg_use(addr);
502
+ collector.reg_use(src);
503
+ collector.reg_def(rd);
504
+ }
505
+ &Inst::Select {
506
+ ref dst,
507
+ condition,
508
+ x,
509
+ y,
510
+ ..
511
+ } => {
512
+ collector.reg_use(condition.rs1);
513
+ collector.reg_use(condition.rs2);
514
+ collector.reg_uses(x.regs());
515
+ collector.reg_uses(y.regs());
516
+ // If there's more than one destination register then use
517
+ // `reg_early_def` to prevent destination registers from overlapping
518
+ // with any operands. This ensures that the lowering doesn't have to
519
+ // deal with a situation such as when the input registers need to be
520
+ // swapped when moved to the destination.
521
+ //
522
+ // When there's only one destination register though don't use an
523
+ // early def because once the register is written no other inputs
524
+ // are read so it's ok for the destination to overlap the sources.
525
+ if dst.regs().len() > 1 {
526
+ for d in dst.regs() {
527
+ collector.reg_early_def(d.clone());
528
+ }
529
+ } else {
530
+ collector.reg_defs(dst.regs());
531
+ }
532
+ }
533
+ &Inst::AtomicCas {
534
+ offset,
535
+ t0,
536
+ dst,
537
+ e,
538
+ addr,
539
+ v,
540
+ ..
541
+ } => {
542
+ collector.reg_uses(&[offset, e, addr, v]);
543
+ collector.reg_early_def(t0);
544
+ collector.reg_early_def(dst);
545
+ }
546
+
547
+ &Inst::RawData { .. } => {}
548
+ &Inst::AtomicStore { src, p, .. } => {
549
+ collector.reg_use(src);
550
+ collector.reg_use(p);
551
+ }
552
+ &Inst::AtomicLoad { rd, p, .. } => {
553
+ collector.reg_use(p);
554
+ collector.reg_def(rd);
555
+ }
556
+ &Inst::AtomicRmwLoop {
557
+ offset,
558
+ dst,
559
+ p,
560
+ x,
561
+ t0,
562
+ ..
563
+ } => {
564
+ collector.reg_uses(&[offset, p, x]);
565
+ collector.reg_early_def(t0);
566
+ collector.reg_early_def(dst);
567
+ }
568
+ &Inst::TrapIf { rs1, rs2, .. } => {
569
+ collector.reg_use(rs1);
570
+ collector.reg_use(rs2);
571
+ }
572
+ &Inst::Unwind { .. } => {}
573
+ &Inst::DummyUse { reg } => {
574
+ collector.reg_use(reg);
575
+ }
576
+ &Inst::FloatRound {
577
+ rd,
578
+ int_tmp,
579
+ f_tmp,
580
+ rs,
581
+ ..
582
+ } => {
583
+ collector.reg_use(rs);
584
+ collector.reg_early_def(int_tmp);
585
+ collector.reg_early_def(f_tmp);
586
+ collector.reg_early_def(rd);
587
+ }
588
+ &Inst::Popcnt {
589
+ sum, step, rs, tmp, ..
590
+ } => {
591
+ collector.reg_use(rs);
592
+ collector.reg_early_def(tmp);
593
+ collector.reg_early_def(step);
594
+ collector.reg_early_def(sum);
595
+ }
596
+ &Inst::Cltz {
597
+ sum, step, tmp, rs, ..
598
+ } => {
599
+ collector.reg_use(rs);
600
+ collector.reg_early_def(tmp);
601
+ collector.reg_early_def(step);
602
+ collector.reg_early_def(sum);
603
+ }
604
+ &Inst::Brev8 {
605
+ rs,
606
+ rd,
607
+ step,
608
+ tmp,
609
+ tmp2,
610
+ ..
611
+ } => {
612
+ collector.reg_use(rs);
613
+ collector.reg_early_def(step);
614
+ collector.reg_early_def(tmp);
615
+ collector.reg_early_def(tmp2);
616
+ collector.reg_early_def(rd);
617
+ }
618
+ &Inst::StackProbeLoop { .. } => {
619
+ // StackProbeLoop has a tmp register and StackProbeLoop used at gen_prologue.
620
+ // t3 will do the job. (t3 is caller-save register and not used directly by compiler like writable_spilltmp_reg)
621
+ // gen_prologue is called at emit stage.
622
+ // no need let reg alloc know.
623
+ }
624
+ &Inst::VecAluRRRR {
625
+ op,
626
+ vd,
627
+ vd_src,
628
+ vs1,
629
+ vs2,
630
+ ref mask,
631
+ ..
632
+ } => {
633
+ debug_assert_eq!(vd_src.class(), RegClass::Vector);
634
+ debug_assert_eq!(vd.to_reg().class(), RegClass::Vector);
635
+ debug_assert_eq!(vs2.class(), RegClass::Vector);
636
+ debug_assert_eq!(vs1.class(), op.vs1_regclass());
637
+
638
+ collector.reg_late_use(vs1);
639
+ collector.reg_late_use(vs2);
640
+ collector.reg_use(vd_src);
641
+ collector.reg_reuse_def(vd, 2); // `vd` == `vd_src`.
642
+ vec_mask_late_operands(mask, collector);
643
+ }
644
+ &Inst::VecAluRRRImm5 {
645
+ op,
646
+ vd,
647
+ vd_src,
648
+ vs2,
649
+ ref mask,
650
+ ..
651
+ } => {
652
+ debug_assert_eq!(vd_src.class(), RegClass::Vector);
653
+ debug_assert_eq!(vd.to_reg().class(), RegClass::Vector);
654
+ debug_assert_eq!(vs2.class(), RegClass::Vector);
655
+
656
+ // If the operation forbids source/destination overlap we need to
657
+ // ensure that the source and destination registers are different.
658
+ if op.forbids_overlaps(mask) {
659
+ collector.reg_late_use(vs2);
660
+ collector.reg_use(vd_src);
661
+ collector.reg_reuse_def(vd, 1); // `vd` == `vd_src`.
662
+ vec_mask_late_operands(mask, collector);
663
+ } else {
664
+ collector.reg_use(vs2);
665
+ collector.reg_use(vd_src);
666
+ collector.reg_reuse_def(vd, 1); // `vd` == `vd_src`.
667
+ vec_mask_operands(mask, collector);
668
+ }
669
+ }
670
+ &Inst::VecAluRRR {
671
+ op,
672
+ vd,
673
+ vs1,
674
+ vs2,
675
+ ref mask,
676
+ ..
677
+ } => {
678
+ debug_assert_eq!(vd.to_reg().class(), RegClass::Vector);
679
+ debug_assert_eq!(vs2.class(), RegClass::Vector);
680
+ debug_assert_eq!(vs1.class(), op.vs1_regclass());
681
+
682
+ collector.reg_use(vs1);
683
+ collector.reg_use(vs2);
684
+
685
+ // If the operation forbids source/destination overlap, then we must
686
+ // register it as an early_def. This encodes the constraint that
687
+ // these must not overlap.
688
+ if op.forbids_overlaps(mask) {
689
+ collector.reg_early_def(vd);
690
+ } else {
691
+ collector.reg_def(vd);
692
+ }
693
+
694
+ vec_mask_operands(mask, collector);
695
+ }
696
+ &Inst::VecAluRRImm5 {
697
+ op,
698
+ vd,
699
+ vs2,
700
+ ref mask,
701
+ ..
702
+ } => {
703
+ debug_assert_eq!(vd.to_reg().class(), RegClass::Vector);
704
+ debug_assert_eq!(vs2.class(), RegClass::Vector);
705
+
706
+ collector.reg_use(vs2);
707
+
708
+ // If the operation forbids source/destination overlap, then we must
709
+ // register it as an early_def. This encodes the constraint that
710
+ // these must not overlap.
711
+ if op.forbids_overlaps(mask) {
712
+ collector.reg_early_def(vd);
713
+ } else {
714
+ collector.reg_def(vd);
715
+ }
716
+
717
+ vec_mask_operands(mask, collector);
718
+ }
719
+ &Inst::VecAluRR {
720
+ op,
721
+ vd,
722
+ vs,
723
+ ref mask,
724
+ ..
725
+ } => {
726
+ debug_assert_eq!(vd.to_reg().class(), op.dst_regclass());
727
+ debug_assert_eq!(vs.class(), op.src_regclass());
728
+
729
+ collector.reg_use(vs);
730
+
731
+ // If the operation forbids source/destination overlap, then we must
732
+ // register it as an early_def. This encodes the constraint that
733
+ // these must not overlap.
734
+ if op.forbids_overlaps(mask) {
735
+ collector.reg_early_def(vd);
736
+ } else {
737
+ collector.reg_def(vd);
738
+ }
739
+
740
+ vec_mask_operands(mask, collector);
741
+ }
742
+ &Inst::VecAluRImm5 {
743
+ op, vd, ref mask, ..
744
+ } => {
745
+ debug_assert_eq!(vd.to_reg().class(), RegClass::Vector);
746
+ debug_assert!(!op.forbids_overlaps(mask));
747
+
748
+ collector.reg_def(vd);
749
+ vec_mask_operands(mask, collector);
750
+ }
751
+ &Inst::VecSetState { rd, .. } => {
752
+ collector.reg_def(rd);
753
+ }
754
+ &Inst::VecLoad {
755
+ to,
756
+ ref from,
757
+ ref mask,
758
+ ..
759
+ } => {
760
+ if let Some(r) = from.get_allocatable_register() {
761
+ collector.reg_use(r);
762
+ }
763
+ collector.reg_def(to);
764
+ vec_mask_operands(mask, collector);
765
+ }
766
+ &Inst::VecStore {
767
+ ref to,
768
+ from,
769
+ ref mask,
770
+ ..
771
+ } => {
772
+ if let Some(r) = to.get_allocatable_register() {
773
+ collector.reg_use(r);
774
+ }
775
+ collector.reg_use(from);
776
+ vec_mask_operands(mask, collector);
777
+ }
778
+ }
779
+ }
780
+
781
+ impl MachInst for Inst {
782
+ type LabelUse = LabelUse;
783
+ type ABIMachineSpec = Riscv64MachineDeps;
784
+
785
+ // https://github.com/riscv/riscv-isa-manual/issues/850
786
+ // all zero will cause invalid opcode.
787
+ const TRAP_OPCODE: &'static [u8] = &[0; 4];
788
+
789
+ fn gen_dummy_use(reg: Reg) -> Self {
790
+ Inst::DummyUse { reg }
791
+ }
792
+
793
+ fn canonical_type_for_rc(rc: RegClass) -> Type {
794
+ match rc {
795
+ regalloc2::RegClass::Int => I64,
796
+ regalloc2::RegClass::Float => F64,
797
+ regalloc2::RegClass::Vector => I8X16,
798
+ }
799
+ }
800
+
801
+ fn is_safepoint(&self) -> bool {
802
+ match self {
803
+ &Inst::Call { .. }
804
+ | &Inst::CallInd { .. }
805
+ | &Inst::TrapIf { .. }
806
+ | &Inst::Udf { .. } => true,
807
+ _ => false,
808
+ }
809
+ }
810
+
811
+ fn get_operands<F: Fn(VReg) -> VReg>(&self, collector: &mut OperandCollector<'_, F>) {
812
+ riscv64_get_operands(self, collector);
813
+ }
814
+
815
+ fn is_move(&self) -> Option<(Writable<Reg>, Reg)> {
816
+ match self {
817
+ Inst::Mov { rd, rm, .. } => Some((rd.clone(), rm.clone())),
818
+ _ => None,
819
+ }
820
+ }
821
+
822
+ fn is_included_in_clobbers(&self) -> bool {
823
+ match self {
824
+ &Inst::Args { .. } => false,
825
+ _ => true,
826
+ }
827
+ }
828
+
829
+ fn is_trap(&self) -> bool {
830
+ match self {
831
+ Self::Udf { .. } => true,
832
+ _ => false,
833
+ }
834
+ }
835
+
836
+ fn is_args(&self) -> bool {
837
+ match self {
838
+ Self::Args { .. } => true,
839
+ _ => false,
840
+ }
841
+ }
842
+
843
+ fn is_term(&self) -> MachTerminator {
844
+ match self {
845
+ &Inst::Jal { .. } => MachTerminator::Uncond,
846
+ &Inst::CondBr { .. } => MachTerminator::Cond,
847
+ &Inst::Jalr { .. } => MachTerminator::Uncond,
848
+ &Inst::Rets { .. } => MachTerminator::Ret,
849
+ &Inst::BrTable { .. } => MachTerminator::Indirect,
850
+ &Inst::ReturnCall { .. } | &Inst::ReturnCallInd { .. } => MachTerminator::RetCall,
851
+ _ => MachTerminator::None,
852
+ }
853
+ }
854
+
855
+ fn is_mem_access(&self) -> bool {
856
+ panic!("TODO FILL ME OUT")
857
+ }
858
+
859
+ fn gen_move(to_reg: Writable<Reg>, from_reg: Reg, ty: Type) -> Inst {
860
+ let x = Inst::Mov {
861
+ rd: to_reg,
862
+ rm: from_reg,
863
+ ty,
864
+ };
865
+ x
866
+ }
867
+
868
+ fn gen_nop(preferred_size: usize) -> Inst {
869
+ if preferred_size == 0 {
870
+ return Inst::Nop0;
871
+ }
872
+ // We can't give a NOP (or any insn) < 4 bytes.
873
+ assert!(preferred_size >= 4);
874
+ Inst::Nop4
875
+ }
876
+
877
+ fn rc_for_type(ty: Type) -> CodegenResult<(&'static [RegClass], &'static [Type])> {
878
+ match ty {
879
+ I8 => Ok((&[RegClass::Int], &[I8])),
880
+ I16 => Ok((&[RegClass::Int], &[I16])),
881
+ I32 => Ok((&[RegClass::Int], &[I32])),
882
+ I64 => Ok((&[RegClass::Int], &[I64])),
883
+ R32 => panic!("32-bit reftype pointer should never be seen on riscv64"),
884
+ R64 => Ok((&[RegClass::Int], &[R64])),
885
+ F32 => Ok((&[RegClass::Float], &[F32])),
886
+ F64 => Ok((&[RegClass::Float], &[F64])),
887
+ I128 => Ok((&[RegClass::Int, RegClass::Int], &[I64, I64])),
888
+ _ if ty.is_vector() => {
889
+ debug_assert!(ty.bits() <= 512);
890
+
891
+ // Here we only need to return a SIMD type with the same size as `ty`.
892
+ // We use these types for spills and reloads, so prefer types with lanes <= 31
893
+ // since that fits in the immediate field of `vsetivli`.
894
+ const SIMD_TYPES: [[Type; 1]; 6] = [
895
+ [types::I8X2],
896
+ [types::I8X4],
897
+ [types::I8X8],
898
+ [types::I8X16],
899
+ [types::I16X16],
900
+ [types::I32X16],
901
+ ];
902
+ let idx = (ty.bytes().ilog2() - 1) as usize;
903
+ let ty = &SIMD_TYPES[idx][..];
904
+
905
+ Ok((&[RegClass::Vector], ty))
906
+ }
907
+ _ => Err(CodegenError::Unsupported(format!(
908
+ "Unexpected SSA-value type: {}",
909
+ ty
910
+ ))),
911
+ }
912
+ }
913
+
914
+ fn gen_jump(target: MachLabel) -> Inst {
915
+ Inst::Jal { label: target }
916
+ }
917
+
918
+ fn worst_case_size() -> CodeOffset {
919
+ // calculate by test function riscv64_worst_case_instruction_size()
920
+ 124
921
+ }
922
+
923
+ fn ref_type_regclass(_settings: &settings::Flags) -> RegClass {
924
+ RegClass::Int
925
+ }
926
+
927
+ fn function_alignment() -> FunctionAlignment {
928
+ FunctionAlignment {
929
+ minimum: 2,
930
+ preferred: 4,
931
+ }
932
+ }
933
+ }
934
+
935
+ //=============================================================================
936
+ // Pretty-printing of instructions.
937
+ pub fn reg_name(reg: Reg) -> String {
938
+ match reg.to_real_reg() {
939
+ Some(real) => match real.class() {
940
+ RegClass::Int => match real.hw_enc() {
941
+ 0 => "zero".into(),
942
+ 1 => "ra".into(),
943
+ 2 => "sp".into(),
944
+ 3 => "gp".into(),
945
+ 4 => "tp".into(),
946
+ 5..=7 => format!("t{}", real.hw_enc() - 5),
947
+ 8 => "fp".into(),
948
+ 9 => "s1".into(),
949
+ 10..=17 => format!("a{}", real.hw_enc() - 10),
950
+ 18..=27 => format!("s{}", real.hw_enc() - 16),
951
+ 28..=31 => format!("t{}", real.hw_enc() - 25),
952
+ _ => unreachable!(),
953
+ },
954
+ RegClass::Float => match real.hw_enc() {
955
+ 0..=7 => format!("ft{}", real.hw_enc() - 0),
956
+ 8..=9 => format!("fs{}", real.hw_enc() - 8),
957
+ 10..=17 => format!("fa{}", real.hw_enc() - 10),
958
+ 18..=27 => format!("fs{}", real.hw_enc() - 16),
959
+ 28..=31 => format!("ft{}", real.hw_enc() - 20),
960
+ _ => unreachable!(),
961
+ },
962
+ RegClass::Vector => format!("v{}", real.hw_enc()),
963
+ },
964
+ None => {
965
+ format!("{:?}", reg)
966
+ }
967
+ }
968
+ }
969
+
970
+ impl Inst {
971
+ fn print_with_state(
972
+ &self,
973
+ _state: &mut EmitState,
974
+ allocs: &mut AllocationConsumer<'_>,
975
+ ) -> String {
976
+ let format_reg = |reg: Reg, allocs: &mut AllocationConsumer<'_>| -> String {
977
+ let reg = allocs.next(reg);
978
+ reg_name(reg)
979
+ };
980
+
981
+ let format_vec_amode = |amode: &VecAMode, allocs: &mut AllocationConsumer<'_>| -> String {
982
+ match amode {
983
+ VecAMode::UnitStride { base } => base.to_string_with_alloc(allocs),
984
+ }
985
+ };
986
+
987
+ let format_mask = |mask: &VecOpMasking, allocs: &mut AllocationConsumer<'_>| -> String {
988
+ match mask {
989
+ VecOpMasking::Enabled { reg } => format!(",{}.t", format_reg(*reg, allocs)),
990
+ VecOpMasking::Disabled => format!(""),
991
+ }
992
+ };
993
+
994
+ let format_regs = |regs: &[Reg], allocs: &mut AllocationConsumer<'_>| -> String {
995
+ let mut x = if regs.len() > 1 {
996
+ String::from("[")
997
+ } else {
998
+ String::default()
999
+ };
1000
+ regs.iter().for_each(|i| {
1001
+ x.push_str(format_reg(i.clone(), allocs).as_str());
1002
+ if *i != *regs.last().unwrap() {
1003
+ x.push_str(",");
1004
+ }
1005
+ });
1006
+ if regs.len() > 1 {
1007
+ x.push_str("]");
1008
+ }
1009
+ x
1010
+ };
1011
+ let format_labels = |labels: &[MachLabel]| -> String {
1012
+ if labels.len() == 0 {
1013
+ return String::from("[_]");
1014
+ }
1015
+ let mut x = String::from("[");
1016
+ labels.iter().for_each(|l| {
1017
+ x.push_str(
1018
+ format!(
1019
+ "{:?}{}",
1020
+ l,
1021
+ if l != labels.last().unwrap() { "," } else { "" },
1022
+ )
1023
+ .as_str(),
1024
+ );
1025
+ });
1026
+ x.push_str("]");
1027
+ x
1028
+ };
1029
+
1030
+ fn format_frm(rounding_mode: FRM) -> String {
1031
+ format!(",{}", rounding_mode.to_static_str())
1032
+ }
1033
+
1034
+ let mut empty_allocs = AllocationConsumer::default();
1035
+ match self {
1036
+ &Inst::Nop0 => {
1037
+ format!("##zero length nop")
1038
+ }
1039
+ &Inst::Nop4 => {
1040
+ format!("##fixed 4-size nop")
1041
+ }
1042
+ &Inst::StackProbeLoop {
1043
+ guard_size,
1044
+ probe_count,
1045
+ tmp,
1046
+ } => {
1047
+ let tmp = format_reg(tmp.to_reg(), allocs);
1048
+ format!(
1049
+ "inline_stack_probe##guard_size={} probe_count={} tmp={}",
1050
+ guard_size, probe_count, tmp
1051
+ )
1052
+ }
1053
+ &Inst::FloatRound {
1054
+ op,
1055
+ rd,
1056
+ int_tmp,
1057
+ f_tmp,
1058
+ rs,
1059
+ ty,
1060
+ } => {
1061
+ let rs = format_reg(rs, allocs);
1062
+ let int_tmp = format_reg(int_tmp.to_reg(), allocs);
1063
+ let f_tmp = format_reg(f_tmp.to_reg(), allocs);
1064
+ let rd = format_reg(rd.to_reg(), allocs);
1065
+ format!(
1066
+ "{} {},{}##int_tmp={} f_tmp={} ty={}",
1067
+ op.op_name(),
1068
+ rd,
1069
+ rs,
1070
+ int_tmp,
1071
+ f_tmp,
1072
+ ty
1073
+ )
1074
+ }
1075
+ &Inst::AtomicStore { src, ty, p } => {
1076
+ let src = format_reg(src, allocs);
1077
+ let p = format_reg(p, allocs);
1078
+ format!("atomic_store.{} {},({})", ty, src, p)
1079
+ }
1080
+ &Inst::DummyUse { reg } => {
1081
+ let reg = format_reg(reg, allocs);
1082
+ format!("dummy_use {}", reg)
1083
+ }
1084
+
1085
+ &Inst::AtomicLoad { rd, ty, p } => {
1086
+ let p = format_reg(p, allocs);
1087
+ let rd = format_reg(rd.to_reg(), allocs);
1088
+ format!("atomic_load.{} {},({})", ty, rd, p)
1089
+ }
1090
+ &Inst::AtomicRmwLoop {
1091
+ offset,
1092
+ op,
1093
+ dst,
1094
+ ty,
1095
+ p,
1096
+ x,
1097
+ t0,
1098
+ } => {
1099
+ let offset = format_reg(offset, allocs);
1100
+ let p = format_reg(p, allocs);
1101
+ let x = format_reg(x, allocs);
1102
+ let t0 = format_reg(t0.to_reg(), allocs);
1103
+ let dst = format_reg(dst.to_reg(), allocs);
1104
+ format!(
1105
+ "atomic_rmw.{} {} {},{},({})##t0={} offset={}",
1106
+ ty, op, dst, x, p, t0, offset
1107
+ )
1108
+ }
1109
+
1110
+ &Inst::RawData { ref data } => match data.len() {
1111
+ 4 => {
1112
+ let mut bytes = [0; 4];
1113
+ for i in 0..bytes.len() {
1114
+ bytes[i] = data[i];
1115
+ }
1116
+ format!(".4byte 0x{:x}", u32::from_le_bytes(bytes))
1117
+ }
1118
+ 8 => {
1119
+ let mut bytes = [0; 8];
1120
+ for i in 0..bytes.len() {
1121
+ bytes[i] = data[i];
1122
+ }
1123
+ format!(".8byte 0x{:x}", u64::from_le_bytes(bytes))
1124
+ }
1125
+ _ => {
1126
+ format!(".data {:?}", data)
1127
+ }
1128
+ },
1129
+ &Inst::Unwind { ref inst } => {
1130
+ format!("unwind {:?}", inst)
1131
+ }
1132
+ &Inst::Brev8 {
1133
+ rs,
1134
+ ty,
1135
+ step,
1136
+ tmp,
1137
+ tmp2,
1138
+ rd,
1139
+ } => {
1140
+ let rs = format_reg(rs, allocs);
1141
+ let step = format_reg(step.to_reg(), allocs);
1142
+ let tmp = format_reg(tmp.to_reg(), allocs);
1143
+ let tmp2 = format_reg(tmp2.to_reg(), allocs);
1144
+ let rd = format_reg(rd.to_reg(), allocs);
1145
+ format!(
1146
+ "brev8 {},{}##tmp={} tmp2={} step={} ty={}",
1147
+ rd, rs, tmp, tmp2, step, ty
1148
+ )
1149
+ }
1150
+ &Inst::Popcnt {
1151
+ sum,
1152
+ step,
1153
+ rs,
1154
+ tmp,
1155
+ ty,
1156
+ } => {
1157
+ let rs = format_reg(rs, allocs);
1158
+ let tmp = format_reg(tmp.to_reg(), allocs);
1159
+ let step = format_reg(step.to_reg(), allocs);
1160
+ let sum = format_reg(sum.to_reg(), allocs);
1161
+ format!("popcnt {},{}##ty={} tmp={} step={}", sum, rs, ty, tmp, step)
1162
+ }
1163
+ &Inst::Cltz {
1164
+ sum,
1165
+ step,
1166
+ rs,
1167
+ tmp,
1168
+ ty,
1169
+ leading,
1170
+ } => {
1171
+ let rs = format_reg(rs, allocs);
1172
+ let tmp = format_reg(tmp.to_reg(), allocs);
1173
+ let step = format_reg(step.to_reg(), allocs);
1174
+ let sum = format_reg(sum.to_reg(), allocs);
1175
+ format!(
1176
+ "{} {},{}##ty={} tmp={} step={}",
1177
+ if leading { "clz" } else { "ctz" },
1178
+ sum,
1179
+ rs,
1180
+ ty,
1181
+ tmp,
1182
+ step
1183
+ )
1184
+ }
1185
+ &Inst::AtomicCas {
1186
+ offset,
1187
+ t0,
1188
+ dst,
1189
+ e,
1190
+ addr,
1191
+ v,
1192
+ ty,
1193
+ } => {
1194
+ let offset = format_reg(offset, allocs);
1195
+ let e = format_reg(e, allocs);
1196
+ let addr = format_reg(addr, allocs);
1197
+ let v = format_reg(v, allocs);
1198
+ let t0 = format_reg(t0.to_reg(), allocs);
1199
+ let dst = format_reg(dst.to_reg(), allocs);
1200
+ format!(
1201
+ "atomic_cas.{} {},{},{},({})##t0={} offset={}",
1202
+ ty, dst, e, v, addr, t0, offset,
1203
+ )
1204
+ }
1205
+ &Inst::BrTable {
1206
+ index,
1207
+ tmp1,
1208
+ tmp2,
1209
+ ref targets,
1210
+ } => {
1211
+ format!(
1212
+ "{} {},{}##tmp1={},tmp2={}",
1213
+ "br_table",
1214
+ format_reg(index, allocs),
1215
+ format_labels(&targets[..]),
1216
+ format_reg(tmp1.to_reg(), allocs),
1217
+ format_reg(tmp2.to_reg(), allocs),
1218
+ )
1219
+ }
1220
+ &Inst::Auipc { rd, imm } => {
1221
+ format!(
1222
+ "{} {},{}",
1223
+ "auipc",
1224
+ format_reg(rd.to_reg(), allocs),
1225
+ imm.as_i32(),
1226
+ )
1227
+ }
1228
+ &Inst::Jalr { rd, base, offset } => {
1229
+ let base = format_reg(base, allocs);
1230
+ let rd = format_reg(rd.to_reg(), allocs);
1231
+ format!("{} {},{}({})", "jalr", rd, offset.as_i16(), base)
1232
+ }
1233
+ &Inst::Lui { rd, ref imm } => {
1234
+ format!(
1235
+ "{} {},{}",
1236
+ "lui",
1237
+ format_reg(rd.to_reg(), allocs),
1238
+ imm.as_i32()
1239
+ )
1240
+ }
1241
+ &Inst::LoadInlineConst { rd, imm, .. } => {
1242
+ let rd = format_reg(rd.to_reg(), allocs);
1243
+ let mut buf = String::new();
1244
+ write!(&mut buf, "auipc {},0; ", rd).unwrap();
1245
+ write!(&mut buf, "ld {},12({}); ", rd, rd).unwrap();
1246
+ write!(&mut buf, "j {}; ", Inst::UNCOMPRESSED_INSTRUCTION_SIZE + 8).unwrap();
1247
+ write!(&mut buf, ".8byte 0x{:x}", imm).unwrap();
1248
+ buf
1249
+ }
1250
+ &Inst::AluRRR {
1251
+ alu_op,
1252
+ rd,
1253
+ rs1,
1254
+ rs2,
1255
+ } => {
1256
+ let rs1_s = format_reg(rs1, allocs);
1257
+ let rs2_s = format_reg(rs2, allocs);
1258
+ let rd_s = format_reg(rd.to_reg(), allocs);
1259
+ match alu_op {
1260
+ AluOPRRR::Adduw if rs2 == zero_reg() => {
1261
+ format!("zext.w {},{}", rd_s, rs1_s)
1262
+ }
1263
+ _ => {
1264
+ format!("{} {},{},{}", alu_op.op_name(), rd_s, rs1_s, rs2_s)
1265
+ }
1266
+ }
1267
+ }
1268
+ &Inst::FpuRR {
1269
+ frm,
1270
+ alu_op,
1271
+ rd,
1272
+ rs,
1273
+ } => {
1274
+ let rs = format_reg(rs, allocs);
1275
+ let rd = format_reg(rd.to_reg(), allocs);
1276
+ let frm = match alu_op {
1277
+ FpuOPRR::FmvXW
1278
+ | FpuOPRR::FmvWX
1279
+ | FpuOPRR::FmvXD
1280
+ | FpuOPRR::FmvDX
1281
+ | FpuOPRR::FclassS
1282
+ | FpuOPRR::FclassD
1283
+ | FpuOPRR::FcvtDW
1284
+ | FpuOPRR::FcvtDWU => String::new(),
1285
+ _ => format_frm(frm),
1286
+ };
1287
+ format!("{} {rd},{rs}{frm}", alu_op.op_name())
1288
+ }
1289
+ &Inst::FpuRRR {
1290
+ alu_op,
1291
+ rd,
1292
+ rs1,
1293
+ rs2,
1294
+ frm,
1295
+ } => {
1296
+ let rs1 = format_reg(rs1, allocs);
1297
+ let rs2 = format_reg(rs2, allocs);
1298
+ let rd = format_reg(rd.to_reg(), allocs);
1299
+ let rs1_is_rs2 = rs1 == rs2;
1300
+ if rs1_is_rs2 && alu_op.is_copy_sign() {
1301
+ // this is move instruction.
1302
+ format!("fmv.{} {rd},{rs1}", if alu_op.is_32() { "s" } else { "d" })
1303
+ } else if rs1_is_rs2 && alu_op.is_copy_neg_sign() {
1304
+ format!("fneg.{} {rd},{rs1}", if alu_op.is_32() { "s" } else { "d" })
1305
+ } else if rs1_is_rs2 && alu_op.is_copy_xor_sign() {
1306
+ format!("fabs.{} {rd},{rs1}", if alu_op.is_32() { "s" } else { "d" })
1307
+ } else {
1308
+ let frm = match alu_op {
1309
+ FpuOPRRR::FsgnjS
1310
+ | FpuOPRRR::FsgnjnS
1311
+ | FpuOPRRR::FsgnjxS
1312
+ | FpuOPRRR::FsgnjD
1313
+ | FpuOPRRR::FsgnjnD
1314
+ | FpuOPRRR::FsgnjxD
1315
+ | FpuOPRRR::FminS
1316
+ | FpuOPRRR::FminD
1317
+ | FpuOPRRR::FmaxS
1318
+ | FpuOPRRR::FmaxD
1319
+ | FpuOPRRR::FeqS
1320
+ | FpuOPRRR::FeqD
1321
+ | FpuOPRRR::FltS
1322
+ | FpuOPRRR::FltD
1323
+ | FpuOPRRR::FleS
1324
+ | FpuOPRRR::FleD => String::new(),
1325
+ _ => format_frm(frm),
1326
+ };
1327
+ format!("{} {rd},{rs1},{rs2}{frm}", alu_op.op_name())
1328
+ }
1329
+ }
1330
+ &Inst::FpuRRRR {
1331
+ alu_op,
1332
+ rd,
1333
+ rs1,
1334
+ rs2,
1335
+ rs3,
1336
+ frm,
1337
+ } => {
1338
+ let rs1 = format_reg(rs1, allocs);
1339
+ let rs2 = format_reg(rs2, allocs);
1340
+ let rs3 = format_reg(rs3, allocs);
1341
+ let rd = format_reg(rd.to_reg(), allocs);
1342
+ format!(
1343
+ "{} {},{},{},{}{}",
1344
+ alu_op.op_name(),
1345
+ rd,
1346
+ rs1,
1347
+ rs2,
1348
+ rs3,
1349
+ format_frm(frm)
1350
+ )
1351
+ }
1352
+ &Inst::AluRRImm12 {
1353
+ alu_op,
1354
+ rd,
1355
+ rs,
1356
+ ref imm12,
1357
+ } => {
1358
+ let rs_s = format_reg(rs, allocs);
1359
+ let rd = format_reg(rd.to_reg(), allocs);
1360
+
1361
+ // Some of these special cases are better known as
1362
+ // their pseudo-instruction version, so prefer printing those.
1363
+ match (alu_op, rs, imm12) {
1364
+ (AluOPRRI::Addi, rs, _) if rs == zero_reg() => {
1365
+ return format!("li {},{}", rd, imm12.as_i16());
1366
+ }
1367
+ (AluOPRRI::Addiw, _, imm12) if imm12.as_i16() == 0 => {
1368
+ return format!("sext.w {},{}", rd, rs_s);
1369
+ }
1370
+ (AluOPRRI::Xori, _, imm12) if imm12.as_i16() == -1 => {
1371
+ return format!("not {},{}", rd, rs_s);
1372
+ }
1373
+ (AluOPRRI::SltiU, _, imm12) if imm12.as_i16() == 1 => {
1374
+ return format!("seqz {},{}", rd, rs_s);
1375
+ }
1376
+ (alu_op, _, _) if alu_op.option_funct12().is_some() => {
1377
+ format!("{} {},{}", alu_op.op_name(), rd, rs_s)
1378
+ }
1379
+ (alu_op, _, imm12) => {
1380
+ format!("{} {},{},{}", alu_op.op_name(), rd, rs_s, imm12.as_i16())
1381
+ }
1382
+ }
1383
+ }
1384
+ &Inst::CsrReg { op, rd, rs, csr } => {
1385
+ let rs_s = format_reg(rs, allocs);
1386
+ let rd_s = format_reg(rd.to_reg(), allocs);
1387
+
1388
+ match (op, csr, rd) {
1389
+ (CsrRegOP::CsrRW, CSR::Frm, rd) if rd.to_reg() == zero_reg() => {
1390
+ format!("fsrm {rs_s}")
1391
+ }
1392
+ _ => {
1393
+ format!("{op} {rd_s},{csr},{rs_s}")
1394
+ }
1395
+ }
1396
+ }
1397
+ &Inst::CsrImm { op, rd, csr, imm } => {
1398
+ let rd_s = format_reg(rd.to_reg(), allocs);
1399
+
1400
+ match (op, csr, rd) {
1401
+ (CsrImmOP::CsrRWI, CSR::Frm, rd) if rd.to_reg() != zero_reg() => {
1402
+ format!("fsrmi {rd_s},{imm}")
1403
+ }
1404
+ _ => {
1405
+ format!("{op} {rd_s},{csr},{imm}")
1406
+ }
1407
+ }
1408
+ }
1409
+ &Inst::Load {
1410
+ rd,
1411
+ op,
1412
+ from,
1413
+ flags: _flags,
1414
+ } => {
1415
+ let base = from.to_string_with_alloc(allocs);
1416
+ let rd = format_reg(rd.to_reg(), allocs);
1417
+ format!("{} {},{}", op.op_name(), rd, base,)
1418
+ }
1419
+ &Inst::Store {
1420
+ to,
1421
+ src,
1422
+ op,
1423
+ flags: _flags,
1424
+ } => {
1425
+ let base = to.to_string_with_alloc(allocs);
1426
+ let src = format_reg(src, allocs);
1427
+ format!("{} {},{}", op.op_name(), src, base,)
1428
+ }
1429
+ &Inst::Args { ref args } => {
1430
+ let mut s = "args".to_string();
1431
+ let mut empty_allocs = AllocationConsumer::default();
1432
+ for arg in args {
1433
+ let preg = format_reg(arg.preg, &mut empty_allocs);
1434
+ let def = format_reg(arg.vreg.to_reg(), allocs);
1435
+ write!(&mut s, " {}={}", def, preg).unwrap();
1436
+ }
1437
+ s
1438
+ }
1439
+ &Inst::Rets { ref rets } => {
1440
+ let mut s = "rets".to_string();
1441
+ let mut empty_allocs = AllocationConsumer::default();
1442
+ for ret in rets {
1443
+ let preg = format_reg(ret.preg, &mut empty_allocs);
1444
+ let vreg = format_reg(ret.vreg, allocs);
1445
+ write!(&mut s, " {vreg}={preg}").unwrap();
1446
+ }
1447
+ s
1448
+ }
1449
+ &Inst::Ret {} => "ret".to_string(),
1450
+
1451
+ &MInst::Extend {
1452
+ rd,
1453
+ rn,
1454
+ signed,
1455
+ from_bits,
1456
+ ..
1457
+ } => {
1458
+ let rn = format_reg(rn, allocs);
1459
+ let rd = format_reg(rd.to_reg(), allocs);
1460
+ return if signed == false && from_bits == 8 {
1461
+ format!("andi {rd},{rn}")
1462
+ } else {
1463
+ let op = if signed { "srai" } else { "srli" };
1464
+ let shift_bits = (64 - from_bits) as i16;
1465
+ format!("slli {rd},{rn},{shift_bits}; {op} {rd},{rd},{shift_bits}")
1466
+ };
1467
+ }
1468
+ &MInst::Call { ref info } => format!("call {}", info.dest.display(None)),
1469
+ &MInst::CallInd { ref info } => {
1470
+ let rd = format_reg(info.rn, allocs);
1471
+ format!("callind {}", rd)
1472
+ }
1473
+ &MInst::ReturnCall {
1474
+ ref callee,
1475
+ ref info,
1476
+ } => {
1477
+ let mut s = format!(
1478
+ "return_call {callee:?} old_stack_arg_size:{} new_stack_arg_size:{}",
1479
+ info.old_stack_arg_size, info.new_stack_arg_size
1480
+ );
1481
+ for ret in &info.uses {
1482
+ let preg = format_reg(ret.preg, &mut empty_allocs);
1483
+ let vreg = format_reg(ret.vreg, allocs);
1484
+ write!(&mut s, " {vreg}={preg}").unwrap();
1485
+ }
1486
+ s
1487
+ }
1488
+ &MInst::ReturnCallInd { callee, ref info } => {
1489
+ let callee = format_reg(callee, allocs);
1490
+ let mut s = format!(
1491
+ "return_call_ind {callee} old_stack_arg_size:{} new_stack_arg_size:{}",
1492
+ info.old_stack_arg_size, info.new_stack_arg_size
1493
+ );
1494
+ for ret in &info.uses {
1495
+ let preg = format_reg(ret.preg, &mut empty_allocs);
1496
+ let vreg = format_reg(ret.vreg, allocs);
1497
+ write!(&mut s, " {vreg}={preg}").unwrap();
1498
+ }
1499
+ s
1500
+ }
1501
+ &MInst::TrapIf {
1502
+ rs1,
1503
+ rs2,
1504
+ cc,
1505
+ trap_code,
1506
+ } => {
1507
+ let rs1 = format_reg(rs1, allocs);
1508
+ let rs2 = format_reg(rs2, allocs);
1509
+ format!("trap_if {trap_code}##({rs1} {cc} {rs2})")
1510
+ }
1511
+ &MInst::Jal { label } => {
1512
+ format!("j {}", label.to_string())
1513
+ }
1514
+ &MInst::CondBr {
1515
+ taken,
1516
+ not_taken,
1517
+ kind,
1518
+ ..
1519
+ } => {
1520
+ let rs1 = format_reg(kind.rs1, allocs);
1521
+ let rs2 = format_reg(kind.rs2, allocs);
1522
+ if not_taken.is_fallthrouh() && taken.as_label().is_none() {
1523
+ format!("{} {},{},0", kind.op_name(), rs1, rs2)
1524
+ } else {
1525
+ let x = format!(
1526
+ "{} {},{},taken({}),not_taken({})",
1527
+ kind.op_name(),
1528
+ rs1,
1529
+ rs2,
1530
+ taken,
1531
+ not_taken
1532
+ );
1533
+ x
1534
+ }
1535
+ }
1536
+ &MInst::Atomic {
1537
+ op,
1538
+ rd,
1539
+ addr,
1540
+ src,
1541
+ amo,
1542
+ } => {
1543
+ let op_name = op.op_name(amo);
1544
+ let addr = format_reg(addr, allocs);
1545
+ let src = format_reg(src, allocs);
1546
+ let rd = format_reg(rd.to_reg(), allocs);
1547
+ if op.is_load() {
1548
+ format!("{} {},({})", op_name, rd, addr)
1549
+ } else {
1550
+ format!("{} {},{},({})", op_name, rd, src, addr)
1551
+ }
1552
+ }
1553
+ &MInst::LoadExtName {
1554
+ rd,
1555
+ ref name,
1556
+ offset,
1557
+ } => {
1558
+ let rd = format_reg(rd.to_reg(), allocs);
1559
+ format!("load_sym {},{}{:+}", rd, name.display(None), offset)
1560
+ }
1561
+ &Inst::ElfTlsGetAddr { rd, ref name } => {
1562
+ let rd = format_reg(rd.to_reg(), allocs);
1563
+ format!("elf_tls_get_addr {rd},{}", name.display(None))
1564
+ }
1565
+ &MInst::LoadAddr { ref rd, ref mem } => {
1566
+ let rs = mem.to_string_with_alloc(allocs);
1567
+ let rd = format_reg(rd.to_reg(), allocs);
1568
+ format!("load_addr {},{}", rd, rs)
1569
+ }
1570
+ &MInst::VirtualSPOffsetAdj { amount } => {
1571
+ format!("virtual_sp_offset_adj {:+}", amount)
1572
+ }
1573
+ &MInst::Mov { rd, rm, ty } => {
1574
+ let rd = format_reg(rd.to_reg(), allocs);
1575
+ let rm = format_reg(rm, allocs);
1576
+
1577
+ let op = match ty {
1578
+ F32 => "fmv.s",
1579
+ F64 => "fmv.d",
1580
+ ty if ty.is_vector() => "vmv1r.v",
1581
+ _ => "mv",
1582
+ };
1583
+
1584
+ format!("{op} {rd},{rm}")
1585
+ }
1586
+ &MInst::MovFromPReg { rd, rm } => {
1587
+ let rd = format_reg(rd.to_reg(), allocs);
1588
+ debug_assert!([px_reg(2), px_reg(8)].contains(&rm));
1589
+ let rm = reg_name(Reg::from(rm));
1590
+ format!("mv {},{}", rd, rm)
1591
+ }
1592
+ &MInst::Fence { pred, succ } => {
1593
+ format!(
1594
+ "fence {},{}",
1595
+ Inst::fence_req_to_string(pred),
1596
+ Inst::fence_req_to_string(succ),
1597
+ )
1598
+ }
1599
+ &MInst::Select {
1600
+ ref dst,
1601
+ condition,
1602
+ ref x,
1603
+ ref y,
1604
+ } => {
1605
+ let c_rs1 = format_reg(condition.rs1, allocs);
1606
+ let c_rs2 = format_reg(condition.rs2, allocs);
1607
+ let x = format_regs(x.regs(), allocs);
1608
+ let y = format_regs(y.regs(), allocs);
1609
+ let dst = dst.map(|r| r.to_reg());
1610
+ let dst = format_regs(dst.regs(), allocs);
1611
+ format!(
1612
+ "select {},{},{}##condition=({} {} {})",
1613
+ dst,
1614
+ x,
1615
+ y,
1616
+ c_rs1,
1617
+ condition.kind.to_static_str(),
1618
+ c_rs2
1619
+ )
1620
+ }
1621
+ &MInst::Udf { trap_code } => format!("udf##trap_code={}", trap_code),
1622
+ &MInst::EBreak {} => String::from("ebreak"),
1623
+ &Inst::VecAluRRRR {
1624
+ op,
1625
+ vd,
1626
+ vd_src,
1627
+ vs1,
1628
+ vs2,
1629
+ ref mask,
1630
+ ref vstate,
1631
+ } => {
1632
+ let vs1_s = format_reg(vs1, allocs);
1633
+ let vs2_s = format_reg(vs2, allocs);
1634
+ let vd_src_s = format_reg(vd_src, allocs);
1635
+ let vd_s = format_reg(vd.to_reg(), allocs);
1636
+ let mask = format_mask(mask, allocs);
1637
+
1638
+ let vd_fmt = if vd_s != vd_src_s {
1639
+ format!("{},{}", vd_s, vd_src_s)
1640
+ } else {
1641
+ vd_s
1642
+ };
1643
+
1644
+ // Note: vs2 and vs1 here are opposite to the standard scalar ordering.
1645
+ // This is noted in Section 10.1 of the RISC-V Vector spec.
1646
+ format!("{op} {vd_fmt},{vs2_s},{vs1_s}{mask} {vstate}")
1647
+ }
1648
+ &Inst::VecAluRRRImm5 {
1649
+ op,
1650
+ vd,
1651
+ imm,
1652
+ vs2,
1653
+ ref mask,
1654
+ ref vstate,
1655
+ ..
1656
+ } => {
1657
+ let vs2_s = format_reg(vs2, allocs);
1658
+ let vd_s = format_reg(vd.to_reg(), allocs);
1659
+ let mask = format_mask(mask, allocs);
1660
+
1661
+ // Some opcodes interpret the immediate as unsigned, lets show the
1662
+ // correct number here.
1663
+ let imm_s = if op.imm_is_unsigned() {
1664
+ format!("{}", imm.bits())
1665
+ } else {
1666
+ format!("{}", imm)
1667
+ };
1668
+
1669
+ format!("{op} {vd_s},{vs2_s},{imm_s}{mask} {vstate}")
1670
+ }
1671
+ &Inst::VecAluRRR {
1672
+ op,
1673
+ vd,
1674
+ vs1,
1675
+ vs2,
1676
+ ref mask,
1677
+ ref vstate,
1678
+ } => {
1679
+ let vs1_s = format_reg(vs1, allocs);
1680
+ let vs2_s = format_reg(vs2, allocs);
1681
+ let vd_s = format_reg(vd.to_reg(), allocs);
1682
+ let mask = format_mask(mask, allocs);
1683
+
1684
+ // Note: vs2 and vs1 here are opposite to the standard scalar ordering.
1685
+ // This is noted in Section 10.1 of the RISC-V Vector spec.
1686
+ match (op, vs2, vs1) {
1687
+ (VecAluOpRRR::VrsubVX, _, vs1) if vs1 == zero_reg() => {
1688
+ format!("vneg.v {vd_s},{vs2_s}{mask} {vstate}")
1689
+ }
1690
+ (VecAluOpRRR::VfsgnjnVV, vs2, vs1) if vs2 == vs1 => {
1691
+ format!("vfneg.v {vd_s},{vs2_s}{mask} {vstate}")
1692
+ }
1693
+ (VecAluOpRRR::VfsgnjxVV, vs2, vs1) if vs2 == vs1 => {
1694
+ format!("vfabs.v {vd_s},{vs2_s}{mask} {vstate}")
1695
+ }
1696
+ (VecAluOpRRR::VmnandMM, vs2, vs1) if vs2 == vs1 => {
1697
+ format!("vmnot.m {vd_s},{vs2_s}{mask} {vstate}")
1698
+ }
1699
+ _ => format!("{op} {vd_s},{vs2_s},{vs1_s}{mask} {vstate}"),
1700
+ }
1701
+ }
1702
+ &Inst::VecAluRRImm5 {
1703
+ op,
1704
+ vd,
1705
+ imm,
1706
+ vs2,
1707
+ ref mask,
1708
+ ref vstate,
1709
+ } => {
1710
+ let vs2_s = format_reg(vs2, allocs);
1711
+ let vd_s = format_reg(vd.to_reg(), allocs);
1712
+ let mask = format_mask(mask, allocs);
1713
+
1714
+ // Some opcodes interpret the immediate as unsigned, lets show the
1715
+ // correct number here.
1716
+ let imm_s = if op.imm_is_unsigned() {
1717
+ format!("{}", imm.bits())
1718
+ } else {
1719
+ format!("{}", imm)
1720
+ };
1721
+
1722
+ match (op, imm) {
1723
+ (VecAluOpRRImm5::VxorVI, imm) if imm == Imm5::maybe_from_i8(-1).unwrap() => {
1724
+ format!("vnot.v {vd_s},{vs2_s}{mask} {vstate}")
1725
+ }
1726
+ _ => format!("{op} {vd_s},{vs2_s},{imm_s}{mask} {vstate}"),
1727
+ }
1728
+ }
1729
+ &Inst::VecAluRR {
1730
+ op,
1731
+ vd,
1732
+ vs,
1733
+ ref mask,
1734
+ ref vstate,
1735
+ } => {
1736
+ let vs_s = format_reg(vs, allocs);
1737
+ let vd_s = format_reg(vd.to_reg(), allocs);
1738
+ let mask = format_mask(mask, allocs);
1739
+
1740
+ format!("{op} {vd_s},{vs_s}{mask} {vstate}")
1741
+ }
1742
+ &Inst::VecAluRImm5 {
1743
+ op,
1744
+ vd,
1745
+ imm,
1746
+ ref mask,
1747
+ ref vstate,
1748
+ } => {
1749
+ let vd_s = format_reg(vd.to_reg(), allocs);
1750
+ let mask = format_mask(mask, allocs);
1751
+
1752
+ format!("{op} {vd_s},{imm}{mask} {vstate}")
1753
+ }
1754
+ &Inst::VecSetState { rd, ref vstate } => {
1755
+ let rd_s = format_reg(rd.to_reg(), allocs);
1756
+ assert!(vstate.avl.is_static());
1757
+ format!("vsetivli {}, {}, {}", rd_s, vstate.avl, vstate.vtype)
1758
+ }
1759
+ Inst::VecLoad {
1760
+ eew,
1761
+ to,
1762
+ from,
1763
+ ref mask,
1764
+ ref vstate,
1765
+ ..
1766
+ } => {
1767
+ let base = format_vec_amode(from, allocs);
1768
+ let vd = format_reg(to.to_reg(), allocs);
1769
+ let mask = format_mask(mask, allocs);
1770
+
1771
+ format!("vl{eew}.v {vd},{base}{mask} {vstate}")
1772
+ }
1773
+ Inst::VecStore {
1774
+ eew,
1775
+ to,
1776
+ from,
1777
+ ref mask,
1778
+ ref vstate,
1779
+ ..
1780
+ } => {
1781
+ let dst = format_vec_amode(to, allocs);
1782
+ let vs3 = format_reg(*from, allocs);
1783
+ let mask = format_mask(mask, allocs);
1784
+
1785
+ format!("vs{eew}.v {vs3},{dst}{mask} {vstate}")
1786
+ }
1787
+ }
1788
+ }
1789
+ }
1790
+
1791
+ /// Different forms of label references for different instruction formats.
1792
+ #[derive(Clone, Copy, Debug, PartialEq, Eq)]
1793
+ pub enum LabelUse {
1794
+ /// 20-bit branch offset (unconditional branches). PC-rel, offset is
1795
+ /// imm << 1. Immediate is 20 signed bits. Use in Jal instructions.
1796
+ Jal20,
1797
+
1798
+ /// The unconditional jump instructions all use PC-relative
1799
+ /// addressing to help support position independent code. The JALR
1800
+ /// instruction was defined to enable a two-instruction sequence to
1801
+ /// jump anywhere in a 32-bit absolute address range. A LUI
1802
+ /// instruction can first load rs1 with the upper 20 bits of a
1803
+ /// target address, then JALR can add in the lower bits. Similarly,
1804
+ /// AUIPC then JALR can jump anywhere in a 32-bit pc-relative
1805
+ /// address range.
1806
+ PCRel32,
1807
+
1808
+ /// All branch instructions use the B-type instruction format. The
1809
+ /// 12-bit B-immediate encodes signed offsets in multiples of 2, and
1810
+ /// is added to the current pc to give the target address. The
1811
+ /// conditional branch range is ±4 KiB.
1812
+ B12,
1813
+
1814
+ /// Equivalent to the `R_RISCV_PCREL_HI20` relocation, Allows setting
1815
+ /// the immediate field of an `auipc` instruction.
1816
+ PCRelHi20,
1817
+
1818
+ /// Similar to the `R_RISCV_PCREL_LO12_I` relocation but pointing to
1819
+ /// the final address, instead of the `PCREL_HI20` label. Allows setting
1820
+ /// the immediate field of I Type instructions such as `addi` or `lw`.
1821
+ ///
1822
+ /// Since we currently don't support offsets in labels, this relocation has
1823
+ /// an implicit offset of 4.
1824
+ PCRelLo12I,
1825
+
1826
+ /// 11-bit PC-relative jump offset. Equivalent to the `RVC_JUMP` relocation
1827
+ RVCJump,
1828
+ }
1829
+
1830
+ impl MachInstLabelUse for LabelUse {
1831
+ /// Alignment for veneer code. Every Riscv64 instruction must be
1832
+ /// 4-byte-aligned.
1833
+ const ALIGN: CodeOffset = 4;
1834
+
1835
+ /// Maximum PC-relative range (positive), inclusive.
1836
+ fn max_pos_range(self) -> CodeOffset {
1837
+ match self {
1838
+ LabelUse::Jal20 => ((1 << 19) - 1) * 2,
1839
+ LabelUse::PCRelLo12I | LabelUse::PCRelHi20 | LabelUse::PCRel32 => {
1840
+ Inst::imm_max() as CodeOffset
1841
+ }
1842
+ LabelUse::B12 => ((1 << 11) - 1) * 2,
1843
+ LabelUse::RVCJump => ((1 << 10) - 1) * 2,
1844
+ }
1845
+ }
1846
+
1847
+ /// Maximum PC-relative range (negative).
1848
+ fn max_neg_range(self) -> CodeOffset {
1849
+ match self {
1850
+ LabelUse::PCRel32 => Inst::imm_min().abs() as CodeOffset,
1851
+ _ => self.max_pos_range() + 2,
1852
+ }
1853
+ }
1854
+
1855
+ /// Size of window into code needed to do the patch.
1856
+ fn patch_size(self) -> CodeOffset {
1857
+ match self {
1858
+ LabelUse::RVCJump => 2,
1859
+ LabelUse::Jal20 | LabelUse::B12 | LabelUse::PCRelHi20 | LabelUse::PCRelLo12I => 4,
1860
+ LabelUse::PCRel32 => 8,
1861
+ }
1862
+ }
1863
+
1864
+ /// Perform the patch.
1865
+ fn patch(self, buffer: &mut [u8], use_offset: CodeOffset, label_offset: CodeOffset) {
1866
+ assert!(use_offset % 2 == 0);
1867
+ assert!(label_offset % 2 == 0);
1868
+ let offset = (label_offset as i64) - (use_offset as i64);
1869
+
1870
+ // re-check range
1871
+ assert!(
1872
+ offset >= -(self.max_neg_range() as i64) && offset <= (self.max_pos_range() as i64),
1873
+ "{:?} offset '{}' use_offset:'{}' label_offset:'{}' must not exceed max range.",
1874
+ self,
1875
+ offset,
1876
+ use_offset,
1877
+ label_offset,
1878
+ );
1879
+ self.patch_raw_offset(buffer, offset);
1880
+ }
1881
+
1882
+ /// Is a veneer supported for this label reference type?
1883
+ fn supports_veneer(self) -> bool {
1884
+ match self {
1885
+ Self::Jal20 | Self::B12 | Self::RVCJump => true,
1886
+ _ => false,
1887
+ }
1888
+ }
1889
+
1890
+ /// How large is the veneer, if supported?
1891
+ fn veneer_size(self) -> CodeOffset {
1892
+ match self {
1893
+ Self::B12 | Self::Jal20 | Self::RVCJump => 8,
1894
+ _ => unreachable!(),
1895
+ }
1896
+ }
1897
+
1898
+ fn worst_case_veneer_size() -> CodeOffset {
1899
+ 8
1900
+ }
1901
+
1902
+ /// Generate a veneer into the buffer, given that this veneer is at `veneer_offset`, and return
1903
+ /// an offset and label-use for the veneer's use of the original label.
1904
+ fn generate_veneer(
1905
+ self,
1906
+ buffer: &mut [u8],
1907
+ veneer_offset: CodeOffset,
1908
+ ) -> (CodeOffset, LabelUse) {
1909
+ let base = writable_spilltmp_reg();
1910
+ {
1911
+ let x = enc_auipc(base, Imm20::ZERO).to_le_bytes();
1912
+ buffer[0] = x[0];
1913
+ buffer[1] = x[1];
1914
+ buffer[2] = x[2];
1915
+ buffer[3] = x[3];
1916
+ }
1917
+ {
1918
+ let x = enc_jalr(writable_zero_reg(), base.to_reg(), Imm12::ZERO).to_le_bytes();
1919
+ buffer[4] = x[0];
1920
+ buffer[5] = x[1];
1921
+ buffer[6] = x[2];
1922
+ buffer[7] = x[3];
1923
+ }
1924
+ (veneer_offset, Self::PCRel32)
1925
+ }
1926
+
1927
+ fn from_reloc(reloc: Reloc, addend: Addend) -> Option<LabelUse> {
1928
+ match (reloc, addend) {
1929
+ (Reloc::RiscvCallPlt, _) => Some(Self::PCRel32),
1930
+ _ => None,
1931
+ }
1932
+ }
1933
+ }
1934
+
1935
+ impl LabelUse {
1936
+ #[allow(dead_code)] // in case it's needed in the future
1937
+ fn offset_in_range(self, offset: i64) -> bool {
1938
+ let min = -(self.max_neg_range() as i64);
1939
+ let max = self.max_pos_range() as i64;
1940
+ offset >= min && offset <= max
1941
+ }
1942
+
1943
+ fn patch_raw_offset(self, buffer: &mut [u8], offset: i64) {
1944
+ let insn = match self {
1945
+ LabelUse::RVCJump => u16::from_le_bytes(buffer[..2].try_into().unwrap()) as u32,
1946
+ _ => u32::from_le_bytes(buffer[..4].try_into().unwrap()),
1947
+ };
1948
+
1949
+ match self {
1950
+ LabelUse::Jal20 => {
1951
+ let offset = offset as u32;
1952
+ let v = ((offset >> 12 & 0b1111_1111) << 12)
1953
+ | ((offset >> 11 & 0b1) << 20)
1954
+ | ((offset >> 1 & 0b11_1111_1111) << 21)
1955
+ | ((offset >> 20 & 0b1) << 31);
1956
+ buffer[0..4].clone_from_slice(&u32::to_le_bytes(insn | v));
1957
+ }
1958
+ LabelUse::PCRel32 => {
1959
+ let insn2 = u32::from_le_bytes([buffer[4], buffer[5], buffer[6], buffer[7]]);
1960
+ Inst::generate_imm(offset as u64)
1961
+ .map(|(imm20, imm12)| {
1962
+ // Encode the OR-ed-in value with zero_reg(). The
1963
+ // register parameter must be in the original
1964
+ // encoded instruction and or'ing in zeroes does not
1965
+ // change it.
1966
+ buffer[0..4].clone_from_slice(&u32::to_le_bytes(
1967
+ insn | enc_auipc(writable_zero_reg(), imm20),
1968
+ ));
1969
+ buffer[4..8].clone_from_slice(&u32::to_le_bytes(
1970
+ insn2 | enc_jalr(writable_zero_reg(), zero_reg(), imm12),
1971
+ ));
1972
+ })
1973
+ // expect make sure we handled.
1974
+ .expect("we have check the range before,this is a compiler error.");
1975
+ }
1976
+
1977
+ LabelUse::B12 => {
1978
+ let offset = offset as u32;
1979
+ let v = ((offset >> 11 & 0b1) << 7)
1980
+ | ((offset >> 1 & 0b1111) << 8)
1981
+ | ((offset >> 5 & 0b11_1111) << 25)
1982
+ | ((offset >> 12 & 0b1) << 31);
1983
+ buffer[0..4].clone_from_slice(&u32::to_le_bytes(insn | v));
1984
+ }
1985
+
1986
+ LabelUse::PCRelHi20 => {
1987
+ // See https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#pc-relative-symbol-addresses
1988
+ //
1989
+ // We need to add 0x800 to ensure that we land at the next page as soon as it goes out of range for the
1990
+ // Lo12 relocation. That relocation is signed and has a maximum range of -2048..2047. So when we get an
1991
+ // offset of 2048, we need to land at the next page and subtract instead.
1992
+ let offset = offset as u32;
1993
+ let hi20 = offset.wrapping_add(0x800) >> 12;
1994
+ let insn = (insn & 0xFFF) | (hi20 << 12);
1995
+ buffer[0..4].clone_from_slice(&u32::to_le_bytes(insn));
1996
+ }
1997
+
1998
+ LabelUse::PCRelLo12I => {
1999
+ // `offset` is the offset from the current instruction to the target address.
2000
+ //
2001
+ // However we are trying to compute the offset to the target address from the previous instruction.
2002
+ // The previous instruction should be the one that contains the PCRelHi20 relocation and
2003
+ // stores/references the program counter (`auipc` usually).
2004
+ //
2005
+ // Since we are trying to compute the offset from the previous instruction, we can
2006
+ // represent it as offset = target_address - (current_instruction_address - 4)
2007
+ // which is equivalent to offset = target_address - current_instruction_address + 4.
2008
+ //
2009
+ // Thus we need to add 4 to the offset here.
2010
+ let lo12 = (offset + 4) as u32 & 0xFFF;
2011
+ let insn = (insn & 0xFFFFF) | (lo12 << 20);
2012
+ buffer[0..4].clone_from_slice(&u32::to_le_bytes(insn));
2013
+ }
2014
+ LabelUse::RVCJump => {
2015
+ debug_assert!(offset & 1 == 0);
2016
+
2017
+ // We currently only support this for the C.J operation, so assert that is the opcode in
2018
+ // the buffer.
2019
+ debug_assert_eq!(insn & 0xFFFF, 0xA001);
2020
+
2021
+ buffer[0..2].clone_from_slice(&u16::to_le_bytes(encode_cj_type(
2022
+ CjOp::CJ,
2023
+ Imm12::from_i16(i16::try_from(offset).unwrap()),
2024
+ )));
2025
+ }
2026
+ }
2027
+ }
2028
+ }
2029
+
2030
+ #[cfg(test)]
2031
+ mod test {
2032
+ use super::*;
2033
+ #[test]
2034
+ fn label_use_max_range() {
2035
+ assert!(LabelUse::B12.max_neg_range() == LabelUse::B12.max_pos_range() + 2);
2036
+ assert!(LabelUse::Jal20.max_neg_range() == LabelUse::Jal20.max_pos_range() + 2);
2037
+ assert!(LabelUse::PCRel32.max_pos_range() == (Inst::imm_max() as CodeOffset));
2038
+ assert!(LabelUse::PCRel32.max_neg_range() == (Inst::imm_min().abs() as CodeOffset));
2039
+ assert!(LabelUse::B12.max_pos_range() == ((1 << 11) - 1) * 2);
2040
+ }
2041
+ }