wasmtime 15.0.1 → 16.0.0

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Files changed (1212) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +83 -103
  3. data/ext/Cargo.toml +6 -6
  4. data/ext/cargo-vendor/cranelift-bforest-0.103.0/.cargo-checksum.json +1 -0
  5. data/ext/cargo-vendor/cranelift-bforest-0.103.0/Cargo.toml +40 -0
  6. data/ext/cargo-vendor/cranelift-bforest-0.103.0/src/lib.rs +183 -0
  7. data/ext/cargo-vendor/cranelift-codegen-0.103.0/.cargo-checksum.json +1 -0
  8. data/ext/cargo-vendor/cranelift-codegen-0.103.0/Cargo.toml +175 -0
  9. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/binemit/mod.rs +171 -0
  10. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/egraph/cost.rs +171 -0
  11. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/egraph/elaborate.rs +750 -0
  12. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/egraph.rs +703 -0
  13. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/ir/dfg.rs +1735 -0
  14. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/ir/pcc.rs +1682 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isa/aarch64/lower/isle.rs +874 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isa/riscv64/inst/mod.rs +2041 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isa/riscv64/inst.isle +2928 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isa/riscv64/lower.isle +2864 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isa/s390x/lower/isle.rs +1029 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isa/x64/lower/isle.rs +1064 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isa/x64/pcc.rs +916 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isle_prelude.rs +977 -0
  23. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/lib.rs +106 -0
  24. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/machinst/isle.rs +896 -0
  25. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/opts/arithmetic.isle +152 -0
  26. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/opts/cprop.isle +237 -0
  27. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/opts/icmp.isle +199 -0
  28. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/opts/selects.isle +76 -0
  29. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/opts.rs +172 -0
  30. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/prelude.isle +649 -0
  31. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/timing.rs +297 -0
  32. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/unionfind.rs +75 -0
  33. data/ext/cargo-vendor/cranelift-codegen-meta-0.103.0/.cargo-checksum.json +1 -0
  34. data/ext/cargo-vendor/cranelift-codegen-meta-0.103.0/Cargo.toml +35 -0
  35. data/ext/cargo-vendor/cranelift-codegen-shared-0.103.0/.cargo-checksum.json +1 -0
  36. data/ext/cargo-vendor/cranelift-codegen-shared-0.103.0/Cargo.toml +22 -0
  37. data/ext/cargo-vendor/cranelift-codegen-shared-0.103.0/src/lib.rs +10 -0
  38. data/ext/cargo-vendor/cranelift-control-0.103.0/.cargo-checksum.json +1 -0
  39. data/ext/cargo-vendor/cranelift-control-0.103.0/Cargo.toml +30 -0
  40. data/ext/cargo-vendor/cranelift-entity-0.103.0/.cargo-checksum.json +1 -0
  41. data/ext/cargo-vendor/cranelift-entity-0.103.0/Cargo.toml +50 -0
  42. data/ext/cargo-vendor/cranelift-entity-0.103.0/src/lib.rs +317 -0
  43. data/ext/cargo-vendor/cranelift-entity-0.103.0/src/primary.rs +516 -0
  44. data/ext/cargo-vendor/cranelift-entity-0.103.0/src/unsigned.rs +71 -0
  45. data/ext/cargo-vendor/cranelift-frontend-0.103.0/.cargo-checksum.json +1 -0
  46. data/ext/cargo-vendor/cranelift-frontend-0.103.0/Cargo.toml +68 -0
  47. data/ext/cargo-vendor/cranelift-frontend-0.103.0/src/lib.rs +189 -0
  48. data/ext/cargo-vendor/cranelift-isle-0.103.0/.cargo-checksum.json +1 -0
  49. data/ext/cargo-vendor/cranelift-isle-0.103.0/Cargo.toml +46 -0
  50. data/ext/cargo-vendor/cranelift-isle-0.103.0/isle_examples/link/multi_constructor_main.rs +88 -0
  51. data/ext/cargo-vendor/cranelift-isle-0.103.0/isle_examples/link/multi_extractor_main.rs +63 -0
  52. data/ext/cargo-vendor/cranelift-isle-0.103.0/src/codegen.rs +886 -0
  53. data/ext/cargo-vendor/cranelift-native-0.103.0/.cargo-checksum.json +1 -0
  54. data/ext/cargo-vendor/cranelift-native-0.103.0/Cargo.toml +43 -0
  55. data/ext/cargo-vendor/cranelift-native-0.103.0/src/lib.rs +184 -0
  56. data/ext/cargo-vendor/cranelift-wasm-0.103.0/.cargo-checksum.json +1 -0
  57. data/ext/cargo-vendor/cranelift-wasm-0.103.0/Cargo.toml +106 -0
  58. data/ext/cargo-vendor/cranelift-wasm-0.103.0/src/environ/dummy.rs +953 -0
  59. data/ext/cargo-vendor/cranelift-wasm-0.103.0/src/lib.rs +62 -0
  60. data/ext/cargo-vendor/cranelift-wasm-0.103.0/src/translation_utils.rs +89 -0
  61. data/ext/cargo-vendor/wasi-cap-std-sync-16.0.0/.cargo-checksum.json +1 -0
  62. data/ext/cargo-vendor/wasi-cap-std-sync-16.0.0/Cargo.toml +102 -0
  63. data/ext/cargo-vendor/wasi-common-16.0.0/.cargo-checksum.json +1 -0
  64. data/ext/cargo-vendor/wasi-common-16.0.0/Cargo.toml +131 -0
  65. data/ext/cargo-vendor/wasi-common-16.0.0/src/lib.rs +76 -0
  66. data/ext/cargo-vendor/wasi-common-16.0.0/src/snapshots/preview_1.rs +1492 -0
  67. data/ext/cargo-vendor/wasmtime-16.0.0/.cargo-checksum.json +1 -0
  68. data/ext/cargo-vendor/wasmtime-16.0.0/Cargo.toml +211 -0
  69. data/ext/cargo-vendor/wasmtime-16.0.0/src/compiler.rs +682 -0
  70. data/ext/cargo-vendor/wasmtime-16.0.0/src/component/component.rs +505 -0
  71. data/ext/cargo-vendor/wasmtime-16.0.0/src/component/func/typed.rs +2400 -0
  72. data/ext/cargo-vendor/wasmtime-16.0.0/src/config.rs +2422 -0
  73. data/ext/cargo-vendor/wasmtime-16.0.0/src/func.rs +2391 -0
  74. data/ext/cargo-vendor/wasmtime-16.0.0/src/lib.rs +520 -0
  75. data/ext/cargo-vendor/wasmtime-16.0.0/src/memory.rs +998 -0
  76. data/ext/cargo-vendor/wasmtime-16.0.0/src/module.rs +1370 -0
  77. data/ext/cargo-vendor/wasmtime-16.0.0/src/stack.rs +73 -0
  78. data/ext/cargo-vendor/wasmtime-16.0.0/src/v128.rs +122 -0
  79. data/ext/cargo-vendor/wasmtime-asm-macros-16.0.0/.cargo-checksum.json +1 -0
  80. data/ext/cargo-vendor/wasmtime-asm-macros-16.0.0/Cargo.toml +22 -0
  81. data/ext/cargo-vendor/wasmtime-cache-16.0.0/.cargo-checksum.json +1 -0
  82. data/ext/cargo-vendor/wasmtime-cache-16.0.0/Cargo.toml +81 -0
  83. data/ext/cargo-vendor/wasmtime-cache-16.0.0/src/lib.rs +235 -0
  84. data/ext/cargo-vendor/wasmtime-cache-16.0.0/src/worker.rs +890 -0
  85. data/ext/cargo-vendor/wasmtime-component-macro-16.0.0/.cargo-checksum.json +1 -0
  86. data/ext/cargo-vendor/wasmtime-component-macro-16.0.0/Cargo.toml +67 -0
  87. data/ext/cargo-vendor/wasmtime-component-util-16.0.0/.cargo-checksum.json +1 -0
  88. data/ext/cargo-vendor/wasmtime-component-util-16.0.0/Cargo.toml +25 -0
  89. data/ext/cargo-vendor/wasmtime-cranelift-16.0.0/.cargo-checksum.json +1 -0
  90. data/ext/cargo-vendor/wasmtime-cranelift-16.0.0/Cargo.toml +112 -0
  91. data/ext/cargo-vendor/wasmtime-cranelift-16.0.0/src/compiler/component.rs +959 -0
  92. data/ext/cargo-vendor/wasmtime-cranelift-16.0.0/src/compiler.rs +1317 -0
  93. data/ext/cargo-vendor/wasmtime-cranelift-16.0.0/src/debug/transform/expression.rs +1252 -0
  94. data/ext/cargo-vendor/wasmtime-cranelift-16.0.0/src/debug/transform/simulate.rs +410 -0
  95. data/ext/cargo-vendor/wasmtime-cranelift-16.0.0/src/debug.rs +18 -0
  96. data/ext/cargo-vendor/wasmtime-cranelift-16.0.0/src/func_environ.rs +2750 -0
  97. data/ext/cargo-vendor/wasmtime-cranelift-shared-16.0.0/.cargo-checksum.json +1 -0
  98. data/ext/cargo-vendor/wasmtime-cranelift-shared-16.0.0/Cargo.toml +71 -0
  99. data/ext/cargo-vendor/wasmtime-environ-16.0.0/.cargo-checksum.json +1 -0
  100. data/ext/cargo-vendor/wasmtime-environ-16.0.0/Cargo.lock +660 -0
  101. data/ext/cargo-vendor/wasmtime-environ-16.0.0/Cargo.toml +125 -0
  102. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/compilation.rs +402 -0
  103. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/component/compiler.rs +47 -0
  104. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/component/translate.rs +951 -0
  105. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/component/types.rs +1876 -0
  106. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/lib.rs +59 -0
  107. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/module.rs +1075 -0
  108. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/module_environ.rs +892 -0
  109. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/module_types.rs +120 -0
  110. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/scopevec.rs +78 -0
  111. data/ext/cargo-vendor/wasmtime-fiber-16.0.0/.cargo-checksum.json +1 -0
  112. data/ext/cargo-vendor/wasmtime-fiber-16.0.0/Cargo.toml +63 -0
  113. data/ext/cargo-vendor/wasmtime-fiber-16.0.0/src/lib.rs +328 -0
  114. data/ext/cargo-vendor/wasmtime-fiber-16.0.0/src/unix.rs +265 -0
  115. data/ext/cargo-vendor/wasmtime-fiber-16.0.0/src/windows.c +9 -0
  116. data/ext/cargo-vendor/wasmtime-jit-16.0.0/.cargo-checksum.json +1 -0
  117. data/ext/cargo-vendor/wasmtime-jit-16.0.0/Cargo.toml +125 -0
  118. data/ext/cargo-vendor/wasmtime-jit-16.0.0/src/code_memory.rs +319 -0
  119. data/ext/cargo-vendor/wasmtime-jit-16.0.0/src/instantiate.rs +772 -0
  120. data/ext/cargo-vendor/wasmtime-jit-16.0.0/src/lib.rs +21 -0
  121. data/ext/cargo-vendor/wasmtime-jit-debug-16.0.0/.cargo-checksum.json +1 -0
  122. data/ext/cargo-vendor/wasmtime-jit-debug-16.0.0/Cargo.toml +67 -0
  123. data/ext/cargo-vendor/wasmtime-jit-icache-coherence-16.0.0/.cargo-checksum.json +1 -0
  124. data/ext/cargo-vendor/wasmtime-jit-icache-coherence-16.0.0/Cargo.toml +46 -0
  125. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/.cargo-checksum.json +1 -0
  126. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/Cargo.toml +139 -0
  127. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/build.rs +28 -0
  128. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/proptest-regressions/instance/allocator/pooling/memory_pool.txt +9 -0
  129. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/arch/aarch64.rs +120 -0
  130. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/arch/mod.rs +32 -0
  131. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/arch/riscv64.rs +88 -0
  132. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/arch/s390x.rs +61 -0
  133. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/arch/x86_64.rs +106 -0
  134. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/cow.rs +888 -0
  135. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/helpers.c +113 -0
  136. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/instance/allocator/pooling/memory_pool.rs +1005 -0
  137. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/instance/allocator/pooling/stack_pool.rs +242 -0
  138. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/instance/allocator/pooling/table_pool.rs +227 -0
  139. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/instance/allocator/pooling.rs +698 -0
  140. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/lib.rs +264 -0
  141. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/libcalls.rs +776 -0
  142. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/mmap.rs +214 -0
  143. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/mpk/enabled.rs +204 -0
  144. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/mpk/pkru.rs +102 -0
  145. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/miri/mod.rs +10 -0
  146. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/miri/traphandlers.rs +42 -0
  147. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/miri/unwind.rs +17 -0
  148. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/miri/vm.rs +63 -0
  149. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/mod.rs +30 -0
  150. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/unix/machports.rs +487 -0
  151. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/unix/macos_traphandlers.rs +28 -0
  152. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/unix/mod.rs +21 -0
  153. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/unix/signals.rs +402 -0
  154. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/unix/unwind.rs +91 -0
  155. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/unix/vm.rs +208 -0
  156. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/windows/mod.rs +6 -0
  157. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/windows/traphandlers.rs +105 -0
  158. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/windows/unwind.rs +46 -0
  159. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/windows/vm.rs +79 -0
  160. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/traphandlers/backtrace.rs +265 -0
  161. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/traphandlers.rs +733 -0
  162. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/vmcontext.rs +1197 -0
  163. data/ext/cargo-vendor/wasmtime-types-16.0.0/.cargo-checksum.json +1 -0
  164. data/ext/cargo-vendor/wasmtime-types-16.0.0/Cargo.toml +36 -0
  165. data/ext/cargo-vendor/wasmtime-types-16.0.0/src/lib.rs +504 -0
  166. data/ext/cargo-vendor/wasmtime-versioned-export-macros-16.0.0/.cargo-checksum.json +1 -0
  167. data/ext/cargo-vendor/wasmtime-versioned-export-macros-16.0.0/Cargo.toml +32 -0
  168. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/.cargo-checksum.json +1 -0
  169. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/Cargo.toml +261 -0
  170. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/lib.rs +137 -0
  171. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/host/io.rs +368 -0
  172. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/host/network.rs +570 -0
  173. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/host/tcp.rs +632 -0
  174. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/host/udp.rs +550 -0
  175. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/mod.rs +328 -0
  176. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/preview0.rs +870 -0
  177. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/preview1.rs +2348 -0
  178. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/stdio.rs +259 -0
  179. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/stream.rs +182 -0
  180. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/table.rs +337 -0
  181. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/tests/all/api.rs +218 -0
  182. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/tests/all/async_.rs +360 -0
  183. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/tests/all/main.rs +113 -0
  184. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/tests/all/preview1.rs +239 -0
  185. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/tests/all/sync.rs +299 -0
  186. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/tests/process_stdin.rs +165 -0
  187. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/wit/command-extended.wit +6 -0
  188. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/wit/deps/cli/command.wit +7 -0
  189. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/wit/deps/cli/imports.wit +20 -0
  190. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/wit/deps/http/proxy.wit +32 -0
  191. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/wit/deps/http/types.wit +570 -0
  192. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/wit/test.wit +22 -0
  193. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/witx/preview0/typenames.witx +746 -0
  194. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/witx/preview0/wasi_unstable.witx +513 -0
  195. data/ext/cargo-vendor/wasmtime-winch-16.0.0/.cargo-checksum.json +1 -0
  196. data/ext/cargo-vendor/wasmtime-winch-16.0.0/Cargo.toml +77 -0
  197. data/ext/cargo-vendor/wasmtime-winch-16.0.0/src/compiler.rs +243 -0
  198. data/ext/cargo-vendor/wasmtime-wit-bindgen-16.0.0/.cargo-checksum.json +1 -0
  199. data/ext/cargo-vendor/wasmtime-wit-bindgen-16.0.0/Cargo.toml +41 -0
  200. data/ext/cargo-vendor/wasmtime-wmemcheck-16.0.0/.cargo-checksum.json +1 -0
  201. data/ext/cargo-vendor/wasmtime-wmemcheck-16.0.0/Cargo.toml +29 -0
  202. data/ext/cargo-vendor/wiggle-16.0.0/.cargo-checksum.json +1 -0
  203. data/ext/cargo-vendor/wiggle-16.0.0/Cargo.toml +115 -0
  204. data/ext/cargo-vendor/wiggle-16.0.0/src/lib.rs +1198 -0
  205. data/ext/cargo-vendor/wiggle-generate-16.0.0/.cargo-checksum.json +1 -0
  206. data/ext/cargo-vendor/wiggle-generate-16.0.0/Cargo.toml +65 -0
  207. data/ext/cargo-vendor/wiggle-generate-16.0.0/src/types/handle.rs +84 -0
  208. data/ext/cargo-vendor/wiggle-generate-16.0.0/src/types/record.rs +132 -0
  209. data/ext/cargo-vendor/wiggle-generate-16.0.0/src/types/variant.rs +191 -0
  210. data/ext/cargo-vendor/wiggle-macro-16.0.0/.cargo-checksum.json +1 -0
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  610. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/aarch64/mod.rs +0 -0
  611. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/aarch64/pcc.rs +0 -0
  612. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/aarch64/settings.rs +0 -0
  613. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/call_conv.rs +0 -0
  614. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/mod.rs +0 -0
  615. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/abi.rs +0 -0
  616. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/args.rs +0 -0
  617. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/emit.rs +0 -0
  618. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/emit_tests.rs +0 -0
  619. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/encode.rs +0 -0
  620. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/imms.rs +0 -0
  621. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/regs.rs +0 -0
  622. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/unwind/systemv.rs +0 -0
  623. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/unwind.rs +0 -0
  624. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/vector.rs +0 -0
  625. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst_vector.isle +0 -0
  626. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/lower/isle/generated_code.rs +0 -0
  627. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/lower/isle.rs +0 -0
  628. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/lower.rs +0 -0
  629. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/mod.rs +0 -0
  630. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/settings.rs +0 -0
  631. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/abi.rs +0 -0
  632. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst/args.rs +0 -0
  633. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst/emit.rs +0 -0
  634. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst/emit_tests.rs +0 -0
  635. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst/imms.rs +0 -0
  636. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst/mod.rs +0 -0
  637. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst/regs.rs +0 -0
  638. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst/unwind/systemv.rs +0 -0
  639. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst/unwind.rs +0 -0
  640. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst.isle +0 -0
  641. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/lower/isle/generated_code.rs +0 -0
  642. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/lower.isle +0 -0
  643. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/lower.rs +0 -0
  644. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/mod.rs +0 -0
  645. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/settings.rs +0 -0
  646. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/unwind/systemv.rs +0 -0
  647. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/unwind/winx64.rs +0 -0
  648. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/unwind.rs +0 -0
  649. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/abi.rs +0 -0
  650. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/encoding/evex.rs +0 -0
  651. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/encoding/mod.rs +0 -0
  652. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/encoding/rex.rs +0 -0
  653. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/encoding/vex.rs +0 -0
  654. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/args.rs +0 -0
  655. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/emit.rs +0 -0
  656. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/emit_state.rs +0 -0
  657. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/emit_tests.rs +0 -0
  658. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/mod.rs +0 -0
  659. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/regs.rs +0 -0
  660. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/unwind/systemv.rs +0 -0
  661. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/unwind/winx64.rs +0 -0
  662. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/unwind.rs +0 -0
  663. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst.isle +0 -0
  664. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/lower/isle/generated_code.rs +0 -0
  665. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/lower.isle +0 -0
  666. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/lower.rs +0 -0
  667. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/mod.rs +0 -0
  668. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/settings.rs +0 -0
  669. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/iterators.rs +0 -0
  670. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/legalizer/globalvalue.rs +0 -0
  671. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/legalizer/mod.rs +0 -0
  672. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/legalizer/table.rs +0 -0
  673. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/loop_analysis.rs +0 -0
  674. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/abi.rs +0 -0
  675. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/blockorder.rs +0 -0
  676. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/buffer.rs +0 -0
  677. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/compile.rs +0 -0
  678. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/helpers.rs +0 -0
  679. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/inst_common.rs +0 -0
  680. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/lower.rs +0 -0
  681. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/mod.rs +0 -0
  682. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/pcc.rs +0 -0
  683. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/reg.rs +0 -0
  684. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/valueregs.rs +0 -0
  685. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/vcode.rs +0 -0
  686. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/nan_canonicalization.rs +0 -0
  687. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/opts/README.md +0 -0
  688. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/opts/bitops.isle +0 -0
  689. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/opts/extends.isle +0 -0
  690. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/opts/generated_code.rs +0 -0
  691. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/opts/remat.isle +0 -0
  692. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/opts/shifts.isle +0 -0
  693. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/opts/vector.isle +0 -0
  694. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/prelude_lower.isle +0 -0
  695. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/prelude_opt.isle +0 -0
  696. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/print_errors.rs +0 -0
  697. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/remove_constant_phis.rs +0 -0
  698. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/result.rs +0 -0
  699. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/scoped_hash_map.rs +0 -0
  700. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/settings.rs +0 -0
  701. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/souper_harvest.rs +0 -0
  702. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/unreachable_code.rs +0 -0
  703. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/value_label.rs +0 -0
  704. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/verifier/mod.rs +0 -0
  705. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/write.rs +0 -0
  706. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/LICENSE +0 -0
  707. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/README.md +0 -0
  708. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/cdsl/formats.rs +0 -0
  709. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/cdsl/instructions.rs +0 -0
  710. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/cdsl/isa.rs +0 -0
  711. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/cdsl/mod.rs +0 -0
  712. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/cdsl/operands.rs +0 -0
  713. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/cdsl/settings.rs +0 -0
  714. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/cdsl/types.rs +0 -0
  715. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/cdsl/typevar.rs +0 -0
  716. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/constant_hash.rs +0 -0
  717. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/error.rs +0 -0
  718. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/gen_inst.rs +0 -0
  719. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/gen_settings.rs +0 -0
  720. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/gen_types.rs +0 -0
  721. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/isa/arm64.rs +0 -0
  722. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/isa/mod.rs +0 -0
  723. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/isa/riscv64.rs +0 -0
  724. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/isa/s390x.rs +0 -0
  725. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/isa/x86.rs +0 -0
  726. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/lib.rs +0 -0
  727. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/shared/entities.rs +0 -0
  728. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/shared/formats.rs +0 -0
  729. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/shared/immediates.rs +0 -0
  730. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/shared/instructions.rs +0 -0
  731. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/shared/mod.rs +0 -0
  732. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/shared/settings.rs +0 -0
  733. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/shared/types.rs +0 -0
  734. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/srcgen.rs +0 -0
  735. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/unique_table.rs +0 -0
  736. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.102.1 → cranelift-codegen-shared-0.103.0}/LICENSE +0 -0
  737. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.102.1 → cranelift-codegen-shared-0.103.0}/README.md +0 -0
  738. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.102.1 → cranelift-codegen-shared-0.103.0}/src/constant_hash.rs +0 -0
  739. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.102.1 → cranelift-codegen-shared-0.103.0}/src/constants.rs +0 -0
  740. /data/ext/cargo-vendor/{cranelift-control-0.102.1 → cranelift-control-0.103.0}/LICENSE +0 -0
  741. /data/ext/cargo-vendor/{cranelift-control-0.102.1 → cranelift-control-0.103.0}/README.md +0 -0
  742. /data/ext/cargo-vendor/{cranelift-control-0.102.1 → cranelift-control-0.103.0}/src/chaos.rs +0 -0
  743. /data/ext/cargo-vendor/{cranelift-control-0.102.1 → cranelift-control-0.103.0}/src/lib.rs +0 -0
  744. /data/ext/cargo-vendor/{cranelift-control-0.102.1 → cranelift-control-0.103.0}/src/zero_sized.rs +0 -0
  745. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/LICENSE +0 -0
  746. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/README.md +0 -0
  747. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/src/boxed_slice.rs +0 -0
  748. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/src/iter.rs +0 -0
  749. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/src/keys.rs +0 -0
  750. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/src/list.rs +0 -0
  751. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/src/map.rs +0 -0
  752. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/src/packed_option.rs +0 -0
  753. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/src/set.rs +0 -0
  754. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/src/sparse.rs +0 -0
  755. /data/ext/cargo-vendor/{cranelift-frontend-0.102.1 → cranelift-frontend-0.103.0}/LICENSE +0 -0
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  757. /data/ext/cargo-vendor/{cranelift-frontend-0.102.1 → cranelift-frontend-0.103.0}/src/frontend.rs +0 -0
  758. /data/ext/cargo-vendor/{cranelift-frontend-0.102.1 → cranelift-frontend-0.103.0}/src/ssa.rs +0 -0
  759. /data/ext/cargo-vendor/{cranelift-frontend-0.102.1 → cranelift-frontend-0.103.0}/src/switch.rs +0 -0
  760. /data/ext/cargo-vendor/{cranelift-frontend-0.102.1 → cranelift-frontend-0.103.0}/src/variable.rs +0 -0
  761. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/README.md +0 -0
  762. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/build.rs +0 -0
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  764. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/fail/bound_var_type_mismatch.isle +0 -0
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  766. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/fail/error1.isle +0 -0
  767. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/fail/extra_parens.isle +0 -0
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  769. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/fail/impure_rhs.isle +0 -0
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  771. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/fail/multi_prio.isle +0 -0
  772. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/link/borrows.isle +0 -0
  773. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/link/borrows_main.rs +0 -0
  774. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/link/iflets.isle +0 -0
  775. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/link/iflets_main.rs +0 -0
  776. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/link/multi_constructor.isle +0 -0
  777. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/link/multi_extractor.isle +0 -0
  778. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/link/test.isle +0 -0
  779. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/link/test_main.rs +0 -0
  780. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/pass/bound_var.isle +0 -0
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  784. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/pass/let.isle +0 -0
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  786. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/pass/prio_trie_bug.isle +0 -0
  787. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/pass/test2.isle +0 -0
  788. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/pass/test3.isle +0 -0
  789. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/pass/test4.isle +0 -0
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  795. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/ast.rs +0 -0
  796. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/compile.rs +0 -0
  797. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/error.rs +0 -0
  798. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/lexer.rs +0 -0
  799. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/lib.rs +0 -0
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  801. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/overlap.rs +0 -0
  802. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/parser.rs +0 -0
  803. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/sema.rs +0 -0
  804. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/serialize.rs +0 -0
  805. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/trie_again.rs +0 -0
  806. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/tests/run_tests.rs +0 -0
  807. /data/ext/cargo-vendor/{cranelift-native-0.102.1 → cranelift-native-0.103.0}/LICENSE +0 -0
  808. /data/ext/cargo-vendor/{cranelift-native-0.102.1 → cranelift-native-0.103.0}/README.md +0 -0
  809. /data/ext/cargo-vendor/{cranelift-native-0.102.1 → cranelift-native-0.103.0}/src/riscv.rs +0 -0
  810. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/LICENSE +0 -0
  811. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/README.md +0 -0
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  814. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/src/environ/mod.rs +0 -0
  815. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/src/environ/spec.rs +0 -0
  816. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/src/func_translator.rs +0 -0
  817. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/src/heap.rs +0 -0
  818. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/src/module_translator.rs +0 -0
  819. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/src/sections_translator.rs +0 -0
  820. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/src/state.rs +0 -0
  821. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/tests/wasm_testsuite.rs +0 -0
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  829. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/embenchen_primes.wat +0 -0
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  831. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/fibonacci.wat +0 -0
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  834. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/icall.wat +0 -0
  835. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/if-reachability-translation-0.wat +0 -0
  836. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/if-reachability-translation-1.wat +0 -0
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  843. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/if-unreachable-else-params.wat +0 -0
  844. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/issue-1306-name-section-with-u32-max-function-index.wasm +0 -0
  845. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/memory.wat +0 -0
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  848. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/multi-10.wat +0 -0
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  864. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/nullref.wat +0 -0
  865. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/passive-data.wat +0 -0
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  867. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/pr2559.wat +0 -0
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  869. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/rust_fannkuch.wat +0 -0
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  874. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/unreachable_code.wat +0 -0
  875. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/LICENSE +0 -0
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  877. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/clocks.rs +0 -0
  878. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/dir.rs +0 -0
  879. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/file.rs +0 -0
  880. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/lib.rs +0 -0
  881. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/net.rs +0 -0
  882. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/sched/unix.rs +0 -0
  883. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/sched/windows.rs +0 -0
  884. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/sched.rs +0 -0
  885. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/stdio.rs +0 -0
  886. /data/ext/cargo-vendor/{wasi-common-15.0.1 → wasi-common-16.0.0}/LICENSE +0 -0
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  1050. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/fact/transcode.rs +0 -0
  1051. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/fact/traps.rs +0 -0
  1052. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/fact.rs +0 -0
  1053. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/obj.rs +0 -0
  1054. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/ref_bits.rs +0 -0
  1055. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/stack_map.rs +0 -0
  1056. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/trap_encoding.rs +0 -0
  1057. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/tunables.rs +0 -0
  1058. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/vmoffsets.rs +0 -0
  1059. /data/ext/cargo-vendor/{wasmtime-cranelift-15.0.1 → wasmtime-fiber-16.0.0}/LICENSE +0 -0
  1060. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-fiber-16.0.0}/build.rs +0 -0
  1061. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-fiber-16.0.0}/src/unix/aarch64.rs +0 -0
  1062. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-fiber-16.0.0}/src/unix/arm.rs +0 -0
  1063. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-fiber-16.0.0}/src/unix/riscv64.rs +0 -0
  1064. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-fiber-16.0.0}/src/unix/s390x.S +0 -0
  1065. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-fiber-16.0.0}/src/unix/x86.rs +0 -0
  1066. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-fiber-16.0.0}/src/unix/x86_64.rs +0 -0
  1067. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-fiber-16.0.0}/src/windows.rs +0 -0
  1068. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-jit-16.0.0}/LICENSE +0 -0
  1069. /data/ext/cargo-vendor/{wasmtime-jit-15.0.1 → wasmtime-jit-16.0.0}/src/debug.rs +0 -0
  1070. /data/ext/cargo-vendor/{wasmtime-jit-15.0.1 → wasmtime-jit-16.0.0}/src/demangling.rs +0 -0
  1071. /data/ext/cargo-vendor/{wasmtime-jit-15.0.1 → wasmtime-jit-16.0.0}/src/profiling/jitdump.rs +0 -0
  1072. /data/ext/cargo-vendor/{wasmtime-jit-15.0.1 → wasmtime-jit-16.0.0}/src/profiling/perfmap.rs +0 -0
  1073. /data/ext/cargo-vendor/{wasmtime-jit-15.0.1 → wasmtime-jit-16.0.0}/src/profiling/vtune.rs +0 -0
  1074. /data/ext/cargo-vendor/{wasmtime-jit-15.0.1 → wasmtime-jit-16.0.0}/src/profiling.rs +0 -0
  1075. /data/ext/cargo-vendor/{wasmtime-jit-debug-15.0.1 → wasmtime-jit-debug-16.0.0}/README.md +0 -0
  1076. /data/ext/cargo-vendor/{wasmtime-jit-debug-15.0.1 → wasmtime-jit-debug-16.0.0}/src/gdb_jit_int.rs +0 -0
  1077. /data/ext/cargo-vendor/{wasmtime-jit-debug-15.0.1 → wasmtime-jit-debug-16.0.0}/src/lib.rs +0 -0
  1078. /data/ext/cargo-vendor/{wasmtime-jit-debug-15.0.1 → wasmtime-jit-debug-16.0.0}/src/perf_jitdump.rs +0 -0
  1079. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-15.0.1 → wasmtime-jit-icache-coherence-16.0.0}/src/lib.rs +0 -0
  1080. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-15.0.1 → wasmtime-jit-icache-coherence-16.0.0}/src/libc.rs +0 -0
  1081. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-15.0.1 → wasmtime-jit-icache-coherence-16.0.0}/src/miri.rs +0 -0
  1082. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-15.0.1 → wasmtime-jit-icache-coherence-16.0.0}/src/win.rs +0 -0
  1083. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-runtime-16.0.0}/LICENSE +0 -0
  1084. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1/src/trampolines → wasmtime-runtime-16.0.0/src/arch}/s390x.S +0 -0
  1085. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/component/libcalls.rs +0 -0
  1086. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/component/resources.rs +0 -0
  1087. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/component.rs +0 -0
  1088. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/debug_builtins.rs +0 -0
  1089. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/export.rs +0 -0
  1090. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/externref.rs +0 -0
  1091. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/imports.rs +0 -0
  1092. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/instance/allocator/on_demand.rs +0 -0
  1093. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/instance/allocator/pooling/index_allocator.rs +0 -0
  1094. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/instance/allocator.rs +0 -0
  1095. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/instance.rs +0 -0
  1096. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/memory.rs +0 -0
  1097. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/mmap_vec.rs +0 -0
  1098. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/module_id.rs +0 -0
  1099. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/mpk/disabled.rs +0 -0
  1100. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/mpk/mod.rs +0 -0
  1101. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/mpk/sys.rs +0 -0
  1102. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/parking_spot.rs +0 -0
  1103. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/send_sync_ptr.rs +0 -0
  1104. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/store_box.rs +0 -0
  1105. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1/src/mmap/miri.rs → wasmtime-runtime-16.0.0/src/sys/miri/mmap.rs} +0 -0
  1106. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1/src/mmap/unix.rs → wasmtime-runtime-16.0.0/src/sys/unix/mmap.rs} +0 -0
  1107. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1/src/mmap/windows.rs → wasmtime-runtime-16.0.0/src/sys/windows/mmap.rs} +0 -0
  1108. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/table.rs +0 -0
  1109. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/traphandlers/coredump.rs +0 -0
  1110. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/vmcontext/vm_host_func_context.rs +0 -0
  1111. /data/ext/cargo-vendor/{wasmtime-jit-15.0.1 → wasmtime-types-16.0.0}/LICENSE +0 -0
  1112. /data/ext/cargo-vendor/{wasmtime-types-15.0.1 → wasmtime-types-16.0.0}/src/error.rs +0 -0
  1113. /data/ext/cargo-vendor/{wasmtime-versioned-export-macros-15.0.1 → wasmtime-versioned-export-macros-16.0.0}/src/lib.rs +0 -0
  1114. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-wasi-16.0.0}/LICENSE +0 -0
  1115. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/README.md +0 -0
  1116. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/build.rs +0 -0
  1117. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/clocks/host.rs +0 -0
  1118. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/clocks.rs +0 -0
  1119. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/command.rs +0 -0
  1120. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/ctx.rs +0 -0
  1121. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/error.rs +0 -0
  1122. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/filesystem.rs +0 -0
  1123. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/clocks.rs +0 -0
  1124. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/env.rs +0 -0
  1125. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/exit.rs +0 -0
  1126. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/filesystem/sync.rs +0 -0
  1127. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/filesystem.rs +0 -0
  1128. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/instance_network.rs +0 -0
  1129. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/mod.rs +0 -0
  1130. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/random.rs +0 -0
  1131. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/tcp_create_socket.rs +0 -0
  1132. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/udp_create_socket.rs +0 -0
  1133. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/ip_name_lookup.rs +0 -0
  1134. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/network.rs +0 -0
  1135. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/pipe.rs +0 -0
  1136. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/poll.rs +0 -0
  1137. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/random.rs +0 -0
  1138. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/stdio/worker_thread_stdin.rs +0 -0
  1139. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/tcp.rs +0 -0
  1140. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/udp.rs +0 -0
  1141. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/write_stream.rs +0 -0
  1142. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/cli/environment.wit +0 -0
  1143. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/cli/exit.wit +0 -0
  1144. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/cli/run.wit +0 -0
  1145. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/cli/stdio.wit +0 -0
  1146. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/cli/terminal.wit +0 -0
  1147. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/clocks/monotonic-clock.wit +0 -0
  1148. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/clocks/wall-clock.wit +0 -0
  1149. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/clocks/world.wit +0 -0
  1150. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/filesystem/preopens.wit +0 -0
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  1153. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/http/handler.wit +0 -0
  1154. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/io/error.wit +0 -0
  1155. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/io/poll.wit +0 -0
  1156. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/io/streams.wit +0 -0
  1157. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/io/world.wit +0 -0
  1158. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/random/insecure-seed.wit +0 -0
  1159. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/random/insecure.wit +0 -0
  1160. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/random/random.wit +0 -0
  1161. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/random/world.wit +0 -0
  1162. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/sockets/instance-network.wit +0 -0
  1163. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/sockets/ip-name-lookup.wit +0 -0
  1164. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/sockets/network.wit +0 -0
  1165. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/sockets/tcp-create-socket.wit +0 -0
  1166. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/sockets/tcp.wit +0 -0
  1167. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/sockets/udp-create-socket.wit +0 -0
  1168. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/sockets/udp.wit +0 -0
  1169. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/sockets/world.wit +0 -0
  1170. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1/witx → wasmtime-wasi-16.0.0/witx/preview1}/typenames.witx +0 -0
  1171. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1/witx → wasmtime-wasi-16.0.0/witx/preview1}/wasi_snapshot_preview1.witx +0 -0
  1172. /data/ext/cargo-vendor/{wasmtime-winch-15.0.1 → wasmtime-winch-16.0.0}/LICENSE +0 -0
  1173. /data/ext/cargo-vendor/{wasmtime-winch-15.0.1 → wasmtime-winch-16.0.0}/src/builder.rs +0 -0
  1174. /data/ext/cargo-vendor/{wasmtime-winch-15.0.1 → wasmtime-winch-16.0.0}/src/lib.rs +0 -0
  1175. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-15.0.1 → wasmtime-wit-bindgen-16.0.0}/src/lib.rs +0 -0
  1176. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-15.0.1 → wasmtime-wit-bindgen-16.0.0}/src/rust.rs +0 -0
  1177. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-15.0.1 → wasmtime-wit-bindgen-16.0.0}/src/source.rs +0 -0
  1178. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-15.0.1 → wasmtime-wit-bindgen-16.0.0}/src/types.rs +0 -0
  1179. /data/ext/cargo-vendor/{wasmtime-wmemcheck-15.0.1 → wasmtime-wmemcheck-16.0.0}/src/lib.rs +0 -0
  1180. /data/ext/cargo-vendor/{wasmtime-types-15.0.1 → wiggle-16.0.0}/LICENSE +0 -0
  1181. /data/ext/cargo-vendor/{wiggle-15.0.1 → wiggle-16.0.0}/README.md +0 -0
  1182. /data/ext/cargo-vendor/{wiggle-15.0.1 → wiggle-16.0.0}/src/borrow.rs +0 -0
  1183. /data/ext/cargo-vendor/{wiggle-15.0.1 → wiggle-16.0.0}/src/error.rs +0 -0
  1184. /data/ext/cargo-vendor/{wiggle-15.0.1 → wiggle-16.0.0}/src/guest_type.rs +0 -0
  1185. /data/ext/cargo-vendor/{wiggle-15.0.1 → wiggle-16.0.0}/src/region.rs +0 -0
  1186. /data/ext/cargo-vendor/{wiggle-15.0.1 → wiggle-16.0.0}/src/wasmtime.rs +0 -0
  1187. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wiggle-generate-16.0.0}/LICENSE +0 -0
  1188. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/README.md +0 -0
  1189. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/codegen_settings.rs +0 -0
  1190. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/config.rs +0 -0
  1191. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/funcs.rs +0 -0
  1192. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/lib.rs +0 -0
  1193. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/lifetimes.rs +0 -0
  1194. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/module_trait.rs +0 -0
  1195. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/names.rs +0 -0
  1196. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/types/error.rs +0 -0
  1197. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/types/flags.rs +0 -0
  1198. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/types/mod.rs +0 -0
  1199. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/wasmtime.rs +0 -0
  1200. /data/ext/cargo-vendor/{wiggle-15.0.1 → wiggle-macro-16.0.0}/LICENSE +0 -0
  1201. /data/ext/cargo-vendor/{wiggle-macro-15.0.1 → wiggle-macro-16.0.0}/src/lib.rs +0 -0
  1202. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/LICENSE +0 -0
  1203. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/build.rs +0 -0
  1204. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/codegen/builtin.rs +0 -0
  1205. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/isa/aarch64/address.rs +0 -0
  1206. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/isa/aarch64/asm.rs +0 -0
  1207. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/isa/aarch64/regs.rs +0 -0
  1208. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/isa/reg.rs +0 -0
  1209. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/isa/x64/address.rs +0 -0
  1210. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/lib.rs +0 -0
  1211. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/regalloc.rs +0 -0
  1212. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/regset.rs +0 -0
@@ -0,0 +1,1117 @@
1
+ //! Assembler library implementation for x64.
2
+
3
+ use crate::{
4
+ isa::reg::Reg,
5
+ masm::{DivKind, IntCmpKind, OperandSize, RemKind, RoundingMode, ShiftKind},
6
+ };
7
+ use cranelift_codegen::{
8
+ entity::EntityRef,
9
+ ir::{types, ConstantPool, ExternalName, LibCall, Opcode, TrapCode, UserExternalNameRef},
10
+ isa::{
11
+ x64::{
12
+ args::{
13
+ self, AluRmiROpcode, Amode, CmpOpcode, DivSignedness, ExtMode, FromWritableReg,
14
+ Gpr, GprMem, GprMemImm, Imm8Gpr, Imm8Reg, RegMem, RegMemImm,
15
+ ShiftKind as CraneliftShiftKind, SseOpcode, SyntheticAmode, WritableGpr,
16
+ WritableXmm, Xmm, XmmMem, XmmMemAligned, CC,
17
+ },
18
+ settings as x64_settings, CallInfo, EmitInfo, EmitState, Inst,
19
+ },
20
+ CallConv,
21
+ },
22
+ settings, Final, MachBuffer, MachBufferFinalized, MachInstEmit, MachInstEmitState, MachLabel,
23
+ VCodeConstantData, VCodeConstants, Writable,
24
+ };
25
+
26
+ use super::address::Address;
27
+ use smallvec::{smallvec, SmallVec};
28
+
29
+ // Conversions between winch-codegen x64 types and cranelift-codegen x64 types.
30
+
31
+ impl From<Reg> for RegMemImm {
32
+ fn from(reg: Reg) -> Self {
33
+ RegMemImm::reg(reg.into())
34
+ }
35
+ }
36
+
37
+ impl From<Reg> for RegMem {
38
+ fn from(value: Reg) -> Self {
39
+ RegMem::Reg { reg: value.into() }
40
+ }
41
+ }
42
+
43
+ impl From<Reg> for WritableGpr {
44
+ fn from(reg: Reg) -> Self {
45
+ let writable = Writable::from_reg(reg.into());
46
+ WritableGpr::from_writable_reg(writable).expect("valid writable gpr")
47
+ }
48
+ }
49
+
50
+ impl From<Reg> for WritableXmm {
51
+ fn from(reg: Reg) -> Self {
52
+ let writable = Writable::from_reg(reg.into());
53
+ WritableXmm::from_writable_reg(writable).expect("valid writable xmm")
54
+ }
55
+ }
56
+
57
+ impl From<Reg> for Gpr {
58
+ fn from(reg: Reg) -> Self {
59
+ Gpr::new(reg.into()).expect("valid gpr")
60
+ }
61
+ }
62
+
63
+ impl From<Reg> for GprMem {
64
+ fn from(value: Reg) -> Self {
65
+ GprMem::new(value.into()).expect("valid gpr")
66
+ }
67
+ }
68
+
69
+ impl From<Reg> for GprMemImm {
70
+ fn from(reg: Reg) -> Self {
71
+ GprMemImm::new(reg.into()).expect("valid gpr")
72
+ }
73
+ }
74
+
75
+ impl From<Reg> for Imm8Gpr {
76
+ fn from(value: Reg) -> Self {
77
+ Imm8Gpr::new(Imm8Reg::Reg { reg: value.into() }).expect("valid Imm8Gpr")
78
+ }
79
+ }
80
+
81
+ impl From<Reg> for Xmm {
82
+ fn from(reg: Reg) -> Self {
83
+ Xmm::new(reg.into()).expect("valid Xmm register")
84
+ }
85
+ }
86
+
87
+ impl From<OperandSize> for args::OperandSize {
88
+ fn from(size: OperandSize) -> Self {
89
+ match size {
90
+ OperandSize::S32 => Self::Size32,
91
+ OperandSize::S64 => Self::Size64,
92
+ s => panic!("Invalid operand size {:?}", s),
93
+ }
94
+ }
95
+ }
96
+
97
+ impl From<DivKind> for DivSignedness {
98
+ fn from(kind: DivKind) -> DivSignedness {
99
+ match kind {
100
+ DivKind::Signed => DivSignedness::Signed,
101
+ DivKind::Unsigned => DivSignedness::Unsigned,
102
+ }
103
+ }
104
+ }
105
+
106
+ impl From<IntCmpKind> for CC {
107
+ fn from(value: IntCmpKind) -> Self {
108
+ match value {
109
+ IntCmpKind::Eq => CC::Z,
110
+ IntCmpKind::Ne => CC::NZ,
111
+ IntCmpKind::LtS => CC::L,
112
+ IntCmpKind::LtU => CC::B,
113
+ IntCmpKind::GtS => CC::NLE,
114
+ IntCmpKind::GtU => CC::NBE,
115
+ IntCmpKind::LeS => CC::LE,
116
+ IntCmpKind::LeU => CC::BE,
117
+ IntCmpKind::GeS => CC::NL,
118
+ IntCmpKind::GeU => CC::NB,
119
+ }
120
+ }
121
+ }
122
+
123
+ impl From<ShiftKind> for CraneliftShiftKind {
124
+ fn from(value: ShiftKind) -> Self {
125
+ match value {
126
+ ShiftKind::Shl => CraneliftShiftKind::ShiftLeft,
127
+ ShiftKind::ShrS => CraneliftShiftKind::ShiftRightArithmetic,
128
+ ShiftKind::ShrU => CraneliftShiftKind::ShiftRightLogical,
129
+ ShiftKind::Rotl => CraneliftShiftKind::RotateLeft,
130
+ ShiftKind::Rotr => CraneliftShiftKind::RotateRight,
131
+ }
132
+ }
133
+ }
134
+
135
+ /// Low level assembler implementation for x64.
136
+ pub(crate) struct Assembler {
137
+ /// The machine instruction buffer.
138
+ buffer: MachBuffer<Inst>,
139
+ /// Constant emission information.
140
+ emit_info: EmitInfo,
141
+ /// Emission state.
142
+ emit_state: EmitState,
143
+ /// x64 flags.
144
+ isa_flags: x64_settings::Flags,
145
+ /// Constant pool.
146
+ pool: ConstantPool,
147
+ /// Constants that will be emitted separately by the MachBuffer.
148
+ constants: VCodeConstants,
149
+ }
150
+
151
+ impl Assembler {
152
+ /// Create a new x64 assembler.
153
+ pub fn new(shared_flags: settings::Flags, isa_flags: x64_settings::Flags) -> Self {
154
+ Self {
155
+ buffer: MachBuffer::<Inst>::new(),
156
+ emit_state: Default::default(),
157
+ emit_info: EmitInfo::new(shared_flags, isa_flags.clone()),
158
+ constants: Default::default(),
159
+ pool: ConstantPool::new(),
160
+ isa_flags,
161
+ }
162
+ }
163
+
164
+ /// Get a mutable reference to underlying
165
+ /// machine buffer.
166
+ pub fn buffer_mut(&mut self) -> &mut MachBuffer<Inst> {
167
+ &mut self.buffer
168
+ }
169
+
170
+ /// Adds a constant to the constant pool and returns its address.
171
+ pub fn add_constant(&mut self, constant: &[u8]) -> Address {
172
+ let handle = self.pool.insert(constant.into());
173
+ Address::constant(handle)
174
+ }
175
+
176
+ /// Return the emitted code.
177
+ pub fn finalize(mut self) -> MachBufferFinalized<Final> {
178
+ let stencil = self
179
+ .buffer
180
+ .finish(&self.constants, self.emit_state.ctrl_plane_mut());
181
+ stencil.apply_base_srcloc(Default::default())
182
+ }
183
+
184
+ fn emit(&mut self, inst: Inst) {
185
+ inst.emit(&[], &mut self.buffer, &self.emit_info, &mut self.emit_state);
186
+ }
187
+
188
+ fn to_synthetic_amode(
189
+ addr: &Address,
190
+ pool: &mut ConstantPool,
191
+ constants: &mut VCodeConstants,
192
+ buffer: &mut MachBuffer<Inst>,
193
+ ) -> SyntheticAmode {
194
+ match addr {
195
+ Address::Offset { base, offset } => {
196
+ SyntheticAmode::real(Amode::imm_reg(*offset as i32, (*base).into()))
197
+ }
198
+ Address::Const(c) => {
199
+ // Defer the creation of the
200
+ // `SyntheticAmode::ConstantOffset` addressing mode
201
+ // until the address is referenced by an actual
202
+ // instrunction.
203
+ let constant_data = pool.get(*c);
204
+ let data = VCodeConstantData::Pool(*c, constant_data.clone());
205
+ // If the constaant data is not marked as used, it will be
206
+ // inserted, therefore, it needs to be registered.
207
+ let needs_registration = !constants.pool_uses(&data);
208
+ let constant = constants.insert(VCodeConstantData::Pool(*c, constant_data.clone()));
209
+
210
+ if needs_registration {
211
+ buffer.register_constant(&constant, &data);
212
+ }
213
+ SyntheticAmode::ConstantOffset(constant)
214
+ }
215
+ }
216
+ }
217
+
218
+ /// Push register.
219
+ pub fn push_r(&mut self, reg: Reg) {
220
+ self.emit(Inst::Push64 { src: reg.into() });
221
+ }
222
+
223
+ /// Pop to register.
224
+ pub fn pop_r(&mut self, dst: Reg) {
225
+ let writable = Writable::from_reg(dst.into());
226
+ let dst = WritableGpr::from_writable_reg(writable).expect("valid writable gpr");
227
+ self.emit(Inst::Pop64 { dst });
228
+ }
229
+
230
+ /// Return instruction.
231
+ pub fn ret(&mut self) {
232
+ self.emit(Inst::Ret {
233
+ stack_bytes_to_pop: 0,
234
+ });
235
+ }
236
+
237
+ /// Register-to-register move.
238
+ pub fn mov_rr(&mut self, src: Reg, dst: Reg, size: OperandSize) {
239
+ self.emit(Inst::MovRR {
240
+ src: src.into(),
241
+ dst: dst.into(),
242
+ size: size.into(),
243
+ });
244
+ }
245
+
246
+ /// Register-to-memory move.
247
+ pub fn mov_rm(&mut self, src: Reg, addr: &Address, size: OperandSize) {
248
+ assert!(addr.is_offset());
249
+ let dst =
250
+ Self::to_synthetic_amode(addr, &mut self.pool, &mut self.constants, &mut self.buffer);
251
+ self.emit(Inst::MovRM {
252
+ size: size.into(),
253
+ src: src.into(),
254
+ dst,
255
+ });
256
+ }
257
+
258
+ /// Immediate-to-memory move.
259
+ pub fn mov_im(&mut self, src: i32, addr: &Address, size: OperandSize) {
260
+ assert!(addr.is_offset());
261
+ let dst =
262
+ Self::to_synthetic_amode(addr, &mut self.pool, &mut self.constants, &mut self.buffer);
263
+ self.emit(Inst::MovImmM {
264
+ size: size.into(),
265
+ simm32: src,
266
+ dst,
267
+ });
268
+ }
269
+
270
+ /// Immediate-to-register move.
271
+ pub fn mov_ir(&mut self, imm: u64, dst: Reg, size: OperandSize) {
272
+ let dst = WritableGpr::from_writable_reg(Writable::from_reg(dst.into()))
273
+ .expect("valid writable gpr");
274
+
275
+ self.emit(Inst::Imm {
276
+ dst_size: size.into(),
277
+ simm64: imm,
278
+ dst,
279
+ });
280
+ }
281
+
282
+ /// Memory-to-register load.
283
+ pub fn mov_mr(&mut self, addr: &Address, dst: Reg, size: OperandSize) {
284
+ use OperandSize::S64;
285
+
286
+ let src =
287
+ Self::to_synthetic_amode(addr, &mut self.pool, &mut self.constants, &mut self.buffer);
288
+
289
+ if size == S64 {
290
+ self.emit(Inst::Mov64MR {
291
+ src,
292
+ dst: dst.into(),
293
+ });
294
+ } else {
295
+ let reg_mem = RegMem::mem(src);
296
+ self.emit(Inst::MovzxRmR {
297
+ ext_mode: ExtMode::LQ,
298
+ src: GprMem::new(reg_mem).expect("valid memory address"),
299
+ dst: dst.into(),
300
+ });
301
+ }
302
+ }
303
+
304
+ /// Integer register conditional move.
305
+ pub fn cmov(&mut self, src: Reg, dst: Reg, cc: IntCmpKind, size: OperandSize) {
306
+ self.emit(Inst::Cmove {
307
+ size: size.into(),
308
+ cc: cc.into(),
309
+ consequent: src.into(),
310
+ alternative: dst.into(),
311
+ dst: dst.into(),
312
+ })
313
+ }
314
+
315
+ /// Single and double precision floating point
316
+ /// register-to-register move.
317
+ pub fn xmm_mov_rr(&mut self, src: Reg, dst: Reg, size: OperandSize) {
318
+ use OperandSize::*;
319
+
320
+ let op = match size {
321
+ S32 => SseOpcode::Movaps,
322
+ S64 => SseOpcode::Movapd,
323
+ S128 => SseOpcode::Movdqa,
324
+ };
325
+
326
+ self.emit(Inst::XmmUnaryRmRUnaligned {
327
+ op,
328
+ src: XmmMem::new(src.into()).expect("valid xmm unaligned"),
329
+ dst: dst.into(),
330
+ });
331
+ }
332
+
333
+ /// Single and double precision floating point load.
334
+ pub fn xmm_mov_mr(&mut self, src: &Address, dst: Reg, size: OperandSize) {
335
+ use OperandSize::*;
336
+
337
+ assert!(dst.is_float());
338
+ let op = match size {
339
+ S32 => SseOpcode::Movss,
340
+ S64 => SseOpcode::Movsd,
341
+ S128 => SseOpcode::Movdqu,
342
+ };
343
+
344
+ let src =
345
+ Self::to_synthetic_amode(src, &mut self.pool, &mut self.constants, &mut self.buffer);
346
+ self.emit(Inst::XmmUnaryRmRUnaligned {
347
+ op,
348
+ src: XmmMem::new(RegMem::mem(src)).expect("valid xmm unaligned"),
349
+ dst: dst.into(),
350
+ });
351
+ }
352
+
353
+ /// Single and double precision floating point store.
354
+ pub fn xmm_mov_rm(&mut self, src: Reg, dst: &Address, size: OperandSize) {
355
+ use OperandSize::*;
356
+
357
+ assert!(src.is_float());
358
+
359
+ let op = match size {
360
+ S32 => SseOpcode::Movss,
361
+ S64 => SseOpcode::Movsd,
362
+ S128 => SseOpcode::Movdqu,
363
+ };
364
+
365
+ let dst =
366
+ Self::to_synthetic_amode(dst, &mut self.pool, &mut self.constants, &mut self.buffer);
367
+ self.emit(Inst::XmmMovRM {
368
+ op,
369
+ src: src.into(),
370
+ dst,
371
+ });
372
+ }
373
+
374
+ /// Floating point register conditional move.
375
+ pub fn xmm_cmov(&mut self, src: Reg, dst: Reg, cc: IntCmpKind, size: OperandSize) {
376
+ let ty = match size {
377
+ OperandSize::S32 => types::F32,
378
+ OperandSize::S64 => types::F64,
379
+ // Move the entire 128 bits via movdqa.
380
+ OperandSize::S128 => types::I128,
381
+ };
382
+
383
+ self.emit(Inst::XmmCmove {
384
+ ty,
385
+ cc: cc.into(),
386
+ consequent: XmmMemAligned::new(src.into()).expect("valid XmmMemAligned"),
387
+ alternative: dst.into(),
388
+ dst: dst.into(),
389
+ })
390
+ }
391
+
392
+ /// Subtract register and register
393
+ pub fn sub_rr(&mut self, src: Reg, dst: Reg, size: OperandSize) {
394
+ self.emit(Inst::AluRmiR {
395
+ size: size.into(),
396
+ op: AluRmiROpcode::Sub,
397
+ src1: dst.into(),
398
+ src2: src.into(),
399
+ dst: dst.into(),
400
+ });
401
+ }
402
+
403
+ /// Subtact immediate register.
404
+ pub fn sub_ir(&mut self, imm: i32, dst: Reg, size: OperandSize) {
405
+ let imm = RegMemImm::imm(imm as u32);
406
+
407
+ self.emit(Inst::AluRmiR {
408
+ size: size.into(),
409
+ op: AluRmiROpcode::Sub,
410
+ src1: dst.into(),
411
+ src2: GprMemImm::new(imm).expect("valid immediate"),
412
+ dst: dst.into(),
413
+ });
414
+ }
415
+
416
+ /// "and" two registers.
417
+ pub fn and_rr(&mut self, src: Reg, dst: Reg, size: OperandSize) {
418
+ self.emit(Inst::AluRmiR {
419
+ size: size.into(),
420
+ op: AluRmiROpcode::And,
421
+ src1: dst.into(),
422
+ src2: src.into(),
423
+ dst: dst.into(),
424
+ });
425
+ }
426
+
427
+ pub fn and_ir(&mut self, imm: i32, dst: Reg, size: OperandSize) {
428
+ let imm = RegMemImm::imm(imm as u32);
429
+ self.emit(Inst::AluRmiR {
430
+ size: size.into(),
431
+ op: AluRmiROpcode::And,
432
+ src1: dst.into(),
433
+ src2: GprMemImm::new(imm).expect("valid immediate"),
434
+ dst: dst.into(),
435
+ });
436
+ }
437
+
438
+ /// "and" two float registers.
439
+ pub fn xmm_and_rr(&mut self, src: Reg, dst: Reg, size: OperandSize) {
440
+ let op = match size {
441
+ OperandSize::S32 => SseOpcode::Andps,
442
+ OperandSize::S64 => SseOpcode::Andpd,
443
+ OperandSize::S128 => unreachable!(),
444
+ };
445
+
446
+ self.emit(Inst::XmmRmR {
447
+ op,
448
+ src1: dst.into(),
449
+ src2: XmmMemAligned::from(Xmm::from(src)),
450
+ dst: dst.into(),
451
+ });
452
+ }
453
+
454
+ /// "and not" two float registers.
455
+ pub fn xmm_andn_rr(&mut self, src: Reg, dst: Reg, size: OperandSize) {
456
+ let op = match size {
457
+ OperandSize::S32 => SseOpcode::Andnps,
458
+ OperandSize::S64 => SseOpcode::Andnpd,
459
+ OperandSize::S128 => unreachable!(),
460
+ };
461
+
462
+ self.emit(Inst::XmmRmR {
463
+ op,
464
+ src1: dst.into(),
465
+ src2: Xmm::from(src).into(),
466
+ dst: dst.into(),
467
+ });
468
+ }
469
+
470
+ pub fn gpr_to_xmm(&mut self, src: Reg, dst: Reg, size: OperandSize) {
471
+ let op = match size {
472
+ OperandSize::S32 => SseOpcode::Movd,
473
+ OperandSize::S64 => SseOpcode::Movq,
474
+ OperandSize::S128 => unreachable!(),
475
+ };
476
+
477
+ self.emit(Inst::GprToXmm {
478
+ op,
479
+ src: src.into(),
480
+ dst: dst.into(),
481
+ src_size: size.into(),
482
+ })
483
+ }
484
+
485
+ pub fn or_rr(&mut self, src: Reg, dst: Reg, size: OperandSize) {
486
+ self.emit(Inst::AluRmiR {
487
+ size: size.into(),
488
+ op: AluRmiROpcode::Or,
489
+ src1: dst.into(),
490
+ src2: src.into(),
491
+ dst: dst.into(),
492
+ });
493
+ }
494
+
495
+ pub fn or_ir(&mut self, imm: i32, dst: Reg, size: OperandSize) {
496
+ let imm = RegMemImm::imm(imm as u32);
497
+
498
+ self.emit(Inst::AluRmiR {
499
+ size: size.into(),
500
+ op: AluRmiROpcode::Or,
501
+ src1: dst.into(),
502
+ src2: GprMemImm::new(imm).expect("valid immediate"),
503
+ dst: dst.into(),
504
+ });
505
+ }
506
+
507
+ pub fn xmm_or_rr(&mut self, src: Reg, dst: Reg, size: OperandSize) {
508
+ let op = match size {
509
+ OperandSize::S32 => SseOpcode::Orps,
510
+ OperandSize::S64 => SseOpcode::Orpd,
511
+ OperandSize::S128 => unreachable!(),
512
+ };
513
+
514
+ self.emit(Inst::XmmRmR {
515
+ op,
516
+ src1: dst.into(),
517
+ src2: XmmMemAligned::from(Xmm::from(src)),
518
+ dst: dst.into(),
519
+ });
520
+ }
521
+
522
+ /// Logical exclusive or with registers.
523
+ pub fn xor_rr(&mut self, src: Reg, dst: Reg, size: OperandSize) {
524
+ self.emit(Inst::AluRmiR {
525
+ size: size.into(),
526
+ op: AluRmiROpcode::Xor,
527
+ src1: dst.into(),
528
+ src2: src.into(),
529
+ dst: dst.into(),
530
+ });
531
+ }
532
+
533
+ pub fn xor_ir(&mut self, imm: i32, dst: Reg, size: OperandSize) {
534
+ let imm = RegMemImm::imm(imm as u32);
535
+
536
+ self.emit(Inst::AluRmiR {
537
+ size: size.into(),
538
+ op: AluRmiROpcode::Xor,
539
+ src1: dst.into(),
540
+ src2: GprMemImm::new(imm).expect("valid immediate"),
541
+ dst: dst.into(),
542
+ });
543
+ }
544
+
545
+ /// Logical exclusive or with float registers.
546
+ pub fn xmm_xor_rr(&mut self, src: Reg, dst: Reg, size: OperandSize) {
547
+ let op = match size {
548
+ OperandSize::S32 => SseOpcode::Xorps,
549
+ OperandSize::S64 => SseOpcode::Xorpd,
550
+ OperandSize::S128 => unreachable!(),
551
+ };
552
+
553
+ self.emit(Inst::XmmRmR {
554
+ op,
555
+ src1: dst.into(),
556
+ src2: XmmMemAligned::from(Xmm::from(src)),
557
+ dst: dst.into(),
558
+ });
559
+ }
560
+
561
+ /// Shift with register and register.
562
+ pub fn shift_rr(&mut self, src: Reg, dst: Reg, kind: ShiftKind, size: OperandSize) {
563
+ self.emit(Inst::ShiftR {
564
+ size: size.into(),
565
+ kind: kind.into(),
566
+ src: dst.into(),
567
+ num_bits: src.into(),
568
+ dst: dst.into(),
569
+ });
570
+ }
571
+
572
+ /// Shift with immediate and register.
573
+ pub fn shift_ir(&mut self, imm: u8, dst: Reg, kind: ShiftKind, size: OperandSize) {
574
+ let imm = imm.into();
575
+
576
+ self.emit(Inst::ShiftR {
577
+ size: size.into(),
578
+ kind: kind.into(),
579
+ src: dst.into(),
580
+ num_bits: Imm8Gpr::new(imm).expect("valid immediate"),
581
+ dst: dst.into(),
582
+ });
583
+ }
584
+
585
+ /// Signed/unsigned division.
586
+ ///
587
+ /// Emits a sequence of instructions to ensure the correctness of
588
+ /// the division invariants. This function assumes that the
589
+ /// caller has correctly allocated the dividend as `(rdx:rax)` and
590
+ /// accounted for the quotient to be stored in `rax`.
591
+ pub fn div(&mut self, divisor: Reg, dst: (Reg, Reg), kind: DivKind, size: OperandSize) {
592
+ let trap = match kind {
593
+ // Signed division has two trapping conditions, integer overflow and
594
+ // divide-by-zero. Check for divide-by-zero explicitly and let the
595
+ // hardware detect overflow.
596
+ //
597
+ // The dividend is sign extended to initialize `rdx`.
598
+ DivKind::Signed => {
599
+ self.emit(Inst::CmpRmiR {
600
+ size: size.into(),
601
+ src: GprMemImm::new(RegMemImm::imm(0)).unwrap(),
602
+ dst: divisor.into(),
603
+ opcode: CmpOpcode::Cmp,
604
+ });
605
+ self.emit(Inst::TrapIf {
606
+ cc: CC::Z,
607
+ trap_code: TrapCode::IntegerDivisionByZero,
608
+ });
609
+ self.emit(Inst::SignExtendData {
610
+ size: size.into(),
611
+ src: dst.0.into(),
612
+ dst: dst.1.into(),
613
+ });
614
+ TrapCode::IntegerOverflow
615
+ }
616
+
617
+ // Unsigned division only traps in one case, on divide-by-zero, so
618
+ // defer that to the trap opcode.
619
+ //
620
+ // The divisor_hi reg is initialized with zero through an
621
+ // xor-against-itself op.
622
+ DivKind::Unsigned => {
623
+ self.emit(Inst::AluRmiR {
624
+ size: size.into(),
625
+ op: AluRmiROpcode::Xor,
626
+ src1: dst.1.into(),
627
+ src2: dst.1.into(),
628
+ dst: dst.1.into(),
629
+ });
630
+ TrapCode::IntegerDivisionByZero
631
+ }
632
+ };
633
+ self.emit(Inst::Div {
634
+ sign: kind.into(),
635
+ size: size.into(),
636
+ trap,
637
+ divisor: GprMem::new(RegMem::reg(divisor.into())).unwrap(),
638
+ dividend_lo: dst.0.into(),
639
+ dividend_hi: dst.1.into(),
640
+ dst_quotient: dst.0.into(),
641
+ dst_remainder: dst.1.into(),
642
+ });
643
+ }
644
+
645
+ /// Signed/unsigned remainder.
646
+ ///
647
+ /// Emits a sequence of instructions to ensure the correctness of the
648
+ /// division invariants and ultimately calculate the remainder.
649
+ /// This function assumes that the
650
+ /// caller has correctly allocated the dividend as `(rdx:rax)` and
651
+ /// accounted for the remainder to be stored in `rdx`.
652
+ pub fn rem(&mut self, divisor: Reg, dst: (Reg, Reg), kind: RemKind, size: OperandSize) {
653
+ match kind {
654
+ // Signed remainder goes through a pseudo-instruction which has
655
+ // some internal branching. The `dividend_hi`, or `rdx`, is
656
+ // initialized here with a `SignExtendData` instruction.
657
+ RemKind::Signed => {
658
+ self.emit(Inst::SignExtendData {
659
+ size: size.into(),
660
+ src: dst.0.into(),
661
+ dst: dst.1.into(),
662
+ });
663
+ self.emit(Inst::CheckedSRemSeq {
664
+ size: size.into(),
665
+ divisor: divisor.into(),
666
+ dividend_lo: dst.0.into(),
667
+ dividend_hi: dst.1.into(),
668
+ dst_quotient: dst.0.into(),
669
+ dst_remainder: dst.1.into(),
670
+ });
671
+ }
672
+
673
+ // Unsigned remainder initializes `dividend_hi` with zero and
674
+ // then executes a normal `div` instruction.
675
+ RemKind::Unsigned => {
676
+ self.emit(Inst::AluRmiR {
677
+ size: size.into(),
678
+ op: AluRmiROpcode::Xor,
679
+ src1: dst.1.into(),
680
+ src2: dst.1.into(),
681
+ dst: dst.1.into(),
682
+ });
683
+ self.emit(Inst::Div {
684
+ sign: DivSignedness::Unsigned,
685
+ trap: TrapCode::IntegerDivisionByZero,
686
+ size: size.into(),
687
+ divisor: GprMem::new(RegMem::reg(divisor.into())).unwrap(),
688
+ dividend_lo: dst.0.into(),
689
+ dividend_hi: dst.1.into(),
690
+ dst_quotient: dst.0.into(),
691
+ dst_remainder: dst.1.into(),
692
+ });
693
+ }
694
+ }
695
+ }
696
+
697
+ /// Multiply immediate and register.
698
+ pub fn mul_ir(&mut self, imm: i32, dst: Reg, size: OperandSize) {
699
+ let imm = RegMemImm::imm(imm as u32);
700
+
701
+ self.emit(Inst::AluRmiR {
702
+ size: size.into(),
703
+ op: AluRmiROpcode::Mul,
704
+ src1: dst.into(),
705
+ src2: GprMemImm::new(imm).expect("valid immediate"),
706
+ dst: dst.into(),
707
+ });
708
+ }
709
+
710
+ /// Multiply register and register.
711
+ pub fn mul_rr(&mut self, src: Reg, dst: Reg, size: OperandSize) {
712
+ self.emit(Inst::AluRmiR {
713
+ size: size.into(),
714
+ op: AluRmiROpcode::Mul,
715
+ src1: dst.into(),
716
+ src2: src.into(),
717
+ dst: dst.into(),
718
+ });
719
+ }
720
+
721
+ /// Add immediate and register.
722
+ pub fn add_ir(&mut self, imm: i32, dst: Reg, size: OperandSize) {
723
+ let imm = RegMemImm::imm(imm as u32);
724
+
725
+ self.emit(Inst::AluRmiR {
726
+ size: size.into(),
727
+ op: AluRmiROpcode::Add,
728
+ src1: dst.into(),
729
+ src2: GprMemImm::new(imm).expect("valid immediate"),
730
+ dst: dst.into(),
731
+ });
732
+ }
733
+
734
+ /// Add register and register.
735
+ pub fn add_rr(&mut self, src: Reg, dst: Reg, size: OperandSize) {
736
+ self.emit(Inst::AluRmiR {
737
+ size: size.into(),
738
+ op: AluRmiROpcode::Add,
739
+ src1: dst.into(),
740
+ src2: src.into(),
741
+ dst: dst.into(),
742
+ });
743
+ }
744
+
745
+ pub fn cmp_ir(&mut self, imm: i32, dst: Reg, size: OperandSize) {
746
+ let imm = RegMemImm::imm(imm as u32);
747
+
748
+ self.emit(Inst::CmpRmiR {
749
+ size: size.into(),
750
+ opcode: CmpOpcode::Cmp,
751
+ src: GprMemImm::new(imm).expect("valid immediate"),
752
+ dst: dst.into(),
753
+ });
754
+ }
755
+
756
+ pub fn cmp_rr(&mut self, src: Reg, dst: Reg, size: OperandSize) {
757
+ self.emit(Inst::CmpRmiR {
758
+ size: size.into(),
759
+ opcode: CmpOpcode::Cmp,
760
+ src: src.into(),
761
+ dst: dst.into(),
762
+ });
763
+ }
764
+
765
+ /// Compares values in src and dst and sets ZF, PF, and CF flags in EFLAGS
766
+ /// register.
767
+ pub fn ucomis(&mut self, src: Reg, dst: Reg, size: OperandSize) {
768
+ let op = match size {
769
+ OperandSize::S32 => SseOpcode::Ucomiss,
770
+ OperandSize::S64 => SseOpcode::Ucomisd,
771
+ OperandSize::S128 => unreachable!(),
772
+ };
773
+
774
+ self.emit(Inst::XmmCmpRmR {
775
+ op,
776
+ src: Xmm::from(src).into(),
777
+ dst: dst.into(),
778
+ });
779
+ }
780
+
781
+ pub fn popcnt(&mut self, src: Reg, size: OperandSize) {
782
+ assert!(
783
+ self.isa_flags.has_popcnt() && self.isa_flags.has_sse42(),
784
+ "Requires has_popcnt and has_sse42 flags"
785
+ );
786
+ self.emit(Inst::UnaryRmR {
787
+ size: size.into(),
788
+ op: args::UnaryRmROpcode::Popcnt,
789
+ src: src.into(),
790
+ dst: src.into(),
791
+ });
792
+ }
793
+
794
+ /// Emit a test instruction with two register operands.
795
+ pub fn test_rr(&mut self, src: Reg, dst: Reg, size: OperandSize) {
796
+ self.emit(Inst::CmpRmiR {
797
+ size: size.into(),
798
+ opcode: CmpOpcode::Test,
799
+ src: src.into(),
800
+ dst: dst.into(),
801
+ })
802
+ }
803
+
804
+ /// Set value in dst to `0` or `1` based on flags in status register and
805
+ /// [`CmpKind`].
806
+ pub fn setcc(&mut self, kind: IntCmpKind, dst: Reg) {
807
+ self.setcc_impl(kind.into(), dst);
808
+ }
809
+
810
+ /// Set value in dst to `1` if parity flag in status register is set, `0`
811
+ /// otherwise.
812
+ pub fn setp(&mut self, dst: Reg) {
813
+ self.setcc_impl(CC::P, dst);
814
+ }
815
+
816
+ /// Set value in dst to `1` if parity flag in status register is not set,
817
+ /// `0` otherwise.
818
+ pub fn setnp(&mut self, dst: Reg) {
819
+ self.setcc_impl(CC::NP, dst);
820
+ }
821
+
822
+ fn setcc_impl(&mut self, cc: CC, dst: Reg) {
823
+ // Clear the dst register or bits 1 to 31 may be incorrectly set.
824
+ // Don't use xor since it updates the status register.
825
+ self.emit(Inst::Imm {
826
+ dst_size: args::OperandSize::Size32, // Always going to be an i32 result.
827
+ simm64: 0,
828
+ dst: dst.into(),
829
+ });
830
+ // Copy correct bit from status register into dst register.
831
+ self.emit(Inst::Setcc {
832
+ cc,
833
+ dst: dst.into(),
834
+ });
835
+ }
836
+
837
+ /// Store the count of leading zeroes in src in dst.
838
+ /// Requires `has_lzcnt` flag.
839
+ pub fn lzcnt(&mut self, src: Reg, dst: Reg, size: OperandSize) {
840
+ assert!(self.isa_flags.has_lzcnt(), "Requires has_lzcnt flag");
841
+ self.emit(Inst::UnaryRmR {
842
+ size: size.into(),
843
+ op: args::UnaryRmROpcode::Lzcnt,
844
+ src: src.into(),
845
+ dst: dst.into(),
846
+ });
847
+ }
848
+
849
+ /// Store the count of trailing zeroes in src in dst.
850
+ /// Requires `has_bmi1` flag.
851
+ pub fn tzcnt(&mut self, src: Reg, dst: Reg, size: OperandSize) {
852
+ assert!(self.isa_flags.has_bmi1(), "Requires has_bmi1 flag");
853
+ self.emit(Inst::UnaryRmR {
854
+ size: size.into(),
855
+ op: args::UnaryRmROpcode::Tzcnt,
856
+ src: src.into(),
857
+ dst: dst.into(),
858
+ });
859
+ }
860
+
861
+ /// Stores position of the most significant bit set in src in dst.
862
+ /// Zero flag is set if src is equal to 0.
863
+ pub fn bsr(&mut self, src: Reg, dst: Reg, size: OperandSize) {
864
+ self.emit(Inst::UnaryRmR {
865
+ size: size.into(),
866
+ op: args::UnaryRmROpcode::Bsr,
867
+ src: src.into(),
868
+ dst: dst.into(),
869
+ });
870
+ }
871
+
872
+ /// Performs integer negation on src and places result in dst.
873
+ pub fn neg(&mut self, src: Reg, dst: Reg, size: OperandSize) {
874
+ self.emit(Inst::Neg {
875
+ size: size.into(),
876
+ src: src.into(),
877
+ dst: dst.into(),
878
+ });
879
+ }
880
+
881
+ /// Stores position of the least significant bit set in src in dst.
882
+ /// Zero flag is set if src is equal to 0.
883
+ pub fn bsf(&mut self, src: Reg, dst: Reg, size: OperandSize) {
884
+ self.emit(Inst::UnaryRmR {
885
+ size: size.into(),
886
+ op: args::UnaryRmROpcode::Bsf,
887
+ src: src.into(),
888
+ dst: dst.into(),
889
+ });
890
+ }
891
+
892
+ /// Performs float addition on src and dst and places result in dst.
893
+ pub fn xmm_add_rr(&mut self, src: Reg, dst: Reg, size: OperandSize) {
894
+ let op = match size {
895
+ OperandSize::S32 => SseOpcode::Addss,
896
+ OperandSize::S64 => SseOpcode::Addsd,
897
+ OperandSize::S128 => unreachable!(),
898
+ };
899
+
900
+ self.emit(Inst::XmmRmRUnaligned {
901
+ op,
902
+ src1: Xmm::from(dst).into(),
903
+ src2: Xmm::from(src).into(),
904
+ dst: dst.into(),
905
+ });
906
+ }
907
+
908
+ /// Performs float subtraction on src and dst and places result in dst.
909
+ pub fn xmm_sub_rr(&mut self, src: Reg, dst: Reg, size: OperandSize) {
910
+ let op = match size {
911
+ OperandSize::S32 => SseOpcode::Subss,
912
+ OperandSize::S64 => SseOpcode::Subsd,
913
+ OperandSize::S128 => unreachable!(),
914
+ };
915
+
916
+ self.emit(Inst::XmmRmRUnaligned {
917
+ op,
918
+ src1: Xmm::from(dst).into(),
919
+ src2: Xmm::from(src).into(),
920
+ dst: dst.into(),
921
+ });
922
+ }
923
+
924
+ /// Performs float multiplication on src and dst and places result in dst.
925
+ pub fn xmm_mul_rr(&mut self, src: Reg, dst: Reg, size: OperandSize) {
926
+ let op = match size {
927
+ OperandSize::S32 => SseOpcode::Mulss,
928
+ OperandSize::S64 => SseOpcode::Mulsd,
929
+ OperandSize::S128 => unreachable!(),
930
+ };
931
+
932
+ self.emit(Inst::XmmRmRUnaligned {
933
+ op,
934
+ src1: Xmm::from(dst).into(),
935
+ src2: Xmm::from(src).into(),
936
+ dst: dst.into(),
937
+ });
938
+ }
939
+
940
+ /// Performs float division on src and dst and places result in dst.
941
+ pub fn xmm_div_rr(&mut self, src: Reg, dst: Reg, size: OperandSize) {
942
+ let op = match size {
943
+ OperandSize::S32 => SseOpcode::Divss,
944
+ OperandSize::S64 => SseOpcode::Divsd,
945
+ OperandSize::S128 => unreachable!(),
946
+ };
947
+
948
+ self.emit(Inst::XmmRmRUnaligned {
949
+ op,
950
+ src1: Xmm::from(dst).into(),
951
+ src2: Xmm::from(src).into(),
952
+ dst: dst.into(),
953
+ });
954
+ }
955
+
956
+ /// Mininum for src and dst XMM registers with results put in dst.
957
+ pub fn xmm_min_seq(&mut self, src: Reg, dst: Reg, size: OperandSize) {
958
+ self.emit(Inst::XmmMinMaxSeq {
959
+ size: size.into(),
960
+ is_min: true,
961
+ lhs: src.into(),
962
+ rhs: dst.into(),
963
+ dst: dst.into(),
964
+ });
965
+ }
966
+
967
+ /// Maximum for src and dst XMM registers with results put in dst.
968
+ pub fn xmm_max_seq(&mut self, src: Reg, dst: Reg, size: OperandSize) {
969
+ self.emit(Inst::XmmMinMaxSeq {
970
+ size: size.into(),
971
+ is_min: false,
972
+ lhs: src.into(),
973
+ rhs: dst.into(),
974
+ dst: dst.into(),
975
+ });
976
+ }
977
+
978
+ /// Perform rounding operation on float register src and place results in
979
+ /// float register dst.
980
+ pub fn xmm_rounds_rr(&mut self, src: Reg, dst: Reg, mode: RoundingMode, size: OperandSize) {
981
+ let op = match size {
982
+ OperandSize::S32 => SseOpcode::Roundss,
983
+ OperandSize::S64 => SseOpcode::Roundsd,
984
+ OperandSize::S128 => unreachable!(),
985
+ };
986
+
987
+ let imm: u8 = match mode {
988
+ RoundingMode::Nearest => 0x00,
989
+ RoundingMode::Down => 0x01,
990
+ RoundingMode::Up => 0x02,
991
+ RoundingMode::Zero => 0x03,
992
+ };
993
+
994
+ self.emit(Inst::XmmUnaryRmRImm {
995
+ op,
996
+ src: XmmMemAligned::from(Xmm::from(src)),
997
+ imm,
998
+ dst: dst.into(),
999
+ })
1000
+ }
1001
+
1002
+ pub fn sqrt(&mut self, src: Reg, dst: Reg, size: OperandSize) {
1003
+ let op = match size {
1004
+ OperandSize::S32 => SseOpcode::Sqrtss,
1005
+ OperandSize::S64 => SseOpcode::Sqrtsd,
1006
+ OperandSize::S128 => unreachable!(),
1007
+ };
1008
+
1009
+ self.emit(Inst::XmmUnaryRmR {
1010
+ op,
1011
+ src: Xmm::from(src).into(),
1012
+ dst: dst.into(),
1013
+ })
1014
+ }
1015
+
1016
+ /// Emit a call to an unknown location through a register.
1017
+ pub fn call_with_reg(&mut self, callee: Reg) {
1018
+ self.emit(Inst::CallUnknown {
1019
+ dest: RegMem::reg(callee.into()),
1020
+ info: Box::new(CallInfo {
1021
+ uses: smallvec![],
1022
+ defs: smallvec![],
1023
+ clobbers: Default::default(),
1024
+ opcode: Opcode::Call,
1025
+ callee_pop_size: 0,
1026
+ callee_conv: CallConv::SystemV,
1027
+ }),
1028
+ });
1029
+ }
1030
+
1031
+ /// Emit a call to a locally defined function through an index.
1032
+ pub fn call_with_index(&mut self, index: u32) {
1033
+ let dest = ExternalName::user(UserExternalNameRef::new(index as usize));
1034
+ self.emit(Inst::CallKnown {
1035
+ dest,
1036
+ info: Box::new(CallInfo {
1037
+ uses: smallvec![],
1038
+ defs: smallvec![],
1039
+ clobbers: Default::default(),
1040
+ opcode: Opcode::Call,
1041
+ callee_pop_size: 0,
1042
+ callee_conv: CallConv::SystemV,
1043
+ }),
1044
+ });
1045
+ }
1046
+
1047
+ /// Emit a call to a well-known libcall.
1048
+ pub fn call_with_lib(&mut self, lib: LibCall) {
1049
+ let dest = ExternalName::LibCall(lib);
1050
+ self.emit(Inst::CallKnown {
1051
+ dest,
1052
+ info: Box::new(CallInfo {
1053
+ uses: smallvec![],
1054
+ defs: smallvec![],
1055
+ clobbers: Default::default(),
1056
+ opcode: Opcode::Call,
1057
+ callee_pop_size: 0,
1058
+ callee_conv: CallConv::SystemV,
1059
+ }),
1060
+ });
1061
+ }
1062
+
1063
+ /// Emits a conditional jump to the given label.
1064
+ pub fn jmp_if(&mut self, cc: impl Into<CC>, taken: MachLabel) {
1065
+ self.emit(Inst::JmpIf {
1066
+ cc: cc.into(),
1067
+ taken,
1068
+ });
1069
+ }
1070
+
1071
+ /// Performs an unconditional jump to the given label.
1072
+ pub fn jmp(&mut self, target: MachLabel) {
1073
+ self.emit(Inst::JmpKnown { dst: target });
1074
+ }
1075
+
1076
+ /// Emits a jump table sequence.
1077
+ pub fn jmp_table(
1078
+ &mut self,
1079
+ targets: SmallVec<[MachLabel; 4]>,
1080
+ default: MachLabel,
1081
+ index: Reg,
1082
+ tmp1: Reg,
1083
+ tmp2: Reg,
1084
+ ) {
1085
+ self.emit(Inst::JmpTableSeq {
1086
+ idx: index.into(),
1087
+ tmp1: Writable::from_reg(tmp1.into()),
1088
+ tmp2: Writable::from_reg(tmp2.into()),
1089
+ default_target: default,
1090
+ targets: Box::new(targets.to_vec()),
1091
+ })
1092
+ }
1093
+
1094
+ /// Emit a trap instruction.
1095
+ pub fn trap(&mut self, code: TrapCode) {
1096
+ self.emit(Inst::Ud2 { trap_code: code })
1097
+ }
1098
+
1099
+ /// Conditional trap.
1100
+ pub fn trapif(&mut self, cc: IntCmpKind, trap_code: TrapCode) {
1101
+ self.emit(Inst::TrapIf {
1102
+ cc: cc.into(),
1103
+ trap_code,
1104
+ });
1105
+ }
1106
+
1107
+ /// Load effective address.
1108
+ pub fn lea(&mut self, addr: &Address, dst: Reg, size: OperandSize) {
1109
+ let addr =
1110
+ Self::to_synthetic_amode(addr, &mut self.pool, &mut self.constants, &mut self.buffer);
1111
+ self.emit(Inst::LoadEffectiveAddress {
1112
+ addr,
1113
+ dst: dst.into(),
1114
+ size: size.into(),
1115
+ });
1116
+ }
1117
+ }