wasmtime 15.0.1 → 16.0.0

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Files changed (1212) hide show
  1. checksums.yaml +4 -4
  2. data/Cargo.lock +83 -103
  3. data/ext/Cargo.toml +6 -6
  4. data/ext/cargo-vendor/cranelift-bforest-0.103.0/.cargo-checksum.json +1 -0
  5. data/ext/cargo-vendor/cranelift-bforest-0.103.0/Cargo.toml +40 -0
  6. data/ext/cargo-vendor/cranelift-bforest-0.103.0/src/lib.rs +183 -0
  7. data/ext/cargo-vendor/cranelift-codegen-0.103.0/.cargo-checksum.json +1 -0
  8. data/ext/cargo-vendor/cranelift-codegen-0.103.0/Cargo.toml +175 -0
  9. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/binemit/mod.rs +171 -0
  10. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/egraph/cost.rs +171 -0
  11. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/egraph/elaborate.rs +750 -0
  12. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/egraph.rs +703 -0
  13. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/ir/dfg.rs +1735 -0
  14. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/ir/pcc.rs +1682 -0
  15. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isa/aarch64/lower/isle.rs +874 -0
  16. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isa/riscv64/inst/mod.rs +2041 -0
  17. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isa/riscv64/inst.isle +2928 -0
  18. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isa/riscv64/lower.isle +2864 -0
  19. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isa/s390x/lower/isle.rs +1029 -0
  20. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isa/x64/lower/isle.rs +1064 -0
  21. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isa/x64/pcc.rs +916 -0
  22. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/isle_prelude.rs +977 -0
  23. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/lib.rs +106 -0
  24. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/machinst/isle.rs +896 -0
  25. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/opts/arithmetic.isle +152 -0
  26. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/opts/cprop.isle +237 -0
  27. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/opts/icmp.isle +199 -0
  28. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/opts/selects.isle +76 -0
  29. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/opts.rs +172 -0
  30. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/prelude.isle +649 -0
  31. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/timing.rs +297 -0
  32. data/ext/cargo-vendor/cranelift-codegen-0.103.0/src/unionfind.rs +75 -0
  33. data/ext/cargo-vendor/cranelift-codegen-meta-0.103.0/.cargo-checksum.json +1 -0
  34. data/ext/cargo-vendor/cranelift-codegen-meta-0.103.0/Cargo.toml +35 -0
  35. data/ext/cargo-vendor/cranelift-codegen-shared-0.103.0/.cargo-checksum.json +1 -0
  36. data/ext/cargo-vendor/cranelift-codegen-shared-0.103.0/Cargo.toml +22 -0
  37. data/ext/cargo-vendor/cranelift-codegen-shared-0.103.0/src/lib.rs +10 -0
  38. data/ext/cargo-vendor/cranelift-control-0.103.0/.cargo-checksum.json +1 -0
  39. data/ext/cargo-vendor/cranelift-control-0.103.0/Cargo.toml +30 -0
  40. data/ext/cargo-vendor/cranelift-entity-0.103.0/.cargo-checksum.json +1 -0
  41. data/ext/cargo-vendor/cranelift-entity-0.103.0/Cargo.toml +50 -0
  42. data/ext/cargo-vendor/cranelift-entity-0.103.0/src/lib.rs +317 -0
  43. data/ext/cargo-vendor/cranelift-entity-0.103.0/src/primary.rs +516 -0
  44. data/ext/cargo-vendor/cranelift-entity-0.103.0/src/unsigned.rs +71 -0
  45. data/ext/cargo-vendor/cranelift-frontend-0.103.0/.cargo-checksum.json +1 -0
  46. data/ext/cargo-vendor/cranelift-frontend-0.103.0/Cargo.toml +68 -0
  47. data/ext/cargo-vendor/cranelift-frontend-0.103.0/src/lib.rs +189 -0
  48. data/ext/cargo-vendor/cranelift-isle-0.103.0/.cargo-checksum.json +1 -0
  49. data/ext/cargo-vendor/cranelift-isle-0.103.0/Cargo.toml +46 -0
  50. data/ext/cargo-vendor/cranelift-isle-0.103.0/isle_examples/link/multi_constructor_main.rs +88 -0
  51. data/ext/cargo-vendor/cranelift-isle-0.103.0/isle_examples/link/multi_extractor_main.rs +63 -0
  52. data/ext/cargo-vendor/cranelift-isle-0.103.0/src/codegen.rs +886 -0
  53. data/ext/cargo-vendor/cranelift-native-0.103.0/.cargo-checksum.json +1 -0
  54. data/ext/cargo-vendor/cranelift-native-0.103.0/Cargo.toml +43 -0
  55. data/ext/cargo-vendor/cranelift-native-0.103.0/src/lib.rs +184 -0
  56. data/ext/cargo-vendor/cranelift-wasm-0.103.0/.cargo-checksum.json +1 -0
  57. data/ext/cargo-vendor/cranelift-wasm-0.103.0/Cargo.toml +106 -0
  58. data/ext/cargo-vendor/cranelift-wasm-0.103.0/src/environ/dummy.rs +953 -0
  59. data/ext/cargo-vendor/cranelift-wasm-0.103.0/src/lib.rs +62 -0
  60. data/ext/cargo-vendor/cranelift-wasm-0.103.0/src/translation_utils.rs +89 -0
  61. data/ext/cargo-vendor/wasi-cap-std-sync-16.0.0/.cargo-checksum.json +1 -0
  62. data/ext/cargo-vendor/wasi-cap-std-sync-16.0.0/Cargo.toml +102 -0
  63. data/ext/cargo-vendor/wasi-common-16.0.0/.cargo-checksum.json +1 -0
  64. data/ext/cargo-vendor/wasi-common-16.0.0/Cargo.toml +131 -0
  65. data/ext/cargo-vendor/wasi-common-16.0.0/src/lib.rs +76 -0
  66. data/ext/cargo-vendor/wasi-common-16.0.0/src/snapshots/preview_1.rs +1492 -0
  67. data/ext/cargo-vendor/wasmtime-16.0.0/.cargo-checksum.json +1 -0
  68. data/ext/cargo-vendor/wasmtime-16.0.0/Cargo.toml +211 -0
  69. data/ext/cargo-vendor/wasmtime-16.0.0/src/compiler.rs +682 -0
  70. data/ext/cargo-vendor/wasmtime-16.0.0/src/component/component.rs +505 -0
  71. data/ext/cargo-vendor/wasmtime-16.0.0/src/component/func/typed.rs +2400 -0
  72. data/ext/cargo-vendor/wasmtime-16.0.0/src/config.rs +2422 -0
  73. data/ext/cargo-vendor/wasmtime-16.0.0/src/func.rs +2391 -0
  74. data/ext/cargo-vendor/wasmtime-16.0.0/src/lib.rs +520 -0
  75. data/ext/cargo-vendor/wasmtime-16.0.0/src/memory.rs +998 -0
  76. data/ext/cargo-vendor/wasmtime-16.0.0/src/module.rs +1370 -0
  77. data/ext/cargo-vendor/wasmtime-16.0.0/src/stack.rs +73 -0
  78. data/ext/cargo-vendor/wasmtime-16.0.0/src/v128.rs +122 -0
  79. data/ext/cargo-vendor/wasmtime-asm-macros-16.0.0/.cargo-checksum.json +1 -0
  80. data/ext/cargo-vendor/wasmtime-asm-macros-16.0.0/Cargo.toml +22 -0
  81. data/ext/cargo-vendor/wasmtime-cache-16.0.0/.cargo-checksum.json +1 -0
  82. data/ext/cargo-vendor/wasmtime-cache-16.0.0/Cargo.toml +81 -0
  83. data/ext/cargo-vendor/wasmtime-cache-16.0.0/src/lib.rs +235 -0
  84. data/ext/cargo-vendor/wasmtime-cache-16.0.0/src/worker.rs +890 -0
  85. data/ext/cargo-vendor/wasmtime-component-macro-16.0.0/.cargo-checksum.json +1 -0
  86. data/ext/cargo-vendor/wasmtime-component-macro-16.0.0/Cargo.toml +67 -0
  87. data/ext/cargo-vendor/wasmtime-component-util-16.0.0/.cargo-checksum.json +1 -0
  88. data/ext/cargo-vendor/wasmtime-component-util-16.0.0/Cargo.toml +25 -0
  89. data/ext/cargo-vendor/wasmtime-cranelift-16.0.0/.cargo-checksum.json +1 -0
  90. data/ext/cargo-vendor/wasmtime-cranelift-16.0.0/Cargo.toml +112 -0
  91. data/ext/cargo-vendor/wasmtime-cranelift-16.0.0/src/compiler/component.rs +959 -0
  92. data/ext/cargo-vendor/wasmtime-cranelift-16.0.0/src/compiler.rs +1317 -0
  93. data/ext/cargo-vendor/wasmtime-cranelift-16.0.0/src/debug/transform/expression.rs +1252 -0
  94. data/ext/cargo-vendor/wasmtime-cranelift-16.0.0/src/debug/transform/simulate.rs +410 -0
  95. data/ext/cargo-vendor/wasmtime-cranelift-16.0.0/src/debug.rs +18 -0
  96. data/ext/cargo-vendor/wasmtime-cranelift-16.0.0/src/func_environ.rs +2750 -0
  97. data/ext/cargo-vendor/wasmtime-cranelift-shared-16.0.0/.cargo-checksum.json +1 -0
  98. data/ext/cargo-vendor/wasmtime-cranelift-shared-16.0.0/Cargo.toml +71 -0
  99. data/ext/cargo-vendor/wasmtime-environ-16.0.0/.cargo-checksum.json +1 -0
  100. data/ext/cargo-vendor/wasmtime-environ-16.0.0/Cargo.lock +660 -0
  101. data/ext/cargo-vendor/wasmtime-environ-16.0.0/Cargo.toml +125 -0
  102. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/compilation.rs +402 -0
  103. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/component/compiler.rs +47 -0
  104. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/component/translate.rs +951 -0
  105. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/component/types.rs +1876 -0
  106. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/lib.rs +59 -0
  107. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/module.rs +1075 -0
  108. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/module_environ.rs +892 -0
  109. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/module_types.rs +120 -0
  110. data/ext/cargo-vendor/wasmtime-environ-16.0.0/src/scopevec.rs +78 -0
  111. data/ext/cargo-vendor/wasmtime-fiber-16.0.0/.cargo-checksum.json +1 -0
  112. data/ext/cargo-vendor/wasmtime-fiber-16.0.0/Cargo.toml +63 -0
  113. data/ext/cargo-vendor/wasmtime-fiber-16.0.0/src/lib.rs +328 -0
  114. data/ext/cargo-vendor/wasmtime-fiber-16.0.0/src/unix.rs +265 -0
  115. data/ext/cargo-vendor/wasmtime-fiber-16.0.0/src/windows.c +9 -0
  116. data/ext/cargo-vendor/wasmtime-jit-16.0.0/.cargo-checksum.json +1 -0
  117. data/ext/cargo-vendor/wasmtime-jit-16.0.0/Cargo.toml +125 -0
  118. data/ext/cargo-vendor/wasmtime-jit-16.0.0/src/code_memory.rs +319 -0
  119. data/ext/cargo-vendor/wasmtime-jit-16.0.0/src/instantiate.rs +772 -0
  120. data/ext/cargo-vendor/wasmtime-jit-16.0.0/src/lib.rs +21 -0
  121. data/ext/cargo-vendor/wasmtime-jit-debug-16.0.0/.cargo-checksum.json +1 -0
  122. data/ext/cargo-vendor/wasmtime-jit-debug-16.0.0/Cargo.toml +67 -0
  123. data/ext/cargo-vendor/wasmtime-jit-icache-coherence-16.0.0/.cargo-checksum.json +1 -0
  124. data/ext/cargo-vendor/wasmtime-jit-icache-coherence-16.0.0/Cargo.toml +46 -0
  125. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/.cargo-checksum.json +1 -0
  126. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/Cargo.toml +139 -0
  127. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/build.rs +28 -0
  128. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/proptest-regressions/instance/allocator/pooling/memory_pool.txt +9 -0
  129. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/arch/aarch64.rs +120 -0
  130. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/arch/mod.rs +32 -0
  131. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/arch/riscv64.rs +88 -0
  132. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/arch/s390x.rs +61 -0
  133. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/arch/x86_64.rs +106 -0
  134. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/cow.rs +888 -0
  135. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/helpers.c +113 -0
  136. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/instance/allocator/pooling/memory_pool.rs +1005 -0
  137. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/instance/allocator/pooling/stack_pool.rs +242 -0
  138. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/instance/allocator/pooling/table_pool.rs +227 -0
  139. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/instance/allocator/pooling.rs +698 -0
  140. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/lib.rs +264 -0
  141. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/libcalls.rs +776 -0
  142. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/mmap.rs +214 -0
  143. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/mpk/enabled.rs +204 -0
  144. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/mpk/pkru.rs +102 -0
  145. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/miri/mod.rs +10 -0
  146. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/miri/traphandlers.rs +42 -0
  147. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/miri/unwind.rs +17 -0
  148. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/miri/vm.rs +63 -0
  149. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/mod.rs +30 -0
  150. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/unix/machports.rs +487 -0
  151. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/unix/macos_traphandlers.rs +28 -0
  152. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/unix/mod.rs +21 -0
  153. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/unix/signals.rs +402 -0
  154. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/unix/unwind.rs +91 -0
  155. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/unix/vm.rs +208 -0
  156. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/windows/mod.rs +6 -0
  157. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/windows/traphandlers.rs +105 -0
  158. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/windows/unwind.rs +46 -0
  159. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/sys/windows/vm.rs +79 -0
  160. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/traphandlers/backtrace.rs +265 -0
  161. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/traphandlers.rs +733 -0
  162. data/ext/cargo-vendor/wasmtime-runtime-16.0.0/src/vmcontext.rs +1197 -0
  163. data/ext/cargo-vendor/wasmtime-types-16.0.0/.cargo-checksum.json +1 -0
  164. data/ext/cargo-vendor/wasmtime-types-16.0.0/Cargo.toml +36 -0
  165. data/ext/cargo-vendor/wasmtime-types-16.0.0/src/lib.rs +504 -0
  166. data/ext/cargo-vendor/wasmtime-versioned-export-macros-16.0.0/.cargo-checksum.json +1 -0
  167. data/ext/cargo-vendor/wasmtime-versioned-export-macros-16.0.0/Cargo.toml +32 -0
  168. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/.cargo-checksum.json +1 -0
  169. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/Cargo.toml +261 -0
  170. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/lib.rs +137 -0
  171. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/host/io.rs +368 -0
  172. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/host/network.rs +570 -0
  173. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/host/tcp.rs +632 -0
  174. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/host/udp.rs +550 -0
  175. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/mod.rs +328 -0
  176. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/preview0.rs +870 -0
  177. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/preview1.rs +2348 -0
  178. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/stdio.rs +259 -0
  179. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/stream.rs +182 -0
  180. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/src/preview2/table.rs +337 -0
  181. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/tests/all/api.rs +218 -0
  182. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/tests/all/async_.rs +360 -0
  183. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/tests/all/main.rs +113 -0
  184. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/tests/all/preview1.rs +239 -0
  185. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/tests/all/sync.rs +299 -0
  186. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/tests/process_stdin.rs +165 -0
  187. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/wit/command-extended.wit +6 -0
  188. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/wit/deps/cli/command.wit +7 -0
  189. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/wit/deps/cli/imports.wit +20 -0
  190. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/wit/deps/http/proxy.wit +32 -0
  191. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/wit/deps/http/types.wit +570 -0
  192. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/wit/test.wit +22 -0
  193. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/witx/preview0/typenames.witx +746 -0
  194. data/ext/cargo-vendor/wasmtime-wasi-16.0.0/witx/preview0/wasi_unstable.witx +513 -0
  195. data/ext/cargo-vendor/wasmtime-winch-16.0.0/.cargo-checksum.json +1 -0
  196. data/ext/cargo-vendor/wasmtime-winch-16.0.0/Cargo.toml +77 -0
  197. data/ext/cargo-vendor/wasmtime-winch-16.0.0/src/compiler.rs +243 -0
  198. data/ext/cargo-vendor/wasmtime-wit-bindgen-16.0.0/.cargo-checksum.json +1 -0
  199. data/ext/cargo-vendor/wasmtime-wit-bindgen-16.0.0/Cargo.toml +41 -0
  200. data/ext/cargo-vendor/wasmtime-wmemcheck-16.0.0/.cargo-checksum.json +1 -0
  201. data/ext/cargo-vendor/wasmtime-wmemcheck-16.0.0/Cargo.toml +29 -0
  202. data/ext/cargo-vendor/wiggle-16.0.0/.cargo-checksum.json +1 -0
  203. data/ext/cargo-vendor/wiggle-16.0.0/Cargo.toml +115 -0
  204. data/ext/cargo-vendor/wiggle-16.0.0/src/lib.rs +1198 -0
  205. data/ext/cargo-vendor/wiggle-generate-16.0.0/.cargo-checksum.json +1 -0
  206. data/ext/cargo-vendor/wiggle-generate-16.0.0/Cargo.toml +65 -0
  207. data/ext/cargo-vendor/wiggle-generate-16.0.0/src/types/handle.rs +84 -0
  208. data/ext/cargo-vendor/wiggle-generate-16.0.0/src/types/record.rs +132 -0
  209. data/ext/cargo-vendor/wiggle-generate-16.0.0/src/types/variant.rs +191 -0
  210. data/ext/cargo-vendor/wiggle-macro-16.0.0/.cargo-checksum.json +1 -0
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  610. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/aarch64/mod.rs +0 -0
  611. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/aarch64/pcc.rs +0 -0
  612. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/aarch64/settings.rs +0 -0
  613. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/call_conv.rs +0 -0
  614. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/mod.rs +0 -0
  615. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/abi.rs +0 -0
  616. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/args.rs +0 -0
  617. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/emit.rs +0 -0
  618. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/emit_tests.rs +0 -0
  619. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/encode.rs +0 -0
  620. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/imms.rs +0 -0
  621. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/regs.rs +0 -0
  622. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/unwind/systemv.rs +0 -0
  623. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/unwind.rs +0 -0
  624. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst/vector.rs +0 -0
  625. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/inst_vector.isle +0 -0
  626. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/lower/isle/generated_code.rs +0 -0
  627. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/lower/isle.rs +0 -0
  628. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/lower.rs +0 -0
  629. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/mod.rs +0 -0
  630. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/riscv64/settings.rs +0 -0
  631. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/abi.rs +0 -0
  632. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst/args.rs +0 -0
  633. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst/emit.rs +0 -0
  634. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst/emit_tests.rs +0 -0
  635. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst/imms.rs +0 -0
  636. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst/mod.rs +0 -0
  637. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst/regs.rs +0 -0
  638. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst/unwind/systemv.rs +0 -0
  639. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst/unwind.rs +0 -0
  640. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/inst.isle +0 -0
  641. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/lower/isle/generated_code.rs +0 -0
  642. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/lower.isle +0 -0
  643. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/lower.rs +0 -0
  644. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/mod.rs +0 -0
  645. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/s390x/settings.rs +0 -0
  646. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/unwind/systemv.rs +0 -0
  647. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/unwind/winx64.rs +0 -0
  648. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/unwind.rs +0 -0
  649. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/abi.rs +0 -0
  650. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/encoding/evex.rs +0 -0
  651. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/encoding/mod.rs +0 -0
  652. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/encoding/rex.rs +0 -0
  653. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/encoding/vex.rs +0 -0
  654. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/args.rs +0 -0
  655. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/emit.rs +0 -0
  656. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/emit_state.rs +0 -0
  657. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/emit_tests.rs +0 -0
  658. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/mod.rs +0 -0
  659. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/regs.rs +0 -0
  660. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/unwind/systemv.rs +0 -0
  661. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/unwind/winx64.rs +0 -0
  662. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst/unwind.rs +0 -0
  663. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/inst.isle +0 -0
  664. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/lower/isle/generated_code.rs +0 -0
  665. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/lower.isle +0 -0
  666. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/lower.rs +0 -0
  667. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/mod.rs +0 -0
  668. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/isa/x64/settings.rs +0 -0
  669. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/iterators.rs +0 -0
  670. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/legalizer/globalvalue.rs +0 -0
  671. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/legalizer/mod.rs +0 -0
  672. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/legalizer/table.rs +0 -0
  673. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/loop_analysis.rs +0 -0
  674. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/abi.rs +0 -0
  675. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/blockorder.rs +0 -0
  676. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/buffer.rs +0 -0
  677. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/compile.rs +0 -0
  678. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/helpers.rs +0 -0
  679. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/inst_common.rs +0 -0
  680. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/lower.rs +0 -0
  681. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/mod.rs +0 -0
  682. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/pcc.rs +0 -0
  683. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/reg.rs +0 -0
  684. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/valueregs.rs +0 -0
  685. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/machinst/vcode.rs +0 -0
  686. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/nan_canonicalization.rs +0 -0
  687. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/opts/README.md +0 -0
  688. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/opts/bitops.isle +0 -0
  689. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/opts/extends.isle +0 -0
  690. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/opts/generated_code.rs +0 -0
  691. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/opts/remat.isle +0 -0
  692. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/opts/shifts.isle +0 -0
  693. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/opts/vector.isle +0 -0
  694. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/prelude_lower.isle +0 -0
  695. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/prelude_opt.isle +0 -0
  696. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/print_errors.rs +0 -0
  697. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/remove_constant_phis.rs +0 -0
  698. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/result.rs +0 -0
  699. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/scoped_hash_map.rs +0 -0
  700. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/settings.rs +0 -0
  701. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/souper_harvest.rs +0 -0
  702. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/unreachable_code.rs +0 -0
  703. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/value_label.rs +0 -0
  704. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/verifier/mod.rs +0 -0
  705. /data/ext/cargo-vendor/{cranelift-codegen-0.102.1 → cranelift-codegen-0.103.0}/src/write.rs +0 -0
  706. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/LICENSE +0 -0
  707. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/README.md +0 -0
  708. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/cdsl/formats.rs +0 -0
  709. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/cdsl/instructions.rs +0 -0
  710. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/cdsl/isa.rs +0 -0
  711. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/cdsl/mod.rs +0 -0
  712. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/cdsl/operands.rs +0 -0
  713. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/cdsl/settings.rs +0 -0
  714. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/cdsl/types.rs +0 -0
  715. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/cdsl/typevar.rs +0 -0
  716. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/constant_hash.rs +0 -0
  717. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/error.rs +0 -0
  718. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/gen_inst.rs +0 -0
  719. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/gen_settings.rs +0 -0
  720. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/gen_types.rs +0 -0
  721. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/isa/arm64.rs +0 -0
  722. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/isa/mod.rs +0 -0
  723. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/isa/riscv64.rs +0 -0
  724. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/isa/s390x.rs +0 -0
  725. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/isa/x86.rs +0 -0
  726. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/lib.rs +0 -0
  727. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/shared/entities.rs +0 -0
  728. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/shared/formats.rs +0 -0
  729. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/shared/immediates.rs +0 -0
  730. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/shared/instructions.rs +0 -0
  731. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/shared/mod.rs +0 -0
  732. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/shared/settings.rs +0 -0
  733. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/shared/types.rs +0 -0
  734. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/srcgen.rs +0 -0
  735. /data/ext/cargo-vendor/{cranelift-codegen-meta-0.102.1 → cranelift-codegen-meta-0.103.0}/src/unique_table.rs +0 -0
  736. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.102.1 → cranelift-codegen-shared-0.103.0}/LICENSE +0 -0
  737. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.102.1 → cranelift-codegen-shared-0.103.0}/README.md +0 -0
  738. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.102.1 → cranelift-codegen-shared-0.103.0}/src/constant_hash.rs +0 -0
  739. /data/ext/cargo-vendor/{cranelift-codegen-shared-0.102.1 → cranelift-codegen-shared-0.103.0}/src/constants.rs +0 -0
  740. /data/ext/cargo-vendor/{cranelift-control-0.102.1 → cranelift-control-0.103.0}/LICENSE +0 -0
  741. /data/ext/cargo-vendor/{cranelift-control-0.102.1 → cranelift-control-0.103.0}/README.md +0 -0
  742. /data/ext/cargo-vendor/{cranelift-control-0.102.1 → cranelift-control-0.103.0}/src/chaos.rs +0 -0
  743. /data/ext/cargo-vendor/{cranelift-control-0.102.1 → cranelift-control-0.103.0}/src/lib.rs +0 -0
  744. /data/ext/cargo-vendor/{cranelift-control-0.102.1 → cranelift-control-0.103.0}/src/zero_sized.rs +0 -0
  745. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/LICENSE +0 -0
  746. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/README.md +0 -0
  747. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/src/boxed_slice.rs +0 -0
  748. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/src/iter.rs +0 -0
  749. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/src/keys.rs +0 -0
  750. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/src/list.rs +0 -0
  751. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/src/map.rs +0 -0
  752. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/src/packed_option.rs +0 -0
  753. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/src/set.rs +0 -0
  754. /data/ext/cargo-vendor/{cranelift-entity-0.102.1 → cranelift-entity-0.103.0}/src/sparse.rs +0 -0
  755. /data/ext/cargo-vendor/{cranelift-frontend-0.102.1 → cranelift-frontend-0.103.0}/LICENSE +0 -0
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  757. /data/ext/cargo-vendor/{cranelift-frontend-0.102.1 → cranelift-frontend-0.103.0}/src/frontend.rs +0 -0
  758. /data/ext/cargo-vendor/{cranelift-frontend-0.102.1 → cranelift-frontend-0.103.0}/src/ssa.rs +0 -0
  759. /data/ext/cargo-vendor/{cranelift-frontend-0.102.1 → cranelift-frontend-0.103.0}/src/switch.rs +0 -0
  760. /data/ext/cargo-vendor/{cranelift-frontend-0.102.1 → cranelift-frontend-0.103.0}/src/variable.rs +0 -0
  761. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/README.md +0 -0
  762. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/build.rs +0 -0
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  764. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/fail/bound_var_type_mismatch.isle +0 -0
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  766. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/fail/error1.isle +0 -0
  767. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/fail/extra_parens.isle +0 -0
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  769. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/fail/impure_rhs.isle +0 -0
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  771. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/fail/multi_prio.isle +0 -0
  772. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/link/borrows.isle +0 -0
  773. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/link/borrows_main.rs +0 -0
  774. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/link/iflets.isle +0 -0
  775. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/link/iflets_main.rs +0 -0
  776. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/link/multi_constructor.isle +0 -0
  777. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/link/multi_extractor.isle +0 -0
  778. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/link/test.isle +0 -0
  779. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/link/test_main.rs +0 -0
  780. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/pass/bound_var.isle +0 -0
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  784. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/pass/let.isle +0 -0
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  786. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/pass/prio_trie_bug.isle +0 -0
  787. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/pass/test2.isle +0 -0
  788. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/pass/test3.isle +0 -0
  789. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/isle_examples/pass/test4.isle +0 -0
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  795. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/ast.rs +0 -0
  796. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/compile.rs +0 -0
  797. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/error.rs +0 -0
  798. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/lexer.rs +0 -0
  799. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/lib.rs +0 -0
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  801. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/overlap.rs +0 -0
  802. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/parser.rs +0 -0
  803. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/sema.rs +0 -0
  804. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/serialize.rs +0 -0
  805. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/src/trie_again.rs +0 -0
  806. /data/ext/cargo-vendor/{cranelift-isle-0.102.1 → cranelift-isle-0.103.0}/tests/run_tests.rs +0 -0
  807. /data/ext/cargo-vendor/{cranelift-native-0.102.1 → cranelift-native-0.103.0}/LICENSE +0 -0
  808. /data/ext/cargo-vendor/{cranelift-native-0.102.1 → cranelift-native-0.103.0}/README.md +0 -0
  809. /data/ext/cargo-vendor/{cranelift-native-0.102.1 → cranelift-native-0.103.0}/src/riscv.rs +0 -0
  810. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/LICENSE +0 -0
  811. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/README.md +0 -0
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  814. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/src/environ/mod.rs +0 -0
  815. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/src/environ/spec.rs +0 -0
  816. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/src/func_translator.rs +0 -0
  817. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/src/heap.rs +0 -0
  818. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/src/module_translator.rs +0 -0
  819. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/src/sections_translator.rs +0 -0
  820. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/src/state.rs +0 -0
  821. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/tests/wasm_testsuite.rs +0 -0
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  829. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/embenchen_primes.wat +0 -0
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  831. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/fibonacci.wat +0 -0
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  834. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/icall.wat +0 -0
  835. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/if-reachability-translation-0.wat +0 -0
  836. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/if-reachability-translation-1.wat +0 -0
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  843. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/if-unreachable-else-params.wat +0 -0
  844. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/issue-1306-name-section-with-u32-max-function-index.wasm +0 -0
  845. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/memory.wat +0 -0
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  848. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/multi-10.wat +0 -0
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  864. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/nullref.wat +0 -0
  865. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/passive-data.wat +0 -0
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  867. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/pr2559.wat +0 -0
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  869. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/rust_fannkuch.wat +0 -0
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  874. /data/ext/cargo-vendor/{cranelift-wasm-0.102.1 → cranelift-wasm-0.103.0}/wasmtests/unreachable_code.wat +0 -0
  875. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/LICENSE +0 -0
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  877. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/clocks.rs +0 -0
  878. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/dir.rs +0 -0
  879. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/file.rs +0 -0
  880. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/lib.rs +0 -0
  881. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/net.rs +0 -0
  882. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/sched/unix.rs +0 -0
  883. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/sched/windows.rs +0 -0
  884. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/sched.rs +0 -0
  885. /data/ext/cargo-vendor/{wasi-cap-std-sync-15.0.1 → wasi-cap-std-sync-16.0.0}/src/stdio.rs +0 -0
  886. /data/ext/cargo-vendor/{wasi-common-15.0.1 → wasi-common-16.0.0}/LICENSE +0 -0
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  1050. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/fact/transcode.rs +0 -0
  1051. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/fact/traps.rs +0 -0
  1052. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/fact.rs +0 -0
  1053. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/obj.rs +0 -0
  1054. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/ref_bits.rs +0 -0
  1055. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/stack_map.rs +0 -0
  1056. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/trap_encoding.rs +0 -0
  1057. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/tunables.rs +0 -0
  1058. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-environ-16.0.0}/src/vmoffsets.rs +0 -0
  1059. /data/ext/cargo-vendor/{wasmtime-cranelift-15.0.1 → wasmtime-fiber-16.0.0}/LICENSE +0 -0
  1060. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-fiber-16.0.0}/build.rs +0 -0
  1061. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-fiber-16.0.0}/src/unix/aarch64.rs +0 -0
  1062. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-fiber-16.0.0}/src/unix/arm.rs +0 -0
  1063. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-fiber-16.0.0}/src/unix/riscv64.rs +0 -0
  1064. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-fiber-16.0.0}/src/unix/s390x.S +0 -0
  1065. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-fiber-16.0.0}/src/unix/x86.rs +0 -0
  1066. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-fiber-16.0.0}/src/unix/x86_64.rs +0 -0
  1067. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-fiber-16.0.0}/src/windows.rs +0 -0
  1068. /data/ext/cargo-vendor/{wasmtime-environ-15.0.1 → wasmtime-jit-16.0.0}/LICENSE +0 -0
  1069. /data/ext/cargo-vendor/{wasmtime-jit-15.0.1 → wasmtime-jit-16.0.0}/src/debug.rs +0 -0
  1070. /data/ext/cargo-vendor/{wasmtime-jit-15.0.1 → wasmtime-jit-16.0.0}/src/demangling.rs +0 -0
  1071. /data/ext/cargo-vendor/{wasmtime-jit-15.0.1 → wasmtime-jit-16.0.0}/src/profiling/jitdump.rs +0 -0
  1072. /data/ext/cargo-vendor/{wasmtime-jit-15.0.1 → wasmtime-jit-16.0.0}/src/profiling/perfmap.rs +0 -0
  1073. /data/ext/cargo-vendor/{wasmtime-jit-15.0.1 → wasmtime-jit-16.0.0}/src/profiling/vtune.rs +0 -0
  1074. /data/ext/cargo-vendor/{wasmtime-jit-15.0.1 → wasmtime-jit-16.0.0}/src/profiling.rs +0 -0
  1075. /data/ext/cargo-vendor/{wasmtime-jit-debug-15.0.1 → wasmtime-jit-debug-16.0.0}/README.md +0 -0
  1076. /data/ext/cargo-vendor/{wasmtime-jit-debug-15.0.1 → wasmtime-jit-debug-16.0.0}/src/gdb_jit_int.rs +0 -0
  1077. /data/ext/cargo-vendor/{wasmtime-jit-debug-15.0.1 → wasmtime-jit-debug-16.0.0}/src/lib.rs +0 -0
  1078. /data/ext/cargo-vendor/{wasmtime-jit-debug-15.0.1 → wasmtime-jit-debug-16.0.0}/src/perf_jitdump.rs +0 -0
  1079. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-15.0.1 → wasmtime-jit-icache-coherence-16.0.0}/src/lib.rs +0 -0
  1080. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-15.0.1 → wasmtime-jit-icache-coherence-16.0.0}/src/libc.rs +0 -0
  1081. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-15.0.1 → wasmtime-jit-icache-coherence-16.0.0}/src/miri.rs +0 -0
  1082. /data/ext/cargo-vendor/{wasmtime-jit-icache-coherence-15.0.1 → wasmtime-jit-icache-coherence-16.0.0}/src/win.rs +0 -0
  1083. /data/ext/cargo-vendor/{wasmtime-fiber-15.0.1 → wasmtime-runtime-16.0.0}/LICENSE +0 -0
  1084. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1/src/trampolines → wasmtime-runtime-16.0.0/src/arch}/s390x.S +0 -0
  1085. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/component/libcalls.rs +0 -0
  1086. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/component/resources.rs +0 -0
  1087. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/component.rs +0 -0
  1088. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/debug_builtins.rs +0 -0
  1089. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/export.rs +0 -0
  1090. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/externref.rs +0 -0
  1091. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/imports.rs +0 -0
  1092. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/instance/allocator/on_demand.rs +0 -0
  1093. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/instance/allocator/pooling/index_allocator.rs +0 -0
  1094. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/instance/allocator.rs +0 -0
  1095. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/instance.rs +0 -0
  1096. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/memory.rs +0 -0
  1097. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/mmap_vec.rs +0 -0
  1098. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/module_id.rs +0 -0
  1099. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/mpk/disabled.rs +0 -0
  1100. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/mpk/mod.rs +0 -0
  1101. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/mpk/sys.rs +0 -0
  1102. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/parking_spot.rs +0 -0
  1103. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/send_sync_ptr.rs +0 -0
  1104. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/store_box.rs +0 -0
  1105. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1/src/mmap/miri.rs → wasmtime-runtime-16.0.0/src/sys/miri/mmap.rs} +0 -0
  1106. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1/src/mmap/unix.rs → wasmtime-runtime-16.0.0/src/sys/unix/mmap.rs} +0 -0
  1107. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1/src/mmap/windows.rs → wasmtime-runtime-16.0.0/src/sys/windows/mmap.rs} +0 -0
  1108. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/table.rs +0 -0
  1109. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/traphandlers/coredump.rs +0 -0
  1110. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-runtime-16.0.0}/src/vmcontext/vm_host_func_context.rs +0 -0
  1111. /data/ext/cargo-vendor/{wasmtime-jit-15.0.1 → wasmtime-types-16.0.0}/LICENSE +0 -0
  1112. /data/ext/cargo-vendor/{wasmtime-types-15.0.1 → wasmtime-types-16.0.0}/src/error.rs +0 -0
  1113. /data/ext/cargo-vendor/{wasmtime-versioned-export-macros-15.0.1 → wasmtime-versioned-export-macros-16.0.0}/src/lib.rs +0 -0
  1114. /data/ext/cargo-vendor/{wasmtime-runtime-15.0.1 → wasmtime-wasi-16.0.0}/LICENSE +0 -0
  1115. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/README.md +0 -0
  1116. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/build.rs +0 -0
  1117. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/clocks/host.rs +0 -0
  1118. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/clocks.rs +0 -0
  1119. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/command.rs +0 -0
  1120. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/ctx.rs +0 -0
  1121. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/error.rs +0 -0
  1122. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/filesystem.rs +0 -0
  1123. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/clocks.rs +0 -0
  1124. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/env.rs +0 -0
  1125. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/exit.rs +0 -0
  1126. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/filesystem/sync.rs +0 -0
  1127. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/filesystem.rs +0 -0
  1128. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/instance_network.rs +0 -0
  1129. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/mod.rs +0 -0
  1130. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/random.rs +0 -0
  1131. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/tcp_create_socket.rs +0 -0
  1132. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/host/udp_create_socket.rs +0 -0
  1133. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/ip_name_lookup.rs +0 -0
  1134. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/network.rs +0 -0
  1135. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/pipe.rs +0 -0
  1136. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/poll.rs +0 -0
  1137. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/random.rs +0 -0
  1138. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/stdio/worker_thread_stdin.rs +0 -0
  1139. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/tcp.rs +0 -0
  1140. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/udp.rs +0 -0
  1141. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/src/preview2/write_stream.rs +0 -0
  1142. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/cli/environment.wit +0 -0
  1143. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/cli/exit.wit +0 -0
  1144. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/cli/run.wit +0 -0
  1145. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/cli/stdio.wit +0 -0
  1146. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/cli/terminal.wit +0 -0
  1147. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/clocks/monotonic-clock.wit +0 -0
  1148. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/clocks/wall-clock.wit +0 -0
  1149. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/clocks/world.wit +0 -0
  1150. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/filesystem/preopens.wit +0 -0
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  1153. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/http/handler.wit +0 -0
  1154. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/io/error.wit +0 -0
  1155. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/io/poll.wit +0 -0
  1156. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/io/streams.wit +0 -0
  1157. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/io/world.wit +0 -0
  1158. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/random/insecure-seed.wit +0 -0
  1159. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/random/insecure.wit +0 -0
  1160. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/random/random.wit +0 -0
  1161. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/random/world.wit +0 -0
  1162. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/sockets/instance-network.wit +0 -0
  1163. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/sockets/ip-name-lookup.wit +0 -0
  1164. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/sockets/network.wit +0 -0
  1165. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/sockets/tcp-create-socket.wit +0 -0
  1166. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/sockets/tcp.wit +0 -0
  1167. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/sockets/udp-create-socket.wit +0 -0
  1168. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/sockets/udp.wit +0 -0
  1169. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wasmtime-wasi-16.0.0}/wit/deps/sockets/world.wit +0 -0
  1170. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1/witx → wasmtime-wasi-16.0.0/witx/preview1}/typenames.witx +0 -0
  1171. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1/witx → wasmtime-wasi-16.0.0/witx/preview1}/wasi_snapshot_preview1.witx +0 -0
  1172. /data/ext/cargo-vendor/{wasmtime-winch-15.0.1 → wasmtime-winch-16.0.0}/LICENSE +0 -0
  1173. /data/ext/cargo-vendor/{wasmtime-winch-15.0.1 → wasmtime-winch-16.0.0}/src/builder.rs +0 -0
  1174. /data/ext/cargo-vendor/{wasmtime-winch-15.0.1 → wasmtime-winch-16.0.0}/src/lib.rs +0 -0
  1175. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-15.0.1 → wasmtime-wit-bindgen-16.0.0}/src/lib.rs +0 -0
  1176. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-15.0.1 → wasmtime-wit-bindgen-16.0.0}/src/rust.rs +0 -0
  1177. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-15.0.1 → wasmtime-wit-bindgen-16.0.0}/src/source.rs +0 -0
  1178. /data/ext/cargo-vendor/{wasmtime-wit-bindgen-15.0.1 → wasmtime-wit-bindgen-16.0.0}/src/types.rs +0 -0
  1179. /data/ext/cargo-vendor/{wasmtime-wmemcheck-15.0.1 → wasmtime-wmemcheck-16.0.0}/src/lib.rs +0 -0
  1180. /data/ext/cargo-vendor/{wasmtime-types-15.0.1 → wiggle-16.0.0}/LICENSE +0 -0
  1181. /data/ext/cargo-vendor/{wiggle-15.0.1 → wiggle-16.0.0}/README.md +0 -0
  1182. /data/ext/cargo-vendor/{wiggle-15.0.1 → wiggle-16.0.0}/src/borrow.rs +0 -0
  1183. /data/ext/cargo-vendor/{wiggle-15.0.1 → wiggle-16.0.0}/src/error.rs +0 -0
  1184. /data/ext/cargo-vendor/{wiggle-15.0.1 → wiggle-16.0.0}/src/guest_type.rs +0 -0
  1185. /data/ext/cargo-vendor/{wiggle-15.0.1 → wiggle-16.0.0}/src/region.rs +0 -0
  1186. /data/ext/cargo-vendor/{wiggle-15.0.1 → wiggle-16.0.0}/src/wasmtime.rs +0 -0
  1187. /data/ext/cargo-vendor/{wasmtime-wasi-15.0.1 → wiggle-generate-16.0.0}/LICENSE +0 -0
  1188. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/README.md +0 -0
  1189. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/codegen_settings.rs +0 -0
  1190. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/config.rs +0 -0
  1191. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/funcs.rs +0 -0
  1192. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/lib.rs +0 -0
  1193. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/lifetimes.rs +0 -0
  1194. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/module_trait.rs +0 -0
  1195. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/names.rs +0 -0
  1196. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/types/error.rs +0 -0
  1197. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/types/flags.rs +0 -0
  1198. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/types/mod.rs +0 -0
  1199. /data/ext/cargo-vendor/{wiggle-generate-15.0.1 → wiggle-generate-16.0.0}/src/wasmtime.rs +0 -0
  1200. /data/ext/cargo-vendor/{wiggle-15.0.1 → wiggle-macro-16.0.0}/LICENSE +0 -0
  1201. /data/ext/cargo-vendor/{wiggle-macro-15.0.1 → wiggle-macro-16.0.0}/src/lib.rs +0 -0
  1202. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/LICENSE +0 -0
  1203. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/build.rs +0 -0
  1204. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/codegen/builtin.rs +0 -0
  1205. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/isa/aarch64/address.rs +0 -0
  1206. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/isa/aarch64/asm.rs +0 -0
  1207. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/isa/aarch64/regs.rs +0 -0
  1208. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/isa/reg.rs +0 -0
  1209. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/isa/x64/address.rs +0 -0
  1210. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/lib.rs +0 -0
  1211. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/regalloc.rs +0 -0
  1212. /data/ext/cargo-vendor/{winch-codegen-0.13.1 → winch-codegen-0.14.0}/src/regset.rs +0 -0
@@ -0,0 +1,2928 @@
1
+ ;; Instruction formats.
2
+ (type MInst
3
+ (enum
4
+ ;; A no-op of zero size.
5
+ (Nop0)
6
+ (Nop4)
7
+
8
+ ;; load immediate
9
+ (Lui
10
+ (rd WritableReg)
11
+ (imm Imm20))
12
+
13
+ (LoadInlineConst
14
+ (rd WritableReg)
15
+ (ty Type)
16
+ (imm u64))
17
+
18
+ (Auipc
19
+ (rd WritableReg)
20
+ (imm Imm20))
21
+
22
+ ;; An ALU operation with one register sources and a register destination.
23
+ (FpuRR
24
+ (alu_op FpuOPRR)
25
+ (frm FRM)
26
+ (rd WritableReg)
27
+ (rs Reg))
28
+
29
+
30
+ ;; An ALU operation with two register sources and a register destination.
31
+ (AluRRR
32
+ (alu_op AluOPRRR)
33
+ (rd WritableReg)
34
+ (rs1 Reg)
35
+ (rs2 Reg))
36
+
37
+ ;; An ALU operation with two register sources and a register destination.
38
+ (FpuRRR
39
+ (alu_op FpuOPRRR)
40
+ (frm FRM)
41
+ (rd WritableReg)
42
+ (rs1 Reg)
43
+ (rs2 Reg))
44
+
45
+ ;; An ALU operation with three register sources and a register destination.
46
+ (FpuRRRR
47
+ (alu_op FpuOPRRRR)
48
+ (frm FRM)
49
+ (rd WritableReg)
50
+ (rs1 Reg)
51
+ (rs2 Reg)
52
+ (rs3 Reg))
53
+
54
+ ;; An ALU operation with a register source and an immediate-12 source, and a register
55
+ ;; destination.
56
+ (AluRRImm12
57
+ (alu_op AluOPRRI)
58
+ (rd WritableReg)
59
+ (rs Reg)
60
+ (imm12 Imm12))
61
+
62
+ ;; A CSR Reading or Writing instruction with a register source and a register destination.
63
+ (CsrReg
64
+ (op CsrRegOP)
65
+ (rd WritableReg)
66
+ (rs Reg)
67
+ (csr CSR))
68
+
69
+ ;; A CSR Writing instruction with an immediate source and a register destination.
70
+ (CsrImm
71
+ (op CsrImmOP)
72
+ (rd WritableReg)
73
+ (imm UImm5)
74
+ (csr CSR))
75
+
76
+ ;; An load
77
+ (Load
78
+ (rd WritableReg)
79
+ (op LoadOP)
80
+ (flags MemFlags)
81
+ (from AMode))
82
+ ;; An Store
83
+ (Store
84
+ (to AMode)
85
+ (op StoreOP)
86
+ (flags MemFlags)
87
+ (src Reg))
88
+
89
+ ;; A pseudo-instruction that captures register arguments in vregs.
90
+ (Args
91
+ (args VecArgPair))
92
+
93
+ ;; A pseudo-instruction that moves vregs to return registers.
94
+ (Rets
95
+ (rets VecRetPair))
96
+
97
+ (Ret)
98
+
99
+ (Extend
100
+ (rd WritableReg)
101
+ (rn Reg)
102
+ (signed bool)
103
+ (from_bits u8)
104
+ (to_bits u8))
105
+
106
+ (Call
107
+ (info BoxCallInfo))
108
+
109
+ ;; A machine indirect-call instruction.
110
+ (CallInd
111
+ (info BoxCallIndInfo))
112
+
113
+ ;; A direct return-call macro instruction.
114
+ (ReturnCall
115
+ (callee BoxExternalName)
116
+ (info BoxReturnCallInfo))
117
+
118
+ ;; An indirect return-call macro instruction.
119
+ (ReturnCallInd
120
+ (callee Reg)
121
+ (info BoxReturnCallInfo))
122
+
123
+ ;; Emits a trap with the given trap code if the comparison succeeds
124
+ (TrapIf
125
+ (rs1 Reg)
126
+ (rs2 Reg)
127
+ (cc IntCC)
128
+ (trap_code TrapCode))
129
+
130
+ (Jal
131
+ ;; (rd WritableReg) don't use
132
+ (label MachLabel))
133
+
134
+ (CondBr
135
+ (taken CondBrTarget)
136
+ (not_taken CondBrTarget)
137
+ (kind IntegerCompare))
138
+
139
+ ;; Load an inline symbol reference.
140
+ (LoadExtName
141
+ (rd WritableReg)
142
+ (name BoxExternalName)
143
+ (offset i64))
144
+
145
+ ;; Load a TLS symbol address
146
+ (ElfTlsGetAddr
147
+ (rd WritableReg)
148
+ (name BoxExternalName))
149
+
150
+ ;; Load address referenced by `mem` into `rd`.
151
+ (LoadAddr
152
+ (rd WritableReg)
153
+ (mem AMode))
154
+
155
+ ;; Marker, no-op in generated code: SP "virtual offset" is adjusted. This
156
+ ;; controls how AMode::NominalSPOffset args are lowered.
157
+ (VirtualSPOffsetAdj
158
+ (amount i64))
159
+
160
+ ;; A MOV instruction. These are encoded as OrR's (AluRRR form) but we
161
+ ;; keep them separate at the `Inst` level for better pretty-printing
162
+ ;; and faster `is_move()` logic.
163
+ (Mov
164
+ (rd WritableReg)
165
+ (rm Reg)
166
+ (ty Type))
167
+
168
+ ;; A MOV instruction, but where the source register is a non-allocatable
169
+ ;; PReg. It's important that the register be non-allocatable, as regalloc2
170
+ ;; will not see it as used.
171
+ (MovFromPReg
172
+ (rd WritableReg)
173
+ (rm PReg))
174
+
175
+ (Fence
176
+ (pred FenceReq)
177
+ (succ FenceReq))
178
+
179
+ (EBreak)
180
+
181
+ ;; An instruction guaranteed to always be undefined and to trigger an illegal instruction at
182
+ ;; runtime.
183
+ (Udf
184
+ (trap_code TrapCode))
185
+ ;; a jump and link register operation
186
+ (Jalr
187
+ ;;Plain unconditional jumps (assembler pseudo-op J) are encoded as a JAL with rd=x0.
188
+ (rd WritableReg)
189
+ (base Reg)
190
+ (offset Imm12))
191
+
192
+ ;; atomic operations.
193
+ (Atomic
194
+ (op AtomicOP)
195
+ (rd WritableReg)
196
+ (addr Reg)
197
+ (src Reg)
198
+ (amo AMO))
199
+ ;; an atomic store
200
+ (AtomicStore
201
+ (src Reg)
202
+ (ty Type)
203
+ (p Reg))
204
+ ;; an atomic load.
205
+ (AtomicLoad
206
+ (rd WritableReg)
207
+ (ty Type)
208
+ (p Reg))
209
+
210
+ ;; an atomic nand need using loop to implement.
211
+ (AtomicRmwLoop
212
+ (offset Reg)
213
+ (op AtomicRmwOp)
214
+ (dst WritableReg)
215
+ (ty Type)
216
+ (p Reg)
217
+ (x Reg)
218
+ (t0 WritableReg))
219
+
220
+ ;; select x or y base on condition
221
+ (Select
222
+ (dst WritableValueRegs)
223
+ (condition IntegerCompare)
224
+ (x ValueRegs)
225
+ (y ValueRegs))
226
+
227
+ (BrTable
228
+ (index Reg)
229
+ (tmp1 WritableReg)
230
+ (tmp2 WritableReg)
231
+ (targets VecMachLabel))
232
+
233
+ ;; atomic compare and set operation
234
+ (AtomicCas
235
+ (offset Reg)
236
+ (t0 WritableReg)
237
+ (dst WritableReg)
238
+ (e Reg)
239
+ (addr Reg)
240
+ (v Reg)
241
+ (ty Type))
242
+
243
+ (RawData (data VecU8))
244
+
245
+ ;; An unwind pseudo-instruction.
246
+ (Unwind
247
+ (inst UnwindInst))
248
+
249
+ ;; A dummy use, useful to keep a value alive.
250
+ (DummyUse
251
+ (reg Reg))
252
+ ;;;
253
+ (FloatRound
254
+ (op FloatRoundOP)
255
+ (rd WritableReg)
256
+ (int_tmp WritableReg)
257
+ (f_tmp WritableReg)
258
+ (rs Reg)
259
+ (ty Type))
260
+
261
+ ;; popcnt if target doesn't support extension B
262
+ ;; use iteration to implement.
263
+ (Popcnt
264
+ (sum WritableReg)
265
+ (step WritableReg)
266
+ (tmp WritableReg)
267
+ (rs Reg)
268
+ (ty Type))
269
+
270
+ ;;; counting leading or trailing zeros.
271
+ (Cltz
272
+ ;; leading or trailing.
273
+ (leading bool)
274
+ (sum WritableReg)
275
+ (step WritableReg)
276
+ (tmp WritableReg)
277
+ (rs Reg)
278
+ (ty Type))
279
+
280
+ (Brev8
281
+ (rs Reg)
282
+ (ty Type)
283
+ (step WritableReg)
284
+ (tmp WritableReg)
285
+ (tmp2 WritableReg)
286
+ (rd WritableReg))
287
+ (StackProbeLoop
288
+ (guard_size u32)
289
+ (probe_count u32)
290
+ (tmp WritableReg))
291
+
292
+ (VecAluRRRR
293
+ (op VecAluOpRRRR)
294
+ (vd WritableReg)
295
+ (vd_src Reg)
296
+ (vs2 Reg)
297
+ (vs1 Reg)
298
+ (mask VecOpMasking)
299
+ (vstate VState))
300
+
301
+ (VecAluRRRImm5
302
+ (op VecAluOpRRRImm5)
303
+ (vd WritableReg)
304
+ (vd_src Reg)
305
+ (vs2 Reg)
306
+ (imm Imm5)
307
+ (mask VecOpMasking)
308
+ (vstate VState))
309
+
310
+ (VecAluRRR
311
+ (op VecAluOpRRR)
312
+ (vd WritableReg)
313
+ (vs2 Reg)
314
+ (vs1 Reg)
315
+ (mask VecOpMasking)
316
+ (vstate VState))
317
+
318
+ (VecAluRRImm5
319
+ (op VecAluOpRRImm5)
320
+ (vd WritableReg)
321
+ (vs2 Reg)
322
+ (imm Imm5)
323
+ (mask VecOpMasking)
324
+ (vstate VState))
325
+
326
+ (VecAluRR
327
+ (op VecAluOpRR)
328
+ (vd WritableReg)
329
+ (vs Reg)
330
+ (mask VecOpMasking)
331
+ (vstate VState))
332
+
333
+ (VecAluRImm5
334
+ (op VecAluOpRImm5)
335
+ (vd WritableReg)
336
+ (imm Imm5)
337
+ (mask VecOpMasking)
338
+ (vstate VState))
339
+
340
+ (VecSetState
341
+ (rd WritableReg)
342
+ (vstate VState))
343
+
344
+ (VecLoad
345
+ (eew VecElementWidth)
346
+ (to WritableReg)
347
+ (from VecAMode)
348
+ (flags MemFlags)
349
+ (mask VecOpMasking)
350
+ (vstate VState))
351
+
352
+ (VecStore
353
+ (eew VecElementWidth)
354
+ (to VecAMode)
355
+ (from Reg)
356
+ (flags MemFlags)
357
+ (mask VecOpMasking)
358
+ (vstate VState))
359
+ ))
360
+
361
+
362
+ (type FloatRoundOP (enum
363
+ (Nearest)
364
+ (Ceil)
365
+ (Floor)
366
+ (Trunc)
367
+ ))
368
+
369
+ (type AtomicOP (enum
370
+ (LrW)
371
+ (ScW)
372
+ (AmoswapW)
373
+ (AmoaddW)
374
+ (AmoxorW)
375
+ (AmoandW)
376
+ (AmoorW)
377
+ (AmominW)
378
+ (AmomaxW)
379
+ (AmominuW)
380
+ (AmomaxuW)
381
+ (LrD)
382
+ (ScD)
383
+ (AmoswapD)
384
+ (AmoaddD)
385
+ (AmoxorD)
386
+ (AmoandD)
387
+ (AmoorD)
388
+ (AmominD)
389
+ (AmomaxD)
390
+ (AmominuD)
391
+ (AmomaxuD)
392
+ ))
393
+
394
+ (type FpuOPRRRR (enum
395
+ ;; float32
396
+ (FmaddS)
397
+ (FmsubS)
398
+ (FnmsubS)
399
+ (FnmaddS)
400
+ ;; float64
401
+ (FmaddD)
402
+ (FmsubD)
403
+ (FnmsubD)
404
+ (FnmaddD)
405
+ ))
406
+
407
+ (type FClassResult (enum
408
+ ;;0 rs1 is −∞.
409
+ (NegInfinite)
410
+ ;; 1 rs1 is a negative normal number.
411
+ (NegNormal)
412
+ ;; 2 rs1 is a negative subnormal number.
413
+ (NegSubNormal)
414
+ ;; 3 rs1 is −0.
415
+ (NegZero)
416
+ ;; 4 rs1 is +0.
417
+ (PosZero)
418
+ ;; 5 rs1 is a positive subnormal number.
419
+ (PosSubNormal)
420
+ ;; 6 rs1 is a positive normal number.
421
+ (PosNormal)
422
+ ;; 7 rs1 is +∞.
423
+ (PosInfinite)
424
+ ;; 8 rs1 is a signaling NaN.
425
+ (SNaN)
426
+ ;; 9 rs1 is a quiet NaN.
427
+ (QNaN)
428
+ ))
429
+
430
+ (type FpuOPRR (enum
431
+ ;; RV32F Standard Extension
432
+ (FsqrtS)
433
+ (FcvtWS)
434
+ (FcvtWuS)
435
+ (FmvXW)
436
+ (FclassS)
437
+ (FcvtSw)
438
+ (FcvtSwU)
439
+ (FmvWX)
440
+
441
+
442
+ ;; RV64F Standard Extension (in addition to RV32F)
443
+ (FcvtLS)
444
+ (FcvtLuS)
445
+ (FcvtSL)
446
+ (FcvtSLU)
447
+
448
+
449
+ ;; RV64D Standard Extension (in addition to RV32D)
450
+ (FcvtLD)
451
+ (FcvtLuD)
452
+ (FmvXD)
453
+ (FcvtDL)
454
+ (FcvtDLu)
455
+ (FmvDX)
456
+
457
+ ;; RV32D Standard Extension
458
+ (FsqrtD)
459
+ (FcvtSD)
460
+ (FcvtDS)
461
+ (FclassD)
462
+ (FcvtWD)
463
+ (FcvtWuD)
464
+ (FcvtDW)
465
+ (FcvtDWU)
466
+ ;; bitmapip
467
+
468
+ ))
469
+
470
+ (type LoadOP (enum
471
+ (Lb)
472
+ (Lh)
473
+ (Lw)
474
+ (Lbu)
475
+ (Lhu)
476
+ (Lwu)
477
+ (Ld)
478
+ (Flw)
479
+ (Fld)
480
+ ))
481
+
482
+ (type StoreOP (enum
483
+ (Sb)
484
+ (Sh)
485
+ (Sw)
486
+ (Sd)
487
+ (Fsw)
488
+ (Fsd)
489
+ ))
490
+
491
+ (type AluOPRRR (enum
492
+ ;; base set
493
+ (Add)
494
+ (Sub)
495
+ (Sll)
496
+ (Slt)
497
+ (SltU)
498
+ (Sgt)
499
+ (Sgtu)
500
+ (Xor)
501
+ (Srl)
502
+ (Sra)
503
+ (Or)
504
+ (And)
505
+
506
+ ;; RV64I Base Instruction Set (in addition to RV32I)
507
+ (Addw)
508
+ (Subw)
509
+ (Sllw)
510
+ (Srlw)
511
+ (Sraw)
512
+
513
+
514
+ ;;RV32M Standard Extension
515
+ (Mul)
516
+ (Mulh)
517
+ (Mulhsu)
518
+ (Mulhu)
519
+ (Div)
520
+ (DivU)
521
+ (Rem)
522
+ (RemU)
523
+
524
+ ;; RV64M Standard Extension (in addition to RV32M)
525
+ (Mulw)
526
+ (Divw)
527
+ (Divuw)
528
+ (Remw)
529
+ (Remuw)
530
+
531
+ ;; Zba: Address Generation Instructions
532
+ (Adduw)
533
+ (Sh1add)
534
+ (Sh1adduw)
535
+ (Sh2add)
536
+ (Sh2adduw)
537
+ (Sh3add)
538
+ (Sh3adduw)
539
+
540
+ ;; Zbb: Bit Manipulation Instructions
541
+ (Andn)
542
+ (Orn)
543
+ (Xnor)
544
+ (Max)
545
+ (Maxu)
546
+ (Min)
547
+ (Minu)
548
+ (Rol)
549
+ (Rolw)
550
+ (Ror)
551
+ (Rorw)
552
+
553
+ ;; Zbs: Single-bit instructions
554
+ (Bclr)
555
+ (Bext)
556
+ (Binv)
557
+ (Bset)
558
+
559
+ ;; Zbc: Carry-less multiplication
560
+ (Clmul)
561
+ (Clmulh)
562
+ (Clmulr)
563
+
564
+ ;; Zbkb: Bit-manipulation for Cryptography
565
+ (Pack)
566
+ (Packw)
567
+ (Packh)
568
+ ))
569
+
570
+
571
+ (type FpuOPRRR (enum
572
+ ;; RV32F Standard Extension
573
+ (FaddS)
574
+ (FsubS)
575
+ (FmulS)
576
+ (FdivS)
577
+
578
+ (FsgnjS)
579
+ (FsgnjnS)
580
+ (FsgnjxS)
581
+ (FminS)
582
+ (FmaxS)
583
+ (FeqS)
584
+ (FltS)
585
+ (FleS)
586
+
587
+ ;; RV32D Standard Extension
588
+ (FaddD)
589
+ (FsubD)
590
+ (FmulD)
591
+ (FdivD)
592
+ (FsgnjD)
593
+ (FsgnjnD)
594
+ (FsgnjxD)
595
+ (FminD)
596
+ (FmaxD)
597
+ (FeqD)
598
+ (FltD)
599
+ (FleD)
600
+ ))
601
+
602
+
603
+
604
+ (type AluOPRRI (enum
605
+ ;; Base ISA
606
+ (Addi)
607
+ (Slti)
608
+ (SltiU)
609
+ (Xori)
610
+ (Ori)
611
+ (Andi)
612
+ (Slli)
613
+ (Srli)
614
+ (Srai)
615
+ (Addiw)
616
+ (Slliw)
617
+ (SrliW)
618
+ (Sraiw)
619
+
620
+ ;; Zba: Address Generation Instructions
621
+ (SlliUw)
622
+
623
+ ;; Zbb: Bit Manipulation Instructions
624
+ (Clz)
625
+ (Clzw)
626
+ (Ctz)
627
+ (Ctzw)
628
+ (Cpop)
629
+ (Cpopw)
630
+ (Sextb)
631
+ (Sexth)
632
+ (Zexth)
633
+ (Rori)
634
+ (Roriw)
635
+ (Rev8)
636
+ (Brev8)
637
+ (Orcb)
638
+
639
+ ;; Zbs: Single-bit instructions
640
+ (Bclri)
641
+ (Bexti)
642
+ (Binvi)
643
+ (Bseti)
644
+ ))
645
+
646
+ (type COpcodeSpace (enum
647
+ (C0)
648
+ (C1)
649
+ (C2)
650
+ ))
651
+
652
+ ;; Opcodes for the CR compressed instruction format
653
+ (type CrOp (enum
654
+ (CMv)
655
+ (CAdd)
656
+ (CJr)
657
+ (CJalr)
658
+ ;; c.ebreak technically isn't a CR format instruction, but it's encoding
659
+ ;; lines up with this format.
660
+ (CEbreak)
661
+ ))
662
+
663
+ ;; Opcodes for the CA compressed instruction format
664
+ (type CaOp (enum
665
+ (CAnd)
666
+ (COr)
667
+ (CXor)
668
+ (CSub)
669
+ (CAddw)
670
+ (CSubw)
671
+ (CMul)
672
+ ))
673
+
674
+ ;; Opcodes for the CJ compressed instruction format
675
+ (type CjOp (enum
676
+ (CJ)
677
+ ))
678
+
679
+ ;; Opcodes for the CI compressed instruction format
680
+ (type CiOp (enum
681
+ (CAddi)
682
+ (CAddiw)
683
+ (CAddi16sp)
684
+ (CSlli)
685
+ (CLi)
686
+ (CLui)
687
+ (CLwsp)
688
+ (CLdsp)
689
+ (CFldsp)
690
+ ))
691
+
692
+ ;; Opcodes for the CIW compressed instruction format
693
+ (type CiwOp (enum
694
+ (CAddi4spn)
695
+ ))
696
+
697
+ ;; Opcodes for the CB compressed instruction format
698
+ (type CbOp (enum
699
+ (CSrli)
700
+ (CSrai)
701
+ (CAndi)
702
+ ))
703
+
704
+ ;; Opcodes for the CSS compressed instruction format
705
+ (type CssOp (enum
706
+ (CSwsp)
707
+ (CSdsp)
708
+ (CFsdsp)
709
+ ))
710
+
711
+ ;; Opcodes for the CS compressed instruction format
712
+ (type CsOp (enum
713
+ (CSw)
714
+ (CSd)
715
+ (CFsd)
716
+ ))
717
+
718
+ ;; Opcodes for the CL compressed instruction format
719
+ (type ClOp (enum
720
+ (CLw)
721
+ (CLd)
722
+ (CFld)
723
+ ))
724
+
725
+ ;; Opcodes for the CSZN compressed instruction format
726
+ (type CsznOp (enum
727
+ (CNot)
728
+ (CZextb)
729
+ (CZexth)
730
+ (CZextw)
731
+ (CSextb)
732
+ (CSexth)
733
+ ))
734
+
735
+ ;; This is a mix of all Zcb memory adressing instructions
736
+ ;;
737
+ ;; Technically they are split across 4 different formats.
738
+ ;; But they are all very similar, so we just group them all together.
739
+ (type ZcbMemOp (enum
740
+ (CLbu)
741
+ (CLhu)
742
+ (CLh)
743
+ (CSb)
744
+ (CSh)
745
+ ))
746
+
747
+
748
+ (type CsrRegOP (enum
749
+ ;; Atomic Read/Write CSR
750
+ (CsrRW)
751
+ ;; Atomic Read and Set Bits in CSR
752
+ (CsrRS)
753
+ ;; Atomic Read and Clear Bits in CSR
754
+ (CsrRC)
755
+ ))
756
+
757
+ (type CsrImmOP (enum
758
+ ;; Atomic Read/Write CSR (Immediate Source)
759
+ (CsrRWI)
760
+ ;; Atomic Read and Set Bits in CSR (Immediate Source)
761
+ (CsrRSI)
762
+ ;; Atomic Read and Clear Bits in CSR (Immediate Source)
763
+ (CsrRCI)
764
+ ))
765
+
766
+ ;; Enum of the known CSR registers
767
+ (type CSR (enum
768
+ ;; Floating-Point Dynamic Rounding Mode
769
+ (Frm)
770
+ ))
771
+
772
+
773
+ (type FRM (enum
774
+ ;; Round to Nearest, ties to Even
775
+ (RNE)
776
+ ;; Round towards Zero
777
+ (RTZ)
778
+ ;; Round Down (towards −∞)
779
+ (RDN)
780
+ ;; Round Up (towards +∞)
781
+ (RUP)
782
+ ;; Round to Nearest, ties to Max Magnitude
783
+ (RMM)
784
+ ;; In instruction’s rm field, selects dynamic rounding mode;
785
+ ;;In Rounding Mode register, Invalid.
786
+ (Fcsr)
787
+ ))
788
+
789
+ (decl pure frm_bits (FRM) UImm5)
790
+ (extern constructor frm_bits frm_bits)
791
+ (convert FRM UImm5 frm_bits)
792
+
793
+ (type FFlagsException (enum
794
+ ;; Invalid Operation
795
+ (NV)
796
+ ;; Divide by Zero
797
+ (DZ)
798
+ ;; Overflow
799
+ (OF)
800
+ ;; Underflow
801
+ (UF)
802
+ ;; Inexact
803
+ (NX)
804
+ ))
805
+
806
+ ;;;; input output read write
807
+ ;;;; SI SO SR SW
808
+ ;;;; PI PO PR PW
809
+ ;;;; lowest four bit are used.
810
+ (type FenceReq (primitive u8))
811
+
812
+ (type BoxCallInfo (primitive BoxCallInfo))
813
+ (type BoxCallIndInfo (primitive BoxCallIndInfo))
814
+ (type BoxReturnCallInfo (primitive BoxReturnCallInfo))
815
+ (type IntegerCompare (primitive IntegerCompare))
816
+ (type AMode (primitive AMode))
817
+ (type OptionReg (primitive OptionReg))
818
+ (type OptionImm12 (primitive OptionImm12))
819
+ (type OptionUimm5 (primitive OptionUimm5))
820
+ (type Imm12 (primitive Imm12))
821
+ (type UImm5 (primitive UImm5))
822
+ (type Imm5 (primitive Imm5))
823
+ (type Imm20 (primitive Imm20))
824
+ (type Imm3 (primitive Imm3))
825
+ (type CondBrTarget (primitive CondBrTarget))
826
+ (type VecU8 (primitive VecU8))
827
+ (type AMO (primitive AMO))
828
+ (type VecMachLabel extern (enum))
829
+
830
+
831
+ ;;;; Newtypes for Different Register Classes ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
832
+
833
+ (type XReg (primitive XReg))
834
+ (type WritableXReg (primitive WritableXReg))
835
+ (type FReg (primitive FReg))
836
+ (type WritableFReg (primitive WritableFReg))
837
+ (type VReg (primitive VReg))
838
+ (type WritableVReg (primitive WritableVReg))
839
+
840
+ ;; Construct a new `XReg` from a `Reg`.
841
+ ;;
842
+ ;; Asserts that the register has a Integer RegClass.
843
+ (decl xreg_new (Reg) XReg)
844
+ (extern constructor xreg_new xreg_new)
845
+ (convert Reg XReg xreg_new)
846
+
847
+ ;; Construct a new `WritableXReg` from a `WritableReg`.
848
+ ;;
849
+ ;; Asserts that the register has a Integer RegClass.
850
+ (decl writable_xreg_new (WritableReg) WritableXReg)
851
+ (extern constructor writable_xreg_new writable_xreg_new)
852
+ (convert WritableReg WritableXReg writable_xreg_new)
853
+
854
+ ;; Put a value into a XReg.
855
+ ;;
856
+ ;; Asserts that the value goes into a XReg.
857
+ (decl put_in_xreg (Value) XReg)
858
+ (rule (put_in_xreg val) (xreg_new (put_in_reg val)))
859
+ (convert Value XReg put_in_xreg)
860
+
861
+ ;; Construct an `InstOutput` out of a single XReg register.
862
+ (decl output_xreg (XReg) InstOutput)
863
+ (rule (output_xreg x) (output_reg x))
864
+ (convert XReg InstOutput output_xreg)
865
+
866
+ ;; Convert a `WritableXReg` to an `XReg`.
867
+ (decl pure writable_xreg_to_xreg (WritableXReg) XReg)
868
+ (extern constructor writable_xreg_to_xreg writable_xreg_to_xreg)
869
+ (convert WritableXReg XReg writable_xreg_to_xreg)
870
+
871
+ ;; Convert a `WritableXReg` to an `WritableReg`.
872
+ (decl pure writable_xreg_to_writable_reg (WritableXReg) WritableReg)
873
+ (extern constructor writable_xreg_to_writable_reg writable_xreg_to_writable_reg)
874
+ (convert WritableXReg WritableReg writable_xreg_to_writable_reg)
875
+
876
+ ;; Convert a `WritableXReg` to an `Reg`.
877
+ (decl pure writable_xreg_to_reg (WritableXReg) Reg)
878
+ (rule (writable_xreg_to_reg x) (writable_xreg_to_writable_reg x))
879
+ (convert WritableXReg Reg writable_xreg_to_reg)
880
+
881
+ ;; Convert an `XReg` to a `Reg`.
882
+ (decl pure xreg_to_reg (XReg) Reg)
883
+ (extern constructor xreg_to_reg xreg_to_reg)
884
+ (convert XReg Reg xreg_to_reg)
885
+
886
+ ;; Convert a `XReg` to a `ValueRegs`.
887
+ (decl xreg_to_value_regs (XReg) ValueRegs)
888
+ (rule (xreg_to_value_regs x) (value_reg x))
889
+ (convert XReg ValueRegs xreg_to_reg)
890
+
891
+ ;; Convert a `WritableXReg` to a `ValueRegs`.
892
+ (decl writable_xreg_to_value_regs (WritableXReg) ValueRegs)
893
+ (rule (writable_xreg_to_value_regs x) (value_reg x))
894
+ (convert WritableXReg ValueRegs writable_xreg_to_value_regs)
895
+
896
+ ;; Allocates a new `WritableXReg`.
897
+ (decl temp_writable_xreg () WritableXReg)
898
+ (rule (temp_writable_xreg) (temp_writable_reg $I64))
899
+
900
+
901
+ ;; Construct a new `FReg` from a `Reg`.
902
+ ;;
903
+ ;; Asserts that the register has a Float RegClass.
904
+ (decl freg_new (Reg) FReg)
905
+ (extern constructor freg_new freg_new)
906
+ (convert Reg FReg freg_new)
907
+
908
+ ;; Construct a new `WritableFReg` from a `WritableReg`.
909
+ ;;
910
+ ;; Asserts that the register has a Float RegClass.
911
+ (decl writable_freg_new (WritableReg) WritableFReg)
912
+ (extern constructor writable_freg_new writable_freg_new)
913
+ (convert WritableReg WritableFReg writable_freg_new)
914
+
915
+ ;; Put a value into a FReg.
916
+ ;;
917
+ ;; Asserts that the value goes into a FReg.
918
+ (decl put_in_freg (Value) FReg)
919
+ (rule (put_in_freg val) (freg_new (put_in_reg val)))
920
+ (convert Value FReg put_in_freg)
921
+
922
+ ;; Construct an `InstOutput` out of a single FReg register.
923
+ (decl output_freg (FReg) InstOutput)
924
+ (rule (output_freg x) (output_reg x))
925
+ (convert FReg InstOutput output_freg)
926
+
927
+ ;; Convert a `WritableFReg` to an `FReg`.
928
+ (decl pure writable_freg_to_freg (WritableFReg) FReg)
929
+ (extern constructor writable_freg_to_freg writable_freg_to_freg)
930
+ (convert WritableFReg FReg writable_freg_to_freg)
931
+
932
+ ;; Convert a `WritableFReg` to an `WritableReg`.
933
+ (decl pure writable_freg_to_writable_reg (WritableFReg) WritableReg)
934
+ (extern constructor writable_freg_to_writable_reg writable_freg_to_writable_reg)
935
+ (convert WritableFReg WritableReg writable_freg_to_writable_reg)
936
+
937
+ ;; Convert a `WritableFReg` to an `Reg`.
938
+ (decl pure writable_freg_to_reg (WritableFReg) Reg)
939
+ (rule (writable_freg_to_reg x) (writable_freg_to_writable_reg x))
940
+ (convert WritableFReg Reg writable_freg_to_reg)
941
+
942
+ ;; Convert an `FReg` to a `Reg`.
943
+ (decl pure freg_to_reg (FReg) Reg)
944
+ (extern constructor freg_to_reg freg_to_reg)
945
+ (convert FReg Reg freg_to_reg)
946
+
947
+ ;; Convert a `FReg` to a `ValueRegs`.
948
+ (decl freg_to_value_regs (FReg) ValueRegs)
949
+ (rule (freg_to_value_regs x) (value_reg x))
950
+ (convert FReg ValueRegs xreg_to_reg)
951
+
952
+ ;; Convert a `WritableFReg` to a `ValueRegs`.
953
+ (decl writable_freg_to_value_regs (WritableFReg) ValueRegs)
954
+ (rule (writable_freg_to_value_regs x) (value_reg x))
955
+ (convert WritableFReg ValueRegs writable_freg_to_value_regs)
956
+
957
+ ;; Allocates a new `WritableFReg`.
958
+ (decl temp_writable_freg () WritableFReg)
959
+ (rule (temp_writable_freg) (temp_writable_reg $F64))
960
+
961
+
962
+
963
+ ;; Construct a new `VReg` from a `Reg`.
964
+ ;;
965
+ ;; Asserts that the register has a Vector RegClass.
966
+ (decl vreg_new (Reg) VReg)
967
+ (extern constructor vreg_new vreg_new)
968
+ (convert Reg VReg vreg_new)
969
+
970
+ ;; Construct a new `WritableVReg` from a `WritableReg`.
971
+ ;;
972
+ ;; Asserts that the register has a Vector RegClass.
973
+ (decl writable_vreg_new (WritableReg) WritableVReg)
974
+ (extern constructor writable_vreg_new writable_vreg_new)
975
+ (convert WritableReg WritableVReg writable_vreg_new)
976
+
977
+ ;; Put a value into a VReg.
978
+ ;;
979
+ ;; Asserts that the value goes into a VReg.
980
+ (decl put_in_vreg (Value) VReg)
981
+ (rule (put_in_vreg val) (vreg_new (put_in_reg val)))
982
+ (convert Value VReg put_in_vreg)
983
+
984
+ ;; Construct an `InstOutput` out of a single VReg register.
985
+ (decl output_vreg (VReg) InstOutput)
986
+ (rule (output_vreg x) (output_reg x))
987
+ (convert VReg InstOutput output_vreg)
988
+
989
+ ;; Convert a `WritableVReg` to an `VReg`.
990
+ (decl pure writable_vreg_to_vreg (WritableVReg) VReg)
991
+ (extern constructor writable_vreg_to_vreg writable_vreg_to_vreg)
992
+ (convert WritableVReg VReg writable_vreg_to_vreg)
993
+
994
+ ;; Convert a `WritableVReg` to an `WritableReg`.
995
+ (decl pure writable_vreg_to_writable_reg (WritableVReg) WritableReg)
996
+ (extern constructor writable_vreg_to_writable_reg writable_vreg_to_writable_reg)
997
+ (convert WritableVReg WritableReg writable_vreg_to_writable_reg)
998
+
999
+ ;; Convert a `WritableVReg` to an `Reg`.
1000
+ (decl pure writable_vreg_to_reg (WritableVReg) Reg)
1001
+ (rule (writable_vreg_to_reg x) (writable_vreg_to_writable_reg x))
1002
+ (convert WritableVReg Reg writable_vreg_to_reg)
1003
+
1004
+ ;; Convert an `VReg` to a `Reg`.
1005
+ (decl pure vreg_to_reg (VReg) Reg)
1006
+ (extern constructor vreg_to_reg vreg_to_reg)
1007
+ (convert VReg Reg vreg_to_reg)
1008
+
1009
+ ;; Convert a `VReg` to a `ValueRegs`.
1010
+ (decl vreg_to_value_regs (VReg) ValueRegs)
1011
+ (rule (vreg_to_value_regs x) (value_reg x))
1012
+ (convert VReg ValueRegs xreg_to_reg)
1013
+
1014
+ ;; Convert a `WritableVReg` to a `ValueRegs`.
1015
+ (decl writable_vreg_to_value_regs (WritableVReg) ValueRegs)
1016
+ (rule (writable_vreg_to_value_regs x) (value_reg x))
1017
+ (convert WritableVReg ValueRegs writable_vreg_to_value_regs)
1018
+
1019
+ ;; Allocates a new `WritableVReg`.
1020
+ (decl temp_writable_vreg () WritableVReg)
1021
+ (rule (temp_writable_vreg) (temp_writable_reg $I8X16))
1022
+
1023
+
1024
+ ;; Converters
1025
+
1026
+ (convert u8 i32 u8_as_i32)
1027
+ (decl u8_as_i32 (u8) i32)
1028
+ (extern constructor u8_as_i32 u8_as_i32)
1029
+
1030
+ ;; ISA Extension helpers
1031
+
1032
+ (decl pure has_m () bool)
1033
+ (extern constructor has_m has_m)
1034
+
1035
+ (decl pure has_v () bool)
1036
+ (extern constructor has_v has_v)
1037
+
1038
+ (decl pure has_zbkb () bool)
1039
+ (extern constructor has_zbkb has_zbkb)
1040
+
1041
+ (decl pure has_zba () bool)
1042
+ (extern constructor has_zba has_zba)
1043
+
1044
+ (decl pure has_zbb () bool)
1045
+ (extern constructor has_zbb has_zbb)
1046
+
1047
+ (decl pure has_zbc () bool)
1048
+ (extern constructor has_zbc has_zbc)
1049
+
1050
+ (decl pure has_zbs () bool)
1051
+ (extern constructor has_zbs has_zbs)
1052
+
1053
+ (decl gen_float_round (FloatRoundOP Reg Type) Reg)
1054
+ (rule
1055
+ (gen_float_round op rs ty)
1056
+ (let
1057
+ ((rd WritableReg (temp_writable_reg ty))
1058
+ (tmp WritableXReg (temp_writable_xreg))
1059
+ (tmp2 WritableFReg (temp_writable_freg))
1060
+ (_ Unit (emit (MInst.FloatRound op rd tmp tmp2 rs ty))))
1061
+ (writable_reg_to_reg rd)))
1062
+
1063
+
1064
+ ;;;; Instruction Helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1065
+
1066
+ ;; RV32I Base Integer Instruction Set
1067
+
1068
+ ;; Helper for emitting the `add` instruction.
1069
+ ;; rd ← rs1 + rs2
1070
+ (decl rv_add (XReg XReg) XReg)
1071
+ (rule (rv_add rs1 rs2)
1072
+ (alu_rrr (AluOPRRR.Add) rs1 rs2))
1073
+
1074
+ ;; Helper for emitting the `addi` ("Add Immediate") instruction.
1075
+ ;; rd ← rs1 + sext(imm)
1076
+ (decl rv_addi (XReg Imm12) XReg)
1077
+ (rule (rv_addi rs1 imm)
1078
+ (alu_rr_imm12 (AluOPRRI.Addi) rs1 imm))
1079
+
1080
+ ;; Helper for emitting the `sub` instruction.
1081
+ ;; rd ← rs1 - rs2
1082
+ (decl rv_sub (XReg XReg) XReg)
1083
+ (rule (rv_sub rs1 rs2)
1084
+ (alu_rrr (AluOPRRR.Sub) rs1 rs2))
1085
+
1086
+ ;; Helper for emitting the `neg` instruction.
1087
+ ;; This instruction is a mnemonic for `sub rd, zero, rs1`.
1088
+ (decl rv_neg (XReg) XReg)
1089
+ (rule (rv_neg rs1)
1090
+ (alu_rrr (AluOPRRR.Sub) (zero_reg) rs1))
1091
+
1092
+ ;; Helper for emitting the `sll` ("Shift Left Logical") instruction.
1093
+ ;; rd ← rs1 << rs2
1094
+ (decl rv_sll (XReg XReg) XReg)
1095
+ (rule (rv_sll rs1 rs2)
1096
+ (alu_rrr (AluOPRRR.Sll) rs1 rs2))
1097
+
1098
+ ;; Helper for emitting the `slli` ("Shift Left Logical Immediate") instruction.
1099
+ ;; rd ← rs1 << uext(imm)
1100
+ (decl rv_slli (XReg Imm12) XReg)
1101
+ (rule (rv_slli rs1 imm)
1102
+ (alu_rr_imm12 (AluOPRRI.Slli) rs1 imm))
1103
+
1104
+ ;; Helper for emitting the `srl` ("Shift Right Logical") instruction.
1105
+ ;; rd ← rs1 >> rs2
1106
+ (decl rv_srl (XReg XReg) XReg)
1107
+ (rule (rv_srl rs1 rs2)
1108
+ (alu_rrr (AluOPRRR.Srl) rs1 rs2))
1109
+
1110
+ ;; Helper for emitting the `srli` ("Shift Right Logical Immediate") instruction.
1111
+ ;; rd ← rs1 >> uext(imm)
1112
+ (decl rv_srli (XReg Imm12) XReg)
1113
+ (rule (rv_srli rs1 imm)
1114
+ (alu_rr_imm12 (AluOPRRI.Srli) rs1 imm))
1115
+
1116
+ ;; Helper for emitting the `sra` ("Shift Right Arithmetic") instruction.
1117
+ ;; rd ← rs1 >> rs2
1118
+ (decl rv_sra (XReg XReg) XReg)
1119
+ (rule (rv_sra rs1 rs2)
1120
+ (alu_rrr (AluOPRRR.Sra) rs1 rs2))
1121
+
1122
+ ;; Helper for emitting the `srai` ("Shift Right Arithmetic Immediate") instruction.
1123
+ ;; rd ← rs1 >> uext(imm)
1124
+ (decl rv_srai (XReg Imm12) XReg)
1125
+ (rule (rv_srai rs1 imm)
1126
+ (alu_rr_imm12 (AluOPRRI.Srai) rs1 imm))
1127
+
1128
+ ;; Helper for emitting the `or` instruction.
1129
+ ;; rd ← rs1 ∨ rs2
1130
+ (decl rv_or (XReg XReg) XReg)
1131
+ (rule (rv_or rs1 rs2)
1132
+ (alu_rrr (AluOPRRR.Or) rs1 rs2))
1133
+
1134
+ ;; Helper for emitting the `ori` ("Or Immediate") instruction.
1135
+ ;; rd ← rs1 ∨ uext(imm)
1136
+ (decl rv_ori (XReg Imm12) XReg)
1137
+ (rule (rv_ori rs1 imm)
1138
+ (alu_rr_imm12 (AluOPRRI.Ori) rs1 imm))
1139
+
1140
+ ;; Helper for emitting the `xor` instruction.
1141
+ ;; rd ← rs1 ⊕ rs2
1142
+ (decl rv_xor (XReg XReg) XReg)
1143
+ (rule (rv_xor rs1 rs2)
1144
+ (alu_rrr (AluOPRRR.Xor) rs1 rs2))
1145
+
1146
+ ;; Helper for emitting the `xori` ("Exlusive Or Immediate") instruction.
1147
+ ;; rd ← rs1 ⊕ uext(imm)
1148
+ (decl rv_xori (XReg Imm12) XReg)
1149
+ (rule (rv_xori rs1 imm)
1150
+ (alu_rr_imm12 (AluOPRRI.Xori) rs1 imm))
1151
+
1152
+ ;; Helper for emitting the `not` instruction.
1153
+ ;; This instruction is a mnemonic for `xori rd, rs1, -1`.
1154
+ (decl rv_not (XReg) XReg)
1155
+ (rule (rv_not rs1)
1156
+ (rv_xori rs1 (imm12_const -1)))
1157
+
1158
+ ;; Helper for emitting the `and` instruction.
1159
+ ;; rd ← rs1 ∧ rs2
1160
+ (decl rv_and (XReg XReg) XReg)
1161
+ (rule (rv_and rs1 rs2)
1162
+ (alu_rrr (AluOPRRR.And) rs1 rs2))
1163
+
1164
+ ;; Helper for emitting the `andi` ("And Immediate") instruction.
1165
+ ;; rd ← rs1 ∧ uext(imm)
1166
+ (decl rv_andi (XReg Imm12) XReg)
1167
+ (rule (rv_andi rs1 imm)
1168
+ (alu_rr_imm12 (AluOPRRI.Andi) rs1 imm))
1169
+
1170
+ ;; Helper for emitting the `slt` ("Set Less Than") instruction.
1171
+ ;; rd ← rs1 < rs2
1172
+ (decl rv_slt (XReg XReg) XReg)
1173
+ (rule (rv_slt rs1 rs2)
1174
+ (alu_rrr (AluOPRRR.Slt) rs1 rs2))
1175
+
1176
+ ;; Helper for emitting the `sltu` ("Set Less Than Unsigned") instruction.
1177
+ ;; rd ← rs1 < rs2
1178
+ (decl rv_sltu (XReg XReg) XReg)
1179
+ (rule (rv_sltu rs1 rs2)
1180
+ (alu_rrr (AluOPRRR.SltU) rs1 rs2))
1181
+
1182
+ ;; Helper for emitting the `snez` instruction.
1183
+ ;; This instruction is a mnemonic for `sltu rd, zero, rs`.
1184
+ (decl rv_snez (XReg) XReg)
1185
+ (rule (rv_snez rs1)
1186
+ (rv_sltu (zero_reg) rs1))
1187
+
1188
+ ;; Helper for emiting the `slti` ("Set Less Than Immediate") instruction.
1189
+ ;; rd ← rs1 < imm
1190
+ (decl rv_slti (XReg Imm12) XReg)
1191
+ (rule (rv_slti rs1 imm)
1192
+ (alu_rr_imm12 (AluOPRRI.Slti) rs1 imm))
1193
+
1194
+ ;; Helper for emiting the `sltiu` ("Set Less Than Immediate Unsigned") instruction.
1195
+ ;; rd ← rs1 < imm
1196
+ (decl rv_sltiu (XReg Imm12) XReg)
1197
+ (rule (rv_sltiu rs1 imm)
1198
+ (alu_rr_imm12 (AluOPRRI.SltiU) rs1 imm))
1199
+
1200
+ ;; Helper for emitting the `seqz` instruction.
1201
+ ;; This instruction is a mnemonic for `sltiu rd, rs, 1`.
1202
+ (decl rv_seqz (XReg) XReg)
1203
+ (rule (rv_seqz rs1)
1204
+ (rv_sltiu rs1 (imm12_const 1)))
1205
+
1206
+
1207
+ ;; RV64I Base Integer Instruction Set
1208
+ ;; Unlike RV32I instructions these are only present in the 64bit ISA
1209
+
1210
+ ;; Helper for emitting the `addw` ("Add Word") instruction.
1211
+ ;; rd ← sext32(rs1) + sext32(rs2)
1212
+ (decl rv_addw (XReg XReg) XReg)
1213
+ (rule (rv_addw rs1 rs2)
1214
+ (alu_rrr (AluOPRRR.Addw) rs1 rs2))
1215
+
1216
+ ;; Helper for emitting the `addiw` ("Add Word Immediate") instruction.
1217
+ ;; rd ← sext32(rs1) + imm
1218
+ (decl rv_addiw (XReg Imm12) XReg)
1219
+ (rule (rv_addiw rs1 imm)
1220
+ (alu_rr_imm12 (AluOPRRI.Addiw) rs1 imm))
1221
+
1222
+ ;; Helper for emitting the `sext.w` ("Sign Extend Word") instruction.
1223
+ ;; This instruction is a mnemonic for `addiw rd, rs, zero`.
1224
+ (decl rv_sextw (XReg) XReg)
1225
+ (rule (rv_sextw rs1)
1226
+ (rv_addiw rs1 (imm12_const 0)))
1227
+
1228
+ ;; Helper for emitting the `subw` ("Subtract Word") instruction.
1229
+ ;; rd ← sext32(rs1) - sext32(rs2)
1230
+ (decl rv_subw (XReg XReg) XReg)
1231
+ (rule (rv_subw rs1 rs2)
1232
+ (alu_rrr (AluOPRRR.Subw) rs1 rs2))
1233
+
1234
+ ;; Helper for emitting the `sllw` ("Shift Left Logical Word") instruction.
1235
+ ;; rd ← sext32(uext32(rs1) << rs2)
1236
+ (decl rv_sllw (XReg XReg) XReg)
1237
+ (rule (rv_sllw rs1 rs2)
1238
+ (alu_rrr (AluOPRRR.Sllw) rs1 rs2))
1239
+
1240
+ ;; Helper for emitting the `slliw` ("Shift Left Logical Immediate Word") instruction.
1241
+ ;; rd ← sext32(uext32(rs1) << imm)
1242
+ (decl rv_slliw (XReg Imm12) XReg)
1243
+ (rule (rv_slliw rs1 imm)
1244
+ (alu_rr_imm12 (AluOPRRI.Slliw) rs1 imm))
1245
+
1246
+ ;; Helper for emitting the `srlw` ("Shift Right Logical Word") instruction.
1247
+ ;; rd ← sext32(uext32(rs1) >> rs2)
1248
+ (decl rv_srlw (XReg XReg) XReg)
1249
+ (rule (rv_srlw rs1 rs2)
1250
+ (alu_rrr (AluOPRRR.Srlw) rs1 rs2))
1251
+
1252
+ ;; Helper for emitting the `srliw` ("Shift Right Logical Immediate Word") instruction.
1253
+ ;; rd ← sext32(uext32(rs1) >> imm)
1254
+ (decl rv_srliw (XReg Imm12) XReg)
1255
+ (rule (rv_srliw rs1 imm)
1256
+ (alu_rr_imm12 (AluOPRRI.SrliW) rs1 imm))
1257
+
1258
+ ;; Helper for emitting the `sraw` ("Shift Right Arithmetic Word") instruction.
1259
+ ;; rd ← sext32(rs1 >> rs2)
1260
+ (decl rv_sraw (XReg XReg) XReg)
1261
+ (rule (rv_sraw rs1 rs2)
1262
+ (alu_rrr (AluOPRRR.Sraw) rs1 rs2))
1263
+
1264
+ ;; Helper for emitting the `sraiw` ("Shift Right Arithmetic Immediate Word") instruction.
1265
+ ;; rd ← sext32(rs1 >> imm)
1266
+ (decl rv_sraiw (XReg Imm12) XReg)
1267
+ (rule (rv_sraiw rs1 imm)
1268
+ (alu_rr_imm12 (AluOPRRI.Sraiw) rs1 imm))
1269
+
1270
+
1271
+ ;; RV32M Extension
1272
+ ;; TODO: Enable these instructions only when we have the M extension
1273
+
1274
+ ;; Helper for emitting the `mul` instruction.
1275
+ ;; rd ← rs1 × rs2
1276
+ (decl rv_mul (XReg XReg) XReg)
1277
+ (rule (rv_mul rs1 rs2)
1278
+ (alu_rrr (AluOPRRR.Mul) rs1 rs2))
1279
+
1280
+ ;; Helper for emitting the `mulh` ("Multiply High Signed Signed") instruction.
1281
+ ;; rd ← (sext(rs1) × sext(rs2)) » xlen
1282
+ (decl rv_mulh (XReg XReg) XReg)
1283
+ (rule (rv_mulh rs1 rs2)
1284
+ (alu_rrr (AluOPRRR.Mulh) rs1 rs2))
1285
+
1286
+ ;; Helper for emitting the `mulhu` ("Multiply High Unsigned Unsigned") instruction.
1287
+ ;; rd ← (uext(rs1) × uext(rs2)) » xlen
1288
+ (decl rv_mulhu (XReg XReg) XReg)
1289
+ (rule (rv_mulhu rs1 rs2)
1290
+ (alu_rrr (AluOPRRR.Mulhu) rs1 rs2))
1291
+
1292
+ ;; Helper for emitting the `div` instruction.
1293
+ ;; rd ← rs1 ÷ rs2
1294
+ (decl rv_div (XReg XReg) XReg)
1295
+ (rule (rv_div rs1 rs2)
1296
+ (alu_rrr (AluOPRRR.Div) rs1 rs2))
1297
+
1298
+ ;; Helper for emitting the `divu` ("Divide Unsigned") instruction.
1299
+ ;; rd ← rs1 ÷ rs2
1300
+ (decl rv_divu (XReg XReg) XReg)
1301
+ (rule (rv_divu rs1 rs2)
1302
+ (alu_rrr (AluOPRRR.DivU) rs1 rs2))
1303
+
1304
+ ;; Helper for emitting the `rem` instruction.
1305
+ ;; rd ← rs1 mod rs2
1306
+ (decl rv_rem (XReg XReg) XReg)
1307
+ (rule (rv_rem rs1 rs2)
1308
+ (alu_rrr (AluOPRRR.Rem) rs1 rs2))
1309
+
1310
+ ;; Helper for emitting the `remu` ("Remainder Unsigned") instruction.
1311
+ ;; rd ← rs1 mod rs2
1312
+ (decl rv_remu (XReg XReg) XReg)
1313
+ (rule (rv_remu rs1 rs2)
1314
+ (alu_rrr (AluOPRRR.RemU) rs1 rs2))
1315
+
1316
+ ;; RV64M Extension
1317
+ ;; TODO: Enable these instructions only when we have the M extension
1318
+
1319
+ ;; Helper for emitting the `mulw` ("Multiply Word") instruction.
1320
+ ;; rd ← uext32(rs1) × uext32(rs2)
1321
+ (decl rv_mulw (XReg XReg) XReg)
1322
+ (rule (rv_mulw rs1 rs2)
1323
+ (alu_rrr (AluOPRRR.Mulw) rs1 rs2))
1324
+
1325
+ ;; Helper for emitting the `divw` ("Divide Word") instruction.
1326
+ ;; rd ← sext32(rs1) ÷ sext32(rs2)
1327
+ (decl rv_divw (XReg XReg) XReg)
1328
+ (rule (rv_divw rs1 rs2)
1329
+ (alu_rrr (AluOPRRR.Divw) rs1 rs2))
1330
+
1331
+ ;; Helper for emitting the `divuw` ("Divide Unsigned Word") instruction.
1332
+ ;; rd ← uext32(rs1) ÷ uext32(rs2)
1333
+ (decl rv_divuw (XReg XReg) XReg)
1334
+ (rule (rv_divuw rs1 rs2)
1335
+ (alu_rrr (AluOPRRR.Divuw) rs1 rs2))
1336
+
1337
+ ;; Helper for emitting the `remw` ("Remainder Word") instruction.
1338
+ ;; rd ← sext32(rs1) mod sext32(rs2)
1339
+ (decl rv_remw (XReg XReg) XReg)
1340
+ (rule (rv_remw rs1 rs2)
1341
+ (alu_rrr (AluOPRRR.Remw) rs1 rs2))
1342
+
1343
+ ;; Helper for emitting the `remuw` ("Remainder Unsigned Word") instruction.
1344
+ ;; rd ← uext32(rs1) mod uext32(rs2)
1345
+ (decl rv_remuw (XReg XReg) XReg)
1346
+ (rule (rv_remuw rs1 rs2)
1347
+ (alu_rrr (AluOPRRR.Remuw) rs1 rs2))
1348
+
1349
+
1350
+ ;; F and D Extensions
1351
+ ;; TODO: Enable these instructions only when we have the F or D extensions
1352
+
1353
+ ;; Helper for emitting the `fadd` instruction.
1354
+ (decl rv_fadd (Type FRM FReg FReg) FReg)
1355
+ (rule (rv_fadd $F32 frm rs1 rs2) (fpu_rrr (FpuOPRRR.FaddS) $F32 frm rs1 rs2))
1356
+ (rule (rv_fadd $F64 frm rs1 rs2) (fpu_rrr (FpuOPRRR.FaddD) $F64 frm rs1 rs2))
1357
+
1358
+ ;; Helper for emitting the `fsub` instruction.
1359
+ (decl rv_fsub (Type FRM FReg FReg) FReg)
1360
+ (rule (rv_fsub $F32 frm rs1 rs2) (fpu_rrr (FpuOPRRR.FsubS) $F32 frm rs1 rs2))
1361
+ (rule (rv_fsub $F64 frm rs1 rs2) (fpu_rrr (FpuOPRRR.FsubD) $F64 frm rs1 rs2))
1362
+
1363
+ ;; Helper for emitting the `fmul` instruction.
1364
+ (decl rv_fmul (Type FRM FReg FReg) FReg)
1365
+ (rule (rv_fmul $F32 frm rs1 rs2) (fpu_rrr (FpuOPRRR.FmulS) $F32 frm rs1 rs2))
1366
+ (rule (rv_fmul $F64 frm rs1 rs2) (fpu_rrr (FpuOPRRR.FmulD) $F64 frm rs1 rs2))
1367
+
1368
+ ;; Helper for emitting the `fdiv` instruction.
1369
+ (decl rv_fdiv (Type FRM FReg FReg) FReg)
1370
+ (rule (rv_fdiv $F32 frm rs1 rs2) (fpu_rrr (FpuOPRRR.FdivS) $F32 frm rs1 rs2))
1371
+ (rule (rv_fdiv $F64 frm rs1 rs2) (fpu_rrr (FpuOPRRR.FdivD) $F64 frm rs1 rs2))
1372
+
1373
+ ;; Helper for emitting the `fsqrt` instruction.
1374
+ (decl rv_fsqrt (Type FRM FReg) FReg)
1375
+ (rule (rv_fsqrt $F32 frm rs1) (fpu_rr (FpuOPRR.FsqrtS) $F32 frm rs1))
1376
+ (rule (rv_fsqrt $F64 frm rs1) (fpu_rr (FpuOPRR.FsqrtD) $F64 frm rs1))
1377
+
1378
+ ;; Helper for emitting the `fmadd` instruction.
1379
+ (decl rv_fmadd (Type FRM FReg FReg FReg) FReg)
1380
+ (rule (rv_fmadd $F32 frm rs1 rs2 rs3) (fpu_rrrr (FpuOPRRRR.FmaddS) $F32 frm rs1 rs2 rs3))
1381
+ (rule (rv_fmadd $F64 frm rs1 rs2 rs3) (fpu_rrrr (FpuOPRRRR.FmaddD) $F64 frm rs1 rs2 rs3))
1382
+
1383
+ ;; Helper for emitting the `fmv.x.w` instruction.
1384
+ (decl rv_fmvxw (FReg) XReg)
1385
+ (rule (rv_fmvxw r) (fpu_rr (FpuOPRR.FmvXW) $I32 (FRM.RNE) r))
1386
+
1387
+ ;; Helper for emitting the `fmv.x.d` instruction.
1388
+ (decl rv_fmvxd (FReg) XReg)
1389
+ (rule (rv_fmvxd r) (fpu_rr (FpuOPRR.FmvXD) $I64 (FRM.RNE) r))
1390
+
1391
+ ;; Helper for emitting the `fmv.w.x` instruction.
1392
+ (decl rv_fmvwx (XReg) FReg)
1393
+ (rule (rv_fmvwx r) (fpu_rr (FpuOPRR.FmvWX) $F32 (FRM.RNE) r))
1394
+
1395
+ ;; Helper for emitting the `fmv.d.x` instruction.
1396
+ (decl rv_fmvdx (XReg) FReg)
1397
+ (rule (rv_fmvdx r) (fpu_rr (FpuOPRR.FmvDX) $F64 (FRM.RNE) r))
1398
+
1399
+ ;; Helper for emitting the `fcvt.d.s` ("Float Convert Double to Single") instruction.
1400
+ (decl rv_fcvtds (FReg) FReg)
1401
+ (rule (rv_fcvtds rs1) (fpu_rr (FpuOPRR.FcvtDS) $F32 (FRM.RNE) rs1))
1402
+
1403
+ ;; Helper for emitting the `fcvt.s.d` ("Float Convert Single to Double") instruction.
1404
+ (decl rv_fcvtsd (FRM FReg) FReg)
1405
+ (rule (rv_fcvtsd frm rs1) (fpu_rr (FpuOPRR.FcvtSD) $F64 frm rs1))
1406
+
1407
+ ;; Helper for emitting the `fcvt.s.w` instruction.
1408
+ (decl rv_fcvtsw (FRM XReg) FReg)
1409
+ (rule (rv_fcvtsw frm rs1) (fpu_rr (FpuOPRR.FcvtSw) $F32 frm rs1))
1410
+
1411
+ ;; Helper for emitting the `fcvt.s.wu` instruction.
1412
+ (decl rv_fcvtswu (FRM XReg) FReg)
1413
+ (rule (rv_fcvtswu frm rs1) (fpu_rr (FpuOPRR.FcvtSwU) $F32 frm rs1))
1414
+
1415
+ ;; Helper for emitting the `fcvt.d.w` instruction.
1416
+ (decl rv_fcvtdw (XReg) FReg)
1417
+ (rule (rv_fcvtdw rs1) (fpu_rr (FpuOPRR.FcvtDW) $F32 (FRM.RNE) rs1))
1418
+
1419
+ ;; Helper for emitting the `fcvt.d.wu` instruction.
1420
+ (decl rv_fcvtdwu (XReg) FReg)
1421
+ (rule (rv_fcvtdwu rs1) (fpu_rr (FpuOPRR.FcvtDWU) $F32 (FRM.RNE) rs1))
1422
+
1423
+ ;; Helper for emitting the `fcvt.s.l` instruction.
1424
+ (decl rv_fcvtsl (FRM XReg) FReg)
1425
+ (rule (rv_fcvtsl frm rs1) (fpu_rr (FpuOPRR.FcvtSL) $F32 frm rs1))
1426
+
1427
+ ;; Helper for emitting the `fcvt.s.lu` instruction.
1428
+ (decl rv_fcvtslu (FRM XReg) FReg)
1429
+ (rule (rv_fcvtslu frm rs1) (fpu_rr (FpuOPRR.FcvtSLU) $F32 frm rs1))
1430
+
1431
+ ;; Helper for emitting the `fcvt.d.l` instruction.
1432
+ (decl rv_fcvtdl (FRM XReg) FReg)
1433
+ (rule (rv_fcvtdl frm rs1) (fpu_rr (FpuOPRR.FcvtDL) $F32 frm rs1))
1434
+
1435
+ ;; Helper for emitting the `fcvt.d.lu` instruction.
1436
+ (decl rv_fcvtdlu (FRM XReg) FReg)
1437
+ (rule (rv_fcvtdlu frm rs1) (fpu_rr (FpuOPRR.FcvtDLu) $F32 frm rs1))
1438
+
1439
+ ;; Helper for emitting the `fcvt.w.s` instruction.
1440
+ (decl rv_fcvtws (FRM FReg) XReg)
1441
+ (rule (rv_fcvtws frm rs1) (fpu_rr (FpuOPRR.FcvtWS) $I64 frm rs1))
1442
+
1443
+ ;; Helper for emitting the `fcvt.l.s` instruction.
1444
+ (decl rv_fcvtls (FRM FReg) XReg)
1445
+ (rule (rv_fcvtls frm rs1) (fpu_rr (FpuOPRR.FcvtLS) $I64 frm rs1))
1446
+
1447
+ ;; Helper for emitting the `fcvt.wu.s` instruction.
1448
+ (decl rv_fcvtwus (FRM FReg) XReg)
1449
+ (rule (rv_fcvtwus frm rs1) (fpu_rr (FpuOPRR.FcvtWuS) $I64 frm rs1))
1450
+
1451
+ ;; Helper for emitting the `fcvt.lu.s` instruction.
1452
+ (decl rv_fcvtlus (FRM FReg) XReg)
1453
+ (rule (rv_fcvtlus frm rs1) (fpu_rr (FpuOPRR.FcvtLuS) $I64 frm rs1))
1454
+
1455
+ ;; Helper for emitting the `fcvt.w.d` instruction.
1456
+ (decl rv_fcvtwd (FRM FReg) XReg)
1457
+ (rule (rv_fcvtwd frm rs1) (fpu_rr (FpuOPRR.FcvtWD) $I64 frm rs1))
1458
+
1459
+ ;; Helper for emitting the `fcvt.l.d` instruction.
1460
+ (decl rv_fcvtld (FRM FReg) XReg)
1461
+ (rule (rv_fcvtld frm rs1) (fpu_rr (FpuOPRR.FcvtLD) $I64 frm rs1))
1462
+
1463
+ ;; Helper for emitting the `fcvt.wu.d` instruction.
1464
+ (decl rv_fcvtwud (FRM FReg) XReg)
1465
+ (rule (rv_fcvtwud frm rs1) (fpu_rr (FpuOPRR.FcvtWuD) $I64 frm rs1))
1466
+
1467
+ ;; Helper for emitting the `fcvt.lu.d` instruction.
1468
+ (decl rv_fcvtlud (FRM FReg) XReg)
1469
+ (rule (rv_fcvtlud frm rs1) (fpu_rr (FpuOPRR.FcvtLuD) $I64 frm rs1))
1470
+
1471
+ ;; Helper for emitting the `fcvt.w.*` instructions.
1472
+ (decl rv_fcvtw (Type FRM FReg) XReg)
1473
+ (rule (rv_fcvtw $F32 frm rs1) (rv_fcvtws frm rs1))
1474
+ (rule (rv_fcvtw $F64 frm rs1) (rv_fcvtwd frm rs1))
1475
+
1476
+ ;; Helper for emitting the `fcvt.l.*` instructions.
1477
+ (decl rv_fcvtl (Type FRM FReg) XReg)
1478
+ (rule (rv_fcvtl $F32 frm rs1) (rv_fcvtls frm rs1))
1479
+ (rule (rv_fcvtl $F64 frm rs1) (rv_fcvtld frm rs1))
1480
+
1481
+ ;; Helper for emitting the `fcvt.wu.*` instructions.
1482
+ (decl rv_fcvtwu (Type FRM FReg) XReg)
1483
+ (rule (rv_fcvtwu $F32 frm rs1) (rv_fcvtwus frm rs1))
1484
+ (rule (rv_fcvtwu $F64 frm rs1) (rv_fcvtwud frm rs1))
1485
+
1486
+ ;; Helper for emitting the `fcvt.lu.*` instructions.
1487
+ (decl rv_fcvtlu (Type FRM FReg) XReg)
1488
+ (rule (rv_fcvtlu $F32 frm rs1) (rv_fcvtlus frm rs1))
1489
+ (rule (rv_fcvtlu $F64 frm rs1) (rv_fcvtlud frm rs1))
1490
+
1491
+ ;; Helper for emitting the `fsgnj` ("Floating Point Sign Injection") instruction.
1492
+ ;; The output of this instruction is `rs1` with the sign bit from `rs2`
1493
+ ;; This implements the `copysign` operation
1494
+ (decl rv_fsgnj (Type FReg FReg) FReg)
1495
+ (rule (rv_fsgnj $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FsgnjS) $F32 (FRM.RNE) rs1 rs2))
1496
+ (rule (rv_fsgnj $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FsgnjD) $F64 (FRM.RNE) rs1 rs2))
1497
+
1498
+ ;; Helper for emitting the `fsgnjn` ("Floating Point Sign Injection Negated") instruction.
1499
+ ;; The output of this instruction is `rs1` with the negated sign bit from `rs2`
1500
+ ;; When `rs1 == rs2` this implements the `neg` operation
1501
+ (decl rv_fsgnjn (Type FReg FReg) FReg)
1502
+ (rule (rv_fsgnjn $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FsgnjnS) $F32 (FRM.RTZ) rs1 rs2))
1503
+ (rule (rv_fsgnjn $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FsgnjnD) $F64 (FRM.RTZ) rs1 rs2))
1504
+
1505
+ ;; Helper for emitting the `fneg` ("Floating Point Negate") instruction.
1506
+ ;; This instruction is a mnemonic for `fsgnjn rd, rs1, rs1`
1507
+ (decl rv_fneg (Type FReg) FReg)
1508
+ (rule (rv_fneg ty rs1) (rv_fsgnjn ty rs1 rs1))
1509
+
1510
+ ;; Helper for emitting the `fsgnjx` ("Floating Point Sign Injection Exclusive") instruction.
1511
+ ;; The output of this instruction is `rs1` with the XOR of the sign bits from `rs1` and `rs2`.
1512
+ ;; When `rs1 == rs2` this implements `fabs`
1513
+ (decl rv_fsgnjx (Type FReg FReg) FReg)
1514
+ (rule (rv_fsgnjx $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FsgnjxS) $F32 (FRM.RDN) rs1 rs2))
1515
+ (rule (rv_fsgnjx $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FsgnjxD) $F64 (FRM.RDN) rs1 rs2))
1516
+
1517
+ ;; Helper for emitting the `fabs` ("Floating Point Absolute") instruction.
1518
+ ;; This instruction is a mnemonic for `fsgnjx rd, rs1, rs1`
1519
+ (decl rv_fabs (Type FReg) FReg)
1520
+ (rule (rv_fabs ty rs1) (rv_fsgnjx ty rs1 rs1))
1521
+
1522
+ ;; Helper for emitting the `feq` ("Float Equal") instruction.
1523
+ (decl rv_feq (Type FReg FReg) XReg)
1524
+ (rule (rv_feq $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FeqS) $I64 (FRM.RDN) rs1 rs2))
1525
+ (rule (rv_feq $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FeqD) $I64 (FRM.RDN) rs1 rs2))
1526
+
1527
+ ;; Helper for emitting the `flt` ("Float Less Than") instruction.
1528
+ (decl rv_flt (Type FReg FReg) XReg)
1529
+ (rule (rv_flt $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FltS) $I64 (FRM.RTZ) rs1 rs2))
1530
+ (rule (rv_flt $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FltD) $I64 (FRM.RTZ) rs1 rs2))
1531
+
1532
+ ;; Helper for emitting the `fle` ("Float Less Than or Equal") instruction.
1533
+ (decl rv_fle (Type FReg FReg) XReg)
1534
+ (rule (rv_fle $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FleS) $I64 (FRM.RNE) rs1 rs2))
1535
+ (rule (rv_fle $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FleD) $I64 (FRM.RNE) rs1 rs2))
1536
+
1537
+ ;; Helper for emitting the `fgt` ("Float Greater Than") instruction.
1538
+ ;; Note: The arguments are reversed
1539
+ (decl rv_fgt (Type FReg FReg) XReg)
1540
+ (rule (rv_fgt ty rs1 rs2) (rv_flt ty rs2 rs1))
1541
+
1542
+ ;; Helper for emitting the `fge` ("Float Greater Than or Equal") instruction.
1543
+ ;; Note: The arguments are reversed
1544
+ (decl rv_fge (Type FReg FReg) XReg)
1545
+ (rule (rv_fge ty rs1 rs2) (rv_fle ty rs2 rs1))
1546
+
1547
+ ;; Helper for emitting the `fmin` instruction.
1548
+ (decl rv_fmin (Type FReg FReg) FReg)
1549
+ (rule (rv_fmin $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FminS) $F32 (FRM.RNE) rs1 rs2))
1550
+ (rule (rv_fmin $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FminD) $F64 (FRM.RNE) rs1 rs2))
1551
+
1552
+ ;; Helper for emitting the `fmax` instruction.
1553
+ (decl rv_fmax (Type FReg FReg) FReg)
1554
+ (rule (rv_fmax $F32 rs1 rs2) (fpu_rrr (FpuOPRRR.FmaxS) $F32 (FRM.RTZ) rs1 rs2))
1555
+ (rule (rv_fmax $F64 rs1 rs2) (fpu_rrr (FpuOPRRR.FmaxD) $F64 (FRM.RTZ) rs1 rs2))
1556
+
1557
+
1558
+ ;; `Zba` Extension Instructions
1559
+
1560
+ ;; Helper for emitting the `adduw` ("Add Unsigned Word") instruction.
1561
+ ;; rd ← uext32(rs1) + uext32(rs2)
1562
+ (decl rv_adduw (XReg XReg) XReg)
1563
+ (rule (rv_adduw rs1 rs2)
1564
+ (alu_rrr (AluOPRRR.Adduw) rs1 rs2))
1565
+
1566
+ ;; Helper for emitting the `zext.w` ("Zero Extend Word") instruction.
1567
+ ;; This instruction is a mnemonic for `adduw rd, rs1, zero`.
1568
+ ;; rd ← uext32(rs1)
1569
+ (decl rv_zextw (XReg) XReg)
1570
+ (rule (rv_zextw rs1)
1571
+ (rv_adduw rs1 (zero_reg)))
1572
+
1573
+ ;; Helper for emitting the `slli.uw` ("Shift Left Logical Immediate Unsigned Word") instruction.
1574
+ ;; rd ← uext32(rs1) << imm
1575
+ (decl rv_slliuw (XReg Imm12) XReg)
1576
+ (rule (rv_slliuw rs1 imm)
1577
+ (alu_rr_imm12 (AluOPRRI.SlliUw) rs1 imm))
1578
+
1579
+
1580
+ ;; `Zbb` Extension Instructions
1581
+
1582
+ ;; Helper for emitting the `andn` ("And Negated") instruction.
1583
+ ;; rd ← rs1 ∧ ~(rs2)
1584
+ (decl rv_andn (XReg XReg) XReg)
1585
+ (rule (rv_andn rs1 rs2)
1586
+ (if-let $true (has_zbb))
1587
+ (alu_rrr (AluOPRRR.Andn) rs1 rs2))
1588
+ (rule (rv_andn rs1 rs2)
1589
+ (if-let $false (has_zbb))
1590
+ (rv_and rs1 (rv_not rs2)))
1591
+
1592
+ ;; Helper for emitting the `orn` ("Or Negated") instruction.
1593
+ ;; rd ← rs1 ∨ ~(rs2)
1594
+ (decl rv_orn (XReg XReg) XReg)
1595
+ (rule (rv_orn rs1 rs2)
1596
+ (alu_rrr (AluOPRRR.Orn) rs1 rs2))
1597
+
1598
+ ;; Helper for emitting the `xnor` ("Exclusive NOR") instruction.
1599
+ ;; rd ← ~(rs1 ^ rs2)
1600
+ (decl rv_xnor (XReg XReg) XReg)
1601
+ (rule (rv_xnor rs1 rs2)
1602
+ (alu_rrr (AluOPRRR.Xnor) rs1 rs2))
1603
+
1604
+ ;; Helper for emitting the `clz` ("Count Leading Zero Bits") instruction.
1605
+ (decl rv_clz (XReg) XReg)
1606
+ (rule (rv_clz rs1)
1607
+ (alu_rr_funct12 (AluOPRRI.Clz) rs1))
1608
+
1609
+ ;; Helper for emitting the `clzw` ("Count Leading Zero Bits in Word") instruction.
1610
+ (decl rv_clzw (XReg) XReg)
1611
+ (rule (rv_clzw rs1)
1612
+ (alu_rr_funct12 (AluOPRRI.Clzw) rs1))
1613
+
1614
+ ;; Helper for emitting the `ctz` ("Count Trailing Zero Bits") instruction.
1615
+ (decl rv_ctz (XReg) XReg)
1616
+ (rule (rv_ctz rs1)
1617
+ (alu_rr_funct12 (AluOPRRI.Ctz) rs1))
1618
+
1619
+ ;; Helper for emitting the `ctzw` ("Count Trailing Zero Bits in Word") instruction.
1620
+ (decl rv_ctzw (XReg) XReg)
1621
+ (rule (rv_ctzw rs1)
1622
+ (alu_rr_funct12 (AluOPRRI.Ctzw) rs1))
1623
+
1624
+ ;; Helper for emitting the `cpop` ("Count Population") instruction.
1625
+ (decl rv_cpop (XReg) XReg)
1626
+ (rule (rv_cpop rs1)
1627
+ (alu_rr_funct12 (AluOPRRI.Cpop) rs1))
1628
+
1629
+ ;; Helper for emitting the `cpopw` ("Count Population") instruction.
1630
+ (decl rv_cpopw (XReg) XReg)
1631
+ (rule (rv_cpopw rs1)
1632
+ (alu_rr_funct12 (AluOPRRI.Cpopw) rs1))
1633
+
1634
+ ;; Helper for emitting the `max` instruction.
1635
+ (decl rv_max (XReg XReg) XReg)
1636
+ (rule (rv_max rs1 rs2)
1637
+ (alu_rrr (AluOPRRR.Max) rs1 rs2))
1638
+
1639
+ ;; Helper for emitting the `maxu` instruction.
1640
+ (decl rv_maxu (XReg XReg) XReg)
1641
+ (rule (rv_maxu rs1 rs2)
1642
+ (alu_rrr (AluOPRRR.Maxu) rs1 rs2))
1643
+
1644
+ ;; Helper for emitting the `min` instruction.
1645
+ (decl rv_min (XReg XReg) XReg)
1646
+ (rule (rv_min rs1 rs2)
1647
+ (alu_rrr (AluOPRRR.Max) rs1 rs2))
1648
+
1649
+ ;; Helper for emitting the `minu` instruction.
1650
+ (decl rv_minu (XReg XReg) XReg)
1651
+ (rule (rv_minu rs1 rs2)
1652
+ (alu_rrr (AluOPRRR.Minu) rs1 rs2))
1653
+
1654
+ ;; Helper for emitting the `sext.b` instruction.
1655
+ (decl rv_sextb (XReg) XReg)
1656
+ (rule (rv_sextb rs1)
1657
+ (alu_rr_imm12 (AluOPRRI.Sextb) rs1 (imm12_const 0)))
1658
+
1659
+ ;; Helper for emitting the `sext.h` instruction.
1660
+ (decl rv_sexth (XReg) XReg)
1661
+ (rule (rv_sexth rs1)
1662
+ (alu_rr_imm12 (AluOPRRI.Sexth) rs1 (imm12_const 0)))
1663
+
1664
+ ;; Helper for emitting the `zext.h` instruction.
1665
+ (decl rv_zexth (XReg) XReg)
1666
+ (rule (rv_zexth rs1)
1667
+ (alu_rr_imm12 (AluOPRRI.Zexth) rs1 (imm12_const 0)))
1668
+
1669
+ ;; Helper for emitting the `rol` ("Rotate Left") instruction.
1670
+ (decl rv_rol (XReg XReg) XReg)
1671
+ (rule (rv_rol rs1 rs2)
1672
+ (alu_rrr (AluOPRRR.Rol) rs1 rs2))
1673
+
1674
+ ;; Helper for emitting the `rolw` ("Rotate Left Word") instruction.
1675
+ (decl rv_rolw (XReg XReg) XReg)
1676
+ (rule (rv_rolw rs1 rs2)
1677
+ (alu_rrr (AluOPRRR.Rolw) rs1 rs2))
1678
+
1679
+ ;; Helper for emitting the `ror` ("Rotate Right") instruction.
1680
+ (decl rv_ror (XReg XReg) XReg)
1681
+ (rule (rv_ror rs1 rs2)
1682
+ (alu_rrr (AluOPRRR.Ror) rs1 rs2))
1683
+
1684
+ ;; Helper for emitting the `rorw` ("Rotate Right Word") instruction.
1685
+ (decl rv_rorw (XReg XReg) XReg)
1686
+ (rule (rv_rorw rs1 rs2)
1687
+ (alu_rrr (AluOPRRR.Rorw) rs1 rs2))
1688
+
1689
+ ;; Helper for emitting the `rori` ("Rotate Right") instruction.
1690
+ (decl rv_rori (XReg Imm12) XReg)
1691
+ (rule (rv_rori rs1 rs2)
1692
+ (alu_rr_imm12 (AluOPRRI.Rori) rs1 rs2))
1693
+
1694
+ ;; Helper for emitting the `roriw` ("Rotate Right Word") instruction.
1695
+ (decl rv_roriw (XReg Imm12) XReg)
1696
+ (rule (rv_roriw rs1 rs2)
1697
+ (alu_rr_imm12 (AluOPRRI.Roriw) rs1 rs2))
1698
+
1699
+ ;; Helper for emitting the `rev8` ("Byte Reverse") instruction.
1700
+ (decl rv_rev8 (XReg) XReg)
1701
+ (rule (rv_rev8 rs1)
1702
+ (alu_rr_funct12 (AluOPRRI.Rev8) rs1))
1703
+
1704
+ ;; Helper for emitting the `brev8` ("Bit Reverse Inside Bytes") instruction.
1705
+ ;; TODO: This instruction is mentioned in some older versions of the
1706
+ ;; spec, but has since disappeared, we should follow up on this.
1707
+ ;; It probably was renamed to `rev.b` which seems to be the closest match.
1708
+ (decl rv_brev8 (XReg) XReg)
1709
+ (rule (rv_brev8 rs1)
1710
+ (alu_rr_funct12 (AluOPRRI.Brev8) rs1))
1711
+
1712
+ ;; `Zbs` Extension Instructions
1713
+
1714
+ (decl rv_bclr (XReg XReg) XReg)
1715
+ (rule (rv_bclr rs1 rs2)
1716
+ (alu_rrr (AluOPRRR.Bclr) rs1 rs2))
1717
+
1718
+ (decl rv_bclri (XReg Imm12) XReg)
1719
+ (rule (rv_bclri rs1 imm)
1720
+ (alu_rr_imm12 (AluOPRRI.Bclri) rs1 imm))
1721
+
1722
+ (decl rv_bext (XReg XReg) XReg)
1723
+ (rule (rv_bext rs1 rs2)
1724
+ (alu_rrr (AluOPRRR.Bext) rs1 rs2))
1725
+
1726
+ (decl rv_bexti (XReg Imm12) XReg)
1727
+ (rule (rv_bexti rs1 imm)
1728
+ (alu_rr_imm12 (AluOPRRI.Bexti) rs1 imm))
1729
+
1730
+ (decl rv_binv (XReg XReg) XReg)
1731
+ (rule (rv_binv rs1 rs2)
1732
+ (alu_rrr (AluOPRRR.Binv) rs1 rs2))
1733
+
1734
+ (decl rv_binvi (XReg Imm12) XReg)
1735
+ (rule (rv_binvi rs1 imm)
1736
+ (alu_rr_imm12 (AluOPRRI.Binvi) rs1 imm))
1737
+
1738
+ (decl rv_bset (XReg XReg) XReg)
1739
+ (rule (rv_bset rs1 rs2)
1740
+ (alu_rrr (AluOPRRR.Bset) rs1 rs2))
1741
+
1742
+ ;; Helper for emitting the `bseti` ("Single-Bit Set Immediate") instruction.
1743
+ (decl rv_bseti (XReg Imm12) XReg)
1744
+ (rule (rv_bseti rs1 imm)
1745
+ (alu_rr_imm12 (AluOPRRI.Bseti) rs1 imm))
1746
+
1747
+ ;; `Zbkb` Extension Instructions
1748
+
1749
+ ;; Helper for emitting the `pack` ("Pack low halves of registers") instruction.
1750
+ (decl rv_pack (XReg XReg) XReg)
1751
+ (rule (rv_pack rs1 rs2)
1752
+ (alu_rrr (AluOPRRR.Pack) rs1 rs2))
1753
+
1754
+ ;; Helper for emitting the `packw` ("Pack low 16-bits of registers") instruction.
1755
+ (decl rv_packw (XReg XReg) XReg)
1756
+ (rule (rv_packw rs1 rs2)
1757
+ (alu_rrr (AluOPRRR.Packw) rs1 rs2))
1758
+
1759
+
1760
+ ;; `Zicsr` Extension Instructions
1761
+
1762
+ ;; Helper for emitting the `csrrwi` instruction.
1763
+ (decl rv_csrrwi (CSR UImm5) XReg)
1764
+ (rule (rv_csrrwi csr imm)
1765
+ (csr_imm (CsrImmOP.CsrRWI) csr imm))
1766
+
1767
+ ;; This is a special case of `csrrwi` when the CSR is the `frm` CSR.
1768
+ (decl rv_fsrmi (FRM) XReg)
1769
+ (rule (rv_fsrmi frm) (rv_csrrwi (CSR.Frm) frm))
1770
+
1771
+
1772
+ ;; Helper for emitting the `csrw` instruction. This is a special case of
1773
+ ;; `csrrw` where the destination register is always `x0`.
1774
+ (decl rv_csrw (CSR XReg) Unit)
1775
+ (rule (rv_csrw csr rs)
1776
+ (csr_reg_dst_zero (CsrRegOP.CsrRW) csr rs))
1777
+
1778
+ ;; This is a special case of `csrw` when the CSR is the `frm` CSR.
1779
+ (decl rv_fsrm (XReg) Unit)
1780
+ (rule (rv_fsrm rs) (rv_csrw (CSR.Frm) rs))
1781
+
1782
+
1783
+
1784
+
1785
+
1786
+
1787
+ ;; Helper for generating a i64 from a pair of Imm20 and Imm12 constants
1788
+ (decl i64_generate_imm (Imm20 Imm12) i64)
1789
+ (extern extractor i64_generate_imm i64_generate_imm)
1790
+
1791
+ ;; Helper for generating a i64 from a shift of a Imm20 constant with LUI
1792
+ (decl i64_shift_for_lui (u64 Imm12) i64)
1793
+ (extern extractor i64_shift_for_lui i64_shift_for_lui)
1794
+
1795
+ ;; Helper for generating a i64 from a shift of a Imm20 constant
1796
+ (decl i64_shift (i64 Imm12) i64)
1797
+ (extern extractor i64_shift i64_shift)
1798
+
1799
+ ;; Immediate Loading rules
1800
+ ;; TODO: Loading the zero reg directly causes a bunch of regalloc errors, we should look into it.
1801
+ ;; TODO: Load floats using `fld` instead of `ld`
1802
+ (decl imm (Type u64) Reg)
1803
+
1804
+ ;; Refs get loaded as integers.
1805
+ (rule 5 (imm $R32 c) (imm $I32 c))
1806
+ (rule 5 (imm $R64 c) (imm $I64 c))
1807
+
1808
+ ;; Floats get loaded as integers and then moved into an F register.
1809
+ (rule 5 (imm $F32 c) (gen_bitcast (imm $I32 c) $I32 $F32))
1810
+ (rule 5 (imm $F64 c) (gen_bitcast (imm $I64 c) $I64 $F64))
1811
+
1812
+ ;; Try to match just an imm12
1813
+ (rule 4 (imm (ty_int ty) c)
1814
+ (if-let (i64_generate_imm (imm20_is_zero) imm12) (i64_sextend_u64 ty c))
1815
+ (rv_addi (zero_reg) imm12))
1816
+
1817
+ ;; We can also try to load using a single LUI.
1818
+ ;; LUI takes a 20 bit immediate, places it on bits 13 to 32 of the register.
1819
+ ;; In RV64 this value is then sign extended to 64bits.
1820
+ (rule 3 (imm (ty_int ty) c)
1821
+ (if-let (i64_generate_imm imm20 (imm12_is_zero)) (i64_sextend_u64 ty c))
1822
+ (rv_lui imm20))
1823
+
1824
+ ;; We can combo addi + lui to represent all 32-bit immediates
1825
+ ;; And some 64-bit immediates as well.
1826
+ (rule 2 (imm (ty_int ty) c)
1827
+ (if-let (i64_generate_imm imm20 imm12) (i64_sextend_u64 ty c))
1828
+ (rv_addi (rv_lui imm20) imm12))
1829
+
1830
+ ;; If the non-zero bits of the immediate fit in 20 bits, we can use LUI + shift
1831
+ (rule 1 (imm (ty_int ty) c)
1832
+ (if-let (i64_shift_for_lui (imm20_from_u64 base) shift) (i64_sextend_u64 ty c))
1833
+ (rv_slli (rv_lui base) shift))
1834
+
1835
+ ;; Combine one of the above rules with a shift-left if possible, This chops off
1836
+ ;; all trailing zeros from the input constant and then attempts if the resulting
1837
+ ;; constant can itself use one of the above rules via the `i64_generate_imm`
1838
+ ;; matcher. This will then recurse on the above rules to materialize a smaller
1839
+ ;; constant which is then shifted left to create the desired constant.
1840
+ (rule 0 (imm (ty_int ty) c)
1841
+ (if-let (i64_shift c_shifted shift) (i64_sextend_u64 ty c)) ;; constant to make
1842
+ (if-let (i64_generate_imm _ _) c_shifted) ;; can the smaller constant be made?
1843
+ (rv_slli (imm ty (i64_as_u64 c_shifted)) shift))
1844
+
1845
+ ;; Otherwise we fall back to loading the immediate from the constant pool.
1846
+ (rule -1 (imm (ty_int ty) c)
1847
+ (gen_load
1848
+ (gen_const_amode (emit_u64_le_const c))
1849
+ (LoadOP.Ld)
1850
+ (mem_flags_trusted)))
1851
+
1852
+ ;; Imm12 Rules
1853
+
1854
+ (decl pure imm12_zero () Imm12)
1855
+ (rule (imm12_zero) (imm12_const 0))
1856
+
1857
+ (decl pure imm12_const (i32) Imm12)
1858
+ (extern constructor imm12_const imm12_const)
1859
+
1860
+ (decl load_imm12 (i32) Reg)
1861
+ (rule
1862
+ (load_imm12 x)
1863
+ (rv_addi (zero_reg) (imm12_const x)))
1864
+
1865
+ ;; for load immediate
1866
+ (decl imm_from_bits (u64) Imm12)
1867
+ (extern constructor imm_from_bits imm_from_bits)
1868
+
1869
+ (decl imm_from_neg_bits (i64) Imm12)
1870
+ (extern constructor imm_from_neg_bits imm_from_neg_bits)
1871
+
1872
+ (decl imm12_const_add (i32 i32) Imm12)
1873
+ (extern constructor imm12_const_add imm12_const_add)
1874
+
1875
+ ;; Performs a fallible add of the `Imm12` value and the 32-bit value provided.
1876
+ (decl pure partial imm12_add (Imm12 i32) Imm12)
1877
+ (extern constructor imm12_add imm12_add)
1878
+
1879
+ (decl imm12_and (Imm12 u64) Imm12)
1880
+ (extern constructor imm12_and imm12_and)
1881
+
1882
+ ;; Imm12 Extractors
1883
+
1884
+ ;; Helper to go directly from a `Value`, when it's an `iconst`, to an `Imm12`.
1885
+ (decl imm12_from_value (Imm12) Value)
1886
+ (extractor (imm12_from_value n) (i64_from_iconst (imm12_from_i64 n)))
1887
+
1888
+ ;; Conceptually the same as `imm12_from_value`, but tries negating the constant
1889
+ ;; value (first sign-extending to handle narrow widths).
1890
+ (decl pure partial imm12_from_negated_value (Value) Imm12)
1891
+ (rule
1892
+ (imm12_from_negated_value (has_type ty (iconst n)))
1893
+ (if-let (imm12_from_u64 imm) (i64_as_u64 (i64_neg (i64_sextend_imm64 ty n))))
1894
+ imm)
1895
+
1896
+ (decl imm12_from_u64 (Imm12) u64)
1897
+ (extern extractor imm12_from_u64 imm12_from_u64)
1898
+
1899
+ (decl imm12_from_i64 (Imm12) i64)
1900
+ (extern extractor imm12_from_i64 imm12_from_i64)
1901
+
1902
+ (decl pure partial u64_to_imm12 (u64) Imm12)
1903
+ (rule (u64_to_imm12 (imm12_from_u64 n)) n)
1904
+
1905
+ (decl pure imm12_is_zero () Imm12)
1906
+ (extern extractor imm12_is_zero imm12_is_zero)
1907
+
1908
+ ;; Imm20
1909
+
1910
+ ;; Extractor that matches if a Imm20 is zero
1911
+ (decl pure imm20_is_zero () Imm20)
1912
+ (extern extractor imm20_is_zero imm20_is_zero)
1913
+
1914
+ (decl imm20_from_u64 (Imm20) u64)
1915
+ (extern extractor imm20_from_u64 imm20_from_u64)
1916
+
1917
+ (decl imm20_from_i64 (Imm20) i64)
1918
+ (extern extractor imm20_from_i64 imm20_from_i64)
1919
+
1920
+
1921
+ ;; Imm5 Extractors
1922
+
1923
+ (decl imm5_from_u64 (Imm5) u64)
1924
+ (extern extractor imm5_from_u64 imm5_from_u64)
1925
+
1926
+ (decl imm5_from_i64 (Imm5) i64)
1927
+ (extern extractor imm5_from_i64 imm5_from_i64)
1928
+
1929
+ ;; Construct a Imm5 from an i8
1930
+ (decl pure partial i8_to_imm5 (i8) Imm5)
1931
+ (extern constructor i8_to_imm5 i8_to_imm5)
1932
+
1933
+ ;; Helper to go directly from a `Value` to an `Imm5`.
1934
+ (decl imm5_from_value (Imm5) Value)
1935
+ (extractor (imm5_from_value n) (i64_from_iconst (imm5_from_i64 n)))
1936
+
1937
+ ;; Like imm5_from_value, but first negates the `Value`.
1938
+ (decl pure partial imm5_from_negated_value (Value) Imm5)
1939
+ (rule (imm5_from_negated_value (has_type ty (iconst n)))
1940
+ (if-let (imm5_from_i64 imm) (i64_neg (i64_sextend_imm64 ty n)))
1941
+ imm)
1942
+
1943
+ ;; Constructor that matches a `Value` equivalent to a replicated Imm5 on all lanes.
1944
+ (decl pure partial replicated_imm5 (Value) Imm5)
1945
+ (rule (replicated_imm5 (splat (imm5_from_value n))) n)
1946
+ (rule (replicated_imm5 (vconst (u128_from_constant n128)))
1947
+ (if-let (u128_replicated_u64 n64) n128)
1948
+ (if-let (u64_replicated_u32 n32) n64)
1949
+ (if-let (u32_replicated_u16 n16) n32)
1950
+ (if-let (u16_replicated_u8 n8) n16)
1951
+ (if-let n (i8_to_imm5 (u8_as_i8 n8)))
1952
+ n)
1953
+
1954
+ ;; Like replicated_imm5, but first negates the `Value`.
1955
+ (decl pure partial negated_replicated_imm5 (Value) Imm5)
1956
+ (rule (negated_replicated_imm5 (splat n))
1957
+ (if-let imm5 (imm5_from_negated_value n))
1958
+ imm5)
1959
+ (rule (negated_replicated_imm5 (vconst (u128_from_constant n128)))
1960
+ (if-let (u128_replicated_u64 n64) n128)
1961
+ (if-let (u64_replicated_u32 n32) n64)
1962
+ (if-let (u32_replicated_u16 n16) n32)
1963
+ (if-let (u16_replicated_u8 n8) n16)
1964
+ (if-let n (i8_to_imm5 (i8_neg (u8_as_i8 n8))))
1965
+ n)
1966
+
1967
+ ;; UImm5 Helpers
1968
+
1969
+ ;; Constructor that matches a `Value` equivalent to a replicated UImm5 on all lanes.
1970
+ (decl pure partial replicated_uimm5 (Value) UImm5)
1971
+ (rule (replicated_uimm5 (splat (uimm5_from_value n))) n)
1972
+ (rule 1 (replicated_uimm5 (vconst (u128_from_constant n128)))
1973
+ (if-let (u128_replicated_u64 n64) n128)
1974
+ (if-let (u64_replicated_u32 n32) n64)
1975
+ (if-let (u32_replicated_u16 n16) n32)
1976
+ (if-let (u16_replicated_u8 n8) n16)
1977
+ (if-let (uimm5_from_u8 n) n8)
1978
+ n)
1979
+
1980
+ ;; Helper to go directly from a `Value`, when it's an `iconst`, to an `UImm5`.
1981
+ (decl uimm5_from_value (UImm5) Value)
1982
+ (extractor (uimm5_from_value n)
1983
+ (iconst (u64_from_imm64 (uimm5_from_u64 n))))
1984
+
1985
+ ;; Extract a `UImm5` from an `u8`.
1986
+ (decl pure partial uimm5_from_u8 (UImm5) u8)
1987
+ (extern extractor uimm5_from_u8 uimm5_from_u8)
1988
+
1989
+ ;; Extract a `UImm5` from an `u64`.
1990
+ (decl pure partial uimm5_from_u64 (UImm5) u64)
1991
+ (extern extractor uimm5_from_u64 uimm5_from_u64)
1992
+
1993
+ ;; Convert a `u64` into an `UImm5`
1994
+ (decl pure partial u64_to_uimm5 (u64) UImm5)
1995
+ (rule (u64_to_uimm5 (uimm5_from_u64 n)) n)
1996
+
1997
+ (decl uimm5_bitcast_to_imm5 (UImm5) Imm5)
1998
+ (extern constructor uimm5_bitcast_to_imm5 uimm5_bitcast_to_imm5)
1999
+
2000
+ ;; Float Helpers
2001
+
2002
+ ;; Returns the bitpattern of the Canonical NaN for the given type.
2003
+ (decl pure canonical_nan_u64 (Type) u64)
2004
+ (rule (canonical_nan_u64 $F32) 0x7fc00000)
2005
+ (rule (canonical_nan_u64 $F64) 0x7ff8000000000000)
2006
+
2007
+ ;; Helper for emitting `MInst.FpuRR` instructions.
2008
+ (decl fpu_rr (FpuOPRR Type FRM Reg) Reg)
2009
+ (rule (fpu_rr op ty frm src)
2010
+ (let ((dst WritableReg (temp_writable_reg ty))
2011
+ (_ Unit (emit (MInst.FpuRR op frm dst src))))
2012
+ dst))
2013
+
2014
+ ;; Helper for emitting `MInst.AluRRR` instructions.
2015
+ (decl alu_rrr (AluOPRRR Reg Reg) Reg)
2016
+ (rule (alu_rrr op src1 src2)
2017
+ (let ((dst WritableXReg (temp_writable_xreg))
2018
+ (_ Unit (emit (MInst.AluRRR op dst src1 src2))))
2019
+ dst))
2020
+
2021
+ ;; Helper for emitting `MInst.AluRRR` instructions.
2022
+ (decl fpu_rrr (FpuOPRRR Type FRM Reg Reg) Reg)
2023
+ (rule (fpu_rrr op ty frm src1 src2)
2024
+ (let ((dst WritableReg (temp_writable_reg ty))
2025
+ (_ Unit (emit (MInst.FpuRRR op frm dst src1 src2))))
2026
+ dst))
2027
+
2028
+ ;; Helper for emitting `MInst.FpuRRRR` instructions.
2029
+ (decl fpu_rrrr (FpuOPRRRR Type FRM Reg Reg Reg) Reg)
2030
+ (rule (fpu_rrrr op ty frm src1 src2 src3)
2031
+ (let ((dst WritableReg (temp_writable_reg ty))
2032
+ (_ Unit (emit (MInst.FpuRRRR op frm dst src1 src2 src3))))
2033
+ dst))
2034
+
2035
+
2036
+ ;; Helper for emitting `MInst.AluRRImm12` instructions.
2037
+ (decl alu_rr_imm12 (AluOPRRI Reg Imm12) Reg)
2038
+ (rule (alu_rr_imm12 op src imm)
2039
+ (let ((dst WritableXReg (temp_writable_xreg))
2040
+ (_ Unit (emit (MInst.AluRRImm12 op dst src imm))))
2041
+ dst))
2042
+
2043
+ ;; some instruction use imm12 as funct12.
2044
+ ;; so we don't need the imm12 paramter.
2045
+ (decl alu_rr_funct12 (AluOPRRI Reg) Reg)
2046
+ (rule (alu_rr_funct12 op src)
2047
+ (let ((dst WritableXReg (temp_writable_xreg))
2048
+ (_ Unit (emit (MInst.AluRRImm12 op dst src (imm12_zero)))))
2049
+ dst))
2050
+
2051
+ ;; Helper for emitting the `Lui` instruction.
2052
+ ;; TODO: This should be something like `emit_u_type`. And should share the
2053
+ ;; `MInst` with `auipc` since these instructions share the U-Type format.
2054
+ (decl rv_lui (Imm20) XReg)
2055
+ (rule (rv_lui imm)
2056
+ (let ((dst WritableXReg (temp_writable_xreg))
2057
+ (_ Unit (emit (MInst.Lui dst imm))))
2058
+ dst))
2059
+
2060
+ ;; Helper for emitting `MInst.CsrImm` instructions.
2061
+ (decl csr_imm (CsrImmOP CSR UImm5) XReg)
2062
+ (rule (csr_imm op csr imm)
2063
+ (let ((dst WritableXReg (temp_writable_xreg))
2064
+ (_ Unit (emit (MInst.CsrImm op dst imm csr))))
2065
+ dst))
2066
+
2067
+ ;; Helper for emitting a `MInst.CsrReg` instruction that writes the result to x0.
2068
+ (decl csr_reg_dst_zero (CsrRegOP CSR XReg) Unit)
2069
+ (rule (csr_reg_dst_zero op csr rs)
2070
+ (emit (MInst.CsrReg op (writable_zero_reg) rs csr)))
2071
+
2072
+
2073
+
2074
+ (decl select_addi (Type) AluOPRRI)
2075
+ (rule 1 (select_addi (fits_in_32 ty)) (AluOPRRI.Addiw))
2076
+ (rule (select_addi (fits_in_64 ty)) (AluOPRRI.Addi))
2077
+
2078
+
2079
+ (decl gen_andi (XReg u64) XReg)
2080
+ (rule 1 (gen_andi x (imm12_from_u64 y))
2081
+ (rv_andi x y))
2082
+
2083
+ (rule 0 (gen_andi x y)
2084
+ (rv_and x (imm $I64 y)))
2085
+
2086
+
2087
+ (decl gen_or (Type ValueRegs ValueRegs) ValueRegs)
2088
+ (rule 1 (gen_or $I128 x y)
2089
+ (value_regs
2090
+ (rv_or (value_regs_get x 0) (value_regs_get y 0))
2091
+ (rv_or (value_regs_get x 1) (value_regs_get y 1))))
2092
+
2093
+ (rule 0 (gen_or (fits_in_64 _) x y)
2094
+ (rv_or (value_regs_get x 0) (value_regs_get y 0)))
2095
+
2096
+
2097
+ (decl lower_ctz (Type Reg) Reg)
2098
+ (rule (lower_ctz ty x)
2099
+ (gen_cltz $false x ty))
2100
+
2101
+ (rule 1 (lower_ctz (fits_in_16 ty) x)
2102
+ (if-let $true (has_zbb))
2103
+ (let ((tmp Reg (gen_bseti x (ty_bits ty))))
2104
+ (rv_ctzw tmp)))
2105
+
2106
+ (rule 2 (lower_ctz $I32 x)
2107
+ (if-let $true (has_zbb))
2108
+ (rv_ctzw x))
2109
+
2110
+ (rule 2 (lower_ctz $I64 x)
2111
+ (if-let $true (has_zbb))
2112
+ (rv_ctz x))
2113
+
2114
+ ;; Count leading zeros from a i128 bit value.
2115
+ ;; We count both halves separately and conditionally add them if it makes sense.
2116
+
2117
+ (decl gen_cltz (bool XReg Type) XReg)
2118
+ (rule (gen_cltz leading rs ty)
2119
+ (let ((tmp WritableXReg (temp_writable_xreg))
2120
+ (step WritableXReg (temp_writable_xreg))
2121
+ (sum WritableXReg (temp_writable_xreg))
2122
+ (_ Unit (emit (MInst.Cltz leading sum step tmp rs ty))))
2123
+ sum))
2124
+
2125
+ ;; Performs a zero extension of the given value
2126
+ (decl zext (Value) XReg)
2127
+
2128
+ ;; In the most generic case, we shift left and then shift right.
2129
+ (rule 0 (zext val @ (value_type (fits_in_32 ty)))
2130
+ (let ((shift Imm12 (imm_from_bits (u64_sub 64 (ty_bits ty)))))
2131
+ (rv_srli (rv_slli val shift) shift)))
2132
+
2133
+ ;; If we are zero extending a U8 we can use a `andi` instruction.
2134
+ (rule 1 (zext val @ (value_type $I8))
2135
+ (rv_andi val (imm12_const 0xff)))
2136
+
2137
+ ;; No point in trying to use `packh` here to zero extend 8 bit values
2138
+ ;; since we can just use `andi` instead which is part of the base ISA.
2139
+
2140
+ ;; If we have the `zbkb` extension `packw` can be used to zero extend 16 bit values
2141
+ (rule 1 (zext val @ (value_type $I16))
2142
+ (if-let $true (has_zbkb))
2143
+ (rv_packw val (zero_reg)))
2144
+
2145
+ ;; If we have the `zbkb` extension `pack` can be used to zero extend 32 bit registers
2146
+ (rule 1 (zext val @ (value_type $I32))
2147
+ (if-let $true (has_zbkb))
2148
+ (rv_pack val (zero_reg)))
2149
+
2150
+ ;; If we have the `zbb` extension we can use the dedicated `zext.h` instruction.
2151
+ (rule 2 (zext val @ (value_type $I16))
2152
+ (if-let $true (has_zbb))
2153
+ (rv_zexth val))
2154
+
2155
+ ;; With `zba` we have a `zext.w` instruction
2156
+ (rule 2 (zext val @ (value_type $I32))
2157
+ (if-let $true (has_zba))
2158
+ (rv_zextw val))
2159
+
2160
+ ;; Ignore sign extensions for values whose representation is already the full
2161
+ ;; register width.
2162
+ (rule 3 (zext val)
2163
+ (if (val_already_extended (ExtendOp.Zero) val))
2164
+ val)
2165
+
2166
+ ;; Performs a signed extension of the given value
2167
+ (decl sext (Value) XReg)
2168
+
2169
+ ;; Same base case as `zext`, shift left-then-right.
2170
+ (rule 0 (sext val @ (value_type (fits_in_32 ty)))
2171
+ (let ((shift Imm12 (imm_from_bits (u64_sub 64 (ty_bits ty)))))
2172
+ (rv_srai (rv_slli val shift) shift)))
2173
+
2174
+ ;; If we have the `zbb` extension we can use the dedicated `sext.b` instruction.
2175
+ (rule 1 (sext val @ (value_type $I8))
2176
+ (if-let $true (has_zbb))
2177
+ (rv_sextb val))
2178
+
2179
+ ;; If we have the `zbb` extension we can use the dedicated `sext.h` instruction.
2180
+ (rule 1 (sext val @ (value_type $I16))
2181
+ (if-let $true (has_zbb))
2182
+ (rv_sexth val))
2183
+
2184
+ ;; When signed extending from 32 to 64 bits we can use a
2185
+ ;; `addiw val 0`. Also known as a `sext.w`
2186
+ (rule 1 (sext val @ (value_type $I32))
2187
+ (rv_sextw val))
2188
+
2189
+ ;; Ignore sign extensions for values whose representation is already the full
2190
+ ;; register width.
2191
+ (rule 2 (sext val)
2192
+ (if (val_already_extended (ExtendOp.Signed) val))
2193
+ val)
2194
+
2195
+ ;; Helper matcher for when a value's representation is already sign or zero
2196
+ ;; extended to the full 64-bit register representation. This is used by `zext`
2197
+ ;; and `sext` above to skip the extension instruction entirely in some
2198
+ ;; circumstances.
2199
+ (decl pure partial val_already_extended (ExtendOp Value) bool)
2200
+ (rule 0 (val_already_extended _ v @ (value_type $I64)) $true)
2201
+
2202
+ ;; When extending our backend always extends to the full register width, so
2203
+ ;; there's no need to extend-an-extend.
2204
+ (rule 1 (val_already_extended (ExtendOp.Zero) (uextend _)) $true)
2205
+ (rule 1 (val_already_extended (ExtendOp.Signed) (sextend _)) $true)
2206
+
2207
+ ;; The result of `icmp`/`fcmp` is zero or one, meaning that it's already sign
2208
+ ;; extended to the full register width.
2209
+ (rule 1 (val_already_extended _ (icmp _ _ _)) $true)
2210
+ (rule 1 (val_already_extended _ (fcmp _ _ _)) $true)
2211
+
2212
+ ;; The lowering for these operations always sign-extend their results due to the
2213
+ ;; use of the `*w` instructions in RV64I. Note that this requires that the
2214
+ ;; extension is from 32 to 64, 16/8-bit operations are explicitly excluded here.
2215
+ ;; There are no native instructions for the 16/8 bit operations so they must
2216
+ ;; fall through to actual sign extension above.
2217
+ (rule 1 (val_already_extended (ExtendOp.Signed) (has_type $I32 (ishl _ _))) $true)
2218
+ (rule 1 (val_already_extended (ExtendOp.Signed) (has_type $I32 (ushr _ _))) $true)
2219
+ (rule 1 (val_already_extended (ExtendOp.Signed) (has_type $I32 (sshr _ _))) $true)
2220
+ (rule 1 (val_already_extended (ExtendOp.Signed) (has_type $I32 (iadd _ _))) $true)
2221
+ (rule 1 (val_already_extended (ExtendOp.Signed) (has_type $I32 (isub _ _))) $true)
2222
+
2223
+ (type ExtendOp
2224
+ (enum
2225
+ (Zero)
2226
+ (Signed)))
2227
+
2228
+ (decl lower_b128_binary (AluOPRRR ValueRegs ValueRegs) ValueRegs)
2229
+ (rule
2230
+ (lower_b128_binary op a b)
2231
+ (let
2232
+ ( ;; low part.
2233
+ (low XReg (alu_rrr op (value_regs_get a 0) (value_regs_get b 0)))
2234
+ ;; high part.
2235
+ (high XReg (alu_rrr op (value_regs_get a 1) (value_regs_get b 1))))
2236
+ (value_regs low high)))
2237
+
2238
+ (decl lower_smlhi (Type XReg XReg) XReg)
2239
+ (rule 1
2240
+ (lower_smlhi $I64 rs1 rs2)
2241
+ (rv_mulh rs1 rs2))
2242
+
2243
+ (rule
2244
+ (lower_smlhi ty rs1 rs2)
2245
+ (let
2246
+ ((tmp XReg (rv_mul rs1 rs2)))
2247
+ (rv_srli tmp (imm12_const (ty_bits ty)))))
2248
+
2249
+ ;;;; construct shift amount.rotl on i128 will use shift to implement. So can call this function.
2250
+ ;;;; this will return shift amount and (ty_bits - "shift amount")
2251
+ ;;;; if ty_bits is greater than 64 like i128, then shmat will fallback to 64.because We are 64 bit platform.
2252
+ (decl gen_shamt (Type XReg) ValueRegs)
2253
+ (extern constructor gen_shamt gen_shamt)
2254
+
2255
+ ;; bseti: Set a single bit in a register, indexed by a constant.
2256
+ (decl gen_bseti (Reg u64) Reg)
2257
+ (rule (gen_bseti val bit)
2258
+ (if-let $false (has_zbs))
2259
+ (if-let $false (u64_le bit 12))
2260
+ (let ((const XReg (imm $I64 (u64_shl 1 bit))))
2261
+ (rv_or val const)))
2262
+
2263
+ (rule (gen_bseti val bit)
2264
+ (if-let $false (has_zbs))
2265
+ (if-let $true (u64_le bit 12))
2266
+ (rv_ori val (imm12_const (u64_as_i32 (u64_shl 1 bit)))))
2267
+
2268
+ (rule (gen_bseti val bit)
2269
+ (if-let $true (has_zbs))
2270
+ (rv_bseti val (imm12_const (u64_as_i32 bit))))
2271
+
2272
+
2273
+ (decl gen_popcnt (XReg) Reg)
2274
+ (rule (gen_popcnt rs)
2275
+ (let
2276
+ ((tmp WritableXReg (temp_writable_xreg))
2277
+ (step WritableXReg (temp_writable_xreg))
2278
+ (sum WritableXReg (temp_writable_xreg))
2279
+ (_ Unit (emit (MInst.Popcnt sum step tmp rs $I64))))
2280
+ (writable_reg_to_reg sum)))
2281
+
2282
+ ;; Generates a AMode that points to a register plus an offset.
2283
+ (decl gen_reg_offset_amode (Reg i64 Type) AMode)
2284
+ (extern constructor gen_reg_offset_amode gen_reg_offset_amode)
2285
+
2286
+ ;; Generates a AMode that an offset from the stack pointer.
2287
+ (decl gen_sp_offset_amode (i64 Type) AMode)
2288
+ (extern constructor gen_sp_offset_amode gen_sp_offset_amode)
2289
+
2290
+ ;; Generates a AMode that an offset from the frame pointer.
2291
+ (decl gen_fp_offset_amode (i64 Type) AMode)
2292
+ (extern constructor gen_fp_offset_amode gen_fp_offset_amode)
2293
+
2294
+ ;; Generates an AMode that points to a stack slot + offset.
2295
+ (decl gen_stack_slot_amode (StackSlot i64 Type) AMode)
2296
+ (extern constructor gen_stack_slot_amode gen_stack_slot_amode)
2297
+
2298
+ ;; Generates a AMode that points to a constant in the constant pool.
2299
+ (decl gen_const_amode (VCodeConstant) AMode)
2300
+ (extern constructor gen_const_amode gen_const_amode)
2301
+
2302
+
2303
+
2304
+ ;; Tries to match a Value + Offset into an AMode
2305
+ (decl amode (Value i32 Type) AMode)
2306
+ (rule 0 (amode addr offset ty) (amode_inner addr offset ty))
2307
+
2308
+ ;; If we are adding a constant offset with an iadd we can instead make that
2309
+ ;; offset part of the amode offset.
2310
+ ;;
2311
+ ;; We can't recurse into `amode` again since that could cause stack overflows.
2312
+ ;; See: https://github.com/bytecodealliance/wasmtime/pull/6968
2313
+ (rule 1 (amode (iadd addr (iconst (simm32 y))) offset ty)
2314
+ (if-let new_offset (s32_add_fallible y offset))
2315
+ (amode_inner addr new_offset ty))
2316
+ (rule 2 (amode (iadd (iconst (simm32 x)) addr) offset ty)
2317
+ (if-let new_offset (s32_add_fallible x offset))
2318
+ (amode_inner addr new_offset ty))
2319
+
2320
+
2321
+ ;; These are the normal rules for generating an AMode.
2322
+ (decl amode_inner (Value i32 Type) AMode)
2323
+
2324
+ ;; In the simplest case we just lower into a Reg+Offset
2325
+ (rule 0 (amode_inner r @ (value_type (ty_addr64 _)) offset ty)
2326
+ (gen_reg_offset_amode r offset ty))
2327
+
2328
+ ;; If the value is a `get_frame_pointer`, we can just use the offset from that.
2329
+ (rule 1 (amode_inner (get_frame_pointer) offset ty)
2330
+ (gen_fp_offset_amode offset ty))
2331
+
2332
+ ;; If the value is a `get_stack_pointer`, we can just use the offset from that.
2333
+ (rule 1 (amode_inner (get_stack_pointer) offset ty)
2334
+ (gen_sp_offset_amode offset ty))
2335
+
2336
+ ;; Similarly if the value is a `stack_addr` we can also turn that into an sp offset.
2337
+ (rule 1 (amode_inner (stack_addr ss ss_offset) amode_offset ty)
2338
+ (if-let combined_offset (s32_add_fallible ss_offset amode_offset))
2339
+ (gen_stack_slot_amode ss combined_offset ty))
2340
+
2341
+
2342
+
2343
+
2344
+ ;; Returns a canonical type for a LoadOP. We only return I64 or F64.
2345
+ (decl load_op_reg_type (LoadOP) Type)
2346
+ (rule 1 (load_op_reg_type (LoadOP.Fld)) $F64)
2347
+ (rule 1 (load_op_reg_type (LoadOP.Flw)) $F64)
2348
+ (rule 0 (load_op_reg_type _) $I64)
2349
+
2350
+ ;; helper function to load from memory.
2351
+ (decl gen_load (AMode LoadOP MemFlags) Reg)
2352
+ (rule (gen_load amode op flags)
2353
+ (let ((dst WritableReg (temp_writable_reg (load_op_reg_type op)))
2354
+ (_ Unit (emit (MInst.Load dst op flags amode))))
2355
+ dst))
2356
+
2357
+ ;; helper function to store to memory.
2358
+ (decl gen_store (AMode StoreOP MemFlags Reg) InstOutput)
2359
+ (rule (gen_store amode op flags src)
2360
+ (side_effect (SideEffectNoResult.Inst (MInst.Store amode op flags src))))
2361
+
2362
+
2363
+
2364
+
2365
+ (decl valid_atomic_transaction (Type) Type)
2366
+ (extern extractor valid_atomic_transaction valid_atomic_transaction)
2367
+
2368
+ ;;helper function.
2369
+ ;;construct an atomic instruction.
2370
+ (decl gen_atomic (AtomicOP Reg Reg AMO) Reg)
2371
+ (rule
2372
+ (gen_atomic op addr src amo)
2373
+ (let
2374
+ ((tmp WritableXReg (temp_writable_xreg))
2375
+ (_ Unit (emit (MInst.Atomic op tmp addr src amo))))
2376
+ tmp))
2377
+
2378
+ ;; helper function
2379
+ (decl get_atomic_rmw_op (Type AtomicRmwOp) AtomicOP)
2380
+ (rule
2381
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.Add))
2382
+ (AtomicOP.AmoaddW))
2383
+ (rule
2384
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.Add))
2385
+ (AtomicOP.AmoaddD))
2386
+
2387
+ (rule
2388
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.And))
2389
+ (AtomicOP.AmoandW))
2390
+
2391
+ (rule
2392
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.And))
2393
+ (AtomicOP.AmoandD))
2394
+
2395
+ (rule
2396
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.Or))
2397
+ (AtomicOP.AmoorW))
2398
+
2399
+ (rule
2400
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.Or))
2401
+ (AtomicOP.AmoorD))
2402
+
2403
+ (rule
2404
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.Smax))
2405
+ (AtomicOP.AmomaxW))
2406
+
2407
+ (rule
2408
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.Smax))
2409
+ (AtomicOP.AmomaxD))
2410
+
2411
+ (rule
2412
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.Smin))
2413
+ (AtomicOP.AmominW))
2414
+
2415
+ (rule
2416
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.Smin))
2417
+ (AtomicOP.AmominD))
2418
+
2419
+ (rule
2420
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.Umax))
2421
+ (AtomicOP.AmomaxuW)
2422
+ )
2423
+
2424
+ (rule
2425
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.Umax))
2426
+ (AtomicOP.AmomaxuD))
2427
+
2428
+ (rule
2429
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.Umin))
2430
+ (AtomicOP.AmominuW))
2431
+
2432
+ (rule
2433
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.Umin))
2434
+ (AtomicOP.AmominuD))
2435
+
2436
+ (rule
2437
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.Xchg))
2438
+ (AtomicOP.AmoswapW))
2439
+
2440
+ (rule
2441
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.Xchg))
2442
+ (AtomicOP.AmoswapD))
2443
+
2444
+ (rule
2445
+ (get_atomic_rmw_op $I32 (AtomicRmwOp.Xor))
2446
+ (AtomicOP.AmoxorW))
2447
+
2448
+ (rule
2449
+ (get_atomic_rmw_op $I64 (AtomicRmwOp.Xor))
2450
+ (AtomicOP.AmoxorD))
2451
+
2452
+ (decl atomic_amo () AMO)
2453
+ (extern constructor atomic_amo atomic_amo)
2454
+
2455
+
2456
+ (decl gen_atomic_load (Reg Type) Reg)
2457
+ (rule
2458
+ (gen_atomic_load p ty)
2459
+ (let
2460
+ ((tmp WritableXReg (temp_writable_xreg))
2461
+ (_ Unit (emit (MInst.AtomicLoad tmp ty p))))
2462
+ (writable_reg_to_reg tmp)))
2463
+
2464
+ ;;;
2465
+ (decl gen_atomic_store (Reg Type Reg) InstOutput)
2466
+ (rule
2467
+ (gen_atomic_store p ty src)
2468
+ (side_effect (SideEffectNoResult.Inst (MInst.AtomicStore src ty p)))
2469
+ )
2470
+
2471
+
2472
+ (decl gen_stack_addr (StackSlot Offset32) Reg)
2473
+ (extern constructor gen_stack_addr gen_stack_addr)
2474
+
2475
+ (decl gen_select_xreg (IntegerCompare XReg XReg) XReg)
2476
+
2477
+ (rule 1 (gen_select_xreg (int_compare_decompose cc x y) x y)
2478
+ (if-let (IntCC.UnsignedLessThan) (intcc_without_eq cc))
2479
+ (if-let $true (has_zbb))
2480
+ (rv_minu x y))
2481
+
2482
+ (rule 1 (gen_select_xreg (int_compare_decompose cc x y) x y)
2483
+ (if-let (IntCC.SignedLessThan) (intcc_without_eq cc))
2484
+ (if-let $true (has_zbb))
2485
+ (rv_min x y))
2486
+
2487
+ (rule 1 (gen_select_xreg (int_compare_decompose cc x y) x y)
2488
+ (if-let (IntCC.UnsignedGreaterThan) (intcc_without_eq cc))
2489
+ (if-let $true (has_zbb))
2490
+ (rv_maxu x y))
2491
+
2492
+ (rule 1 (gen_select_xreg (int_compare_decompose cc x y) x y)
2493
+ (if-let (IntCC.SignedGreaterThan) (intcc_without_eq cc))
2494
+ (if-let $true (has_zbb))
2495
+ (rv_max x y))
2496
+
2497
+ (rule 0 (gen_select_xreg c x y)
2498
+ (let
2499
+ ((dst WritableReg (temp_writable_xreg))
2500
+ (_ Unit (emit (MInst.Select dst c x y))))
2501
+ (writable_reg_to_reg dst)))
2502
+
2503
+
2504
+ (decl gen_select_vreg (IntegerCompare VReg VReg) VReg)
2505
+ (rule (gen_select_vreg c x y)
2506
+ (let
2507
+ ((dst WritableReg (temp_writable_vreg))
2508
+ (_ Unit (emit (MInst.Select dst c (vreg_to_reg x) (vreg_to_reg y)))))
2509
+ (writable_reg_to_reg dst)))
2510
+ (decl gen_select_freg (IntegerCompare FReg FReg) FReg)
2511
+ (rule (gen_select_freg c x y)
2512
+ (let
2513
+ ((dst WritableReg (temp_writable_freg))
2514
+ (_ Unit (emit (MInst.Select dst c (freg_to_reg x) (freg_to_reg y)))))
2515
+ (writable_reg_to_reg dst)))
2516
+ (decl gen_select_regs (IntegerCompare ValueRegs ValueRegs) ValueRegs)
2517
+ (rule (gen_select_regs c x y)
2518
+ (let
2519
+ ((dst1 WritableReg (temp_writable_xreg))
2520
+ (dst2 WritableReg (temp_writable_xreg))
2521
+ (_ Unit (emit (MInst.Select (writable_value_regs dst1 dst2) c x y))))
2522
+ (value_regs dst1 dst2)))
2523
+
2524
+ (decl udf (TrapCode) InstOutput)
2525
+ (rule
2526
+ (udf code)
2527
+ (side_effect (SideEffectNoResult.Inst (MInst.Udf code))))
2528
+
2529
+ (decl load_op (Type) LoadOP)
2530
+ (extern constructor load_op load_op)
2531
+
2532
+ (decl store_op (Type) StoreOP)
2533
+ (extern constructor store_op store_op)
2534
+
2535
+
2536
+ ;;;; load extern name
2537
+ (decl load_ext_name (ExternalName i64) Reg)
2538
+ (extern constructor load_ext_name load_ext_name)
2539
+
2540
+ (decl elf_tls_get_addr (ExternalName) Reg)
2541
+ (rule (elf_tls_get_addr name)
2542
+ (let ((dst WritableReg (temp_writable_reg $I64))
2543
+ (_ Unit (emit (MInst.ElfTlsGetAddr dst name))))
2544
+ dst))
2545
+
2546
+ ;;; some float binary operation
2547
+ ;;; 1. need move into x reister.
2548
+ ;;; 2. do the operation.
2549
+ ;;; 3. move back.
2550
+ (decl lower_float_binary (AluOPRRR FReg FReg Type) FReg)
2551
+ (rule
2552
+ (lower_float_binary op rs1 rs2 ty)
2553
+ (let ((x_rs1 XReg (move_f_to_x rs1 ty))
2554
+ (x_rs2 XReg (move_f_to_x rs2 ty))
2555
+ (tmp XReg (alu_rrr op x_rs1 x_rs2)))
2556
+ (move_x_to_f tmp (float_int_of_same_size ty))))
2557
+
2558
+
2559
+ (decl i128_sub (ValueRegs ValueRegs) ValueRegs)
2560
+ (rule
2561
+ (i128_sub x y )
2562
+ (let
2563
+ (;; low part.
2564
+ (low XReg (rv_sub (value_regs_get x 0) (value_regs_get y 0)))
2565
+ ;; compute borrow.
2566
+ (borrow XReg (rv_sltu (value_regs_get x 0) low))
2567
+ ;;
2568
+ (high_tmp XReg (rv_sub (value_regs_get x 1) (value_regs_get y 1)))
2569
+ ;;
2570
+ (high XReg (rv_sub high_tmp borrow)))
2571
+ (value_regs low high)))
2572
+
2573
+ ;; Consume a CmpResult, producing a branch on its result.
2574
+ (decl cond_br (IntegerCompare CondBrTarget CondBrTarget) SideEffectNoResult)
2575
+ (rule (cond_br cmp then else)
2576
+ (SideEffectNoResult.Inst
2577
+ (MInst.CondBr then else cmp)))
2578
+
2579
+ ;; Helper for emitting the `j` mnemonic, an unconditional jump to label.
2580
+ (decl rv_j (MachLabel) SideEffectNoResult)
2581
+ (rule (rv_j label)
2582
+ (SideEffectNoResult.Inst (MInst.Jal label)))
2583
+
2584
+ ;; Construct an IntegerCompare value.
2585
+ (decl int_compare (IntCC XReg XReg) IntegerCompare)
2586
+ (extern constructor int_compare int_compare)
2587
+
2588
+ ;; Extract the components of an `IntegerCompare`
2589
+ (decl int_compare_decompose (IntCC XReg XReg) IntegerCompare)
2590
+ (extern extractor infallible int_compare_decompose int_compare_decompose)
2591
+
2592
+ (decl label_to_br_target (MachLabel) CondBrTarget)
2593
+ (extern constructor label_to_br_target label_to_br_target)
2594
+ (convert MachLabel CondBrTarget label_to_br_target)
2595
+
2596
+ (decl cmp_eqz (XReg) IntegerCompare)
2597
+ (rule (cmp_eqz r) (int_compare (IntCC.Equal) r (zero_reg)))
2598
+
2599
+ (decl cmp_nez (XReg) IntegerCompare)
2600
+ (rule (cmp_nez r) (int_compare (IntCC.NotEqual) r (zero_reg)))
2601
+
2602
+ (decl cmp_eq (XReg XReg) IntegerCompare)
2603
+ (rule (cmp_eq rs1 rs2) (int_compare (IntCC.Equal) rs1 rs2))
2604
+
2605
+ (decl cmp_ne (XReg XReg) IntegerCompare)
2606
+ (rule (cmp_ne rs1 rs2) (int_compare (IntCC.NotEqual) rs1 rs2))
2607
+
2608
+ (decl cmp_lt (XReg XReg) IntegerCompare)
2609
+ (rule (cmp_lt rs1 rs2) (int_compare (IntCC.SignedLessThan) rs1 rs2))
2610
+
2611
+ (decl cmp_ltz (XReg) IntegerCompare)
2612
+ (rule (cmp_ltz rs) (int_compare (IntCC.SignedLessThan) rs (zero_reg)))
2613
+
2614
+ (decl cmp_gt (XReg XReg) IntegerCompare)
2615
+ (rule (cmp_gt rs1 rs2) (int_compare (IntCC.SignedGreaterThan) rs1 rs2))
2616
+
2617
+ (decl cmp_ge (XReg XReg) IntegerCompare)
2618
+ (rule (cmp_ge rs1 rs2) (int_compare (IntCC.SignedGreaterThanOrEqual) rs1 rs2))
2619
+
2620
+ (decl cmp_le (XReg XReg) IntegerCompare)
2621
+ (rule (cmp_le rs1 rs2) (int_compare (IntCC.SignedLessThanOrEqual) rs1 rs2))
2622
+
2623
+ (decl cmp_gtu (XReg XReg) IntegerCompare)
2624
+ (rule (cmp_gtu rs1 rs2) (int_compare (IntCC.UnsignedGreaterThan) rs1 rs2))
2625
+
2626
+ (decl cmp_geu (XReg XReg) IntegerCompare)
2627
+ (rule (cmp_geu rs1 rs2) (int_compare (IntCC.UnsignedGreaterThanOrEqual) rs1 rs2))
2628
+
2629
+ (decl cmp_ltu (XReg XReg) IntegerCompare)
2630
+ (rule (cmp_ltu rs1 rs2) (int_compare (IntCC.UnsignedLessThan) rs1 rs2))
2631
+
2632
+ (decl cmp_leu (XReg XReg) IntegerCompare)
2633
+ (rule (cmp_leu rs1 rs2) (int_compare (IntCC.UnsignedLessThanOrEqual) rs1 rs2))
2634
+
2635
+ ;; Helper to generate an `IntegerCompare` which represents the "truthy" value of
2636
+ ;; the input provided.
2637
+ ;;
2638
+ ;; This is used in `Select` and `brif` for example to generate conditional
2639
+ ;; branches. The returned comparison, when taken, represents that `Value` is
2640
+ ;; nonzero. When not taken the input `Value` is zero.
2641
+ (decl is_nonzero_cmp (Value) IntegerCompare)
2642
+
2643
+ ;; Base case - convert to a "truthy" value and compare it against zero.
2644
+ ;;
2645
+ ;; Note that non-64-bit types need to be extended since the upper bits from
2646
+ ;; Cranelift's point of view are undefined. Favor a zero extension for 8-bit
2647
+ ;; types because that's a single `andi` instruction, but favor sign-extension
2648
+ ;; for 16 and 32-bit types because many RISC-V which operate on the low 32-bits.
2649
+ ;; Additionally the base 64-bit ISA has a single instruction for sign-extending
2650
+ ;; from 32 to 64-bits which makes that a bit cheaper if used.
2651
+ ;; of registers sign-extend the results.
2652
+ (rule 0 (is_nonzero_cmp val @ (value_type (fits_in_64 _)))
2653
+ (cmp_nez (sext val)))
2654
+ (rule 1 (is_nonzero_cmp val @ (value_type $I8))
2655
+ (cmp_nez (zext val)))
2656
+ (rule 1 (is_nonzero_cmp val @ (value_type $I128))
2657
+ (cmp_nez (rv_or (value_regs_get val 0) (value_regs_get val 1))))
2658
+
2659
+ ;; If the input value is itself an `icmp` or `fcmp` we can avoid generating the
2660
+ ;; result of the comparison and instead move the comparison directly into the
2661
+ ;; `IntegerCompare` that's returned.
2662
+ (rule 2 (is_nonzero_cmp (maybe_uextend (icmp cc a b @ (value_type (fits_in_64 _)))))
2663
+ (icmp_to_int_compare cc a b))
2664
+ (rule 2 (is_nonzero_cmp (maybe_uextend (fcmp cc a @ (value_type ty) b)))
2665
+ (fcmp_to_float_compare cc ty a b))
2666
+
2667
+ ;; Creates an `IntegerCompare` from an `icmp` node's parts. This will extend
2668
+ ;; values as necessary to their full register width to perform the
2669
+ ;; comparison. The returned `IntegerCompare` is suitable to use in conditional
2670
+ ;; branches for example.
2671
+ ;;
2672
+ ;; Note that this should ideally only be used when the `IntegerCompare` returned
2673
+ ;; is fed into a branch. If `IntegerCompare` is materialized this will miss out
2674
+ ;; on optimizations to compare against constants using some native instructions.
2675
+ (decl icmp_to_int_compare (IntCC Value Value) IntegerCompare)
2676
+ (rule 0 (icmp_to_int_compare cc a b @ (value_type (fits_in_64 in_ty)))
2677
+ (int_compare cc (put_value_in_reg_for_icmp cc a) (put_value_in_reg_for_icmp cc b)))
2678
+ (rule 1 (icmp_to_int_compare cc a b @ (value_type $I128))
2679
+ (cmp_nez (lower_icmp_i128 cc a b)))
2680
+
2681
+ ;; Places a `Value` into a full register width to prepare for a comparison
2682
+ ;; using `IntCC`.
2683
+ ;;
2684
+ ;; This is largely a glorified means of choosing sign-extension or
2685
+ ;; zero-extension for the `Value` input.
2686
+ (decl put_value_in_reg_for_icmp (IntCC Value) XReg)
2687
+
2688
+ ;; Base cases, use the `cc` to determine whether to zero or sign extend.
2689
+ (rule 0 (put_value_in_reg_for_icmp cc val)
2690
+ (zext val))
2691
+ (rule 1 (put_value_in_reg_for_icmp cc val)
2692
+ (if (signed_cond_code cc))
2693
+ (sext val))
2694
+
2695
+ ;; For equality and inequality favor sign extension since it's generally
2696
+ ;; easier to perform sign extension on RV64 via native instructions. For 8-bit
2697
+ ;; types though use zero-extension since that's a single instruction `and`.
2698
+ (rule 2 (put_value_in_reg_for_icmp (IntCC.Equal) val @ (value_type (fits_in_64 _)))
2699
+ (sext val))
2700
+ (rule 2 (put_value_in_reg_for_icmp (IntCC.NotEqual) val @ (value_type (fits_in_64 _)))
2701
+ (sext val))
2702
+ (rule 3 (put_value_in_reg_for_icmp (IntCC.Equal) val @ (value_type $I8))
2703
+ (zext val))
2704
+ (rule 3 (put_value_in_reg_for_icmp (IntCC.NotEqual) val @ (value_type $I8))
2705
+ (zext val))
2706
+
2707
+ ;; As a special case use `x0` directly if a constant is 0.
2708
+ (rule 4 (put_value_in_reg_for_icmp _ (i64_from_iconst 0))
2709
+ (zero_reg))
2710
+
2711
+
2712
+ (decl partial lower_branch (Inst MachLabelSlice) Unit)
2713
+ (rule (lower_branch (jump _) (single_target label))
2714
+ (emit_side_effect (rv_j label)))
2715
+
2716
+ (rule (lower_branch (brif v _ _) (two_targets then else))
2717
+ (emit_side_effect (cond_br (is_nonzero_cmp v) then else)))
2718
+
2719
+ (decl lower_br_table (Reg MachLabelSlice) Unit)
2720
+ (extern constructor lower_br_table lower_br_table)
2721
+
2722
+ (rule (lower_branch (br_table index _) targets)
2723
+ (lower_br_table index targets))
2724
+
2725
+ (decl load_ra () Reg)
2726
+ (extern constructor load_ra load_ra)
2727
+
2728
+
2729
+ ;; Generates a bitcast instruction.
2730
+ ;; Args are: src, src_ty, dst_ty
2731
+ (decl gen_bitcast (Reg Type Type) Reg)
2732
+ (rule 1 (gen_bitcast r $F32 $I32) (rv_fmvxw r))
2733
+ (rule 1 (gen_bitcast r $F64 $I64) (rv_fmvxd r))
2734
+ (rule 1 (gen_bitcast r $I32 $F32) (rv_fmvwx r))
2735
+ (rule 1 (gen_bitcast r $I64 $F64) (rv_fmvdx r))
2736
+ (rule (gen_bitcast r _ _) r)
2737
+
2738
+ (decl move_f_to_x (FReg Type) XReg)
2739
+ (rule (move_f_to_x r $F32) (gen_bitcast r $F32 $I32))
2740
+ (rule (move_f_to_x r $F64) (gen_bitcast r $F64 $I64))
2741
+
2742
+ (decl move_x_to_f (XReg Type) FReg)
2743
+ (rule (move_x_to_f r $I32) (gen_bitcast r $I32 $F32))
2744
+ (rule (move_x_to_f r $I64) (gen_bitcast r $I64 $F64))
2745
+
2746
+ (decl float_int_of_same_size (Type) Type)
2747
+ (rule (float_int_of_same_size $F32) $I32)
2748
+ (rule (float_int_of_same_size $F64) $I64)
2749
+
2750
+
2751
+ (decl gen_brev8 (Reg Type) Reg)
2752
+ (rule 1
2753
+ (gen_brev8 rs _)
2754
+ (if-let $true (has_zbkb))
2755
+ (rv_brev8 rs))
2756
+ (rule
2757
+ (gen_brev8 rs ty)
2758
+ (if-let $false (has_zbkb))
2759
+ (let
2760
+ ((tmp WritableXReg (temp_writable_xreg))
2761
+ (tmp2 WritableXReg (temp_writable_xreg))
2762
+ (step WritableXReg (temp_writable_xreg))
2763
+ (rd WritableXReg (temp_writable_xreg))
2764
+ (_ Unit (emit (MInst.Brev8 rs ty step tmp tmp2 rd))))
2765
+ (writable_reg_to_reg rd)))
2766
+
2767
+ ;; Negates x
2768
+ ;; Equivalent to 0 - x
2769
+ (decl neg (Type ValueRegs) ValueRegs)
2770
+ (rule 1 (neg (fits_in_64 (ty_int ty)) val)
2771
+ (value_reg
2772
+ (rv_neg (value_regs_get val 0))))
2773
+
2774
+ (rule 2 (neg $I128 val)
2775
+ (i128_sub (value_regs_zero) val))
2776
+
2777
+
2778
+ ;; Builds an instruction sequence that traps if the comparision succeeds.
2779
+ (decl gen_trapif (IntCC XReg XReg TrapCode) InstOutput)
2780
+ (rule (gen_trapif cc a b trap_code)
2781
+ (side_effect (SideEffectNoResult.Inst (MInst.TrapIf a b cc trap_code))))
2782
+
2783
+ ;; Builds an instruction sequence that traps if the input is non-zero.
2784
+ (decl gen_trapnz (XReg TrapCode) InstOutput)
2785
+ (rule (gen_trapnz test trap_code)
2786
+ (gen_trapif (IntCC.NotEqual) test (zero_reg) trap_code))
2787
+
2788
+ ;; Builds an instruction sequence that traps if the input is zero.
2789
+ (decl gen_trapz (XReg TrapCode) InstOutput)
2790
+ (rule (gen_trapz test trap_code)
2791
+ (gen_trapif (IntCC.Equal) test (zero_reg) trap_code))
2792
+
2793
+ ;;;; Helpers for Emitting Calls ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2794
+
2795
+ (decl gen_call (SigRef ExternalName RelocDistance ValueSlice) InstOutput)
2796
+ (extern constructor gen_call gen_call)
2797
+
2798
+ (decl gen_call_indirect (SigRef Value ValueSlice) InstOutput)
2799
+ (extern constructor gen_call_indirect gen_call_indirect)
2800
+
2801
+ ;;; this is trying to imitate aarch64 `madd` instruction.
2802
+ (decl madd (XReg XReg XReg) XReg)
2803
+ (rule
2804
+ (madd n m a)
2805
+ (let
2806
+ ((t XReg (rv_mul n m)))
2807
+ (rv_add t a)))
2808
+
2809
+ ;;;; Helpers for bmask ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2810
+
2811
+ ;; Generates either 0 if `Value` is zero or -1 otherwise.
2812
+ (decl gen_bmask (Value) XReg)
2813
+
2814
+ ;; Base cases: use `snez` after a sign extension to ensure that the entire
2815
+ ;; register is defined. For i128 we test both the upper and lower half.
2816
+ (rule 0 (gen_bmask val @ (value_type (fits_in_64 _)))
2817
+ (let ((non_zero XReg (rv_snez (sext val))))
2818
+ (rv_neg non_zero)))
2819
+ (rule 1 (gen_bmask val @ (value_type $I128))
2820
+ (let ((non_zero XReg (rv_snez (rv_or (value_regs_get val 0) (value_regs_get val 1)))))
2821
+ (rv_neg non_zero)))
2822
+
2823
+ ;; If the input value is an `icmp` or an `fcmp` directly then the `snez` can
2824
+ ;; be omitted because the result of the icmp or fcmp is a 0 or 1 directly. This
2825
+ ;; means we can go straight to the `neg` instruction to produce the final
2826
+ ;; result.
2827
+ (rule 2 (gen_bmask val @ (maybe_uextend (icmp _ _ _))) (rv_neg val))
2828
+ (rule 2 (gen_bmask val @ (maybe_uextend (fcmp _ _ _))) (rv_neg val))
2829
+
2830
+ (decl lower_bmask (Value Type) ValueRegs)
2831
+ (rule 0 (lower_bmask val (fits_in_64 _))
2832
+ (value_reg (gen_bmask val)))
2833
+ (rule 1 (lower_bmask val $I128)
2834
+ (let ((bits XReg (gen_bmask val)))
2835
+ (value_regs bits bits)))
2836
+
2837
+ ;;;; Helpers for physical registers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2838
+
2839
+ (decl gen_mov_from_preg (PReg) Reg)
2840
+
2841
+ (rule
2842
+ (gen_mov_from_preg rm)
2843
+ (let ((rd WritableXReg (temp_writable_xreg))
2844
+ (_ Unit (emit (MInst.MovFromPReg rd rm))))
2845
+ rd))
2846
+
2847
+ (decl fp_reg () PReg)
2848
+ (extern constructor fp_reg fp_reg)
2849
+
2850
+ (decl sp_reg () PReg)
2851
+ (extern constructor sp_reg sp_reg)
2852
+
2853
+ ;; Helper for creating the zero register.
2854
+ (decl zero_reg () XReg)
2855
+ (extern constructor zero_reg zero_reg)
2856
+ (extern extractor zero_reg is_zero_reg)
2857
+
2858
+ (decl value_regs_zero () ValueRegs)
2859
+ (rule (value_regs_zero)
2860
+ (value_regs (imm $I64 0) (imm $I64 0)))
2861
+
2862
+ (decl writable_zero_reg () WritableReg)
2863
+ (extern constructor writable_zero_reg writable_zero_reg)
2864
+
2865
+
2866
+ ;;;; Helpers for floating point comparisons ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2867
+
2868
+ (type FloatCompare (enum
2869
+ ;; The comparison succeeded if `r` is one
2870
+ (One (r XReg))
2871
+ ;; The comparison succeeded if `r` is zero
2872
+ (Zero (r XReg))
2873
+ ))
2874
+
2875
+ (decl float_compare_invert (FloatCompare) FloatCompare)
2876
+ (rule (float_compare_invert (FloatCompare.One r)) (FloatCompare.Zero r))
2877
+ (rule (float_compare_invert (FloatCompare.Zero r)) (FloatCompare.One r))
2878
+
2879
+ (decl float_to_int_compare (FloatCompare) IntegerCompare)
2880
+ (rule (float_to_int_compare (FloatCompare.One r)) (cmp_nez r))
2881
+ (rule (float_to_int_compare (FloatCompare.Zero r)) (cmp_eqz r))
2882
+ (convert FloatCompare IntegerCompare float_to_int_compare)
2883
+
2884
+ ;; Compare two floating point numbers and return a zero/non-zero result.
2885
+ (decl fcmp_to_float_compare (FloatCC Type FReg FReg) FloatCompare)
2886
+
2887
+ ;; Direct codegen for unordered comparisons is not that efficient, so invert
2888
+ ;; the comparison to get an ordered comparison and generate that. Then invert
2889
+ ;; the result to produce the final fcmp result.
2890
+ (rule 0 (fcmp_to_float_compare cc ty a b)
2891
+ (if-let $true (floatcc_unordered cc))
2892
+ (float_compare_invert (fcmp_to_float_compare (floatcc_complement cc) ty a b)))
2893
+
2894
+ ;; a is not nan && b is not nan
2895
+ (rule 1 (fcmp_to_float_compare (FloatCC.Ordered) ty a b)
2896
+ (FloatCompare.One (rv_and (is_not_nan ty a) (is_not_nan ty b))))
2897
+
2898
+ (decl is_not_nan (Type FReg) XReg)
2899
+ (rule (is_not_nan ty a) (rv_feq ty a a))
2900
+
2901
+ ;; a == b
2902
+ (rule 1 (fcmp_to_float_compare (FloatCC.Equal) ty a b)
2903
+ (FloatCompare.One (rv_feq ty a b)))
2904
+
2905
+ ;; a != b
2906
+ ;; == !(a == b)
2907
+ (rule 1 (fcmp_to_float_compare (FloatCC.NotEqual) ty a b)
2908
+ (FloatCompare.Zero (rv_feq ty a b)))
2909
+
2910
+ ;; a < b || a > b
2911
+ (rule 1 (fcmp_to_float_compare (FloatCC.OrderedNotEqual) ty a b)
2912
+ (FloatCompare.One (rv_or (rv_flt ty a b) (rv_fgt ty a b))))
2913
+
2914
+ ;; a < b
2915
+ (rule 1 (fcmp_to_float_compare (FloatCC.LessThan) ty a b)
2916
+ (FloatCompare.One (rv_flt ty a b)))
2917
+
2918
+ ;; a <= b
2919
+ (rule 1 (fcmp_to_float_compare (FloatCC.LessThanOrEqual) ty a b)
2920
+ (FloatCompare.One (rv_fle ty a b)))
2921
+
2922
+ ;; a > b
2923
+ (rule 1 (fcmp_to_float_compare (FloatCC.GreaterThan) ty a b)
2924
+ (FloatCompare.One (rv_fgt ty a b)))
2925
+
2926
+ ;; a >= b
2927
+ (rule 1 (fcmp_to_float_compare (FloatCC.GreaterThanOrEqual) ty a b)
2928
+ (FloatCompare.One (rv_fge ty a b)))