vertigo_vhdl 0.8.5 → 0.8.10
Sign up to get free protection for your applications and to get access to all the features.
- checksums.yaml +4 -4
- data/lib/vertigo/parser.rb +28 -5
- data/lib/vertigo/tb_generator.rb +20 -7
- data/lib/vertigo/version.rb +1 -1
- data/tests/parser_tests/test_adder_rca_vhdl93.vhd +37 -0
- metadata +4 -85
- data/tests/ghdl_tests/test_fsm.vhd +0 -162
- data/tests/parser_tests/else.vhd +0 -64
- data/tests/parser_tests/pingpong.vhd +0 -34
- data/tests/parser_tests/test_accelerator_pp.vhd +0 -144
- data/tests/parser_tests/test_aggregate_pp.vhd +0 -15
- data/tests/parser_tests/test_archi_1_pp.vhd +0 -41
- data/tests/parser_tests/test_array_array_00_pp.vhd +0 -25
- data/tests/parser_tests/test_array_urange_pp.vhd +0 -25
- data/tests/parser_tests/test_chu-1_pp.vhd +0 -104
- data/tests/parser_tests/test_concat_pp.vhd +0 -14
- data/tests/parser_tests/test_counter_pp.vhd +0 -35
- data/tests/parser_tests/test_de2_pp.vhd +0 -274
- data/tests/parser_tests/test_encode_pp.vhd +0 -2549
- data/tests/parser_tests/test_fsm_pp.vhd +0 -125
- data/tests/parser_tests/test_fsm_synth_pp.vhd +0 -197
- data/tests/parser_tests/test_function-01_pp.vhd +0 -18
- data/tests/parser_tests/test_lfsr_pp.vhd +0 -44
- data/tests/parser_tests/test_microwatt_cache_ram_pp.vhd +0 -68
- data/tests/parser_tests/test_microwatt_common_pp.vhd +0 -336
- data/tests/parser_tests/test_microwatt_control_pp.vhd +0 -187
- data/tests/parser_tests/test_microwatt_core_debug_pp.vhd +0 -104
- data/tests/parser_tests/test_microwatt_core_pp.vhd +0 -231
- data/tests/parser_tests/test_microwatt_core_tb_pp.vhd +0 -43
- data/tests/parser_tests/test_microwatt_countzero_pp.vhd +0 -120
- data/tests/parser_tests/test_microwatt_countzero_tb_pp.vhd +0 -70
- data/tests/parser_tests/test_microwatt_cr_file_pp.vhd +0 -74
- data/tests/parser_tests/test_microwatt_cr_hazard_pp.vhd +0 -51
- data/tests/parser_tests/test_microwatt_crhelpers_pp.vhd +0 -48
- data/tests/parser_tests/test_microwatt_dcache_pp.vhd +0 -481
- data/tests/parser_tests/test_microwatt_dcache_tb_pp.vhd +0 -98
- data/tests/parser_tests/test_microwatt_decode1_pp.vhd +0 -138
- data/tests/parser_tests/test_microwatt_decode2_pp.vhd +0 -300
- data/tests/parser_tests/test_microwatt_decode_types_pp.vhd +0 -67
- data/tests/parser_tests/test_microwatt_divider_pp.vhd +0 -132
- data/tests/parser_tests/test_microwatt_divider_tb_pp.vhd +0 -95
- data/tests/parser_tests/test_microwatt_dmi_dtm_dummy_pp.vhd +0 -29
- data/tests/parser_tests/test_microwatt_dmi_dtm_tb_pp.vhd +0 -197
- data/tests/parser_tests/test_microwatt_dmi_dtm_xilinx_pp.vhd +0 -139
- data/tests/parser_tests/test_microwatt_execute1_pp.vhd +0 -689
- data/tests/parser_tests/test_microwatt_fetch1_pp.vhd +0 -88
- data/tests/parser_tests/test_microwatt_fetch2_pp.vhd +0 -79
- data/tests/parser_tests/test_microwatt_glibc_random_helpers_pp.vhd +0 -25
- data/tests/parser_tests/test_microwatt_glibc_random_pp.vhd +0 -41
- data/tests/parser_tests/test_microwatt_gpr_hazard_pp.vhd +0 -68
- data/tests/parser_tests/test_microwatt_helpers_pp.vhd +0 -153
- data/tests/parser_tests/test_microwatt_icache_pp.vhd +0 -337
- data/tests/parser_tests/test_microwatt_icache_tb_pp.vhd +0 -104
- data/tests/parser_tests/test_microwatt_insn_helpers_pp.vhd +0 -208
- data/tests/parser_tests/test_microwatt_loadstore1_pp.vhd +0 -222
- data/tests/parser_tests/test_microwatt_logical_pp.vhd +0 -87
- data/tests/parser_tests/test_microwatt_multiply_pp.vhd +0 -84
- data/tests/parser_tests/test_microwatt_multiply_tb_pp.vhd +0 -75
- data/tests/parser_tests/test_microwatt_plru_pp.vhd +0 -46
- data/tests/parser_tests/test_microwatt_plru_tb_pp.vhd +0 -93
- data/tests/parser_tests/test_microwatt_ppc_fx_insns_pp.vhd +0 -665
- data/tests/parser_tests/test_microwatt_register_file_pp.vhd +0 -86
- data/tests/parser_tests/test_microwatt_rotator_pp.vhd +0 -149
- data/tests/parser_tests/test_microwatt_rotator_tb_pp.vhd +0 -134
- data/tests/parser_tests/test_microwatt_sim_bram_helpers_pp.vhd +0 -52
- data/tests/parser_tests/test_microwatt_sim_bram_pp.vhd +0 -53
- data/tests/parser_tests/test_microwatt_sim_console_pp.vhd +0 -43
- data/tests/parser_tests/test_microwatt_sim_jtag_pp.vhd +0 -64
- data/tests/parser_tests/test_microwatt_sim_jtag_socket_pp.vhd +0 -36
- data/tests/parser_tests/test_microwatt_sim_uart_pp.vhd +0 -90
- data/tests/parser_tests/test_microwatt_soc_pp.vhd +0 -195
- data/tests/parser_tests/test_microwatt_utils_pp.vhd +0 -39
- data/tests/parser_tests/test_microwatt_wishbone_arbiter_pp.vhd +0 -54
- data/tests/parser_tests/test_microwatt_wishbone_bram_tb_pp.vhd +0 -157
- data/tests/parser_tests/test_microwatt_wishbone_bram_wrapper_pp.vhd +0 -62
- data/tests/parser_tests/test_microwatt_wishbone_debug_master_pp.vhd +0 -124
- data/tests/parser_tests/test_microwatt_wishbone_types_pp.vhd +0 -38
- data/tests/parser_tests/test_microwatt_writeback_pp.vhd +0 -87
- data/tests/parser_tests/test_package-1_pp.vhd +0 -53
- data/tests/parser_tests/test_precedence_pp.vhd +0 -16
- data/tests/parser_tests/test_selected_sig_pp.vhd +0 -10
- data/tests/parser_tests/test_slice_pp.vhd +0 -16
- data/tests/parser_tests/test_tb-00_pp.vhd +0 -71
- data/tests/parser_tests/test_type_decl_02_pp.vhd +0 -11
- data/tests/parser_tests/test_use_pp.vhd +0 -10
- data/tests/parser_tests/test_while_1_pp.vhd +0 -26
- data/tests/parser_tests/test_with-00_pp.vhd +0 -12
- data/tests/tb_gen_tests/test_accelerator.vhd +0 -160
@@ -1,67 +0,0 @@
|
|
1
|
-
-- generated by Vertigo VHDL tool
|
2
|
-
library ieee;
|
3
|
-
use ieee.std_logic_1164.all;
|
4
|
-
|
5
|
-
package decode_types is
|
6
|
-
|
7
|
-
type insn_type_t is (op_illegal,op_nop,op_add,op_addpcis,op_and,op_attn,op_b,op_bc,op_bcreg,op_bperm,op_cmp,op_cmpb,op_cmpeqb,op_cmprb,op_cntz,op_crand,op_crandc,op_creqv,op_crnand,op_crnor,op_cror,op_crorc,op_crxor,op_darn,op_dcbf,op_dcbst,op_dcbt,op_dcbtst,op_dcbz,op_div,op_dive,op_exts,op_extswsli,op_icbi,op_icbt,op_isel,op_isync,op_load,op_store,op_maddhd,op_maddhdu,op_maddld,op_mcrf,op_mcrxr,op_mcrxrx,op_mfcr,op_mfmsr,op_mfspr,op_mod,op_mtcrf,op_mtmsrd,op_mtspr,op_mul_l64,op_mul_h64,op_mul_h32,op_or,op_popcnt,op_prty,op_rfid,op_rlc,op_rlcl,op_rlcr,op_sc,op_setb,op_shl,op_shr,op_sync,op_td,op_tdi,op_tw,op_twi,op_xor,op_sim_config);
|
8
|
-
|
9
|
-
type input_reg_a_t is (none,ra,ra_or_zero,spr);
|
10
|
-
|
11
|
-
type input_reg_b_t is (none,rb,const_ui,const_si,const_si_hi,const_ui_hi,const_li,const_bd,const_ds,const_m1,const_sh,const_sh32,spr);
|
12
|
-
|
13
|
-
type input_reg_c_t is (none,rs);
|
14
|
-
|
15
|
-
type output_reg_a_t is (none,rt,ra,spr);
|
16
|
-
|
17
|
-
type rc_t is (none,one,rc);
|
18
|
-
|
19
|
-
type carry_in_t is (zero,ca,one);
|
20
|
-
constant sh_offset : integer := 0;
|
21
|
-
constant mb_offset : integer := 1;
|
22
|
-
constant me_offset : integer := 1;
|
23
|
-
constant sh32_offset : integer := 0;
|
24
|
-
constant mb32_offset : integer := 1;
|
25
|
-
constant me32_offset : integer := 2;
|
26
|
-
constant fxm_offset : integer := 0;
|
27
|
-
constant bo_offset : integer := 0;
|
28
|
-
constant bi_offset : integer := 1;
|
29
|
-
constant bh_offset : integer := 2;
|
30
|
-
constant bf_offset : integer := 0;
|
31
|
-
constant l_offset : integer := 1;
|
32
|
-
constant too_offset : integer := 0;
|
33
|
-
|
34
|
-
type unit_t is (none,alu,ldst);
|
35
|
-
|
36
|
-
type length_t is (none,is1b,is2b,is4b,is8b);
|
37
|
-
|
38
|
-
type decode_rom_t is record
|
39
|
-
unit : unit_t;
|
40
|
-
insn_type : insn_type_t;
|
41
|
-
input_reg_a : input_reg_a_t;
|
42
|
-
input_reg_b : input_reg_b_t;
|
43
|
-
input_reg_c : input_reg_c_t;
|
44
|
-
output_reg_a : output_reg_a_t;
|
45
|
-
input_cr : std_ulogic;
|
46
|
-
output_cr : std_ulogic;
|
47
|
-
invert_a : std_ulogic;
|
48
|
-
invert_out : std_ulogic;
|
49
|
-
input_carry : carry_in_t;
|
50
|
-
output_carry : std_ulogic;
|
51
|
-
length : length_t;
|
52
|
-
byte_reverse : std_ulogic;
|
53
|
-
sign_extend : std_ulogic;
|
54
|
-
update : std_ulogic;
|
55
|
-
reserve : std_ulogic;
|
56
|
-
is_32bit : std_ulogic;
|
57
|
-
is_signed : std_ulogic;
|
58
|
-
rc : rc_t;
|
59
|
-
lr : std_ulogic;
|
60
|
-
sgl_pipe : std_ulogic;
|
61
|
-
end record;
|
62
|
-
constant decode_rom_init : decode_rom_t := (unit => none,insn_type => op_illegal,input_reg_a => none,input_reg_b => none,input_reg_c => none,output_reg_a => none,input_cr => '0',output_cr => '0',invert_a => '0',invert_out => '0',input_carry => zero,output_carry => '0',length => none,byte_reverse => '0',sign_extend => '0',update => '0',reserve => '0',is_32bit => '0',is_signed => '0',rc => none,lr => '0',sgl_pipe => '0');
|
63
|
-
|
64
|
-
end decode_types;
|
65
|
-
|
66
|
-
package body decode_types is
|
67
|
-
end decode_types;
|
@@ -1,132 +0,0 @@
|
|
1
|
-
-- generated by Vertigo VHDL tool
|
2
|
-
library ieee;
|
3
|
-
use ieee.std_logic_1164.all;
|
4
|
-
use ieee.numeric_std.all;
|
5
|
-
library work;
|
6
|
-
use work.common.all;
|
7
|
-
use work.decode_types.all;
|
8
|
-
|
9
|
-
entity divider is
|
10
|
-
port(
|
11
|
-
clk : in std_logic;
|
12
|
-
rst : in std_logic;
|
13
|
-
d_in : in execute1todividertype;
|
14
|
-
d_out : out dividertoexecute1type);
|
15
|
-
end entity divider;
|
16
|
-
|
17
|
-
architecture behaviour of divider is
|
18
|
-
signal dend : std_ulogic_vector(128 downto 0);
|
19
|
-
signal div : unsigned(63 downto 0);
|
20
|
-
signal quot : std_ulogic_vector(63 downto 0);
|
21
|
-
signal result : std_ulogic_vector(63 downto 0);
|
22
|
-
signal sresult : std_ulogic_vector(64 downto 0);
|
23
|
-
signal oresult : std_ulogic_vector(63 downto 0);
|
24
|
-
signal running : std_ulogic;
|
25
|
-
signal count : unsigned(6 downto 0);
|
26
|
-
signal neg_result : std_ulogic;
|
27
|
-
signal is_modulus : std_ulogic;
|
28
|
-
signal is_32bit : std_ulogic;
|
29
|
-
signal extended : std_ulogic;
|
30
|
-
signal is_signed : std_ulogic;
|
31
|
-
signal overflow : std_ulogic;
|
32
|
-
signal ovf32 : std_ulogic;
|
33
|
-
signal did_ovf : std_ulogic;
|
34
|
-
begin
|
35
|
-
|
36
|
-
|
37
|
-
divider_0 : process(clk)
|
38
|
-
begin
|
39
|
-
if rising_edge(clk) then
|
40
|
-
if rst = '1' then
|
41
|
-
dend <= (others => '0');
|
42
|
-
div <= (others => '0');
|
43
|
-
quot <= (others => '0');
|
44
|
-
running <= '0';
|
45
|
-
count <= "0000000";
|
46
|
-
elsif d_in.valid = '1' then
|
47
|
-
if d_in.is_extended = '1' then
|
48
|
-
dend <= '0' & d_in.dividend & x"0000000000000000";
|
49
|
-
else
|
50
|
-
dend <= '0' & x"0000000000000000" & d_in.dividend;
|
51
|
-
end if;
|
52
|
-
div <= unsigned(d_in.divisor);
|
53
|
-
quot <= (others => '0');
|
54
|
-
neg_result <= d_in.neg_result;
|
55
|
-
is_modulus <= d_in.is_modulus;
|
56
|
-
extended <= d_in.is_extended;
|
57
|
-
is_32bit <= d_in.is_32bit;
|
58
|
-
is_signed <= d_in.is_signed;
|
59
|
-
count <= "1111111";
|
60
|
-
running <= '1';
|
61
|
-
overflow <= '0';
|
62
|
-
ovf32 <= '0';
|
63
|
-
elsif running = '1' then
|
64
|
-
if count = "0111111" then
|
65
|
-
running <= '0';
|
66
|
-
end if;
|
67
|
-
overflow <= quot(63);
|
68
|
-
if dend(128) = '1' or unsigned(dend(127 downto 64)) >= div then
|
69
|
-
ovf32 <= ovf32 or quot(31);
|
70
|
-
dend <= std_ulogic_vector(unsigned(dend(127 downto 64)) - div) & dend(63 downto 0) & '0';
|
71
|
-
quot <= quot(62 downto 0) & '1';
|
72
|
-
count <= count + 1;
|
73
|
-
elsif dend(128 downto 57) = x"000000000000000000" and count(6 downto 3) /= "0111" then
|
74
|
-
ovf32 <= or(ovf32 & quot(31 downto 24));
|
75
|
-
dend <= dend(120 downto 0) & x"00";
|
76
|
-
quot <= quot(55 downto 0) & x"00";
|
77
|
-
count <= count + 8;
|
78
|
-
else
|
79
|
-
ovf32 <= ovf32 or quot(31);
|
80
|
-
dend <= dend(127 downto 0) & '0';
|
81
|
-
quot <= quot(62 downto 0) & '0';
|
82
|
-
count <= count + 1;
|
83
|
-
end if;
|
84
|
-
else
|
85
|
-
count <= "0000000";
|
86
|
-
end if;
|
87
|
-
end if;
|
88
|
-
end process;
|
89
|
-
|
90
|
-
divider_1 : process(all)
|
91
|
-
begin
|
92
|
-
if is_modulus = '1' then
|
93
|
-
result <= dend(128 downto 65);
|
94
|
-
else
|
95
|
-
result <= quot;
|
96
|
-
end if;
|
97
|
-
if neg_result = '1' then
|
98
|
-
sresult <= std_ulogic_vector(signed('0' & result));
|
99
|
-
else
|
100
|
-
sresult <= '0' & result;
|
101
|
-
end if;
|
102
|
-
did_ovf <= '0';
|
103
|
-
if is_32bit = '0' then
|
104
|
-
did_ovf <= overflow or (is_signed and (sresult(64) xor sresult(63)));
|
105
|
-
elsif is_signed = '1' then
|
106
|
-
if ovf32 = '1' or sresult(32) /= sresult(31) then
|
107
|
-
did_ovf <= '1';
|
108
|
-
end if;
|
109
|
-
else
|
110
|
-
did_ovf <= ovf32;
|
111
|
-
end if;
|
112
|
-
if did_ovf = '1' then
|
113
|
-
oresult <= (others => '0');
|
114
|
-
elsif (is_32bit = '1') and (is_modulus = '0') then
|
115
|
-
oresult <= x"00000000" & sresult(31 downto 0);
|
116
|
-
else
|
117
|
-
oresult <= sresult(63 downto 0);
|
118
|
-
end if;
|
119
|
-
end process;
|
120
|
-
|
121
|
-
divider_out : process(clk)
|
122
|
-
begin
|
123
|
-
if rising_edge(clk) then
|
124
|
-
d_out.valid <= '0';
|
125
|
-
d_out.write_reg_data <= oresult;
|
126
|
-
d_out.overflow <= did_ovf;
|
127
|
-
if count = "1000000" then
|
128
|
-
d_out.valid <= '1';
|
129
|
-
end if;
|
130
|
-
end if;
|
131
|
-
end process;
|
132
|
-
end behaviour;
|
@@ -1,95 +0,0 @@
|
|
1
|
-
-- generated by Vertigo VHDL tool
|
2
|
-
library ieee;
|
3
|
-
use ieee.std_logic_1164.all;
|
4
|
-
use ieee.numeric_std.all;
|
5
|
-
library work;
|
6
|
-
use work.decode_types.all;
|
7
|
-
use work.common.all;
|
8
|
-
use work.glibc_random.all;
|
9
|
-
use work.ppc_fx_insns.all;
|
10
|
-
|
11
|
-
entity divider_tb is
|
12
|
-
end entity divider_tb;
|
13
|
-
|
14
|
-
architecture behave of divider_tb is
|
15
|
-
signal clk : std_ulogic;
|
16
|
-
signal rst : std_ulogic;
|
17
|
-
constant clk_period : time := 10 ns;
|
18
|
-
signal d1 : execute1todividertype;
|
19
|
-
signal d2 : dividertoexecute1type;
|
20
|
-
begin
|
21
|
-
|
22
|
-
divider_0 : entity work.divider
|
23
|
-
port map(
|
24
|
-
clk => clk,
|
25
|
-
rst => rst,
|
26
|
-
d_in => d1,
|
27
|
-
d_out => d2);
|
28
|
-
|
29
|
-
|
30
|
-
clk_process : process
|
31
|
-
begin
|
32
|
-
clk <= '0';
|
33
|
-
wait clk_period / 2;
|
34
|
-
clk <= '1';
|
35
|
-
wait clk_period / 2;
|
36
|
-
end process;
|
37
|
-
|
38
|
-
stim_process : process
|
39
|
-
variable ra : std_ulogic_vector(63 downto 0);
|
40
|
-
variable rb : std_ulogic_vector(63 downto 0);
|
41
|
-
variable rt : std_ulogic_vector(63 downto 0);
|
42
|
-
variable behave_rt : std_ulogic_vector(63 downto 0);
|
43
|
-
variable si : std_ulogic_vector(15 downto 0);
|
44
|
-
variable d128 : std_ulogic_vector(127 downto 0);
|
45
|
-
variable q128 : std_ulogic_vector(127 downto 0);
|
46
|
-
variable q64 : std_ulogic_vector(63 downto 0);
|
47
|
-
variable rem32 : std_ulogic_vector(31 downto 0);
|
48
|
-
begin
|
49
|
-
rst <= '1';
|
50
|
-
wait clk_period;
|
51
|
-
rst <= '0';
|
52
|
-
d1.valid <= '1';
|
53
|
-
d1.dividend <= x"0000000010001000";
|
54
|
-
d1.divisor <= x"0000000000001111";
|
55
|
-
d1.is_signed <= '0';
|
56
|
-
d1.is_32bit <= '0';
|
57
|
-
d1.is_extended <= '0';
|
58
|
-
d1.is_modulus <= '0';
|
59
|
-
d1.neg_result <= '0';
|
60
|
-
wait clk_period;
|
61
|
-
assert d2.valid = '0';
|
62
|
-
d1.valid <= '0';
|
63
|
-
assert d2.valid = '1';
|
64
|
-
assert d2.write_reg_data = x"000000000000f001"
|
65
|
-
report "result " & to_hstring(d2.write_reg_data);
|
66
|
-
wait clk_period;
|
67
|
-
assert d2.valid = '0'
|
68
|
-
report "valid";
|
69
|
-
d1.valid <= '1';
|
70
|
-
wait clk_period;
|
71
|
-
assert d2.valid = '0'
|
72
|
-
report "valid";
|
73
|
-
d1.valid <= '0';
|
74
|
-
assert d2.valid = '1';
|
75
|
-
assert d2.write_reg_data = x"000000000000f001"
|
76
|
-
report "result " & to_hstring(d2.write_reg_data);
|
77
|
-
wait clk_period;
|
78
|
-
assert d2.valid = '0';
|
79
|
-
report "test divd";
|
80
|
-
report "test divdu";
|
81
|
-
report "test divde";
|
82
|
-
report "test divdeu";
|
83
|
-
report "test divw";
|
84
|
-
report "test divwu";
|
85
|
-
report "test divwe";
|
86
|
-
report "test divweu";
|
87
|
-
report "test modsd";
|
88
|
-
report "test modud";
|
89
|
-
report "test modsw";
|
90
|
-
report "test moduw";
|
91
|
-
assert false
|
92
|
-
report "end of test" severity failure;
|
93
|
-
wait ;
|
94
|
-
end process;
|
95
|
-
end behave;
|
@@ -1,29 +0,0 @@
|
|
1
|
-
-- generated by Vertigo VHDL tool
|
2
|
-
library ieee;
|
3
|
-
use ieee.std_logic_1164.all;
|
4
|
-
library work;
|
5
|
-
use work.wishbone_types.all;
|
6
|
-
|
7
|
-
entity dmi_dtm is
|
8
|
-
generic(
|
9
|
-
abits : integer8 := 8;
|
10
|
-
dbits : integer32 := 32);
|
11
|
-
port(
|
12
|
-
sys_clk : in std_ulogic;
|
13
|
-
sys_reset : in std_ulogic;
|
14
|
-
dmi_addr : out std_ulogic_vector(abits - 1 downto 0);
|
15
|
-
dmi_din : in std_ulogic_vector(dbits - 1 downto 0);
|
16
|
-
dmi_dout : out std_ulogic_vector(dbits - 1 downto 0);
|
17
|
-
dmi_req : out std_ulogic;
|
18
|
-
dmi_wr : out std_ulogic;
|
19
|
-
dmi_ack : in std_ulogic);
|
20
|
-
end entity dmi_dtm;
|
21
|
-
|
22
|
-
architecture behaviour of dmi_dtm is
|
23
|
-
begin
|
24
|
-
|
25
|
-
dmi_addr <= (others => '0');
|
26
|
-
dmi_dout <= (others => '0');
|
27
|
-
dmi_req <= '0';
|
28
|
-
dmi_wr <= '0';
|
29
|
-
end behaviour;
|
@@ -1,197 +0,0 @@
|
|
1
|
-
-- generated by Vertigo VHDL tool
|
2
|
-
library ieee;
|
3
|
-
use ieee.std_logic_1164.all;
|
4
|
-
use ieee.numeric_std.all;
|
5
|
-
library work;
|
6
|
-
use work.common.all;
|
7
|
-
use work.wishbone_types.all;
|
8
|
-
library unisim;
|
9
|
-
use unisim.vcomponents.all;
|
10
|
-
|
11
|
-
entity dmi_dtm_tb is
|
12
|
-
end entity dmi_dtm_tb;
|
13
|
-
|
14
|
-
architecture behave of dmi_dtm_tb is
|
15
|
-
signal clk : std_ulogic;
|
16
|
-
signal rst : std_ulogic;
|
17
|
-
constant clk_period : time := 10 ns;
|
18
|
-
constant jclk_period : time := 30 ns;
|
19
|
-
signal dmi_addr : std_ulogic_vector(7 downto 0);
|
20
|
-
signal dmi_din : std_ulogic_vector(63 downto 0);
|
21
|
-
signal dmi_dout : std_ulogic_vector(63 downto 0);
|
22
|
-
signal dmi_req : std_ulogic;
|
23
|
-
signal dmi_wr : std_ulogic;
|
24
|
-
signal dmi_ack : std_ulogic;
|
25
|
-
alias j : glob_jtag_t is glob_jtag ;
|
26
|
-
signal wishbone_ram_in : wishbone_slave_out;
|
27
|
-
signal wishbone_ram_out : wishbone_master_out;
|
28
|
-
begin
|
29
|
-
|
30
|
-
dtm : entity work.dmi_dtm
|
31
|
-
port map(
|
32
|
-
sys_clk => clk,
|
33
|
-
sys_reset => rst,
|
34
|
-
dmi_addr => dmi_addr,
|
35
|
-
dmi_din => dmi_din,
|
36
|
-
dmi_dout => dmi_dout,
|
37
|
-
dmi_req => dmi_req,
|
38
|
-
dmi_wr => dmi_wr,
|
39
|
-
dmi_ack => dmi_ack);
|
40
|
-
|
41
|
-
simple_ram_0 : entity work.wishbone_bram_wrapper
|
42
|
-
port map(
|
43
|
-
clk => clk,
|
44
|
-
rst => rst,
|
45
|
-
wishbone_in => wishbone_ram_out,
|
46
|
-
wishbone_out => wishbone_ram_in);
|
47
|
-
|
48
|
-
wishbone_debug_0 : entity work.wishbone_debug_master
|
49
|
-
port map(
|
50
|
-
clk => clk,
|
51
|
-
rst => rst,
|
52
|
-
dmi_addr => dmi_addr(1 downto 0),
|
53
|
-
dmi_dout => dmi_din,
|
54
|
-
dmi_din => dmi_dout,
|
55
|
-
dmi_wr => dmi_wr,
|
56
|
-
dmi_ack => dmi_ack,
|
57
|
-
dmi_req => dmi_req,
|
58
|
-
wb_in => wishbone_ram_in,
|
59
|
-
wb_out => wishbone_ram_out);
|
60
|
-
|
61
|
-
|
62
|
-
sys_clk : process
|
63
|
-
begin
|
64
|
-
clk <= '1';
|
65
|
-
wait clk_period / 2;
|
66
|
-
clk <= '0';
|
67
|
-
wait clk_period / 2;
|
68
|
-
end process;
|
69
|
-
|
70
|
-
sys_sim : process
|
71
|
-
begin
|
72
|
-
rst <= '1';
|
73
|
-
wait clk_period;
|
74
|
-
rst <= '0';
|
75
|
-
wait ;
|
76
|
-
end process;
|
77
|
-
|
78
|
-
sim_jtag : process
|
79
|
-
|
80
|
-
procedure clock(
|
81
|
-
count : in integer) is
|
82
|
-
begin
|
83
|
-
;
|
84
|
-
end clock;
|
85
|
-
|
86
|
-
procedure shift_out(
|
87
|
-
val : in std_ulogic_vector) is
|
88
|
-
begin
|
89
|
-
;
|
90
|
-
end shift_out;
|
91
|
-
|
92
|
-
procedure shift_in(
|
93
|
-
val : out std_ulogic_vector) is
|
94
|
-
begin
|
95
|
-
;
|
96
|
-
end shift_in;
|
97
|
-
|
98
|
-
procedure send_command(
|
99
|
-
addr : in std_ulogic_vector(7 downto 0);
|
100
|
-
data : in std_ulogic_vector(63 downto 0);
|
101
|
-
op : in std_ulogic_vector(1 downto 0)) is
|
102
|
-
begin
|
103
|
-
j.capture <= '1';
|
104
|
-
()
|
105
|
-
j.capture <= '0';
|
106
|
-
()
|
107
|
-
j.shift <= '1';
|
108
|
-
()
|
109
|
-
()
|
110
|
-
()
|
111
|
-
j.shift <= '0';
|
112
|
-
j.update <= '1';
|
113
|
-
()
|
114
|
-
j.update <= '0';
|
115
|
-
()
|
116
|
-
end send_command;
|
117
|
-
|
118
|
-
procedure read_resp(
|
119
|
-
op : out std_ulogic_vector(1 downto 0);
|
120
|
-
data : out std_ulogic_vector(63 downto 0)) is
|
121
|
-
#<Vertigo::Variable:0x000055d91bc0f3b0>
|
122
|
-
begin
|
123
|
-
j.capture <= '1';
|
124
|
-
()
|
125
|
-
j.capture <= '0';
|
126
|
-
()
|
127
|
-
j.shift <= '1';
|
128
|
-
()
|
129
|
-
()
|
130
|
-
()
|
131
|
-
j.shift <= '0';
|
132
|
-
j.update <= '1';
|
133
|
-
()
|
134
|
-
j.update <= '0';
|
135
|
-
()
|
136
|
-
end read_resp;
|
137
|
-
|
138
|
-
procedure dmi_write(
|
139
|
-
addr : in std_ulogic_vector(7 downto 0);
|
140
|
-
data : in std_ulogic_vector(63 downto 0)) is
|
141
|
-
#<Vertigo::Variable:0x000055d91bc0bc38>
|
142
|
-
#<Vertigo::Variable:0x000055d91bc0b8f0>
|
143
|
-
#<Vertigo::Variable:0x000055d91bc0b5a8>
|
144
|
-
begin
|
145
|
-
()
|
146
|
-
;
|
147
|
-
end dmi_write;
|
148
|
-
|
149
|
-
procedure dmi_read(
|
150
|
-
addr : in std_ulogic_vector(7 downto 0);
|
151
|
-
data : out std_ulogic_vector(63 downto 0)) is
|
152
|
-
#<Vertigo::Variable:0x000055d91bc09190>
|
153
|
-
#<Vertigo::Variable:0x000055d91bc08e48>
|
154
|
-
begin
|
155
|
-
()
|
156
|
-
;
|
157
|
-
end dmi_read;
|
158
|
-
variable data : std_ulogic_vector(63 downto 0);
|
159
|
-
begin
|
160
|
-
j.reset <= '1';
|
161
|
-
j.sel <= "0000";
|
162
|
-
j.capture <= '0';
|
163
|
-
j.update <= '0';
|
164
|
-
j.shift <= '0';
|
165
|
-
j.tdi <= '0';
|
166
|
-
j.tms <= '0';
|
167
|
-
j.runtest <= '0';
|
168
|
-
()
|
169
|
-
j.reset <= '0';
|
170
|
-
()
|
171
|
-
j.sel <= "0010";
|
172
|
-
()
|
173
|
-
()
|
174
|
-
report "read addr reg:" & to_hstring(data);
|
175
|
-
report "writing addr reg to all 1's";
|
176
|
-
()
|
177
|
-
()
|
178
|
-
report "read addr reg:" & to_hstring(data);
|
179
|
-
report "writing ctrl reg to all 1's";
|
180
|
-
()
|
181
|
-
()
|
182
|
-
report "read ctrl reg:" & to_hstring(data);
|
183
|
-
report "read memory at 0...\n";
|
184
|
-
()
|
185
|
-
()
|
186
|
-
()
|
187
|
-
report "00:" & to_hstring(data);
|
188
|
-
()
|
189
|
-
report "08:" & to_hstring(data);
|
190
|
-
()
|
191
|
-
report "10:" & to_hstring(data);
|
192
|
-
()
|
193
|
-
report "18:" & to_hstring(data);
|
194
|
-
()
|
195
|
-
()
|
196
|
-
end process;
|
197
|
-
end behave;
|