vertigo_vhdl 0.8.5 → 0.8.10

data/tests/parser_tests/test_package-1_pp.vhd

@@ -1,53 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
- 
-package alu_package is
-  constant interval : time := 8 ns;
-  signal sig_a : std_logic_vector(1 downto 0);
-  signal sig_b : std_logic_vector(1 downto 0);
-  signal sig_sel : std_logic_vector(1 downto 0);
-  signal sig_res : std_logic_vector(1 downto 0);
-   
-  procedure load_data(
-    a : out std_logic_vector(1 downto 0);
-    b : out std_logic_vector(1 downto 0);
-    sel : out std_logic_vector(1 downto 0));
-   
-  procedure check_data(
-    sel : out std_logic_vector(1 downto 0));
- 
-end alu_package;
- 
-package body alu_package is
-   
-  procedure load_data(
-    a : out std_logic_vector(1 downto 0);
-    b : out std_logic_vector(1 downto 0);
-    sel : out std_logic_vector(1 downto 0)) is
-  begin
-    a <= sig_a;
-    b <= sig_b;
-    sel <= sig_sel;
-  end load_data;
-   
-  procedure check_data(
-    sel : out std_logic_vector(1 downto 0)) is
-  begin
-    sel <= sig_sel;
-    if (sig_sel = "00") then
-      assert (sig_res = (sig_a + sig_b))
-        report "error detected in addition!" severity warning;
-    elsif (sig_sel = "01") then
-      assert (sig_res = (sig_a - sig_b))
-        report "error detected in subtraction!" severity warning;
-    elsif (sig_sel = "10") then
-      assert (sig_res = (sig_a and sig_b))
-        report "and operation error!" severity warning;
-    elsif (sig_sel = "11") then
-      assert (sig_res = (sig_a or sig_b))
-        report "or operation error!" severity warning;
-    end if;
-  end check_data;
-end alu_package;

data/tests/parser_tests/test_precedence_pp.vhd

@@ -1,16 +0,0 @@
--- generated by Vertigo VHDL tool
- 
-entity test is
-end entity test;
- 
-architecture bhv of test is
-begin
- 
-   
-  process
-  begin
-    if clk'event and clk = '1' then
-      report "hourra!";
-    end if;
-  end process;
-end bhv;

data/tests/parser_tests/test_selected_sig_pp.vhd

@@ -1,10 +0,0 @@
--- generated by Vertigo VHDL tool
-architecture mux_4_vers_1 of porte_4_vers_1 is
-begin
- 
-  with adr select s <=
-    a when "00",
-    b when "01",
-    c when "10",
-    d when others,;
-end mux_4_vers_1;

data/tests/parser_tests/test_slice_pp.vhd

@@ -1,16 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
- 
-entity test is
-end entity test;
- 
-architecture arch of test is
-  constant cst : std_logic_vector(15 downto 0) := x"1234";
-  signal s1 : std_logic_vector(31 downto 0);
-  signal s2 : std_logic_vector(31 downto 0);
-begin
- 
-  s2 <= s1(15 downto 0) & cst;
-end arch;

data/tests/parser_tests/test_tb-00_pp.vhd

@@ -1,71 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
- 
-entity decoder_tb is
-end entity decoder_tb;
- 
-architecture tb of decoder_tb is
-  signal t_i : std_logic_vector(1 downto 0) := "00";
-  signal t_o : std_logic_vector(3 downto 0);
-  component decoder is
-    port(
-        i : in std_logic_vector(1 downto 0);
-        o : out std_logic_vector(3 downto 0));
-  end component;
-begin
- 
-  u_decoder : component decoder
-    port map(
-      t_i,
-      t_o);
-   
-   
-  process
-    variable err_cnt : integer := 0;
-  begin
-    wait 10 ns;
-    t_i <= "00";
-    wait 1 ns;
-    assert (t_o = "0001")
-      report "error case 0" severity error;
-    if (t_o /= "0001") then
-      err_cnt := err_cnt + 1;
-    end if;
-    wait 10 ns;
-    t_i <= "01";
-    wait 1 ns;
-    assert (t_o = "0010")
-      report "error case 1" severity error;
-    if (t_o /= "0010") then
-      err_cnt := err_cnt + 1;
-    end if;
-    wait 10 ns;
-    t_i <= "10";
-    wait 1 ns;
-    assert (t_o = "0100")
-      report "error case 2" severity error;
-    if (t_o /= "0100") then
-      err_cnt := err_cnt + 1;
-    end if;
-    wait 10 ns;
-    t_i <= "11";
-    wait 1 ns;
-    assert (t_o = "1000")
-      report "error case 3" severity error;
-    if (t_o /= "1000") then
-      err_cnt := err_cnt + 1;
-    end if;
-    wait 10 ns;
-    t_i <= "uu";
-    if (err_cnt = 0) then
-      assert false
-        report "testbench of adder completed successfully!" severity note;
-    else
-      assert true
-        report "something wrong, try again" severity error;
-    end if;
-    wait ;
-  end process;
-end tb;

data/tests/parser_tests/test_type_decl_02_pp.vhd

@@ -1,11 +0,0 @@
--- generated by Vertigo VHDL tool
- 
-entity test is
-end entity test;
- 
-architecture test_var of test is
-   
-  type testit is array(natural range <>) of boolean;
-begin
- 
-end test_var;

data/tests/parser_tests/test_use_pp.vhd

@@ -1,10 +0,0 @@
--- generated by Vertigo VHDL tool
-library ieee;
-library std;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.accelerator_pkg.all;
- 
-entity test is
-end entity test;
- 

data/tests/parser_tests/test_while_1_pp.vhd

@@ -1,26 +0,0 @@
--- generated by Vertigo VHDL tool
-architecture test_while of while_tester is
-begin
- 
-   
-  clk_1 : process(clock)
-  begin
-    ;
-  end process;
-   
-  process
-  begin
-    ;
-  end process;
-   
-  shift_3 : process(input_x)
-    variable i : positive := 1;
-  begin
-    ;
-  end process;
-   
-  shift_4 : process(input_x)
-  begin
-    ;
-  end process;
-end test_while;

data/tests/parser_tests/test_with-00_pp.vhd

@@ -1,12 +0,0 @@
--- generated by Vertigo VHDL tool
-architecture flow of ttimer is
-begin
- 
-  with s_sum select dig_sig1 <=
-    "10000001" when 0,
-    "11001111" when 1,
-    "10010010" when 2,
-    "10000110" when 3,
-    "10000100" when 59,;
-  dig_sig0 <= "10000001" when s_sum >= 0 and s_sum <= 9 else "11001111" when s_sum >= 10 and s_sum <= 19 else "10010010" when s_sum >= 20 and s_sum <= 29 else "10000110" when s_sum >= 30 and s_sum <= 39 else "11001100" when s_sum >= 40 and s_sum <= 49 else  "10100100";
-end flow;

data/tests/tb_gen_tests/test_accelerator.vhd

@@ -1,160 +0,0 @@
-library ieee,std;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.accelerator_pkg.all;
-
-entity accelerator is
-  port(
-    clock          : in  std_logic;
-    reset_n      : in  std_logic;
-    bus_addr     : in  std_logic_vector(31 downto 0);
-    bus_data_p2a : in  std_logic_vector(31 downto 0);
-    bus_data_a2p : out std_logic_vector(31 downto 0);
-    bus_rd       : in  std_logic;
-    bus_wr       : in  std_logic
-    );
-end accelerator;
-
-architecture rtl of accelerator is
-
-  type regs_t is record
-    a, b, res : std_logic_vector(31 downto 0);
-    ctrl      : std_logic;
-    status    : std_logic_vector(1 downto 0);  --busy,done
-  end record;
-
-  constant INIT_REGS : regs_t := (
-    (others => '0'),
-    (others => '0'),
-    (others => '0'),
-    '0',
-    "00"
-    );
-
-  signal ifregs : regs_t;
-
-  type   state_t is (idle, running);
-  signal state, state_c : state_t;
-
-  type vars_t is record
-    go   : std_logic;
-    a, b : unsigned(31 downto 0);
-    done : std_logic;
-  end record;
-
-  -- constant VARS_INIT : vars_t := (
-  --   '0',
-  --   to_unsigned(0, 32),
-  --   to_unsigned(0, 32),
-  --   '0');
-
-  signal vars, vars_c : vars_t;
-
-begin
-  --========================================
-  -- Bus interface
-  --========================================
-  bus_wr_proc : process(clk, reset_n)
-  begin
-    if reset_n = '0' then
-      ifregs <= INIT_REGS;
-    elsif rising_edge(clk) then
-      ifregs.ctrl <= '0';                               --autoreset
-      if bus_wr = '1' then
-        case bus_addr is
-          when ADDR_A =>
-            ifregs.a <= bus_data_p2a;
-          when ADDR_B =>
-            ifregs.b <= bus_data_p2a;
-          when ADDR_CTRL =>
-            ifregs.ctrl <= bus_data_p2a(0);             --write/clear a go
-          when ADDR_STATUS =>
-            ifregs.status <= bus_data_p2a(1 downto 0);  --clear rdy
-          when others => null;
-        end case;
-      elsif vars.done = '1' then
-        ifregs.res       <= std_logic_vector(vars.a);  --BUG : vars.a ne passait pas
-                                                       --=> FIX lexer : selected_name
-        --ifregs.status(0) <= vars.done;  --BUG : (0) ne passe pas
-        ifregs.status <= vars.done;  --BUG : (0) ne passe pas
-      end if;
-    end if;
-  end process;
-
-  bus_rd_proc : process(reset_n, clk)
-  begin
-    if reset_n = '0' then
-      bus_data_a2p <= (others => '0');
-    elsif rising_edge(clk) then
-      if bus_rd = '1' then
-        case bus_addr is
-          when ADDR_A =>
-            bus_data_a2p <= ifregs.a;
-          when ADDR_B =>
-            bus_data_a2p <= ifregs.b;
-          when ADDR_CTRL =>
-            null;
-            --bus_data_a2p <= X"0000000" & "000" & ifregs.ctrl;  --write/clear a go
-          when ADDR_STATUS =>
-            null;
-            bus_data_a2p <= X"0000000" & "00" & ifregs.status;
-          when ADDR_RES =>
-            bus_data_a2p <= ifregs.res;
-          when others => null;
-        end case;
-      end if;
-    end if;
-  end process;
-
---=============================================
--- BUG
---=============================================
-
-  reg : process(clk, reset_n)
-  begin
-    if reset_n = '0' then
-      state <= idle;
-      vars  <= VARS_INIT;
-    elsif rising_edge(clk) then
-      state <= state_c;
-      vars  <= vars_c;
-      if ifregs.ctrl = '1' then
-        vars.a  <= unsigned(ifregs.a);
-        vars.b  <= unsigned(ifregs.b);
-        vars.go <= '1';
-      end if;
-    end if;
-  end process;
-
-  comb : process (state, vars)
-    variable state_v : state_t;
-    variable vars_v  : vars_t;
-  begin
-    state_v := state;
-    vars_v  := vars;
-    case state_v is
-      when idle =>
-        if vars_v.go = '1' then
-          state_v   := running;
-          vars_v.go := '0';
-        else
-          vars_v := VARS_INIT;
-        end if;
-      when running =>
-        if vars_v.a /= vars_v.b then
-          if vars_v.a > vars_v.b then
-            vars_v.a := vars_v.a-vars_v.b;
-          else
-            vars_v.b := vars_v.b-vars_v.a;
-          end if;
-        else
-          vars_v.done := '1';
-          state_v     := idle;
-        end if;
-      when others => null;
-    end case;
-    state_c <= state_v;
-    vars_c  <= vars_v;
-  end process;
-
-end rtl;