vertigo_vhdl 0.8.5 → 0.8.10
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- checksums.yaml +4 -4
- data/lib/vertigo/parser.rb +28 -5
- data/lib/vertigo/tb_generator.rb +20 -7
- data/lib/vertigo/version.rb +1 -1
- data/tests/parser_tests/test_adder_rca_vhdl93.vhd +37 -0
- metadata +4 -85
- data/tests/ghdl_tests/test_fsm.vhd +0 -162
- data/tests/parser_tests/else.vhd +0 -64
- data/tests/parser_tests/pingpong.vhd +0 -34
- data/tests/parser_tests/test_accelerator_pp.vhd +0 -144
- data/tests/parser_tests/test_aggregate_pp.vhd +0 -15
- data/tests/parser_tests/test_archi_1_pp.vhd +0 -41
- data/tests/parser_tests/test_array_array_00_pp.vhd +0 -25
- data/tests/parser_tests/test_array_urange_pp.vhd +0 -25
- data/tests/parser_tests/test_chu-1_pp.vhd +0 -104
- data/tests/parser_tests/test_concat_pp.vhd +0 -14
- data/tests/parser_tests/test_counter_pp.vhd +0 -35
- data/tests/parser_tests/test_de2_pp.vhd +0 -274
- data/tests/parser_tests/test_encode_pp.vhd +0 -2549
- data/tests/parser_tests/test_fsm_pp.vhd +0 -125
- data/tests/parser_tests/test_fsm_synth_pp.vhd +0 -197
- data/tests/parser_tests/test_function-01_pp.vhd +0 -18
- data/tests/parser_tests/test_lfsr_pp.vhd +0 -44
- data/tests/parser_tests/test_microwatt_cache_ram_pp.vhd +0 -68
- data/tests/parser_tests/test_microwatt_common_pp.vhd +0 -336
- data/tests/parser_tests/test_microwatt_control_pp.vhd +0 -187
- data/tests/parser_tests/test_microwatt_core_debug_pp.vhd +0 -104
- data/tests/parser_tests/test_microwatt_core_pp.vhd +0 -231
- data/tests/parser_tests/test_microwatt_core_tb_pp.vhd +0 -43
- data/tests/parser_tests/test_microwatt_countzero_pp.vhd +0 -120
- data/tests/parser_tests/test_microwatt_countzero_tb_pp.vhd +0 -70
- data/tests/parser_tests/test_microwatt_cr_file_pp.vhd +0 -74
- data/tests/parser_tests/test_microwatt_cr_hazard_pp.vhd +0 -51
- data/tests/parser_tests/test_microwatt_crhelpers_pp.vhd +0 -48
- data/tests/parser_tests/test_microwatt_dcache_pp.vhd +0 -481
- data/tests/parser_tests/test_microwatt_dcache_tb_pp.vhd +0 -98
- data/tests/parser_tests/test_microwatt_decode1_pp.vhd +0 -138
- data/tests/parser_tests/test_microwatt_decode2_pp.vhd +0 -300
- data/tests/parser_tests/test_microwatt_decode_types_pp.vhd +0 -67
- data/tests/parser_tests/test_microwatt_divider_pp.vhd +0 -132
- data/tests/parser_tests/test_microwatt_divider_tb_pp.vhd +0 -95
- data/tests/parser_tests/test_microwatt_dmi_dtm_dummy_pp.vhd +0 -29
- data/tests/parser_tests/test_microwatt_dmi_dtm_tb_pp.vhd +0 -197
- data/tests/parser_tests/test_microwatt_dmi_dtm_xilinx_pp.vhd +0 -139
- data/tests/parser_tests/test_microwatt_execute1_pp.vhd +0 -689
- data/tests/parser_tests/test_microwatt_fetch1_pp.vhd +0 -88
- data/tests/parser_tests/test_microwatt_fetch2_pp.vhd +0 -79
- data/tests/parser_tests/test_microwatt_glibc_random_helpers_pp.vhd +0 -25
- data/tests/parser_tests/test_microwatt_glibc_random_pp.vhd +0 -41
- data/tests/parser_tests/test_microwatt_gpr_hazard_pp.vhd +0 -68
- data/tests/parser_tests/test_microwatt_helpers_pp.vhd +0 -153
- data/tests/parser_tests/test_microwatt_icache_pp.vhd +0 -337
- data/tests/parser_tests/test_microwatt_icache_tb_pp.vhd +0 -104
- data/tests/parser_tests/test_microwatt_insn_helpers_pp.vhd +0 -208
- data/tests/parser_tests/test_microwatt_loadstore1_pp.vhd +0 -222
- data/tests/parser_tests/test_microwatt_logical_pp.vhd +0 -87
- data/tests/parser_tests/test_microwatt_multiply_pp.vhd +0 -84
- data/tests/parser_tests/test_microwatt_multiply_tb_pp.vhd +0 -75
- data/tests/parser_tests/test_microwatt_plru_pp.vhd +0 -46
- data/tests/parser_tests/test_microwatt_plru_tb_pp.vhd +0 -93
- data/tests/parser_tests/test_microwatt_ppc_fx_insns_pp.vhd +0 -665
- data/tests/parser_tests/test_microwatt_register_file_pp.vhd +0 -86
- data/tests/parser_tests/test_microwatt_rotator_pp.vhd +0 -149
- data/tests/parser_tests/test_microwatt_rotator_tb_pp.vhd +0 -134
- data/tests/parser_tests/test_microwatt_sim_bram_helpers_pp.vhd +0 -52
- data/tests/parser_tests/test_microwatt_sim_bram_pp.vhd +0 -53
- data/tests/parser_tests/test_microwatt_sim_console_pp.vhd +0 -43
- data/tests/parser_tests/test_microwatt_sim_jtag_pp.vhd +0 -64
- data/tests/parser_tests/test_microwatt_sim_jtag_socket_pp.vhd +0 -36
- data/tests/parser_tests/test_microwatt_sim_uart_pp.vhd +0 -90
- data/tests/parser_tests/test_microwatt_soc_pp.vhd +0 -195
- data/tests/parser_tests/test_microwatt_utils_pp.vhd +0 -39
- data/tests/parser_tests/test_microwatt_wishbone_arbiter_pp.vhd +0 -54
- data/tests/parser_tests/test_microwatt_wishbone_bram_tb_pp.vhd +0 -157
- data/tests/parser_tests/test_microwatt_wishbone_bram_wrapper_pp.vhd +0 -62
- data/tests/parser_tests/test_microwatt_wishbone_debug_master_pp.vhd +0 -124
- data/tests/parser_tests/test_microwatt_wishbone_types_pp.vhd +0 -38
- data/tests/parser_tests/test_microwatt_writeback_pp.vhd +0 -87
- data/tests/parser_tests/test_package-1_pp.vhd +0 -53
- data/tests/parser_tests/test_precedence_pp.vhd +0 -16
- data/tests/parser_tests/test_selected_sig_pp.vhd +0 -10
- data/tests/parser_tests/test_slice_pp.vhd +0 -16
- data/tests/parser_tests/test_tb-00_pp.vhd +0 -71
- data/tests/parser_tests/test_type_decl_02_pp.vhd +0 -11
- data/tests/parser_tests/test_use_pp.vhd +0 -10
- data/tests/parser_tests/test_while_1_pp.vhd +0 -26
- data/tests/parser_tests/test_with-00_pp.vhd +0 -12
- data/tests/tb_gen_tests/test_accelerator.vhd +0 -160
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
|
|
1
1
|
---
|
2
2
|
SHA256:
|
3
|
-
metadata.gz:
|
4
|
-
data.tar.gz:
|
3
|
+
metadata.gz: beaea4415336c64910ab051d6882dbc9e5320f65a9531a2862a336f30142d7ff
|
4
|
+
data.tar.gz: f190bce2287c4d40b69a191e5c34ae6bfaee628f3c19213ddec253d8c4fb6a0f
|
5
5
|
SHA512:
|
6
|
-
metadata.gz:
|
7
|
-
data.tar.gz:
|
6
|
+
metadata.gz: e35cadb37ba4f987501b079bc9c69f73bbb3d1699ec1966410448e4dd4637b26f5d3aa205121cf1fbebcf94c6ccf4de21dd21e121a3291793d6c264bfb980b32
|
7
|
+
data.tar.gz: 6bdd446db85780a7bd16214776651fed9896d6cfd5edf5e4a4fae483bb0b2d8323cf6d890722f346586f0e2ceabf0bbeefda219d46cfa65bc64cfd9fdebc76e9
|
data/lib/vertigo/parser.rb
CHANGED
@@ -801,12 +801,25 @@ module Vertigo
|
|
801
801
|
expect :if
|
802
802
|
ret.cond=parse_expression
|
803
803
|
expect :generate
|
804
|
-
|
804
|
+
# maybe local declarations :
|
805
|
+
if showNext.is_a? [:signal,:constant]
|
806
|
+
while showNext.is_not_a?(:begin)
|
807
|
+
parse_decls
|
808
|
+
end
|
809
|
+
end
|
810
|
+
|
811
|
+
#...or simply "begin"
|
812
|
+
if showNext.is_a?(:begin)
|
805
813
|
acceptIt
|
806
814
|
end
|
807
|
-
ret.body=
|
815
|
+
ret.body=body=Body.new
|
816
|
+
|
817
|
+
while !showNext.is_a?(:end)
|
818
|
+
body << parse_concurrent_stmt
|
819
|
+
end
|
808
820
|
expect :end
|
809
821
|
expect :generate
|
822
|
+
maybe :ident
|
810
823
|
expect :semicolon
|
811
824
|
ret
|
812
825
|
end
|
@@ -818,16 +831,26 @@ module Vertigo
|
|
818
831
|
expect :in
|
819
832
|
ret.range=parse_discrete_range
|
820
833
|
expect :generate
|
821
|
-
|
822
|
-
|
834
|
+
|
835
|
+
# maybe local declarations :
|
836
|
+
if showNext.is_a? [:signal,:constant]
|
837
|
+
while showNext.is_not_a?(:begin)
|
838
|
+
parse_decls
|
839
|
+
end
|
840
|
+
end
|
841
|
+
|
842
|
+
#...or simply "begin"
|
843
|
+
if showNext.is_a?(:begin)
|
844
|
+
acceptIt
|
823
845
|
end
|
824
846
|
ret.body=body=Body.new
|
825
|
-
|
847
|
+
|
826
848
|
while !showNext.is_a?(:end)
|
827
849
|
body << parse_concurrent_stmt
|
828
850
|
end
|
829
851
|
expect :end
|
830
852
|
expect :generate
|
853
|
+
maybe :ident
|
831
854
|
expect :semicolon
|
832
855
|
ret
|
833
856
|
end
|
data/lib/vertigo/tb_generator.rb
CHANGED
@@ -1,9 +1,12 @@
|
|
1
1
|
module Vertigo
|
2
2
|
|
3
3
|
class TestBenchGenerator
|
4
|
+
|
4
5
|
attr_accessor :ast
|
5
6
|
attr_accessor :entity,:arch
|
6
7
|
attr_accessor :clk,:rst
|
8
|
+
attr_accessor :options
|
9
|
+
|
7
10
|
def initialize options={}
|
8
11
|
@options=options
|
9
12
|
@supplemental_libs_h=options[:supplemental_libs_h]||{}
|
@@ -17,7 +20,8 @@ module Vertigo
|
|
17
20
|
@tb_name=@entity_name+"_tb"
|
18
21
|
tb_filename=@tb_name+".vhd"
|
19
22
|
File.open(tb_filename,'w'){|f| f.puts vhdl_tb}
|
20
|
-
puts "=> generated testbench : #{tb_filename}"
|
23
|
+
puts "=> generated testbench : #{tb_filename}" unless options[:mute]
|
24
|
+
return tb_filename
|
21
25
|
end
|
22
26
|
|
23
27
|
def line n=80
|
@@ -57,6 +61,15 @@ module Vertigo
|
|
57
61
|
code << "end loop;"
|
58
62
|
code.indent=2
|
59
63
|
code << "end procedure;"
|
64
|
+
code.newline
|
65
|
+
code << "procedure toggle(signal s : inout std_logic) is"
|
66
|
+
code << "begin"
|
67
|
+
code << " wait until rising_edge(clk);"
|
68
|
+
code << " s <=not(s);"
|
69
|
+
code << " wait until rising_edge(clk);"
|
70
|
+
code << " s <=not(s);"
|
71
|
+
code << "end procedure;"
|
72
|
+
code.newline
|
60
73
|
@entity.ports.each do |port|
|
61
74
|
port_name=port.name.str.ljust(@max_length_str)
|
62
75
|
port_type=port.type.str
|
@@ -132,7 +145,7 @@ module Vertigo
|
|
132
145
|
code << "report \"waiting for asynchronous reset\";"
|
133
146
|
code << "wait until #{@reset_name}='1';"
|
134
147
|
code << "wait_cycles(10);"
|
135
|
-
code << "wait_cycles(
|
148
|
+
code << "wait_cycles(200);"
|
136
149
|
code << "report \"end of simulation\";"
|
137
150
|
code << "running <= false;"
|
138
151
|
code << "wait;"
|
@@ -148,27 +161,27 @@ module Vertigo
|
|
148
161
|
puts msg="ERROR : no entity found"
|
149
162
|
raise msg
|
150
163
|
end
|
151
|
-
puts "=> found entity '#{entity.name.str}'"
|
164
|
+
puts "=> found entity '#{entity.name.str}'" unless options[:mute]
|
152
165
|
@arch=ast.design_units.find{|du| du.is_a? Architecture}
|
153
166
|
if @arch.nil?
|
154
167
|
puts msg="ERROR : no architecture found"
|
155
168
|
raise msg
|
156
169
|
end
|
157
170
|
|
158
|
-
puts "=> found architecture '#{arch.name.str}'"
|
171
|
+
puts "=> found architecture '#{arch.name.str}'" unless options[:mute]
|
159
172
|
@entity_name=@entity.name.str
|
160
173
|
@arch_name=@arch.name.str
|
161
174
|
[@entity,@arch]
|
162
175
|
end
|
163
176
|
|
164
177
|
def detecting_clk_and_reset entity_arch
|
165
|
-
puts "=> detecting clock and reset"
|
178
|
+
puts "=> detecting clock and reset" unless options[:mute]
|
166
179
|
entity,arch=entity_arch
|
167
180
|
inputs=entity.ports.select{|port| port.is_a?(Input)}
|
168
181
|
@clk = inputs.sort_by{|input| levenshtein_distance(input.name.str,"clk")}.first
|
169
182
|
@rst = inputs.sort_by{|input| levenshtein_distance(input.name.str,"reset_n")}.first
|
170
|
-
puts "\t-most probable clk : #{@clk.name.str}"
|
171
|
-
puts "\t-most probable reset : #{@rst.name.str}"
|
183
|
+
puts "\t-most probable clk : #{@clk.name.str}" unless options[:mute]
|
184
|
+
puts "\t-most probable reset : #{@rst.name.str}" unless options[:mute]
|
172
185
|
@max_length_str=entity.ports.map{|port| port.name.str.size}.max
|
173
186
|
@excluded=[@clk,@rst]
|
174
187
|
@reset_name=@rst.name.str
|
data/lib/vertigo/version.rb
CHANGED
@@ -0,0 +1,37 @@
|
|
1
|
+
library ieee;
|
2
|
+
use ieee.std_logic_1164.all;
|
3
|
+
use ieee.numeric_std.all;
|
4
|
+
|
5
|
+
architecture rca_vhdl_93 of adder is
|
6
|
+
signal co : std_logic_vector(N-1 downto 0);
|
7
|
+
begin
|
8
|
+
|
9
|
+
gen_loop: for i in 0 to N-1 generate
|
10
|
+
|
11
|
+
bit0 : if i=0 generate
|
12
|
+
fa_0: entity work.fa(arch)
|
13
|
+
port map(
|
14
|
+
a => a(0),
|
15
|
+
b => b(0),
|
16
|
+
ci => '0',
|
17
|
+
s => sum(0),
|
18
|
+
co => co(0)
|
19
|
+
);
|
20
|
+
end generate bit0;
|
21
|
+
|
22
|
+
other_bits : if i >0 generate
|
23
|
+
fa_i : entity work.fa(arch)
|
24
|
+
port map(
|
25
|
+
a => a(i),
|
26
|
+
b => b(i),
|
27
|
+
ci => co(i-1),
|
28
|
+
s => sum(i),
|
29
|
+
co => co(i)
|
30
|
+
);
|
31
|
+
end generate other_bits;
|
32
|
+
|
33
|
+
end generate gen_loop;
|
34
|
+
|
35
|
+
carry <= co(N-1);
|
36
|
+
|
37
|
+
end architecture;
|
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: vertigo_vhdl
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 0.8.
|
4
|
+
version: 0.8.10
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Jean-Christophe Le Lann
|
8
8
|
autorequire:
|
9
9
|
bindir: bin
|
10
10
|
cert_chain: []
|
11
|
-
date: 2021-
|
11
|
+
date: 2021-09-07 00:00:00.000000000 Z
|
12
12
|
dependencies: []
|
13
13
|
description: A Ruby handwritten VHDL parser and utilities
|
14
14
|
email: jean-christophe.le_lann@ensta-bretagne.fr
|
@@ -37,167 +37,86 @@ files:
|
|
37
37
|
- lib/vertigo/visitor_vertigo_rkgen.rb
|
38
38
|
- tests/ghdl_tests/fsm.vhd
|
39
39
|
- tests/ghdl_tests/fsm_synth.vhd
|
40
|
-
- tests/ghdl_tests/test_fsm.vhd
|
41
|
-
- tests/parser_tests/else.vhd
|
42
|
-
- tests/parser_tests/pingpong.vhd
|
43
40
|
- tests/parser_tests/test_MUST_fail.vhd
|
44
41
|
- tests/parser_tests/test_accelerator.vhd
|
45
|
-
- tests/parser_tests/
|
42
|
+
- tests/parser_tests/test_adder_rca_vhdl93.vhd
|
46
43
|
- tests/parser_tests/test_aggregate.vhd
|
47
|
-
- tests/parser_tests/test_aggregate_pp.vhd
|
48
44
|
- tests/parser_tests/test_archi_1.vhd
|
49
|
-
- tests/parser_tests/test_archi_1_pp.vhd
|
50
45
|
- tests/parser_tests/test_array_array_00.vhd
|
51
|
-
- tests/parser_tests/test_array_array_00_pp.vhd
|
52
46
|
- tests/parser_tests/test_array_urange.vhd
|
53
|
-
- tests/parser_tests/test_array_urange_pp.vhd
|
54
47
|
- tests/parser_tests/test_chu-1.vhd
|
55
|
-
- tests/parser_tests/test_chu-1_pp.vhd
|
56
48
|
- tests/parser_tests/test_concat.vhd
|
57
|
-
- tests/parser_tests/test_concat_pp.vhd
|
58
49
|
- tests/parser_tests/test_counter.vhd
|
59
|
-
- tests/parser_tests/test_counter_pp.vhd
|
60
50
|
- tests/parser_tests/test_de2.vhd
|
61
|
-
- tests/parser_tests/test_de2_pp.vhd
|
62
51
|
- tests/parser_tests/test_encode.vhd
|
63
|
-
- tests/parser_tests/test_encode_pp.vhd
|
64
52
|
- tests/parser_tests/test_fsm.vhd
|
65
|
-
- tests/parser_tests/test_fsm_pp.vhd
|
66
53
|
- tests/parser_tests/test_fsm_synth.vhd
|
67
|
-
- tests/parser_tests/test_fsm_synth_pp.vhd
|
68
54
|
- tests/parser_tests/test_function-01.vhd
|
69
|
-
- tests/parser_tests/test_function-01_pp.vhd
|
70
55
|
- tests/parser_tests/test_lfsr.vhd
|
71
|
-
- tests/parser_tests/test_lfsr_pp.vhd
|
72
56
|
- tests/parser_tests/test_microwatt_cache_ram.vhd
|
73
|
-
- tests/parser_tests/test_microwatt_cache_ram_pp.vhd
|
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homepage: http://www.github.com/JC-LL/vertigo
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licenses:
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- GPL-2.0-only
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@@ -217,7 +136,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
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requirements: []
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summary: VHDL parser and utilities
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@@ -1,162 +0,0 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity fsm is
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port (
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reset_n: in std_logic;
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clk: in std_logic;
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switches: in std_logic_vector (7 downto 0);
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leds: out std_logic_vector (7 downto 0)
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);
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end entity;
|
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-
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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architecture rtl of fsm is
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signal wrap_reset_n: std_logic;
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signal wrap_clk: std_logic;
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signal wrap_switches: std_logic_vector (7 downto 0);
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signal wrap_leds: std_logic_vector (7 downto 0);
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signal state : std_logic_vector (2 downto 0);
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signal state_c : std_logic_vector (2 downto 0);
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signal n4_o : std_logic;
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signal n9_q : std_logic_vector (2 downto 0);
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signal n12_o : std_logic;
|
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signal n14_o : std_logic_vector (2 downto 0);
|
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signal n15_o : std_logic;
|
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signal n17_o : std_logic_vector (2 downto 0);
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signal n18_o : std_logic;
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signal n20_o : std_logic_vector (2 downto 0);
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signal n21_o : std_logic;
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signal n23_o : std_logic_vector (2 downto 0);
|
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signal n24_o : std_logic;
|
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signal n26_o : std_logic_vector (2 downto 0);
|
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signal n27_o : std_logic;
|
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signal n29_o : std_logic_vector (2 downto 0);
|
38
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signal n30_o : std_logic;
|
39
|
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signal n32_o : std_logic_vector (2 downto 0);
|
40
|
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signal n33_o : std_logic;
|
41
|
-
signal n35_o : std_logic_vector (2 downto 0);
|
42
|
-
signal n36_o : std_logic_vector (1 downto 0);
|
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signal n37_o : std_logic_vector (2 downto 0);
|
44
|
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signal n38_o : std_logic_vector (2 downto 0);
|
45
|
-
signal n39_o : std_logic;
|
46
|
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signal n40_o : std_logic_vector (2 downto 0);
|
47
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signal n44_o : std_logic;
|
48
|
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signal n45_o : std_logic_vector (7 downto 0);
|
49
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signal n48_o : std_logic;
|
50
|
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signal n49_o : std_logic_vector (7 downto 0);
|
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signal n52_o : std_logic;
|
52
|
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signal n53_o : std_logic_vector (7 downto 0);
|
53
|
-
signal n56_o : std_logic;
|
54
|
-
signal n57_o : std_logic_vector (7 downto 0);
|
55
|
-
signal n60_o : std_logic;
|
56
|
-
signal n61_o : std_logic_vector (7 downto 0);
|
57
|
-
signal n64_o : std_logic;
|
58
|
-
signal n65_o : std_logic_vector (7 downto 0);
|
59
|
-
signal n68_o : std_logic;
|
60
|
-
signal n69_o : std_logic_vector (7 downto 0);
|
61
|
-
begin
|
62
|
-
wrap_reset_n <= reset_n;
|
63
|
-
wrap_clk <= clk;
|
64
|
-
wrap_switches <= switches;
|
65
|
-
leds <= wrap_leds;
|
66
|
-
wrap_leds <= n45_o;
|
67
|
-
-- fsm.vhd:16:10
|
68
|
-
state <= n9_q; -- (signal)
|
69
|
-
-- fsm.vhd:16:16
|
70
|
-
state_c <= n40_o; -- (signal)
|
71
|
-
-- fsm.vhd:20:15
|
72
|
-
n4_o <= not wrap_reset_n;
|
73
|
-
-- fsm.vhd:22:5
|
74
|
-
process (wrap_clk, n4_o)
|
75
|
-
begin
|
76
|
-
if n4_o = '1' then
|
77
|
-
n9_q <= "000";
|
78
|
-
elsif rising_edge (wrap_clk) then
|
79
|
-
n9_q <= state_c;
|
80
|
-
end if;
|
81
|
-
end process;
|
82
|
-
-- fsm.vhd:33:20
|
83
|
-
n12_o <= wrap_switches (0);
|
84
|
-
-- fsm.vhd:33:9
|
85
|
-
n14_o <= state when n12_o = '0' else "001";
|
86
|
-
-- fsm.vhd:37:20
|
87
|
-
n15_o <= wrap_switches (1);
|
88
|
-
-- fsm.vhd:37:9
|
89
|
-
n17_o <= state when n15_o = '0' else "010";
|
90
|
-
-- fsm.vhd:41:20
|
91
|
-
n18_o <= wrap_switches (2);
|
92
|
-
-- fsm.vhd:41:9
|
93
|
-
n20_o <= state when n18_o = '0' else "011";
|
94
|
-
-- fsm.vhd:45:20
|
95
|
-
n21_o <= wrap_switches (3);
|
96
|
-
-- fsm.vhd:45:9
|
97
|
-
n23_o <= state when n21_o = '0' else "100";
|
98
|
-
-- fsm.vhd:49:20
|
99
|
-
n24_o <= wrap_switches (4);
|
100
|
-
-- fsm.vhd:49:9
|
101
|
-
n26_o <= state when n24_o = '0' else "101";
|
102
|
-
-- fsm.vhd:53:20
|
103
|
-
n27_o <= wrap_switches (5);
|
104
|
-
-- fsm.vhd:53:9
|
105
|
-
n29_o <= state when n27_o = '0' else "110";
|
106
|
-
-- fsm.vhd:57:20
|
107
|
-
n30_o <= wrap_switches (6);
|
108
|
-
-- fsm.vhd:57:9
|
109
|
-
n32_o <= state when n30_o = '0' else "111";
|
110
|
-
-- fsm.vhd:61:20
|
111
|
-
n33_o <= wrap_switches (7);
|
112
|
-
-- fsm.vhd:61:9
|
113
|
-
n35_o <= state when n33_o = '0' else "000";
|
114
|
-
-- fsm.vhd:31:10
|
115
|
-
n36_o <= state (1 downto 0);
|
116
|
-
-- fsm.vhd:31:10
|
117
|
-
with n36_o select n37_o <=
|
118
|
-
n14_o when "00",
|
119
|
-
n17_o when "01",
|
120
|
-
n20_o when "10",
|
121
|
-
n23_o when "11",
|
122
|
-
"XXX" when others;
|
123
|
-
-- fsm.vhd:31:10
|
124
|
-
with n36_o select n38_o <=
|
125
|
-
n26_o when "00",
|
126
|
-
n29_o when "01",
|
127
|
-
n32_o when "10",
|
128
|
-
n35_o when "11",
|
129
|
-
"XXX" when others;
|
130
|
-
-- fsm.vhd:31:10
|
131
|
-
n39_o <= state (2);
|
132
|
-
-- fsm.vhd:31:10
|
133
|
-
n40_o <= n37_o when n39_o = '0' else n38_o;
|
134
|
-
-- fsm.vhd:71:56
|
135
|
-
n44_o <= '1' when state = "000" else '0';
|
136
|
-
-- fsm.vhd:71:46
|
137
|
-
n45_o <= n49_o when n44_o = '0' else "00000000";
|
138
|
-
-- fsm.vhd:72:56
|
139
|
-
n48_o <= '1' when state = "001" else '0';
|
140
|
-
-- fsm.vhd:71:60
|
141
|
-
n49_o <= n53_o when n48_o = '0' else "00000001";
|
142
|
-
-- fsm.vhd:73:56
|
143
|
-
n52_o <= '1' when state = "010" else '0';
|
144
|
-
-- fsm.vhd:72:60
|
145
|
-
n53_o <= n57_o when n52_o = '0' else "00000010";
|
146
|
-
-- fsm.vhd:74:56
|
147
|
-
n56_o <= '1' when state = "011" else '0';
|
148
|
-
-- fsm.vhd:73:60
|
149
|
-
n57_o <= n61_o when n56_o = '0' else "00000011";
|
150
|
-
-- fsm.vhd:75:56
|
151
|
-
n60_o <= '1' when state = "100" else '0';
|
152
|
-
-- fsm.vhd:74:60
|
153
|
-
n61_o <= n65_o when n60_o = '0' else "00000100";
|
154
|
-
-- fsm.vhd:76:56
|
155
|
-
n64_o <= '1' when state = "101" else '0';
|
156
|
-
-- fsm.vhd:75:60
|
157
|
-
n65_o <= n69_o when n64_o = '0' else "00000101";
|
158
|
-
-- fsm.vhd:77:56
|
159
|
-
n68_o <= '1' when state = "110" else '0';
|
160
|
-
-- fsm.vhd:76:60
|
161
|
-
n69_o <= "00000111" when n68_o = '0' else "00000110";
|
162
|
-
end rtl;
|